A low-noise high-linearity capacitive humidity sensor MEMS conditioning chip circuit and detection method

Abstract

The application provides a low-noise high-linearity capacitive humidity sensor MEMS conditioning chip circuit and a detection method, and belongs to the technical field of CMOS integrated circuits.The circuit comprises a calibration enhanced correlated double sampling capacitive voltage converter, a low-pass filter and a sigma-delta ADC with a MASH 2-2 structure;an input end of the calibration enhanced correlated double sampling capacitive voltage converter is connected with a sensing element, the sensing element comprises a variable capacitor Cs and a reference capacitor C0;an input end of the low-pass filter is connected with an output end of the calibration enhanced correlated double sampling capacitive voltage converter; and an input end of the sigma-delta ADC with the MASH 2-2 structure is connected with an output end of the low-pass filter.The application realizes single-chip integration of humidity signal reading and processing and a front-end reading circuit, has an extremely low input noise base, an extremely high linearity, a lower power consumption and an enhanced calibration function, and is suitable for humidity detection in complex environments.

Description

Technical Field

[0001] This invention belongs to the field of CMOS integrated circuit technology, specifically relating to a low-noise, high-linearity capacitive humidity sensor MEMS conditioning chip circuit and detection method. Background Technology

[0002] With the continuous development of technology, humidity sensing technology has been widely used in various fields, especially in environmental monitoring, industrial control, weather forecasting, and smart homes. Capacitive humidity sensors, due to their high sensitivity, low power consumption, and long lifespan, have become one of the important technologies in the field of humidity measurement.

[0003] However, capacitive humidity sensors face several challenges in practical applications. Since the sensor output signal is typically weak and easily affected by external environmental interference, achieving higher measurement accuracy and reliability requires the design of low-noise and high-linearity signal conditioning circuits. Especially in miniaturized MEMS (Micro-Electro-Mechanical Systems) technology, ensuring low noise and high linearity of the circuit while maintaining low power consumption and high integration is a key technical challenge. On the other hand, parasitic inductance and capacitance, due to factors such as bond wire length, interfere with the weak capacitive signal when the MEMS is coupled to the interface circuit. Suppressing the impact of parasitic capacitance generated by the cross-domain coupling between the MEMS and the interface circuit on the system's detection accuracy is also a critical issue.

[0004] The output signal of a capacitive humidity sensor is typically a weak change in capacitance, which is easily affected by environmental noise and other external factors, leading to a decrease in measurement accuracy. Current humidity sensor signal conditioning circuits usually rely on low-noise amplifiers, sophisticated analog front-ends, and high-precision analog-to-digital converters to ensure accurate signal extraction. However, these circuit designs often face challenges in noise suppression and signal linearization, especially in MEMS technology, where high integration and area constraints make it difficult for traditional circuit design methods to effectively meet the requirements for low noise and high linearity. Summary of the Invention

[0005] The purpose of this invention is to overcome the above-mentioned technical problems and provide a low-noise, high-linearity capacitive humidity sensor MEMS conditioning chip circuit and detection method.

[0006] The objective of this invention is achieved through the following technical solution:

[0007] A low-noise, high-linearity capacitive humidity sensor MEMS conditioning chip circuit includes: a calibration-enhanced correlated dual-sampling capacitive voltage converter, a low-pass filter, and a MASH 2-2 structure Σ-Δ ADC. The input terminal of the calibration-enhanced correlated dual-sampling capacitive voltage converter is connected to a sensing element, which includes a variable capacitor Cs and a reference capacitor C0. The input terminal of the low-pass filter is connected to the output terminal of the calibration-enhanced correlated dual-sampling capacitive voltage converter, and the input terminal of the MASH 2-2 structure Σ-Δ ADC is connected to the output terminal of the low-pass filter.

[0008] The calibration-enhanced correlated dual-sampling capacitor voltage converter includes a drive voltage terminal Vdrv, a coarse compensation capacitor array and a fine compensation capacitor array, a correlated dual-sampling capacitor, and a fully differential operational amplifier. The drive voltage Vdrv is connected to one end of the variable capacitor Cs and the reference capacitor C0. The coarse compensation capacitor array and the fine compensation capacitor array are connected between the other end of the reference capacitor C0 and ground for calibrating parasitic capacitance and static mismatch. The correlated dual-sampling capacitor is connected between the variable capacitor Cs and the reference capacitor C0 and the input terminal of the fully differential operational amplifier. The positive output terminal of the fully differential operational amplifier is connected to its negative input terminal via a first feedback capacitor CF, and its negative output terminal is connected to its positive input terminal via a second feedback capacitor CF.

[0009] Furthermore, the conditioning chip circuit also includes an oscillator, a reference circuit, a clock circuit, a temperature sensor, a programmable memory, and an SPI interface. The oscillator is connected to the clock circuit, and the SPI interface is connected to the programmable memory.

[0010] Furthermore, the values ​​of the first feedback capacitor CF and the second feedback capacitor CF are both one-quarter of the value of the reference capacitor C0.

[0011] Furthermore, the calibration-enhanced correlated dual-sampling capacitor voltage converter also includes switches S1 and S2, which are used to realize time-division operation of the reset phase and the sampling conversion phase. In the reset phase, switch S2 is closed and switch S1 is open, and the offset voltage and 1 / f noise charge of the fully differential operational amplifier are stored in the correlated dual-sampling capacitor. In the sampling conversion phase, switch S1 is closed and S2 is open, and the driving voltage charges the variable capacitor Cs and the reference capacitor C0. The resulting charge difference is transferred to the feedback capacitor CF and converted into a differential output voltage.

[0012] Furthermore, the switches S1 and S2 are controlled by non-overlapping clocks and are not turned on simultaneously; the switch S1 is a sampling switch and the switch S2 is a reset switch.

[0013] Furthermore, the Σ-Δ ADC of the MASH 2-2 structure includes:

[0014] The first-stage integrator adopts a dual-sampling integrator structure, and its input is connected to the output of the low-pass filter. The first-stage integrator includes a correlated dual-sampling network and a chopper operational amplifier OP1. The output of the correlated dual-sampling network is connected to the input of the chopper operational amplifier OP1.

[0015] The input of the second-stage integrator OP2 is connected to the output of the first-stage integrator.

[0016] The third-stage integrator OP3 and the fourth-stage integrator OP4 are connected, with the output of the second-stage integrator OP2 connected to the input of the third-stage integrator OP3, and the output of the third-stage integrator OP3 connected to the input of the fourth-stage integrator OP4, forming the second-stage modulation path.

[0017] The first dynamic latch comparator D1 has its input connected to the output of the second stage integrator OP2, and is used to output the first quantized code stream.

[0018] The second dynamic latch comparator D2 has its input connected to the output of the fourth-stage integrator OP4 and is used to output the second quantized code stream.

[0019] The noise cancellation module has its input terminals connected to the output terminals of the first dynamic latch comparator D1 and the second dynamic latch comparator D2, respectively, and is used for digital reconstruction.

[0020] A digital filter is connected to the output of the noise cancellation module.

[0021] A passive switched capacitor adder is used to add interstage feedforward signals.

[0022] Furthermore, the dual-sampling integrator in the first-stage integrator splits the sampling capacitor into two twin sampling networks, enabling parallel operations of sampling by one network and integration by the other.

[0023] Furthermore, the variable capacitor Cs is a humidity-sensitive MEMS capacitor, the reference capacitor C0 is an on-chip fixed capacitor, and both the coarse compensation capacitor array and the fine compensation capacitor array are digitally adjustable capacitor arrays.

[0024] Furthermore, the MEMS humidity sensor corresponding to the variable capacitor Cs is directly stacked above the CMOS interface circuit of the conditioning chip, and a circular opening for humidity sensing is provided on the top of the package.

[0025] The present invention may also include:

[0026] A method for humidity detection based on the above-mentioned capacitive humidity sensor MEMS conditioning chip circuit includes the following steps:

[0027] The humidity change is converted into a differential capacitance change of the variable capacitor Cs;

[0028] The capacitance change is converted into a differential voltage signal by calibrating an enhanced correlated dual-sampling capacitor voltage converter;

[0029] The differential voltage signal is filtered by a low-pass filter;

[0030] The filtered analog signal is input to a Σ-Δ ADC of MASH 2-2 structure and converted into a digital signal;

[0031] The digital signal is output as the humidity detection result.

[0032] The beneficial effects of this invention are as follows:

[0033] This invention features extremely low noise floor and offset. It introduces correlated double sampling (CDS) technology into the calibration-enhanced correlated double sampling capacitor voltage converter (CE-CDS-CVC). Through switching timing control, the static offset voltage and 1 / f noise charge of the fully differential operational amplifier are first stored in the correlated double sampling capacitor (CCDS), and then released in reverse during the sampling conversion stage, effectively canceling the offset and low-frequency noise. Simultaneously, the first-stage integrator of the MASH 2-2 Σ-Δ ADC further integrates a correlated double sampling network and a chopper operational amplifier. These two components work together to modulate residual offset and low-frequency noise to high frequencies, which are then filtered out by subsequent digital filters. This multi-layered noise reduction mechanism results in extremely low input reference noise for the entire conditioning chip, enabling precise extraction of minute changes (on the order of fF) in the humidity-sensitive capacitor, significantly improving the resolution and signal-to-noise ratio of humidity measurements.

[0034] This invention achieves high linearity signal conversion by employing a two-stage compensation capacitor array (Crough and Cprecise) to precisely calibrate the reference capacitor C0, eliminating nonlinear errors caused by static mismatch. Furthermore, the CVC itself uses a fully differential switched capacitor structure, coupled with an operational amplifier with high common-mode rejection ratio (CMRR), effectively suppressing power supply noise and common-mode interference.

[0035] This invention employs a packaging method where the MEMS sensor is directly stacked on top of the CMOS interface circuit, significantly shortening the bonding wire length and minimizing parasitic inductance and capacitance. A circular opening at the top of the package ensures fast humidity response while reducing external parasitic coupling. This allows the invention to operate stably in complex electromagnetic environments, making it particularly suitable for highly integrated MEMS systems.

[0036] This invention achieves low power consumption, high integration, and multifunctionality at multiple levels. The high integration not only reduces the number of external components and lowers the system cost, but also improves the system's reliability.

[0037] The calibration-enhanced correlated dual-sampling capacitor voltage converter of this invention has the function of enhanced calibration, which can effectively suppress the influence of parasitic capacitance generated by cross-domain coupling of MEMS and interface circuit on the detection accuracy of the system. Attached Figure Description

[0038] Appendix Figure 1 This is a structural block diagram of the present invention;

[0039] Appendix Figure 2 The circuit diagram for the calibration enhancement-correlated dual-sampling capacitor voltage converter of this invention is shown below.

[0040] Appendix Figure 3 This is a circuit diagram of the Σ-Δ ADC with the MASH 2-2 structure of this invention. Detailed Implementation

[0041] The present invention will now be further described with reference to the accompanying drawings.

[0042] This invention provides a low-noise, high-linearity capacitive humidity sensor MEMS conditioning chip circuit, such as... Figure 1 As shown, this embodiment provides a low-noise, high-linearity capacitive humidity sensor MEMS conditioning chip circuit, which includes: a calibration-enhanced correlated dual-sampling capacitor voltage converter (CE-CDS-CVC), a low-pass filter (LPF), and a MASH 2-2 structure Σ-Δ ADC.

[0043] The input terminal of the CE-CDS-CVC is connected to a sensing element. The sensing element includes a reference capacitor C0 and a variable capacitor Cs. The variable capacitor Cs is a humidity-sensitive MEMS capacitor whose capacitance changes linearly with the ambient relative humidity; the reference capacitor C0 is an on-chip integrated fixed capacitor that does not respond to humidity changes. C0 and Cs together form a differential capacitor input pair to suppress common-mode interference.

[0044] The output terminals (differential output voltages VOUT+ and VOUT-) of the CE-CDS-CVC are connected to the differential input terminals of the LPF. The output terminal of the LPF is connected to the differential input terminal of the MASH 2-2 structure Σ-Δ ADC. The digital output terminal of the MASH 2-2 structure Σ-Δ ADC serves as the digital output signal of the entire conditioning chip, representing the humidity detection result.

[0045] In addition, the conditioning chip in this embodiment also integrates an oscillator, a reference circuit, a clock circuit, a temperature sensor, a programmable memory, and an SPI interface to provide on-chip clock, bias voltage / current, operating timing, temperature compensation, and digital configuration and readout functions.

[0046] The specific workflow of CE-CDS-CVC:

[0047] The circuit is controlled by two non-overlapping clocks, switch S2 (reset) and switch S1 (sampling), and operates in two stages. The actions of all components form a closed loop in the timing sequence.

[0048] Phase 1: Reset Phase (Switch S2 high, switch S1 low)

[0049] When switch S2 is closed, the non-inverting and inverting input terminals of the operational amplifier are shorted to VCM through the switch, and the operational amplifier operates in the reset state.

[0050] The op-amp's static offset voltage and 1 / f noise charge are stored in the CCDS;

[0051] CF discharges through switch S2, the voltage across it is reset to VCM, and the residual charge from the previous cycle is cleared.

[0052] Crough and Cprecise maintain the calibrated capacitance values, continuously offsetting the static mismatch between C0 and Cs.

[0053] Phase 2: Sampling and Conversion Phase (Switch S1 High, Switch S2 Low)

[0054] With S2 open and S1 closed, Vdrv charges C0 and Cs, generating a charge proportional to the capacitance: QS = Vdrv × Cs, Q0 = Vdrv × C0; resulting in a charge difference ΔQ = Vdrv × ΔC.

[0055] The charge difference ΔQ is transferred to the input side of the op-amp through the switch. According to the virtual short and virtual open characteristics, ΔQ is completely transferred to the feedback capacitor CF and converted into the output voltage: VOUT=ΔQ / CF=Vdrv×ΔC / CF;

[0056] At the same time, the offset charge stored in CCDS is released in reverse to cancel the offset and 1 / f noise of the op-amp, so that the output retains only the signal related to ΔC (humidity);

[0057] The common-mode voltage VCM maintains the operational amplifier's operating point stability, suppresses common-mode interference, and ensures the linearity of the differential output.

[0058] The LPF adopts a fully differential input architecture matched with the CE-CDS-CVC. Its positive and negative input ports are connected one-to-one with the VOUT+ and VOUT- of the CE-CDS-CVC, respectively, ensuring complete reception of the differential signal and avoiding common-mode noise interference caused by single-ended input. As a low-pass filter, the core function of the LPF is to filter out residual high-frequency noise in the CE-CDS-CVC output signal (such as clock noise generated by circuit switching and high-frequency noise introduced by external electromagnetic interference), while retaining the low-frequency effective signal related to humidity. The cutoff frequency of the LPF is customized according to the overall operating clock frequency of the chip and the sampling frequency of the MASH 2-2∑-Δ ADC, ensuring that the effective signal passes through without attenuation, high-frequency noise is significantly suppressed, and the linearity of the signal is not changed during the filtering process, ensuring the linear transmission of the humidity signal. The output signal of the LPF is still a differential analog voltage signal. Compared with the output signal of the CE-CDS-CVC, its signal-to-noise ratio is further improved, providing a high-fidelity analog input signal for the subsequent analog-to-digital conversion of the ADC.

[0059] The differential analog voltage signal filtered by the LPF serves as the input to the MASH 2-2∑-Δ ADC. The ADC input port employs a high input impedance design to achieve impedance matching with the low output impedance of the LPF output port, preventing signal reflection and attenuation during transmission due to impedance mismatch and ensuring complete signal reception. Taking advantage of the design characteristics of the ADC's first-stage dual-sampling integrator, the continuous analog signal transmitted by the LPF is implemented with single-cycle dual sampling: the integrator splits the sampling capacitor into two, forming twin sampling networks. While one sampling network samples the signal transmitted by the LPF, the other sampling network simultaneously integrates, achieving parallel sampling and integration operations. This design is compatible with the continuous signal output of the LPF, significantly improving signal sampling efficiency and reducing noise introduction during the sampling process.

[0060] Furthermore, to reduce the impact of parasitic capacitance generated by cross-domain coupling between MEMS and interface circuits on the system's detection accuracy, the humidity sensor is directly stacked on top of the CMOS interface circuit chip, rather than through traditional planar side-by-side integration. This approach offers several advantages: extremely small stacking spacing, bringing the humidity sensor closest to the on-chip temperature sensor, minimizing spatial differences in temperature and humidity measurements, and improving cross-compensation accuracy; shortening the bonding wire length between the sensor and interface circuit, reducing interference from parasitic inductance and capacitance on weak capacitive signals; and reducing the overall package size. A circular opening is provided on the top of the package to ensure humidity detection and maintain fast response.

[0061] Example 1:

[0062] As attached Figure 2As shown, the calibration-enhanced correlated dual-sampling capacitor voltage converter (CE-CDS-CVC) includes:

[0063] The driving voltage Vdrv is connected to the variable capacitor Cs and the reference capacitor C0;

[0064] The reference capacitor C0 is connected to GND by a coarse compensation capacitor array Crough and a fine compensation capacitor array Cprecise.

[0065] There is a switch S2 between the reference capacitor C0 and the intermediate level VCM;

[0066] There is a switch S2 between the variable capacitor Cs and the intermediate level VCM;

[0067] The reference capacitor C0 is connected in series with the switch S1, and the related dual sampling capacitor CCDS is connected to the negative input terminal of the operational amplifier.

[0068] The variable capacitor Cs is connected in series with the switch S1, and the related double sampling capacitor CCDS is connected to the positive input terminal of the operational amplifier.

[0069] The point between the switch S1 and the sampling capacitor CCDS, on the Cs branch, is defined as point A;

[0070] The point between the switch S1 and the sampling capacitor CCDS on the C0 branch is defined as point B.

[0071] There is a switch S2 between point A and the intermediate level VCM;

[0072] There is a switch S2 between point B and the intermediate level VCM;

[0073] The positive input terminal and the negative output terminal of the operational amplifier are connected in sequence to switch S2 and capacitor CF.

[0074] The negative input terminal and the positive output terminal of the operational amplifier are connected in sequence to switch S2 and capacitor CF.

[0075] Point A is connected to switch S1 and switch S2 in sequence with the negative output terminal of the operational amplifier. The point between S1 and S2 is defined as point C.

[0076] Point B is connected to switch S1 and switch S2 in sequence with the positive output terminal of the operational amplifier. The area between S1 and S2 is defined as point D.

[0077] Point C is connected to capacitor CF;

[0078] Point D is connected to capacitor CF;

[0079] The positive output terminal VOUT+ and the negative output terminal VOUT- of the operational amplifier are the outputs of CVC.

[0080] Specifically:

[0081] The core circuitry of the calibration-enhanced correlated dual-sampling capacitor voltage converter (CVC) consists of an input sensing module, a compensation and calibration module, a CDS correlated dual-sampling module, a feedback amplification module, and a clock control module. This CVC circuit employs a fully differential switched-capacitor architecture. Its core objective is to accurately convert minute capacitance changes (fF level) caused by humidity into a voltage signal. Simultaneously, it suppresses offset, parasitics, and noise through device-level optimization, providing a high signal-to-noise ratio signal for the subsequent ADC. Figure 2 The Crough module is a coarse-compensation capacitor array. Addressing the significant parasitic capacitance introduced by packaging and bonding wires, it uses digital control to select different capacitor combinations within the array, calibrating the effective capacitance value of C0 to perfectly match the actual effective capacitance of Cs, achieving a coarse-tuning accuracy of tens of fF. Building upon this coarse-tuning, the Cprecise fine-compensation capacitor array further compensates for minor mismatch errors, achieving a matching accuracy of several fF between C0 and Cs. This ensures that only humidity-induced ΔC is detected, preventing static offset from dominating the output. The CCDS (Correlated Double Sampling) module is the core component of the Correlation Double Sampling (CDS) technology. CCDS suppresses static offset voltage and low-frequency 1 / f noise, ensuring the output retains only the signal related to ΔC. The Crough and Cprecise modules minimize the impact of parasitic capacitance generated by cross-domain coupling between MEMS and interface circuits on detection accuracy.

[0082] This technology has the following key features:

[0083] Confirmation of CF value: In this invention, the value of CF is one-quarter of C0, at which point the gain is 4. The advantage of doing so is that no additional PGA is required, simplifying the architecture, avoiding noise amplification caused by excessive gain, and matching the driving capability of the op-amp to ensure that the bandwidth meets the conversion time requirements.

[0084] Two-stage compensation capacitor array: coarse adjustment to deal with large parasitics, fine adjustment to ensure matching accuracy. The two work together to reduce the mismatch error from "50% RH / 1% capacitor mismatch" to "<0.1% RH error", which is the core guarantee for the high precision of the system.

[0085] Non-overlapping clock and delay switch: avoids S1 and S2 being turned on simultaneously, prevents signal distortion caused by charge leakage, and the clock phase difference is precisely controlled by the chip's internal oscillator, while also adapting to the sampling frequency of the subsequent ADC.

[0086] Fully differential architecture: All components are differentially symmetrically designed, and with the high CMRR of the op-amp, common-mode signals such as power supply noise and electromagnetic interference are suppressed, further improving the output signal-to-noise ratio.

[0087] Example 2:

[0088] As attached Figure 3 As shown, the MASH 2-2 structure Σ-Δ ADC includes chopper operational amplifiers OP1 and OP2, OP3, and OP4 based on correlation double sampling, two comparators, several capacitors, and timing control, wherein:

[0089] VIP and VIN are the inputs to the MASH 2-2∑-Δ ADC;

[0090] The VIP and VIN are respectively connected to the input of the relevant dual sampling network;

[0091] The output of the related dual sampling network is connected to the input of the chopper operational amplifier OP1;

[0092] The outputs of OP1 are connected to the inputs of the second-stage integrator, which is composed of operational amplifier OP2.

[0093] The output of the two-stage modulation composed of OP2 is connected to comparator D1;

[0094] The output of OP2 is connected to a third-stage integrator composed of operational amplifier OP3;

[0095] The first dynamic latch comparator D1 outputs Don1 and Don2;

[0096] The output of the third-stage integrator, which is composed of operational amplifier OP3, is connected to the input of the fourth-stage integrator, which is composed of operational amplifier OP4.

[0097] The output of the fourth-stage integrator, which is composed of operational amplifier OP4, is connected to comparator D2;

[0098] The second dynamic latch comparator D2 has outputs Dop1 and Dop2;

[0099] Don1, Don2, Dop1, and Dop2 are connected to a noise cancellation module;

[0100] The noise cancellation module is connected to a digital filter;

[0101] The modulator composed of OP1, OP2, OP3, OP4, D1, and D2 is a MASH 2-2 structure;

[0102] Specifically, this embodiment consists of one dual-sampling integrator, three conventional integrators, a feedback DAC, a passive adder, and two dynamic latch comparators. Since a conventional integrator can only sample and integrate once per clock cycle, its sampling rate equals the input clock frequency. This invention, however, uses a dual-sampling integrator in the first stage. This dual-sampling technique splits the sampling capacitor into two integrator circuits, creating a twin sampling network. This allows one sampling network to sample while the other integrates, enabling the integrator to perform two samples per sampling cycle, thereby increasing the sampling frequency and reducing noise. The subsequent integrator stages still utilize conventional integrators.

[0103] The first dynamic latch comparator D1 and the second dynamic latch comparator D2 serve as the quantizers of the modulator, comparing the output of the integrator. The modulator designed in this invention uses one-bit quantization, and the output signals Don and Dop are fed back to the input via a DAC. The feedback DAC is implemented using switched capacitors. Because only one-bit quantization is used, feedback can be achieved with just a single-bit DAC. The modulator's adder is implemented using a passive adder. Although active adders offer higher accuracy and better linearity, they require an additional operational amplifier and an additional time interval for summation. Passive adders, on the other hand, do not require an additional operational amplifier; they use switched capacitors to achieve signal feedforward and summation, thus reducing power consumption.

[0104] Example 3:

[0105] Based on the conditioning chip circuit described in any of the above embodiments, this embodiment provides a humidity detection method, including the following steps:

[0106] Step 1: Convert the change in ambient humidity into a differential capacitance change ΔC of the variable capacitor Cs (relative to the reference capacitor C0).

[0107] Step 2: Convert ΔC into a differential voltage signal using CE-CDS-CVC. This process uses correlated double sampling to suppress offset and 1 / f noise, and uses coarse and fine two-stage compensation calibration to cancel parasitic capacitance and static mismatch.

[0108] Step 3: Filter the differential voltage signal through a low-pass filter to remove high-frequency switching noise and out-of-band interference.

[0109] Step 4: Input the filtered analog signal into a Σ-Δ ADC with a MASH 2-2 structure to convert it into a digital signal.

[0110] Step 5: Output the digital signal as the humidity detection result, which can be read through the SPI interface or output after calibration by a temperature sensor.

[0111] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A low-noise, high-linearity capacitive humidity sensor MEMS conditioning chip circuit, characterized in that, include: The system comprises a calibration-enhanced correlated-dual-sampling capacitor voltage converter, a low-pass filter, and a MASH 2-2 structure Σ-Δ ADC. The input of the calibration-enhanced correlated-dual-sampling capacitor voltage converter is connected to a sensing element, which includes a variable capacitor Cs and a reference capacitor C0. The input of the low-pass filter is connected to the output of the calibration-enhanced correlated-dual-sampling capacitor voltage converter, and the input of the MASH 2-2 structure Σ-Δ ADC is connected to the output of the low-pass filter. The calibration-enhanced correlated dual-sampling capacitor voltage converter includes a drive voltage terminal Vdrv, a coarse compensation capacitor array and a fine compensation capacitor array, a correlated dual-sampling capacitor, and a fully differential operational amplifier. The drive voltage Vdrv is connected to one end of the variable capacitor Cs and the reference capacitor C0. The coarse compensation capacitor array and the fine compensation capacitor array are connected between the other end of the reference capacitor C0 and ground, and are used to calibrate parasitic capacitance and static mismatch. The relevant dual sampling capacitor is connected between the variable capacitor Cs and the reference capacitor C0 and the input terminal of the fully differential operational amplifier; the positive output terminal of the fully differential operational amplifier is connected to its negative input terminal via the first feedback capacitor CF, and its negative output terminal is connected to its positive input terminal via the second feedback capacitor CF.

2. The low-noise, high-linearity capacitive humidity sensor MEMS conditioning chip circuit according to claim 1, characterized in that, The conditioning chip circuit also includes an oscillator, a reference circuit, a clock circuit, a temperature sensor, a programmable memory, and an SPI interface. The oscillator is connected to the clock circuit, and the SPI interface is connected to the programmable memory.

3. The low-noise, high-linearity capacitive humidity sensor MEMS conditioning chip circuit according to claim 1, characterized in that, The values ​​of the first feedback capacitor CF and the second feedback capacitor CF are both one-quarter of the value of the reference capacitor C0.

4. The low-noise, high-linearity capacitive humidity sensor MEMS conditioning chip circuit according to claim 1, characterized in that, The calibration-enhanced correlated dual-sampling capacitor voltage converter also includes switches S1 and S2, which are used to realize time-division operation of the reset phase and the sampling conversion phase; during the reset phase, switch S2 is closed and switch S1 is open, and the offset voltage and 1 / f noise charge of the fully differential operational amplifier are stored in the correlated dual-sampling capacitor; During the sampling and conversion phase, the switch S1 is closed and S2 is open. The driving voltage charges the variable capacitor Cs and the reference capacitor C0, and the resulting charge difference is transferred to the feedback capacitor CF and converted into a differential output voltage.

5. The low-noise, high-linearity capacitive humidity sensor MEMS conditioning chip circuit according to claim 4, characterized in that, The switches S1 and S2 are controlled by a non-overlapping clock and are not turned on at the same time; the switch S1 is a sampling switch and the switch S2 is a reset switch.

6. The low-noise, high-linearity capacitive humidity sensor MEMS conditioning chip circuit according to claim 1, characterized in that, The MASH 2-2 structure Σ-Δ ADC includes: The first-stage integrator adopts a dual-sampling integrator structure, and its input is connected to the output of the low-pass filter. The first-stage integrator includes a correlated dual-sampling network and a chopper operational amplifier OP1. The output of the correlated dual-sampling network is connected to the input of the chopper operational amplifier OP1. The input of the second-stage integrator OP2 is connected to the output of the first-stage integrator. The third-stage integrator OP3 and the fourth-stage integrator OP4 are connected, with the output of the second-stage integrator OP2 connected to the input of the third-stage integrator OP3, and the output of the third-stage integrator OP3 connected to the input of the fourth-stage integrator OP4, forming the second-stage modulation path. The first dynamic latch comparator D1 has its input connected to the output of the second stage integrator OP2, and is used to output the first quantized code stream. The second dynamic latch comparator D2 has its input connected to the output of the fourth-stage integrator OP4 and is used to output the second quantized code stream. The noise cancellation module has its input terminals connected to the output terminals of the first dynamic latch comparator D1 and the second dynamic latch comparator D2, respectively, and is used for digital reconstruction. A digital filter is connected to the output of the noise cancellation module. A passive switched capacitor adder is used to add interstage feedforward signals.

7. The low-noise, high-linearity capacitive humidity sensor MEMS conditioning chip circuit according to claim 6, characterized in that, The dual-sampling integrator in the first-stage integrator splits the sampling capacitor into two twin sampling networks, enabling parallel operations where one network samples and the other network integrates.

8. The low-noise, high-linearity capacitive humidity sensor MEMS conditioning chip circuit according to claim 1, characterized in that, The variable capacitor Cs is a humidity-sensitive MEMS capacitor, the reference capacitor C0 is an on-chip fixed capacitor, and both the coarse compensation capacitor array and the fine compensation capacitor array are digitally adjustable capacitor arrays.

9. The low-noise, high-linearity capacitive humidity sensor MEMS conditioning chip circuit according to claim 1, characterized in that, The MEMS humidity sensor corresponding to the variable capacitor Cs is directly stacked above the CMOS interface circuit of the conditioning chip, and a circular opening for humidity sensing is provided on the top of the package.

10. A method for humidity detection based on the MEMS conditioning chip circuit of the capacitive humidity sensor according to any one of claims 1 to 9, characterized in that, Includes the following steps: The humidity change is converted into a differential capacitance change of the variable capacitor Cs; The capacitance change is converted into a differential voltage signal by calibrating an enhanced correlated dual-sampling capacitor voltage converter; The differential voltage signal is filtered by a low-pass filter; The filtered analog signal is input to a Σ-Δ ADC of MASH 2-2 structure and converted into a digital signal; The digital signal is output as the humidity detection result.

Images