Jtag debugging method and chip

Abstract

The application provides a JTAG debugging method and a chip. A register mapping module in the application comprises a first control register configured with TCK, TRST, TMS and TDI bits and a second control register configured with a TDO bit. A mode switching module switches to an internal register to simulate a JTAG debugging mode, and each JTAG signal is mapped to a corresponding register bit. A timing simulation module outputs a JTAG timing rule. A CPU writes a level into the first control register in time division to generate a simulated JTAG timing to drive a TAP state machine. A JTAG chain outputs a TDO level and stores it into the second control register. The CPU reads the register to obtain debugging data. The application completely simulates a JTAG interaction process based on an on-chip register, does not need a special debugging pin and an external debugger, is suitable for a pin-free remote debugging scene, and effectively solves the defects of a single mode and poor scene adaptability of a traditional JTAG debugging scheme.

Description

Technical Field

[0001] This application relates to the field of network communication technology, and in particular to a JTAG debugging method and chip. Background Technology

[0002] JTAG (Joint Test Action Group) is an industry organization that develops boundary scan test specifications for circuit boards / chips in the electronics industry. Within the industry, the test interfaces and protocols it defines are collectively referred to as JTAG. JTAG utilizes dedicated debug pins such as TCK (Test Clock), TMS (Test Mode Select), TDI (Test Data Input), TDO (Test Data Output), and TRST (Test Reset) in conjunction with an external JTAG debugger to perform debugging functions such as reading and writing registers, accessing memory, and locating faults in various sub-modules or firmware (FW) within the chip. It is widely used in the research and development and mass production testing of CPUs (Central Processing Units) and programmable chips (FPGAs, ASICs, NPUs, DPUs, etc.).

[0003] Traditional JTAG debugging only supports a single mode of connecting the debugger via external GPIO (General Purpose Input Output) pins. JTAG debugging requires multiple dedicated GPIO debugging pins (such as TCK, TMS, TDI, TDO, and TRST pins). When pin resources are scarce in chip deployment scenarios and dedicated JTAG GPIO pins cannot be reserved, debugging cannot be achieved. For programmable chips with limited pin resources, the occupation of JTAG pins will squeeze the layout space of other functional pins, limiting the chip integration density.

[0004] Existing JTAG-related alternative debugging solutions have significant limitations: some solutions rely on software agents and interrupts for debugging, failing to simulate standard JTAG timing and TAP state machines, and are therefore incompatible with standard JTAG instructions; some solutions still retain independent JTAG hardware modules, resulting in significant hardware overhead; and others can only enable and disable JTAG paths, unable to generate complete JTAG debugging timings. In other words, existing debugging solutions cannot simultaneously support flexible switching between external GPIO JTAG debugging and internal register-simulated JTAG debugging modes, making them unsuitable for diverse chip debugging scenarios. Summary of the Invention

[0005] To address the problems of existing technologies that cannot flexibly switch between external GPIO JTAG debugging and internal register-simulated JTAG debugging modes simultaneously, or are incompatible with standard JTAG instructions, have high hardware overhead, or cannot generate complete JTAG timing sequences, making it difficult to meet the debugging needs of multiple scenarios, this application provides a JTAG debugging solution that simulates JTAG timing sequences through internal control registers, achieving pinless debugging without the need for a JTAG debugger, and is compatible with standard JTAG functions.

[0006] In a first aspect, this application provides a JTAG debugging method applied to a chip to be debugged. The chip to be debugged includes a mode switching module, a register mapping module, and a timing simulation module. The register mapping module integrates a first control register and a second control register. The first control register is configured with a test clock (TCK) bit, a test reset (TRST) bit, a test mode selection (TMS) bit, and a test data input (TDI) bit. The second control register is configured with a test data output (TDO) bit. The method includes: The mode switching module receives a mode selection instruction and switches the debugging mode to the internal register simulated JTAG debugging mode. In the internal register simulated JTAG debugging mode, the TCK, TRST, TMS, and TDI signals corresponding to JTAG debugging are mapped to the TCK bit, TRST bit, TMS bit, and TDI bit of the first control register, respectively, and the TDO signal corresponding to JTAG debugging is mapped to the TDO bit of the second control register. The timing simulation module outputs JTAG timing rules. Based on the timing rules, the CPU writes corresponding level bits to the TCK bit, TRST bit, TMS bit and TDI bit of the first control register in a time-division manner to generate simulated JTAG input timing signals. The timing signals are used to input the JTAG chain to drive the TAP state machine to complete state transitions. The JTAG chain writes the output TDO feedback level into the TDO bit of the second control register; The CPU reads the TDO bit of the second control register in a time-sharing manner to obtain the debug return data output by the JTAG chain.

[0007] Optionally, the first control register is further configured with a mode selection SEL bit, and the chip under test also supports external GPIO JTAG debugging mode; the chip under test also includes an external GPIO module, which integrates TCK, TRST, TMS, TDI and TDO debugging pins for connecting to an external JTAG debugger. When the mode switching module determines that the SEL bit of the first control register changes from 0 to 1, it switches the debugging mode to the internal register simulation JTAG debugging mode, opens the debugging channel with the register mapping module and the timing simulation module, and disconnects the debugging channel with the external GPIO module. When the mode switching module determines that the SEL bit of the first control register changes from 1 to 0, it switches the debug mode to the external GPIO JTAG debug mode, opens the debug channel with the external GPIO module, and disconnects the debug channel with the register mapping module and the timing simulation module.

[0008] Optionally, the JTAG timing rules output by the timing simulation module include the TCK clock duty cycle; When writing corresponding level bits to the TCK, TRST, TMS, and TDI bits of the first control register in a time-division multiplexing manner based on the timing rules to generate a simulated JTAG input timing signal, the TCK clock duty cycle is the first duty cycle; when the CPU reads the TDO bit of the second control register in a time-division multiplexing manner to obtain the debug return data output by the JTAG chain, the TCK clock duty cycle is adjusted to the second duty cycle, wherein the first duty cycle is greater than the second duty cycle.

[0009] Optionally, the first duty cycle is 1 / 2 and the second duty cycle is 1 / 3.

[0010] Optionally, while switching from the first debugging mode to the second debugging mode, the mode switching module caches the current running state of the TAP state machine in the first debugging mode; when switching from the second debugging mode to the first debugging mode, the mode switching module restores the running state of the TAP state machine based on the cached current running state of the TAP state machine in the first debugging mode.

[0011] Optionally, in the JTAG debugging mode emulated by the internal register of the chip under test, the TCK, TRST, TMS, TDI and TDO debugging pins of the external GPIO module can be configured as general-purpose GPIO pins.

[0012] Optionally, the first control register is a 32-bit or 64-bit register, wherein the lower 5 bits of the first control register are configured as TCK bit, TRST bit, TMS bit, TDI bit and SEL bit, and the remaining bits are reserved bits; The second control register is a 32-bit or 64-bit register, wherein the lowest bit of the second control register is configured as the TDO bit, and the remaining bits are reserved bits.

[0013] Secondly, this application provides a chip, the chip comprising: a mode switching module, a register mapping module connected to the mode switching module, and a timing simulation module connected to the register mapping module, wherein the register mapping module integrates a first control register and a second control register, the first control register being configured with a test clock TCK bit, a test reset TRST bit, a test mode selection TMS bit, and a test data input TDI bit, and the second control register being configured with a test data output TDO bit; The mode switching module is used to receive a mode selection instruction and switch the debugging mode to the internal register simulated JTAG debugging mode. In the internal register simulated JTAG debugging mode, the TCK, TRST, TMS, and TDI signals corresponding to JTAG debugging are respectively mapped to the TCK bit, TRST bit, TMS bit, and TDI bit of the first control register, and the TDO signal corresponding to JTAG debugging is mapped to the TDO bit of the second control register. The timing simulation module is used to output JTAG timing rules. Based on the timing rules, the CPU writes corresponding level bits to the TCK bit, TRST bit, TMS bit, and TDI bit of the first control register in a time-division multiplexing manner to generate simulated JTAG input timing signals. The timing signals are used to input the JTAG chain to drive the TAP state machine to complete state transitions. The JTAG chain writes the output TDO feedback level into the TDO bit of the second control register. The CPU is also used to time-division multiplex the TDO bit of the second control register to obtain the debug return data output by the JTAG chain.

[0014] Optionally, the first control register is further configured with a mode selection SEL bit, and the chip also supports external GPIO JTAG debug mode; the chip also includes an external GPIO module connected to the mode switching module, and the external GPIO module integrates TCK, TRST, TMS, TDI and TDO debug pins for connecting to an external JTAG debugger. The mode switching module is specifically used to switch the debug mode to the internal register simulation JTAG debug mode when it is determined that the SEL bit of the first control register changes from 0 to 1, open the debug channel with the register mapping module and the timing simulation module, and disconnect the debug channel with the external GPIO module. The mode switching module is specifically used to switch the debug mode to the external GPIO JTAG debug mode when it is determined that the SEL bit of the first control register changes from 1 to 0, to open the debug channel with the external GPIO module, and to disconnect the debug channel with the register mapping module and the timing simulation module.

[0015] Optionally, while switching from the first debugging mode to the second debugging mode, the mode switching module is also used to cache the current running state of the TAP state machine in the first debugging mode; when switching from the second debugging mode to the first debugging mode, the mode switching module is also used to restore the running state of the TAP state machine based on the cached current running state of the TAP state machine in the first debugging mode.

[0016] The technical solutions provided in this application embodiment may include the following beneficial effects: In the JTAG debugging mode of the internal register module, this application maps the TCK, TRST, TMS, TDI, and TDO signals to on-chip dedicated control registers through the register mapping module. In conjunction with the timing simulation module, standard JTAG timing is generated. The CPU reads and writes the control registers to drive the TAP state machine to jump. No dedicated JTAG debugger is required, and the chip to be debugged does not need to be configured with dedicated GPIO pins such as TCK, TMS, TDI, TDO, and TRST. This saves pin resources, improves chip integration, reduces debugging hardware costs, and improves the efficiency of remote debugging and batch testing.

[0017] By strictly simulating the timing interactions of TCK, TMS, TDI, TDO, and TRST through control registers, it is compatible with the standard JTAG instruction set and can reuse existing JTAG debugging processes and scripts.

[0018] By dynamically adjusting the TCK duty cycle during the TDO reading phase, the duration of stable TDO level maintenance is extended, significantly reducing the probability of misjudgment in TDO data sampling and effectively improving the overall debugging reliability of the internal register module in JTAG debugging mode.

[0019] Furthermore, the chip under test also supports external GPIO JTAG debugging mode. Through the mode switching module, it realizes dual-mode switching between external GPIO JTAG and internal register simulated JTAG and completes signal isolation. It can simultaneously adapt to various usage scenarios such as offline field hardware debugging and pinless remote batch testing, effectively solving the shortcomings of traditional JTAG debugging solutions in terms of single mode and poor scenario adaptability. Attached Figure Description

[0020] Figure 1 This is a flowchart illustrating a JTAG debugging method according to an embodiment of this application; Figure 2 This is a schematic diagram illustrating the mapping of various fields of a control register according to an embodiment of this application; Figure 3 This is a schematic diagram of a simulation timing shown in one embodiment of this application; Figure 4 This is a schematic diagram of a chip structure shown in one embodiment of this application. Detailed Implementation

[0021] The exemplary embodiments will now be described in detail. When the description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification; they are merely exemplary embodiments of apparatuses and methods consistent with some aspects of this specification.

[0022] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. The singular forms “a,” “the,” and “the” used in this specification are also intended to include the plural forms unless the context clearly indicates otherwise. This specification may use terms such as “first,” “second,” “third,” etc., to describe various information or structural modules for the purpose of more clearly describing the scheme, and should not be construed as indicating or implying relative importance or implicitly specifying the number, order, or position of the indicated technical features. Thus, a feature defined with “first,” “second,” “third,” etc., may explicitly or implicitly include one or more of that feature. In the description of this specification, unless otherwise stated, “multiple” means two or more; “if” can be interpreted as “when,” “when,” or “in response to a determination.” In this specification, “and / or” is used to describe the relationship between related objects, indicating that three relationships may exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural.

[0023] The embodiments described in this specification will now be described in detail.

[0024] like Figure 1 The diagram shown is a flowchart of a JTAG debugging method according to an embodiment of this application, applied to a chip to be debugged. The chip to be debugged includes a mode switching module, a register mapping module, and a timing simulation module. The register mapping module integrates a first control register and a second control register. The first control register is configured with a test clock (TCK) bit, a test reset (TRST) bit, a test mode selection (TMS) bit, and a test data input (TDI) bit. The second control register is configured with a test data output (TDO) bit. The method includes the following steps: Step 101: The mode switching module receives the mode selection instruction and switches the debug mode to the internal register simulated JTAG debug mode.

[0025] In the internal register emulation JTAG debugging mode, the TCK, TRST, TMS, and TDI signals corresponding to JTAG debugging are mapped to the TCK bit, TRST bit, TMS bit, and TDI bit of the first control register, respectively, and the TDO signal corresponding to JTAG debugging is mapped to the TDO bit of the second control register.

[0026] In this embodiment of the application, the first control register is further configured with a mode selection SEL bit.

[0027] For example, see Figure 2 The diagram shown is a mapping diagram of each field of a control register according to an embodiment of this application. The description of each field of the first control register (Control reg A, 32-bit register) is shown in Table 1.

[0028] Table 1

[0029] That is, the bits of Control reg A are defined as follows: bit0=TCK, bit1=TRST, bit2=TMS, bit3=TDI, bit4=SEL (mode selection, SEL=1 represents mode two), and the remaining bits are reserved; among them, mode one is the external GPIO JTAG debugging mode, and mode two is the internal register simulated JTAG debugging mode.

[0030] The descriptions of each field of the second control register (Control reg B, 32-bit register) are shown in Table 2.

[0031] Table 2

[0032] That is, the bits of Control reg A are defined as follows: bit0=TDO, and the remaining bits are reserved.

[0033] In this embodiment of the application, preferably, the first control register is a 32-bit or 64-bit register, wherein the lower 5 bits of the first control register are configured as TCK bit, TRST bit, TMS bit, TDI bit, and SEL bit, and the remaining bits are reserved bits. The second control register is a 32-bit or 64-bit register, wherein the lowest bit of the second control register is configured as TDO bit, and the remaining bits are reserved bits.

[0034] The chip to be debugged also supports external GPIO JTAG debugging mode; the chip to be debugged also includes an external GPIO module, which integrates TCK, TRST, TMS, TDI and TDO debugging pins for connecting to an external JTAG debugger.

[0035] In practical applications, the specific addresses mapped to the first and second control registers within the chip are defined by each chip, and no specific limitation is made here in this embodiment. In this embodiment, Control reg A is mapped to physical address 0x10 and Control reg B is mapped to physical address 0x20 as an example for illustration.

[0036] In this embodiment of the application, when the mode switching module determines that the SEL bit of the first control register changes from 0 to 1, it switches the debugging mode to the internal register simulation JTAG debugging mode, opens the debugging channel with the register mapping module and the timing simulation module, and disconnects the debugging channel with the external GPIO module.

[0037] Optionally, the CPU can write a value to the lower 5 bits of the first control register. The purpose of writing the value to the lower 5 bits of the first control register is to pull the SEL bit of the first control register high (bit4=1) and switch the debugging to the internal register simulated JTAG debugging mode.

[0038] Preferably, at time t0, the data 10000 (binary) is written to the first control register at physical address 0x10; only SEL (bit 4) is set to 1, while TCK, TRST, TMS, and TDI are all low. After the hardware detects that SEL=1, it caches the current TAP state machine context, connects the register mapping module and the internal JTAG chain, completes the internal simulated JTAG mode switching, and outputs the internal register simulated JTAG debug mode ready flag.

[0039] It should be noted that if the value of the SEL bit (bit4) in the first control register is 1, it means that the chip under test is currently in the internal register simulation JTAG debugging mode.

[0040] The debug chip is in internal register simulation JTAG debug mode. The mode switching module opens the debug channel between the register mapping module and the timing simulation module. The timing simulation module is activated and begins operation.

[0041] In this embodiment of the application, while the mode switching module switches from the first debugging mode to the second debugging mode, it caches the current running state of the TAP state machine in the first debugging mode; when the mode switching module switches from the second debugging mode to the first debugging mode, it restores the running state of the TAP state machine based on the cached current running state of the TAP state machine in the first debugging mode.

[0042] In practical applications, the mode switching module can switch the JTAG signal path using a multiplexer (MUX) hardware circuit. Internally, the module has a dedicated status register for real-time storage of the current state code of the TAP (Test Access Port) state machine in the TAP controller. During the switching between two debug modes, the hardware automatically saves and restores the current state of the TAP state machine, ensuring continuity and preventing interruption of the debugging process due to path switching by the mode switching module.

[0043] In this embodiment of the application, if the first debugging mode is the external GPIO JTAG debugging mode, then the second debugging mode is the internal register simulated JTAG debugging mode; if the first debugging mode is the internal register simulated JTAG debugging mode, then the second debugging mode is the external GPIO JTAG debugging mode. In this embodiment of the application, no specific limitation is made.

[0044] In this embodiment, electrical signals are isolated between the two debugging paths during mode switching to prevent crosstalk between the two signals and interference with the debugging timing; at the same time, the TAP state machine context before switching is cached to save the debugging state in the debugging mode before switching, so as to achieve seamless recovery after switching back to the previous mode.

[0045] Step 102: Start the timing simulation module and output JTAG timing rules.

[0046] In this embodiment, a preferred implementation is to achieve JTAG timing output through software delay or timer. No specific limitations are imposed in this embodiment.

[0047] In practical applications, a preferred implementation is to use a timing simulation module to simulate timing generation in JTAG debugging mode using the control register. Specifically, the timing simulation module uses an on-chip general-purpose hardware timer to generate fixed-cycle interrupts. Within the interrupt service routine corresponding to the timer, the CPU periodically updates the signal bits in the first control register, sequentially generating simulated timing signals TCK, TMS, TRST, and TDI. Preferably, the operating frequency range of the simulated TCK clock can be 10kHz to 1MHz, and the timing accuracy can be guaranteed by the reference clock accuracy of the on-chip hardware timer.

[0048] Step 103: The CPU writes corresponding level bits to the TCK bit, TRST bit, TMS bit and TDI bit of the first control register in a time-division manner according to the timing rules to generate a simulated JTAG input timing signal. The timing signal is used to input the JTAG chain to drive the TAP state machine to complete the state transition.

[0049] Step 104: The JTAG chain writes the output TDO feedback level into the TDO bit of the second control register.

[0050] Step 105: The CPU reads the TDO bit of the second control register in a time-sharing manner to obtain the debug return data output by the JTAG chain.

[0051] The following explanation continues using the example of Control reg A being mapped to physical address 0x10 and Control reg B being mapped to physical address 0x20. The CPU performs the following operations based on the JTAG timing rules output by the timing simulation module; see [link to relevant documentation]. Figure 3 The image shown is a schematic diagram illustrating a simulation timing sequence according to an embodiment of this application: t1: Write 0x10 (First Control Register) b'10010 Binary: bit4 bit3 bit2 bit1 bit0 = 1 0 0 1 0, that is, SEL=1, TDI=0, TMS=0, TRST=1, TCK=0; Operation Explanation: Maintain internal analog JTAG debug mode; TDI is set low, TMS is low, TRST is pulled high to reset the JTAG link, TCK is kept low, and the system waits for the rising edge of the clock.

[0052] t2: write 0x10 b'11011 Binary: 1 1 0 1 1, that is, SEL=1, TDI=1, TMS=0, TRST=1, TCK=1; Operation Explanation: TCK is pulled high to generate a rising edge, latching the current TMS low level; TDI is set high to shift high-level serial data into the JTAG chain, and TRST keeps the reset valid.

[0053] t3: write 0x10 b'11010 Binary: 1 1 0 1 0, which means SEL=1, TDI=1, TMS=0, TRST=1, TCK=0; Operation Explanation: When TCK is pulled low, a complete JTAG clock cycle is completed; the levels of TDI, TMS, and TRST remain unchanged.

[0054] t4: write 0x10 b'11111 Binary: 1 1 1 1 1, that is, SEL=1, TDI=1, TMS=1, TRST=1, TCK=1; Operation Explanation: TMS high switches TAP state; TCK rises again, TDI goes high, and TRST remains reset.

[0055] t5: write 0x10 b'10110 Binary: 1 0 1 1 0, that is, SEL=1, TDI=0, TMS=1, TRST=1, TCK=0; Operation Explanation: When TCK is pulled low, TDI switches to a low level; TMS and TRST remain high to maintain reset and status control.

[0056] t6: write 0x10 b'11111 Binary: 1 1 1 1 1, that is, SEL=1, TDI=1, TMS=1, TRST=1, TCK=1; Operation explanation: Pulling TCK high again forms a rising edge, TDI returns to high level, and TMS and TRST remain at high level.

[0057] t7: write 0x10 b'10010 Binary: 1 0 0 1 0, that is, SEL=1, TDI=0, TMS=0, TRST=1, TCK=0; Operation Explanation: When TCK is pulled low, TMS is pulled low, TDI is set low, and TRST remains at the reset level, stabilizing the link state.

[0058] t8: read 0x20 (second control register) b'1 Operation explanation: Read the second control register TDO. The TDO output bit corresponding to this shift is high level 1.

[0059] t9: write 0x10 b'10011 Binary: 1 0 0 1 1, that is, SEL=1, TDI=0, TMS=0, TRST=1, TCK=1; Operation explanation: When TCK rises, TMS remains low and TDI remains low, continuing serial shift input.

[0060] t10: write 0x10 b'10010 Binary: 1 0 0 1 0, that is, SEL=1, TDI=0, TMS=0, TRST=1, TCK=0; Operation explanation: When TCK is pulled down to low level, the current clock cycle is completed, and the other control levels remain unchanged.

[0061] t11: read 0x20 b'0 Operation explanation: Read the second control register TDO. The current TDO feedback output is low level 0.

[0062] t12: write 0x10 b'10011 Binary: 1 0 0 1 1, that is, SEL=1, TDI=0, TMS=0, TRST=1, TCK=1; Operation Explanation: When TCK is pulled high again to generate a rising edge, the TMS level is latched to perform a serial shift.

[0063] t13: write 0x10 b'10010 Binary: 1 0 0 1 0, that is, SEL=1, TDI=0, TMS=0, TRST=1, TCK=0; Operation explanation: TCK is pulled low to end a single clock cycle, while the control signal remains unchanged.

[0064] t14: read 0x20 b'1 Explanation: Read the second control register TDO. The output bit of TDO is high level 1.

[0065] t15: write 0x10 b'10011 Binary: 1 0 0 1 1, that is, SEL=1, TDI=0, TMS=0, TRST=1, TCK=1; Operation explanation: On the rising edge of TCK, serial data is continuously shifted into the JTAG chain.

[0066] t16: write 0x10 b'10010 Binary: 1 0 0 1 0, that is, SEL=1, TDI=0, TMS=0, TRST=1, TCK=0; Operation explanation: Pulling TCK low completes a set of clock timing outputs.

[0067] t17: read 0x20 b'1 Operation Explanation: The second control register TDO is read for the last time in the entire timing sequence, and the output bit is high level 1.

[0068] In summary, the TDO read by the CPU is b'1011.

[0069] Furthermore, in this embodiment of the application, the JTAG timing rules output by the timing simulation module include the TCK clock duty cycle.

[0070] When the CPU writes corresponding level bits to the TCK, TRST, TMS, and TDI bits of the first control register in a time-division multiplexing manner based on the timing rules to generate a simulated JTAG input timing signal, the TCK clock duty cycle is the first duty cycle; when the CPU reads the TDO bit of the second control register in a time-division multiplexing manner to obtain the debug return data output by the JTAG chain, the TCK clock duty cycle is adjusted to the second duty cycle, wherein the first duty cycle is greater than the second duty cycle.

[0071] In one preferred embodiment of this application, the first duty cycle is 1 / 2 and the second duty cycle is 1 / 3.

[0072] In practical applications, in the JTAG debugging mode simulating internal registers, the TCK duty cycle can be adjusted via CPU software control. Specifically, the CPU updates the signal bits of the first control register in the interrupt service routine according to the timing: when performing a TDI write shift operation, the continuous write intervals of TCK high and low levels remain equal, forming a 1 / 2 duty cycle clock; when performing a TDO read operation, the CPU can extend the duration of the TCK low level through software strategies, adjusting TCK to a 1 / 3 duty cycle, and wait for the TDO level output by the JTAG scan chain to stabilize before reading the second control register to acquire the TDO bit, thus improving sampling reliability.

[0073] In this embodiment, the duty cycle of the TCK clock is adjusted from 1 / 2 to 1 / 3, which shortens the high-level sampling interval of TCK within a single TCK cycle and extends the low-level maintenance duration. After TDO is serially output by the JTAG chain, it has a longer level stability and transmission latching time during the TCK low-level phase, avoiding the TDO level from entering the sampling moment before the shift switching is stable. This significantly reduces the probability of TDO reading misjudgment and sampling error, and improves the accuracy of acquiring the feedback bits of the second control register TDO.

[0074] In this embodiment of the application, the chip to be debugged can configure the TCK, TRST, TMS, TDI and TDO debug pins of the external GPIO module as general GPIO pins in the JTAG debugging mode simulated by the internal register.

[0075] In other words, during JTAG debugging simulation using internal registers, the original dedicated JTAG debugging pins are reused as general-purpose GPIOs, freeing up pin resources, reducing chip packaging and circuit board design costs, and improving hardware pin reuse rate.

[0076] As can be seen from the above, in this embodiment of the application, the chip to be debugged also supports external GPIO JTAG debugging mode. Therefore, when the mode switching module determines that the SEL bit of the first control register changes from 1 to 0, it switches the debugging mode to external GPIO JTAG debugging mode, opens the debugging channel with the external GPIO module, and disconnects the debugging channel with the register mapping module and the timing simulation module. At this time, the JTAG timing is provided by the external JTAG debugger, and the timing simulation module is in a sleep state.

[0077] In this embodiment, the chip to be debugged has a built-in standard hardware TAP controller (Test Access Port Controller) and JTAG chain. The two debugging paths, internal register simulating JTAG debugging mode and external GPIO JTAG debugging mode, share the same TAP state machine and JTAG chain hardware resources. There is no need to configure separate TAP controllers and JTAG chains for the two debugging modes, which greatly reduces the chip hardware logic overhead. The mode switching module is only used to switch the input source of the full set of JTAG signals (TCK, TMS, TRST, TDI) to the TAP state machine. It does not change the hardware structure and working logic of the backend TAP controller and JTAG chain: When the SEL bit of the first control register is configured to 1, the signal input source is switched to the address of the first control register. The CPU generates the simulated TCK, TMS, TRST, and TDI timing signals through the first control register and sends them to the TAP state machine. When the SEL bit of the first control register is configured to 0, the signal input source is switched to the external GPIO pin. The external JTAG debugger inputs the standard JTAG timing signals through the external pin and sends them to the same TAP state machine. In both modes, the hardware behavior of the JTAG chain in performing shift, state transition, data latching, and TDO feedback output fully complies with the JTAG debugging standard, ensuring consistency between internal analog debugging and external hardware debugging behavior. The debugging instructions and data interaction logic are universal and without difference.

[0078] In practical applications, writing data to the SEL bit of the first control register sets the SEL bit to 0. Hardware triggers a switch to external GPIO JTAG debug mode, caches the current TAP state machine context, and connects the TCK, TRST, TMS, TDI, and TDO pins of the external GPIO module to the internal JTAG chain. Simultaneously, the timing simulation module shuts down, stopping the output of the analog clock timing. The external JTAG debugger inputs standard TCK, TRST, TMS, and TDI timing signals through the JTAG pins multiplexed from the chip's external GPIO. The internal JTAG link receives the control and timing signals input from the external pins to complete instruction shifting and data interaction. The TDO feedback signal generated by the shift is directly output to the JTAG debugger via the external GPIO pin. The JTAG debugger acquires the TDO serial bit stream to complete conventional JTAG debugging operations such as reading and writing to the chip and reading its status.

[0079] This application also provides a chip, for example, see [link to relevant documentation]. Figure 4 The diagram shown is a schematic of a chip structure according to an embodiment of this application; the chip includes: a mode switching module, a register mapping module connected to the mode switching module, and a timing simulation module connected to the register mapping module, wherein the register mapping module integrates a first control register and a second control register, the first control register is configured with a test clock TCK bit, a test reset TRST bit, a test mode selection TMS bit, and a test data input TDI bit, and the second control register is configured with a test data output TDO bit; The mode switching module is used to receive a mode selection instruction and switch the debugging mode to the internal register simulated JTAG debugging mode. In the internal register simulated JTAG debugging mode, the TCK, TRST, TMS, and TDI signals corresponding to JTAG debugging are mapped to the TCK bit, TRST bit, TMS bit, and TDI bit of the first control register, respectively, and the TDO signal corresponding to JTAG debugging is mapped to the TDO bit of the second control register. The timing simulation module is used to output JTAG timing rules. Based on the timing rules, the CPU writes corresponding level bits to the TCK bit, TRST bit, TMS bit, and TDI bit of the first control register in a time-division multiplexing manner to generate simulated JTAG input timing signals. The timing signals are used to input the JTAG chain to drive the TAP state machine to complete state transitions. The JTAG chain writes the output TDO feedback level into the TDO bit of the second control register. The CPU is also used to time-division multiplex the TDO bit of the second control register to obtain the debug return data output by the JTAG chain.

[0080] In this embodiment of the application, the first control register is further configured with a mode selection SEL bit, and the chip to be debugged also supports external GPIO JTAG debugging mode; the chip to be debugged also includes an external GPIO module connected to the mode switching module, and the external GPIO module integrates TCK, TRST, TMS, TDI and TDO debugging pins for connecting to an external JTAG debugger. The mode switching module is specifically used to switch the debug mode to the internal register simulation JTAG debug mode when it is determined that the SEL bit of the first control register changes from 0 to 1, open the debug channel with the register mapping module and the timing simulation module, and disconnect the debug channel with the external GPIO module. The mode switching module is specifically used to switch the debug mode to the external GPIO JTAG debug mode when it is determined that the SEL bit of the first control register changes from 1 to 0, to open the debug channel with the external GPIO module, and to disconnect the debug channel with the register mapping module and the timing simulation module.

[0081] In this embodiment of the application, the JTAG timing rules output by the timing simulation module include the TCK clock duty cycle; When writing corresponding level bits to the TCK, TRST, TMS, and TDI bits of the first control register in a time-division multiplexing manner based on the timing rules to generate a simulated JTAG input timing signal, the TCK clock duty cycle is the first duty cycle; when the CPU reads the TDO bit of the second control register in a time-division multiplexing manner to obtain the debug return data output by the JTAG chain, the TCK clock duty cycle is adjusted to the second duty cycle, wherein the first duty cycle is greater than the second duty cycle. Preferably, the first duty cycle is 1 / 2 and the second duty cycle is 1 / 3.

[0082] In this embodiment of the application, while switching the first debugging mode to the second debugging mode, the mode switching module is also used to cache the current running state of the TAP state machine in the first debugging mode; when switching the second debugging mode to the first debugging mode, the mode switching module is also used to restore the running state of the TAP state machine based on the cached current running state of the TAP state machine in the first debugging mode.

[0083] In this embodiment of the application, the chip to be debugged can configure the TCK, TRST, TMS, TDI and TDO debug pins of the external GPIO module as general GPIO pins in the JTAG debugging mode simulated by the internal register.

[0084] In this embodiment of the application, the first control register is a 32-bit or 64-bit register, wherein the lower 5 bits of the first control register are configured as TCK bit, TRST bit, TMS bit, TDI bit and SEL bit, and the remaining bits are reserved bits; The second control register is a 32-bit or 64-bit register, wherein the lowest bit of the second control register is configured as the TDO bit, and the remaining bits are reserved bits.

[0085] The specific implementation process of the functions and roles of each module in the chip is detailed in the corresponding steps of the above method, and will not be repeated here.

[0086] For the chip embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The chip embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of the solution in this specification according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0087] The foregoing has described exemplary embodiments of this specification. It should be understood that in some cases, the modules described in this specification may be divided in a manner different from that in the embodiments, and the described actions or steps may be performed in a different order than that in the embodiments, while still achieving the desired result. Furthermore, the processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0088] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of protection of this specification.

Claims

1. A JTAG debugging method, characterized in that, The method is applied to a chip under test, which includes a mode switching module, a register mapping module, and a timing simulation module. The register mapping module integrates a first control register and a second control register. The first control register is configured with a test clock (TCK) bit, a test reset (TRST) bit, a test mode selection (TMS) bit, and a test data input (TDI) bit. The second control register is configured with a test data output (TDO) bit. The method includes: The mode switching module receives a mode selection instruction and switches the debugging mode to the internal register simulated JTAG debugging mode. In the internal register simulated JTAG debugging mode, the TCK, TRST, TMS, and TDI signals corresponding to JTAG debugging are mapped to the TCK bit, TRST bit, TMS bit, and TDI bit of the first control register, respectively, and the TDO signal corresponding to JTAG debugging is mapped to the TDO bit of the second control register. The timing simulation module is started and outputs JTAG timing rules; The CPU writes corresponding level bits to the TCK bit, TRST bit, TMS bit and TDI bit of the first control register in a time-division manner according to the timing rules, generating a simulated JTAG input timing signal. The timing signal is used to input the JTAG chain to drive the test access port TAP state machine to complete the state transition. The JTAG chain writes the output TDO feedback level into the TDO bit of the second control register; The CPU reads the TDO bit of the second control register in a time-sharing manner to obtain the debug return data output by the JTAG chain.

2. The method according to claim 1, characterized in that, The first control register is also configured with a mode selection SEL bit, and the chip under test also supports external GPIO JTAG debugging mode; the chip under test also includes an external GPIO module, which integrates TCK, TRST, TMS, TDI and TDO debugging pins for connecting to an external JTAG debugger. When the mode switching module determines that the SEL bit of the first control register changes from 0 to 1, it switches the debugging mode to the internal register simulation JTAG debugging mode, opens the debugging channel with the register mapping module and the timing simulation module, and disconnects the debugging channel with the external GPIO module. When the mode switching module determines that the SEL bit of the first control register changes from 1 to 0, it switches the debug mode to the external GPIO JTAG debug mode, opens the debug channel with the external GPIO module, and disconnects the debug channel with the register mapping module and the timing simulation module.

3. The method according to claim 1, characterized in that, The JTAG timing rules output by the timing simulation module include the TCK clock duty cycle; When writing corresponding level bits to the TCK, TRST, TMS, and TDI bits of the first control register in a time-division multiplexing manner based on the timing rules to generate a simulated JTAG input timing signal, the TCK clock duty cycle is the first duty cycle; when the CPU reads the TDO bit of the second control register in a time-division multiplexing manner to obtain the debug return data output by the JTAG chain, the TCK clock duty cycle is adjusted to the second duty cycle, wherein the first duty cycle is greater than the second duty cycle.

4. The method according to claim 3, characterized in that, The first duty cycle is 1 / 2, and the second duty cycle is 1 / 3.

5. The method according to any one of claims 1 to 4, characterized in that, While switching from the first debugging mode to the second debugging mode, the mode switching module caches the current running state of the TAP state machine in the first debugging mode; when switching from the second debugging mode to the first debugging mode, the mode switching module restores the running state of the TAP state machine based on the cached current running state of the TAP state machine in the first debugging mode.

6. The method according to claim 2, characterized in that, In the JTAG debugging mode simulated by the internal register, the TCK, TRST, TMS, TDI, and TDO debugging pins of the external GPIO module can be configured as general-purpose GPIO pins.

7. The method according to claim 1, characterized in that, The first control register is a 32-bit or 64-bit register, wherein the lower 5 bits of the first control register are configured as TCK bit, TRST bit, TMS bit, TDI bit and SEL bit, and the remaining bits are reserved bits; The second control register is a 32-bit or 64-bit register, wherein the lowest bit of the second control register is configured as the TDO bit, and the remaining bits are reserved bits.

8. A chip, characterized in that, The chip includes: a mode switching module, a register mapping module connected to the mode switching module, and a timing simulation module connected to the register mapping module. The register mapping module integrates a first control register and a second control register. The first control register is configured with a test clock TCK bit, a test reset TRST bit, a test mode selection TMS bit, and a test data input TDI bit. The second control register is configured with a test data output TDO bit. The mode switching module is used to receive a mode selection instruction and switch the debugging mode to the internal register simulated JTAG debugging mode. In the internal register simulated JTAG debugging mode, the TCK, TRST, TMS, and TDI signals corresponding to JTAG debugging are respectively mapped to the TCK bit, TRST bit, TMS bit, and TDI bit of the first control register, and the TDO signal corresponding to JTAG debugging is mapped to the TDO bit of the second control register. The timing simulation module is used to output JTAG timing rules. Based on the timing rules, the CPU writes corresponding level bits to the TCK bit, TRST bit, TMS bit, and TDI bit of the first control register in a time-division multiplexing manner to generate simulated JTAG input timing signals. The timing signals are used to input the JTAG chain to drive the TAP state machine to complete state transitions. The JTAG chain writes the output TDO feedback level into the TDO bit of the second control register. The CPU is also used to time-division multiplex the TDO bit of the second control register to obtain the debug return data output by the JTAG chain.

9. The chip according to claim 8, characterized in that, The first control register is also configured with a mode selection SEL bit, and the chip also supports external GPIO JTAG debug mode; the chip also includes an external GPIO module connected to the mode switching module, and the external GPIO module integrates TCK, TRST, TMS, TDI and TDO debug pins for connecting to an external JTAG debugger; The mode switching module is specifically used to switch the debug mode to the internal register simulation JTAG debug mode when it is determined that the SEL bit of the first control register changes from 0 to 1, open the debug channel with the register mapping module and the timing simulation module, and disconnect the debug channel with the external GPIO module. The mode switching module is specifically used to switch the debug mode to the external GPIO JTAG debug mode when it is determined that the SEL bit of the first control register changes from 1 to 0, to open the debug channel with the external GPIO module, and to disconnect the debug channel with the register mapping module and the timing simulation module.

10. The chip according to claim 8 or 9, characterized in that, While switching from the first debugging mode to the second debugging mode, the mode switching module is also used to cache the current running state of the TAP state machine in the first debugging mode; when switching from the second debugging mode to the first debugging mode, the mode switching module is also used to restore the running state of the TAP state machine based on the cached current running state of the TAP state machine in the first debugging mode.

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