A parallel task adaptive scheduling system for high-density chip cluster programming

Abstract

The application relates to the technical field of semiconductor chip programming and automatic testing, and discloses a parallel task adaptive scheduling system for high-density chip cluster programming, which comprises an upper computer node and a programmable gate array connected through a communication bus. The upper computer node abstracts the chips to be programmed into a finite state machine with a characteristic resource request vector, and uses a multi-dimensional resource token bucket to perform admission control on concurrent state transition requests to intercept overload instructions. For the instructions passing the control, the system combines the prime number solution of channel binding to issue a delay time for phase error correction, so that the instruction issuing time of multiple channels is discretely distributed, thereby suppressing the power surge caused by physical level synchronous flip. The application effectively avoids the risk of high-concurrency hardware power consumption exceeding the limit, and improves the transmission efficiency of the communication bus without interfering with the instruction timing.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip programming and automated testing technology, specifically to a parallel task adaptive scheduling system for high-density chip cluster programming. Background Technology

[0002] In the integrated circuit manufacturing and packaging testing stages, automated programming equipment is typically used to cluster and concurrently program large quantities of chips to improve production efficiency. With the increasing density of physical slots on a single board, the power supply and communication bandwidth requirements for chips performing erase, program, and verification operations are significantly increased. In particular, when non-volatile memory media undergo erase and write operations, the activation of the internal charge pump generates high transient drive currents, and the transitions in the underlying physical states directly correspond to significant changes in power consumption.

[0003] In existing parallel programming scheduling schemes, systems often employ static concurrency thresholds or simple linear polling mechanisms for task dispatch. Due to a lack of dynamic awareness of microscopic physical loads, when the host computer simultaneously sends erase / write commands to multiple physical channels, multiple underlying devices will simultaneously perform high-power level switching actions within the same time slice. This can lead to transient overcurrents and power surges in the system's main power supply, easily triggering hardware overcurrent protection or causing device damage. To mitigate the risk of power overload, some existing alternatives forcibly insert fixed protection delays into the command sequence. However, the chip programming process involves not only timing control but also the transmission and verification of a large amount of firmware data. Forcibly inserting static delays disrupts the continuity of data transmission, resulting in significant bus idle periods. Simultaneously, status polling commands and large amounts of firmware data crowd the backbone communication bus transmission channel. Without effective time slot utilization mechanisms, simply delaying to avoid these delays not only wastes bus bandwidth but also exacerbates communication congestion and scheduling timeouts. Existing technologies struggle to achieve a dynamic balance between mitigating power consumption peaks caused by multi-channel concurrency and improving bus bandwidth utilization, thus limiting the execution efficiency and stability of high-density chip cluster programming devices. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a parallel task adaptive scheduling system for high-density chip cluster programming, thus solving the problems.

[0005] The first aspect of the present invention provides a parallel task adaptive scheduling system for high-density chip cluster programming, including a host computer node and a programmable gate array (PGA). The host computer node and the PGA are connected via a communication bus, and the PGA is connected to multiple chips to be programmed in physical slots via an end-point bus. The host computer node includes a scheduling module and a token module.

[0006] The scheduling module abstracts the chip to be programmed into a finite state machine configured with a feature resource request vector and obtains state transition requests; the token module constructs a multi-dimensional resource token bucket, performs admission adjudication based on the feature resource request vector and the remaining capacity of the multi-dimensional resource token bucket, assigns the adjudicated instructions to the execution subset and deducts the corresponding capacity; the scheduling module calculates the phase shift delay time for the instructions in the execution subset and dispatches instructions to the programmable gate array accordingly; the programmable gate array controls the chip to be programmed to perform physical operations and report hardware state update messages; the scheduling module parses the hardware state update messages to advance the logical pointer of the finite state machine; the token module performs capacity reclamation of the multi-dimensional resource token bucket.

[0007] In a preferred embodiment of the present invention, the feature resource request vector is a two-dimensional array variable containing nominal power consumption weight and nominal communication bandwidth weight; the multi-dimensional resource token bucket contains a transient power consumption safety capacity limit parameter and a maximum concurrent throughput bandwidth parameter; the token module sets the initial value of the real-time remaining capacity of the multi-dimensional resource token bucket to the transient power consumption safety capacity limit parameter and the maximum concurrent throughput bandwidth parameter.

[0008] Furthermore, the host computer node also includes a derivative monitoring module; the derivative monitoring module maintains a time sampling window within the system, extracts the capacity change of the multidimensional resource token bucket, and calculates the transient resource consumption discrete derivative; the derivative monitoring module compares the transient resource consumption discrete derivative with a safety judgment threshold, and calculates the reference clock expansion coefficient of the current scheduling cycle in conjunction with the preset minimum instruction parsing delay, tuning gain coefficient, and maximum allowable delay limit.

[0009] Furthermore, the scheduling module retrieves the dedicated prime number statically bound to the corresponding physical slot, multiplies the dedicated prime number with the reference clock extension coefficient, and performs modulo-limiting processing in conjunction with the global effective waiting window limit to generate an independent discrete phase misalignment instruction delivery delay time. When the delay times calculated by multiple physical slots fall within the same hardware minimum timing resolution range, or the time interval between adjacent instruction delivery is less than the minimum protection interval, the scheduling module performs a secondary offset on the subsequent channels according to the channel order to generate the actual delivery delay time after collision resolution.

[0010] Furthermore, the host computer node also includes a gap injection module; the gap injection module reads the remaining countdown time of each instruction to be issued that is in a delayed waiting state in the timed transmission queue, and selects the minimum value among them to determine the idle time gap length of the communication bus; the gap injection module traverses the physical slot set, addresses the chip whose current state machine pointer is in the comparison and verification state to establish it as the target data injection node, and performs micro data slice injection to the target data injection node within the idle time gap length.

[0011] Furthermore, the gap injection module obtains the fixed time loss required for the communication bus to initiate a discontinuous data burst transmission and marks it as a protocol overhead constant; the gap injection module determines whether the length of the idle time gap is sufficient to cover the sum of the protocol overhead constant and the minimum net payload transmission time threshold; if the determination is not correct, the gap injection module abandons this idle time gap.

[0012] Furthermore, the gap injection module subtracts the protocol overhead constant from the idle time gap length, and deducts the bus arbitration protection time and the timed transmission queue wake-up protection time to obtain the dynamic net payload time gap; the gap injection module, together with the physical transmission rate of the communication bus, the upper limit of the data buffer depth of the target channel, the bus transmission efficiency conversion factor, and the length of the remaining verification data that the target chip has not yet sent, calculates and generates the upper limit of the maximum data slice length together with the dynamic net payload time gap.

[0013] Furthermore, the gap injection module generates micro data slices by truncating them according to the maximum data slice length limit, and constructs a chained access descriptor in main memory that includes the base address of the slice data source, the base address of the target buffer on the programmable gate array side, and the transmission length; the gap injection module submits the chained access descriptor to the underlying system bus control terminal, wakes up the access controller in the programmable gate array, and temporarily occupies the communication bus to transmit the micro data slices before the phase delay waiting time expires.

[0014] Furthermore, the programmable gate array is equipped with a state machine array; the state machine array monitors the physical pin levels, status registers, and feedback flags on each end bus, and generates the hardware status update message after confirming the status change; the scheduling module configures an independent operation timeout timer for the channel performing physical operations, and the timer starts from the actual completion time of the instruction transmission; if the hardware status update message is not received within the timeout threshold, the scheduling module advances the corresponding chip logic pointer to the fault termination state and triggers the resource forced reclamation process.

[0015] Furthermore, the token module applies a mutex lock to the multidimensional resource token bucket, extracts the feature resource request vector of the corresponding logical state node, performs minimum value clamping protection in combination with the preset global limit capacity parameter, restores the real-time remaining capacity of the multidimensional resource token bucket through reverse accumulation operation, and then releases the mutex lock.

[0016] A second aspect of the present invention provides an adaptive scheduling method for parallel tasks in high-density chip cluster programming, applied to the aforementioned adaptive scheduling system for parallel tasks in high-density chip cluster programming, the method comprising:

[0017] The chip to be programmed is abstracted as a finite state machine configured with characteristic resource request vectors, the state transition requests are obtained, and the remaining capacity of the multidimensional resource token bucket is initialized.

[0018] Based on the characteristic resource request vector and the remaining capacity of the multidimensional resource token bucket, an admission decision is made, and the instruction is assigned to the execution subset and the corresponding capacity is deducted.

[0019] The error phase delay time is calculated for the instructions within the execution subset, and instructions are dispatched accordingly to control the chip to be programmed to perform physical operations.

[0020] The system receives a hardware status update message reported after the physical operation is completed, parses the message to advance the logical pointer of the finite state machine, and performs capacity reclamation of the multidimensional resource token bucket.

[0021] This invention provides an adaptive scheduling system for parallel tasks in high-density chip cluster programming. It has the following advantages:

[0022] 1. This invention abstracts the chip's physical operation process into a finite state machine with characteristic resource request vectors, and combines it with a multi-dimensional resource token bucket to perform admission adjudication. This mechanism transforms the underlying physical limitations of power consumption and bandwidth into logical quotas at the software level, assesses the system's real-time remaining capacity before issuing concurrent instructions, thereby avoiding transient power consumption exceeding limits and power surge problems caused by multiple physical channels simultaneously performing high-load operations.

[0023] 2. This invention introduces a phase-shift delay calculation mechanism based on channel-specific prime numbers and the discrete derivatives of system transient resource consumption, generating independent delivery delay times for instructions that pass the admission decision. This scheduling method ensures that the actual time of instruction reception in each physical slot is discretely distributed on the microscopic time axis, avoiding multiple chips synchronously performing physical level flips within the same time slice, reducing the transient peak current of the system's main power supply, and improving the stability of the underlying hardware operation.

[0024] 3. This invention constructs a micro-data slice gap injection mechanism to extract idle time slots on the communication bus during the instruction phase delay waiting phase. After deducting a fixed protocol overhead constant and confirming the validity of the remaining net payload time slots, the system calculates and generates slice data of the corresponding length for transmission. This design utilizes the bus idle period generated by phase delay scheduling to preload verification data without interfering with the normal instruction scheduling timing, thereby improving the actual transmission efficiency of the backbone communication bus. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the topology and module connection relationship of a high-density cluster programming and scheduling system provided in an embodiment of the present invention;

[0026] Figure 2 A flowchart of a high-density cluster programming and scheduling method provided in an embodiment of the present invention;

[0027] Figure 3 This is a system hardware model and underlying physical resource initialization flowchart provided in an embodiment of the present invention;

[0028] Figure 4 This is a flowchart of an active state transition admission evaluation based on a multi-dimensional token, provided in an embodiment of the present invention.

[0029] Figure 5 A flowchart of the timing and control logic for dynamic surge prevention phase misalignment scheduling based on derivatives provided in an embodiment of the present invention;

[0030] Figure 6 A flowchart of gap microdata slice injection based on overhead threshold provided in an embodiment of the present invention;

[0031] Figure 7 A flowchart of the underlying physical state closed-loop feedback and resource lifecycle recycling provided in an embodiment of the present invention;

[0032] Figure 8 This is a timing diagram of the transient resource consumption discrete derivative response and phase delay distribution provided in an embodiment of the present invention;

[0033] Figure 9 This is a comparison curve of the transient total current response of the power supply network with that of the traditional scheduling mechanism, provided in an embodiment of the present invention;

[0034] Figure 10 A comparison diagram of the timing distribution of communication bus occupancy provided by the gap micro-data slice injection mechanism in an embodiment of the present invention.

[0035] Among them, 100 is the high-density cluster programming and scheduling system; 110 is the host computer node; 111 is the scheduling module; 112 is the token module; 113 is the derivative monitoring module; 114 is the gap injection module; 120 is the programmable gate array; 121 is the access controller; 122 is the state machine array; 130 is the communication bus; 140 is the end bus; and 150 is the physical slot. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] See attached document Figure 1 This invention provides a parallel task adaptive scheduling system for high-density chip cluster programming. The high-density cluster programming scheduling system includes a host computer node 110, a programmable gate array 120, and a communication bus 130 connecting the host computer node 110 and the programmable gate array 120.

[0038] The output side of the programmable gate array 120 is provided with several end buses 140. Each end bus 140 is connected to a corresponding physical slot 150 according to its spatial position in the board structure, thereby forming a communication topology with hierarchical isolation between the backbone bus and the end buses between the communication bus 130 and each physical slot 150.

[0039] In the data transmission direction, the communication bus 130 is used to carry the multiplexed data stream and control command stream issued by the host computer node 110. After receiving the multiplexed data stream and control command stream, the programmable gate array 120 parses the corresponding data or command and routes it to the corresponding end bus 140 according to the address information of the target physical slot 150.

[0040] Because each end bus 140 has an independent pin fan-out path and electrical drive circuit, the electrical influence between different physical slots 150 when performing low-level communication actions such as level pull-down, level toggle, and clock synchronization is limited to a preset allowable range, thereby reducing the risk of false triggering or communication abnormalities caused by inter-channel crosstalk. The effective communication bandwidth of the communication bus 130 is configured to be greater than the sum of the bandwidths required by each end bus 140 to transmit the basic command stream.

[0041] The host computer node 110 is equipped with a scheduling module 111, a token module 112, a derivative monitoring module 113, and a gap injection module 114 in its memory space.

[0042] The scheduling module 111 is used to periodically acquire the operating status of each physical slot 150 and maintain the global state machine network corresponding to each physical slot 150. The token module 112 is communicatively connected to the scheduling module 111 and is used to store the real-time remaining capacity vector of the system's global physical resources. When it receives a state transition request for a single physical slot 150, it performs resource condition determination and quota pre-deduction processing.

[0043] The derivative monitoring module 113 is used to sample the capacity change in the token module 112 along the time axis, calculate the discrete derivative value to characterize the density of transient power consumption requests in the system, and determine the surge protection delay coefficient based on the discrete derivative value. The gap injection module 114 is used to slice, encapsulate, and inject the required verification data stream of the chip in the verification-related state according to the bus idle period formed by the surge protection delay coefficient.

[0044] The programmable gate array 120 includes an access controller 121 and a state machine array 122 in its logic resources. The access controller 121 parses the data slice descriptors issued by the host computer node 110 and controls the segmented data to be transmitted in bursts via the communication bus 130. The state machine array 122 includes multiple lower-level driver units corresponding to the number of end buses 140; each lower-level driver unit generates physical timing signals on the corresponding end bus 140 in parallel according to the register data mapped by the access controller 121.

[0045] See attached document Figure 2 , Figure 2 The flowchart of a high-density cluster programming and scheduling method according to an embodiment of the present invention is shown. This method can be applied to the aforementioned high-density cluster programming and scheduling system and includes the following steps.

[0046] S10: Obtain and initialize system hardware physical resource parameters, establish a mapping relationship between physical slots and global coprime sequences; construct a multi-dimensional physical resource token bucket based on the hardware physical resource parameters, and define chip programming state machine nodes and the feature resource request vectors corresponding to each state machine node.

[0047] S20: Asynchronously poll the execution status of each physical channel to identify chips that meet the state transition readiness conditions; extract the corresponding feature resource request vector according to the target state to be transitioned, and perform an atomic condition comparison between the feature resource request vector and the real-time remaining capacity in the multi-dimensional physical resource token bucket; pre-deduct resource weights for chips that meet the admission conditions, and assign them to the execution subset of the current scheduling cycle.

[0048] S30: Sample the capacity change of physical resource tokens within a preset time window, calculate the discrete derivative representing the resource consumption rate; dynamically tune the reference clock extension coefficient based on the offset between the discrete derivative and a preset security threshold; and calculate the independent discrete phase-out instruction issuance delay time of each chip in the execution subset in combination with the coprime sequence corresponding to the physical slot, and issue the corresponding instruction in a phase-out manner.

[0049] S40: During the physical idle time gap formed by the phase delay of the communication bus 130, the chip in the verification state is addressed; the length of the physical idle time gap is determined by an effective overhead threshold, and when the injection condition is met, the upper limit of the micro data slice size is calculated in combination with the current available bandwidth and the underlying buffer capacity; then a chained access descriptor is generated, and the slice data is injected into the physical idle time gap without affecting the timely issuance of subsequent high-power instructions, and the communication bus 130 is temporarily occupied to transmit to the underlying buffer.

[0050] S50: Receive the hardware completion status message uploaded by the programmable gate array 120 via the communication bus 130; trigger the capacity reclamation of the multi-dimensional physical resource token bucket according to the hardware completion status message, and advance the state machine pointer of the corresponding chip; repeat the above scheduling process before all chips corresponding to each physical slot 150 enter the preset termination state or fault termination state.

[0051] See attached document Figure 3 In step S10, the process of initializing hardware physical resource parameters, mapping global coprime sequences, constructing multidimensional physical resource token buckets, and defining chip programming state machine nodes and feature resource request vectors may include the following sub-steps.

[0052] S101 identifies the underlying hardware topology, determines the valid physical channels, and statically binds coprime multipliers to each physical slot.

[0053] After the system powers on and resets, the host computer node 110 initiates a topology probe request to the programmable gate array 120 via the communication bus 130. The state machine array 122 in the programmable gate array 120 responds to the topology probe request, returning the number and corresponding numbers of the end buses 140 with complete electrical connections on the current hardware board. The scheduling module 111 establishes a set of valid physical slots based on the returned results. ,in, This represents the total number of channels currently available in the system, with each element representing a physical slot of 150.

[0054] After establishing the channel set, the scheduling module 111 creates a static mapping table in memory for the set. Each physical slot Bind to an independent prime number variable The scheduling module 111 extracts the previous channels sequentially according to the ascending order of their hardware addresses. A set of prime numbers is generated by consecutive prime numbers. A one-to-one key-value pair relationship is established. In a preferred embodiment, when the total number of available channels N in the system is greater than a preset concurrency threshold, the scheduling module 111 can divide all physical slots into several independent groups. Within each group, the first M identical consecutive prime numbers are mapped sequentially, and independent time slice rotation offsets are configured between each group for reuse and isolation. This avoids the prime multiplier allocated to the end channel being too large, which would cause the subsequently calculated discrete delay time to seriously exceed the limit. The implementation of mapping a global coprime sequence provides the cardinality support for the discrete time axis operation of subsequent surge prevention and phase misalignment scheduling, ensuring that each physical slot presents an aperiodic discrete distribution state when the time parameter expands.

[0055] S102, obtain the underlying communication protocol overhead parameters, and set the pre-addressing and communication establishment time constants.

[0056] The gap injection module 114 reads the system's underlying driver interface or, based on the pre-completed transmission delay calibration results, determines the fixed time loss required for the communication bus 130 to initiate a discontinuous data transmission, and calibrates this fixed time loss as a protocol overhead constant. .

[0057] When the communication bus 130 performs discrete data burst transmissions, it typically involves fixed time consumption for transaction layer packetization, address addressing, bus arbitration, and handshake confirmation via the programmable gate array 120 side registers. Protocol overhead constants. This constant is used to quantify the total fixed time consumption mentioned above. The physical significance of obtaining this constant is to provide a step threshold on the micro-time axis for the subsequent micro-data slice injection process, so as to avoid the abnormal system resource inversion caused by the time consumption of the payload to be transmitted being less than the communication establishment time.

[0058] S103, construct a multi-dimensional physical resource token bucket, and initialize the system's global transient resource security limit and remaining capacity.

[0059] Token module 112 allocates a specific memory region to construct a global physical resource control model and generates a multi-dimensional resource token bucket. The multidimensional resource token bucket contains two core capacity parameters, which are recorded as follows: .

[0060] Since electrical parameters at the hardware level cannot be directly used in the multi-dimensional numerical comparison calculations of the software scheduling state machine, the system introduces a token bucket mechanism to abstract objective physical constraints into logical quotas within the software. Specifically, the system reads the extreme short-circuit current threshold or overcurrent protection trigger current parameters of the external power supply module, calculates the system's global extreme physical power consumption in combination with the hardware power supply voltage, and converts it into a transient power consumption safety capacity upper limit parameter according to a preset dimensionless normalization scaling factor. .

[0061] This parameter represents the logical mapping of the maximum total power consumption of physical state transitions that the hardware device can simultaneously handle within a single microsecond-level time slice. The system reads the controller hardware parameters of the communication bus 130, extracts its maximum concurrent throughput bandwidth parameter at the physical layer, and calibrates it after the same normalization process. In the initial state of the system, the token module 112 will display the real-time remaining capacity vector of the multi-dimensional resource token bucket. The initial value is set to .

[0062] In this way, the system converts the underlying physical constraints such as power supply capacity and bus throughput capacity into logical capacity that can participate in software scheduling and judgment, providing a unified resource measurement basis for subsequent multi-channel state transition admission.

[0063] S104, establish the single-channel chip state machine structure and configure the state dictionary and feature resource request vector.

[0064] The scheduling module 111 abstracts the chips to be programmed in each physical slot 150 into a finite state machine. The set of state nodes S of this finite state machine can be represented as: ; in, This indicates an idle waiting state. This represents the physical sector erase status. This represents the firmware data programming write status. This indicates the comparison and verification status. This indicates the terminal's completion status. This indicates a fault termination status and is used to identify abnormal channels that no longer participate in subsequent normal programming scheduling due to underlying communication abnormalities, physical operation timeouts, verification failures exceeding limits, or chip damage.

[0065] The underlying timing control involved in reading and writing chip storage media can be configured according to the specific chip's datasheet, memory interface specifications, and corresponding electrical parameters, which will not be described in detail in this embodiment.

[0066] To facilitate unified scheduling of resource usage under different physical states, the scheduling module 111 establishes a state dictionary in memory and configures corresponding feature resource request vectors for each non-termination state based on pre-imported chip specification electrical characteristics, production line calibration data, or previous energy consumption sampling results. The feature resource request vector is a two-dimensional array variable containing nominal power consumption weights and nominal communication bandwidth weights: ; in, Used to quantify the state of a single chip upon entering its state. The weight of the local transient power consumption request caused by the start of the internal charge pump or the violent switching of the pin level is obtained by mapping the maximum instantaneous current consumption in this state to the above normalized scaling factor. Used to quantify the state. The chip's exclusive request weight for the data throughput of the communication bus 130.

[0067] Since erase operations are typically accompanied by high-voltage injection and do not require intensive data interaction, the dictionary will... The dictionary is configured with a combination of high-power weights and low-bandwidth weights; since the verification operation does not require changing the physical lattice charge but relies on a large amount of data comparison, the dictionary will... The configuration combines low-power weights with high-bandwidth weights. The design of the feature resource request vector provides structured data support for the multi-dimensional resource token module to implement atomic admission decisions.

[0068] See attached document Figure 4 In step S20, the process of asynchronously polling the execution status of each physical channel, capturing the ready chip for state transition, determining the admission of execution resources, and generating an execution subset may include the following sub-steps.

[0069] S201 executes asynchronous state polling, reads the underlying channel state, and generates a subset of state transition requests.

[0070] The scheduling module 111 sends status polling messages to the programmable gate array 120 via the communication bus 130 according to a preset polling period. This polling process does not depend on the actual time spent on the current physical operation of a single chip and is used to periodically collect the execution status of each physical channel. The hardware completion status message uploaded by the programmable gate array 120 when it detects the completion of a physical operation is used to immediately trigger subsequent resource reclamation and status advancement. When both the polling result and the hardware completion status message exist, the scheduling module 111 prioritizes the hardware completion status message to perform status advancement and uses the polling result for anomaly verification, packet loss compensation, or retransmission judgment.

[0071] In one implementation, the preset polling period is greater than the time required for the communication bus 130 to transmit one basic status message, but less than the execution time of the shortest physical operation in the chip state machine. This avoids status capture lag while reducing the bandwidth usage of the communication bus 130 by invalid polling.

[0072] After receiving the status polling message, the programmable gate array 120 summarizes the physical pin status, status register value, and execution completion flag bit fed back by each lower-level driver unit in the state machine array 122, and encapsulates them into a status matrix, which is then uploaded to the host computer node 110. If the data packet corresponding to the status matrix times out, is lost, or has a verification error, the scheduling module 111 can initiate a retransmission request in the next polling cycle to maintain the integrity of the status acquisition results.

[0073] The scheduling module 111 parses the uploaded status matrix and retrieves the set of valid physical slots in the system. The scheduling module 111 identifies chips that have completed their hardware operations and are waiting to proceed to the next logical operation. For any given chip, if its underlying hardware feedback indicates that the current stage of the task has been completed, the scheduling module 111 recognizes it as a ready chip on the verge of a state transition. The scheduling module 111 then aggregates all the ready chips detected within the current polling cycle to form a request subset. ,in .

[0074] For the reading and writing of the underlying hardware flag register and the hardware handshake feedback logic, those skilled in the art can refer to the digital integrated circuit communication interface specification for configuration. The interaction of its underlying registers is a well-known technology in this field and will not be described in detail here.

[0075] S202, extract the target state resource request vector for the chip in the request subset, and perform multidimensional token admission determination.

[0076] For a subset of requests Any chip in The scheduling module 111 determines the next target state to be advanced based on the state machine transition path in the single-channel chip logic running node architecture. Subsequently, the scheduling module 111 extracts the corresponding state from the state dictionary in memory. The feature resource request vector can be represented as: ; in, Indicates chip Enter the next state of the target Required nominal power consumption weight Indicates chip Enter the next state of the target The required nominal communication bandwidth weight.

[0077] To avoid resource overselling or data re-entry anomalies under concurrent conditions, an exclusive access mechanism is typically required during the judgment process. When the token module 112 receives a comparison request from the scheduling module 111, it applies a software mutex lock to the data structure of the multi-dimensional resource token bucket B. In practice, if the host computer node 110 is running a real-time operating system, this atomicity protection can also be achieved by temporarily disabling system global interrupts or invoking a hardware spinlock. This operation restricts the process from retrieving the current token capacity to completing the judgment calculation; other threads within the system cannot tamper with the capacity data, thus ensuring atomicity of the comparison.

[0078] Token module 112 extracts the real-time remaining capacity vector of the multidimensional resource token bucket at time t. With chips The feature resource request vector is used to perform two-dimensional logical judgment. The judgment condition function is as follows: ; in, For the admission determination results, Indicates time The system's remaining transient power consumption safety capacity limit. Indicates time The remaining backbone bus throughput bandwidth capacity limit of the system. For chips The nominal power consumption weight required for the next state of the target The nominal communication bandwidth weight required for the next state of the target.

[0079] S203, perform resource pre-deduction based on the admission determination result, and form the execution subset of the current scheduling cycle.

[0080] The token module 112 performs branching processing based on the results of the atomicity condition comparison described above. In principle, the system verifies the power supply margin and bus margin separately, aiming to limit the concurrency scale from the physical source.

[0081] If the judgment result is Condition A value of 1 indicates that the current system has remaining quota to support chips. Safely enter the next state of the target This avoids triggering physical power overload or bus congestion. At this time, the token module 112 performs real-time subtraction in the multi-dimensional resource token bucket to complete the pre-deduction of resource quotas. The capacity update calculation formula is as follows: ; ; After completing the pre-deduction calculation, the token module 112 releases the mutex lock. The scheduling module 111 then places the chip... From the request subset Remove from the middle and store the execution subset that has been approved to enter the actual state of progress. By pre-deducting resources before physical instructions are actually issued, the system can lock in the power consumption and communication capacity required for subsequent state transitions in advance, reducing the risk of power overload or bus congestion caused by resource contention under concurrent scheduling.

[0082] In one implementation, the token module 112 also establishes a resource occupancy record for the chip CI when performing resource pre-deduction. This resource occupancy record includes at least the physical slot number, target status, pre-deducted power consumption weight, pre-deducted bandwidth weight, reserved occupancy flag, and actual issuance flag. For chips already added to the execution subset... Tasks that are written to the scheduled sending queue but have not yet been actually issued physical commands have their resources in a reserved state. If the task is canceled before actual issuance due to channel failure, scheduling reset, data anomaly, or external interruption, the token module 112 performs a reserved resource rollback based on the resource occupancy record, returning the corresponding power consumption weight and bandwidth weight to the multi-dimensional resource token bucket B. For tasks that have already been issued, their resource occupancy continues until the underlying physical operation is completed or the timeout failure is confirmed before being reclaimed.

[0083] If the judgment result is Condition A value of 0 indicates that the current system's physical resources are insufficient to support the chip's transition. The token module 112 directly releases the mutex and refuses to allocate resources. The scheduling module 111 then... Maintain the current idle waiting state and do not add it to the execution subset. The chip will re-participate in the admission evaluation in the next clock polling cycle.

[0084] To prevent chips with high resource request weights from being denied admission for extended periods, thus creating a scheduling dead zone, the scheduling module 111 can be configured with a wait counter. When a chip is denied admission multiple times consecutively, the system can temporarily block other low-weight requests to prioritize resource allocation for the suspended chip. The system iterates through and processes a subset of requests. All elements within, until a full execution subset is generated for the current scheduling period. .

[0085] See attached document Figure 5 In step S30, the process of calculating the discrete derivative of the physical resource token consumption rate within a preset time window, tuning the reference clock extension coefficient based on the discrete derivative, and generating the phase-out delay in combination with the coprime sequence may include the following sub-steps.

[0086] S301, set the time sampling window, extract the capacity change of physical resource tokens, and calculate the discrete derivative of transient resource consumption.

[0087] The derivative monitoring module 113 maintains a sliding time sampling window within the system, and the window time length is denoted as... In practice, the lower limit of the time sampling window length is typically greater than the inherent time of a single state poll on the communication bus 130, while the upper limit is less than the discharge drop response time of the external power supply capacitor of the underlying chip. Those skilled in the art can calculate the critical time required for the voltage to drop to the safe threshold using the capacitor discharge formula, based on the capacitance value and maximum transient discharge current of the system motherboard decoupling capacitor, and use this critical time as... The basis for its value.

[0088] The derivative monitoring module 113 periodically retrieves the multi-dimensional resource token bucket from the token module 112 at the current time based on the time sampling window. Transient power consumption safety capacity limit and at the previous sampling time Capacity record value The derivative monitoring module 113 performs discrete derivative calculations, using the following formula: ; in, This represents the discrete derivative of transient resource consumption. The deduction of power consumption quota in the multidimensional resource token bucket corresponds to the reservation or actual issuance of high-power state transition tasks, and its numerical change can reflect the degree of concentrated request for transient power consumption resources by the system within the current time window.

[0089] Discrete derivative of transient resource consumption In a physical sense, this derivative characterizes the density of transient power consumption requests in the current system, and its value is positively correlated with the current ramp-up slope experienced by the underlying power supply network. By calculating this derivative, the system transforms the invisible hardware-layer concurrent surges into a continuous computational metric that can be quantified by software programs.

[0090] S302, calculate the reference clock extension coefficient for the current scheduling cycle based on the discrete derivative value and the safety judgment threshold.

[0091] The derivative monitoring module 113 obtains the discrete derivative of transient resource consumption. Then, dynamic tuning of the reference clock extension factor is performed. The system internally presets four basic control parameters: minimum instruction resolution delay. Tuning gain coefficient Safety judgment threshold and maximum allowable latency limit .

[0092] in, This indicates the inherent time delay required from the time the communication bus 130 initiates transmission until the programmable gate array 120 completes message parsing; It can be set according to the load transient recovery capability of the power supply module's voltage regulator or the power network design margin; K is used to limit the maximum value of the phase delay to avoid excessive delay causing bus communication timeouts or hardware watchdog resets; K is used to limit the impact of the discrete derivative exceeding the safety threshold on the delay spread.

[0093] In one implementation, the tuning gain coefficient According to Perform initial configuration, where, The derivative of the maximum transient resource consumption allowed by the system design.

[0094] The derivative monitoring module 113 calculates the reference clock spread factor at the current time. The calculation formula is as follows: ; when Not exceeding the safety threshold hour, When the value is 0, the system maintains the minimum instruction parsing latency. ;when Exceed hour, It increases as the excess portion increases, thus widening the interval between subsequent instruction issuances when concurrent transition requests are concentrated. Through right Upper limit clamping can prevent excessive delays caused by abnormal sampling or extreme load conditions.

[0095] S303, by combining the coprime sequence bound to the physical slot with the reference clock expansion coefficient, generates the independent discrete phase misalignment command issuance delay time for each channel.

[0096] For the execution subset generated in the aforementioned steps The scheduling module 111 extracts the operation tasks that are about to issue high-power instructions and calculates the delay offset for time axis phase misalignment. For the execution subset... Each instruction chip inside The scheduling module 111 retrieves the dedicated prime number that was statically bound to it during the initialization phase. .

[0097] Scheduling module 111 will allocate prime numbers The expansion factor of the reference clock calculated at the current time Multiplication is performed, and modulo-limiting is applied in conjunction with the hardware effective wait window limit to generate microsecond-level independent discrete phase-shifting instruction issuance delay times. The calculation formula is as follows: ; in, This is a preset global effective wait window limit. When the delay times calculated by two or more channels fall within the same hardware minimum timing resolution range, or the planned time interval between adjacent high-power instructions is less than the preset minimum protection interval... At that time, the scheduling module 111 performs a secondary offset on the subsequent channels according to the channel number, waiting counter, or prime number weight, so that the actual time interval between the issuance of adjacent high-power instructions is not less than [a certain value]. .

[0098] Optional supplementary formulas are as follows: ; in, This refers to the actual delivery delay time after collision resolution. The scheduling module 111 determines the non-negative integer offset factor based on the channel sorting. To avoid bus timing anomalies caused by continuous backward offsets under extreme concurrency conditions, the scheduling module 111 adjusts the actual transmission delay time after collision resolution. Perform upper limit verification. If determined... Exceeding the preset maximum allowable latency limit Or the global effective wait window limit The scheduling module 111 intercepts the current instruction issued by the channel and forcibly postpones the corresponding state transition request to the available time slot of the next scheduling cycle to ensure that the underlying hardware watchdog is not reset.

[0099] S304 issues a delay time to postpone the high-power startup instruction according to the phase misalignment instruction, and performs surge protection phase misalignment scheduling.

[0100] Delay time for issuing independent discrete phase-shifting commands for each channel Subsequently, the host computer node 110 does not directly trigger the underlying hardware actions. The scheduling module 111 configures the high-power startup instruction of the target chip in the timed transmission queue and starts the process based on... The countdown interception.

[0101] During the countdown waiting period, the host computer node 110 does not dispatch the instruction to the corresponding channel of the programmable gate array 120 via the communication bus 130. After the time expires, the scheduling module 111 will release the interception and issue a command through the communication bus 130 to execute the physical state transition.

[0102] By proactively introducing a targeted delay mechanism, the scheduling system performs deterministic discrete planning of instruction dispatch times at the source. This control process, which forcibly disperses time, helps to mitigate sudden current peaks that would otherwise be concentrated and triggered within the same microsecond range due to polling mechanisms. This reduces the risk of bus power supply drops or system crashes caused by sudden local large current surges.

[0103] See attached document Figure 6 In step S40, the process of addressing and verifying the status chip, determining whether the time slot has effective data carrying capacity, calculating the micro data slice size, and injecting the slice data into the underlying buffer during the physical idle time slot formed by the phase delay of the communication bus 130 may include the following sub-steps.

[0104] S401 determines the idle time gap of the communication bus caused by the phase misalignment delay and addresses the chip in the comparison and verification state.

[0105] The gap injection module 114 monitors the timed transmission queue in the scheduling module 111. When the system performs surge protection phase reversal scheduling, some high-power start instructions are temporarily suspended before the corresponding delay time expires, thus forming an available idle time gap on the micro time axis of the communication bus 130.

[0106] When multiple channels are simultaneously in a delayed waiting state, the gap injection module 114 reads the remaining countdown time of each instruction to be issued in the timed transmission queue, and selects the minimum value as the current bus idle time gap length available for data injection. Determined by using the minimum remaining countdown time. This can prevent micro-data slice transmission from exceeding the limit and occupying the planned issuance time of subsequent high-power instructions.

[0107] In determining Then, the gap injection module 114 traverses the set of valid physical slots C to find the state machine pointer that is currently in the comparison and verification state. The chip. Located in Chips in this state typically do not need to perform high-power memory media erase / write operations, but they do need to receive or read firmware reference data for comparison, making them suitable as target nodes for gap data injection.

[0108] For those in the comparison and verification state The chip, during the state admission phase, has already followed the feature resource request vector. Bandwidth weight in A corresponding communication bandwidth is reserved. When performing micro-data slice injection, the gap injection module 114 uses this reserved bandwidth. Current idle time slot of communication bus 130 and the target buffer capacity of the 120-side programmable gate array. As a common constraint, the data verification injection process is still subject to the bandwidth control constraints of the multidimensional resource token bucket.

[0109] The gap injection module 114 establishes the addressed comparison and verification status chip as the target data injection node and uses the bus idle time forcibly generated by the surge protection mechanism to preload the underlying data.

[0110] S402 determines the validity of idle time slots based on protocol overhead constants.

[0111] When the communication bus 130 initiates a discontinuous data burst transmission, it typically needs to go through processes such as target addressing, bus arbitration, transaction encapsulation, and handshaking with the programmable gate array 120 side registers. The fixed time corresponding to the above processes is determined by the protocol overhead constant calibrated during the initialization phase. express.

[0112] Gap injection module 114 according to protocol overhead constant and minimum net payload transmission time threshold For the current idle time slot length Filtering and judgment are performed. The minimum net payload transmission time threshold is... The physical clock cycle required to transmit a minimum hardware bus width data block can be determined based on the communication bus 130.

[0113] In one implementation, the step filter function It can be represented as: ; like =0 indicates that the current idle time slot is insufficient to cover the protocol establishment overhead and the minimum effective payload transmission time; forcibly initiating slice injection at this time may encroach on the subsequent normal instruction cycle, so the gap injection module 114 abandons this idle time slot.

[0114] like =1 indicates that the current idle time slot has effective data carrying capacity, and the gap injection module 114 continues to perform net load time slot calculation and micro data slice size calculation.

[0115] S403, after removing protocol overhead and protection margin, calculates the upper limit of micro data slice size.

[0116] After passing the step threshold filtering judgment, the gap injection module 114 performs the time axis stripping calculation. The gap injection module 114 calculates the total idle time gap length. Subtract the fixed protocol overhead constant from the middle And further deduct the bus arbitration protection time. and the timed send queue wake-up protection time Obtain the actual dynamic net load time slots that can be used to carry valid verification data. The calculation formula is: ; in, This is used to cover the arbitration protection time required for the communication bus 130 to switch from verification data transmission to high-power instruction issuance tasks. Used to cover the wake-up protection time required for timed sending queue triggering, message assembly, and access controller 121 response.

[0117] The gap injection module 114 reads the currently configured physical transmission rate of the communication bus 130 through the underlying driver interface. And read the upper limit of the data buffer FIFO depth allocated to the target channel on the 120-side programmable gate array. Combined with dynamic net load time slots The gap injection module 114 calculates the maximum data slice length limit that the system can support for transmission within the current idle time window. The calculation formula is as follows: ; in, This is a bus transmission efficiency conversion factor used to compensate for level setup errors and hardware clock jitter losses on the physical link; This refers to the length of the remaining verification data that the target comparison and verification status chip has not yet issued. (Introduction) It can prevent the generation of invalid slices that exceed the remaining data length during the transmission of the last slice.

[0118] Those skilled in the art can, based on the physical characteristics of the bus hardware and the impedance matching of long-distance transmission, [determine / convert the following]. The value range is set between 0.85 and 0.95. (Rounding function) This function is used to round down the calculated theoretical length to an absolute number of bytes conforming to the bus hardware alignment specification. A minimum value function is introduced. With buffer limit The comparison clamping is designed to prevent memory overflow and data truncation caused by a single slice load exceeding the physical boundaries of the underlying hardware cache when the network is extremely idle or the bus bandwidth is extremely high. The above calculation process enables accurate and secure data capacity measurement for irregular time fragments at the microsecond level.

[0119] S404 constructs a chained access descriptor and completes slice data transfer within the idle time slot.

[0120] For the complete firmware reference data stream required by the target comparison and verification status chip, the gap injection module 114 calculates the maximum data slice length limit. The data is truncated at its boundaries and divided into blocks to generate micro-data slices that adapt to the current available micro-time slots.

[0121] To avoid the significant interrupt overhead caused by direct read / write operations to registers by the central processing unit, the gap injection module 114 establishes a data structure in main memory, constructing a structure that includes the base address of the slice data source, the base address of the target buffer on the programmable gate array 120 side, and the transmission length. The chained access descriptor. In one optional implementation, the chained access descriptor includes at least the source data base address, the destination buffer base address, the transfer length, the destination physical slot number, the destination end bus number, the check status flag, the next descriptor pointer, the descriptor valid bit, and the transfer completion interrupt flag.

[0122] The next descriptor pointer is used to organize multiple micro-data slices into a descriptor linked list according to the order of their distribution; the descriptor validity bit is used by the access controller 121 to determine whether the current descriptor meets the execution conditions; the transmission completion interrupt flag bit is used to notify the gap injection module 114 to update the remaining data length after the slice transmission is completed. .

[0123] When the system direct memory access controller is available, the gap injection module 114 submits the chained access descriptor to the underlying system bus control terminal and wakes up the access controller 121 in the programmable gate array 120. After parsing the chained access descriptor, the access controller 121 temporarily occupies the communication bus 130 before the current surge protection delay waiting window expires, and transmits the corresponding micro data slice to the target buffer area on the programmable gate array 120 side.

[0124] When a timing conflict occurs between the gap injection task and the high-power instruction delivery task in the timed transmission queue, the high-power instruction delivery task has a higher arbitration priority. In this case, the gap injection task is suspended, truncated, or postponed to the next idle time slot to ensure that the high-power instruction delivery time determined by the surge protection phase misalignment scheduling is not disrupted.

[0125] After the sliced ​​data enters the target buffer on the programmable gate array 120, the state machine array 122 maps the buffered data to the corresponding end bus 140 according to the target physical slot number and the target end bus number, so that the chip in the comparison and verification state can perform subsequent data comparison.

[0126] The memory mapping method for chained access descriptors, the register configuration of the direct memory access controller, and the bus arbitration rules can be implemented according to the DMA protocol and register mapping relationship supported by the specific hardware platform. In this embodiment, through the above processing, without affecting the established surge protection phase reversal scheduling, the idle time of the communication bus generated by the phase reversal delay is used for verification data preloading, thereby improving the effective utilization rate of the backbone communication bus 130.

[0127] See attached document Figure 7 In this embodiment, the process of capturing the physical operation completion signal of the underlying chip, performing reverse accumulation and recycling of resource quotas, advancing the target chip state machine logic pointer and performing system global convergence determination in step S50 may include the following sub-steps.

[0128] S501 receives the underlying hardware completion status message to confirm that the single-stage physical operation of the target chip is complete.

[0129] The state machine array 122 inside the programmable gate array 120 continuously monitors the physical pin levels, status registers, and feedback flags on each end bus 140. When a chip in a physical slot 150 completes the current single-stage physical operation, the status indicator pin, status register, or end bus feedback flag corresponding to that chip changes state. After sampling and confirming this state change, the state machine array 122 generates a hardware state update message corresponding to the target channel and uploads it to the host computer node 110 via the communication bus 130. This hardware state update message serves as the underlying hardware completion state message that triggers resource reclamation and state advancement.

[0130] The scheduling module 111 in the host computer node 110 parses the hardware status update message, obtains the channel number that initiated the status update and the corresponding operation completion identifier, and confirms that the current physical operation of the chip in that channel has been completed.

[0131] To prevent the underlying chip from occupying scheduling resources for an extended period due to physical media damage, communication anomalies, or hardware feedback link failures, the scheduling module 111 configures an independent operation timeout timer for each channel performing a physical operation. This operation timeout timer starts counting from the moment the physical operation instruction corresponding to the target channel is actually sent and completed, rather than from the moment of admission determination or resource pre-deduction, in order to avoid the surge protection phase delay stage being mistakenly included in the actual physical operation time of the chip.

[0132] In one optional implementation, the timeout threshold of the operation timeout timer is determined based on the maximum execution time of this type of physical operation specified in the target chip datasheet, and multiplied by a preset redundancy tolerance coefficient; the redundancy tolerance coefficient can be configured to be 1.2 to 1.5.

[0133] If no state update signal is received within the preset timeout threshold, the scheduling module 111 will forcibly mark the chip as faulty and advance its state machine pointer to the specified state. This will halt subsequent communication and trigger a forced resource reclamation process for the channel. The forced resource reclamation process includes releasing reserved resources that have been pre-deducted but not yet actually issued for the channel, as well as releasing occupied resources that have been actually executed but failed to return a completion signal due to timeout.

[0134] S502, extract the feature resource request weights and perform capacity reclamation of the multidimensional physical resource token bucket.

[0135] In the confirmation channel The internal chip has completed the current state normally. After a physical operation or a timeout fault occurs on the channel, the system releases the logical resources occupied during that phase. The scheduling module 111 extracts the state from the state dictionary in system memory. Corresponding feature resource request vector .

[0136] After receiving the recycling request from the scheduling module 111, the token module 112 applies a mutex lock to the data structure of the multi-dimensional resource token bucket B to prevent data contention during concurrent recycling across multiple channels. The token module 112 performs a reverse accumulation addition operation to restore the resource level; the calculation formula is as follows: ; ; in, and This represents the updated real-time remaining capacity. and These are the global limit capacity parameters calibrated during system initialization. In some specific embodiments, The value can be calculated by those skilled in the art based on the maximum output power of the motherboard power supply module design minus the static noise power consumption of the system to maintain basic operation; The value of can be determined based on the maximum physical bandwidth defined by the communication bus protocol. The above addition operation incorporates a minimum value function. Upper limit clamping protection is implemented. This clamping operation prevents the remaining system capacity after reclamation from overflowing the physical safety boundary in the event of abnormal retries or timing misalignments in software logic. After completing the addition operation, the token module 112 releases the mutex lock, completing the closed loop of the resource lifecycle at the logical level.

[0137] S503 advances the logic pointer of the single-node state machine to establish a state baseline for the next round of scheduling polling.

[0138] After resource recovery is complete, the scheduling module 111 targets the chips that have successfully completed physical operations. The scheduling module 111 updates the status monitoring table of the chip in the host computer's memory. The scheduling module 111 then moves the logical pointer corresponding to the chip from its current state... Proceed to the next logical state node .

[0139] If it is determined at this point that the chip has completed all the predetermined erase, write, and verification processes, its logic pointer will be advanced to the terminal completion state. For chips that trigger forced resource reclamation due to timeout, communication anomalies, or verification failure exceeding limits, the scheduling module 111 will not advance them to the next normal logical state, but will instead advance their logical pointer to the fault termination state. The jump of the state logic pointer provides a data benchmark for the subsequent extraction of target state feature vectors and the generation of request subsets.

[0140] S504 performs a global convergence determination of the execution system, maintains the cyclic operation of the scheduling system, or triggers a termination event.

[0141] The scheduling module 111 periodically traverses the state machine pointer records of all channels in the system's valid physical slot set C. The system determines whether the logical pointers of all mapped channels have reached the terminal completion state. Or it may be marked as a fault termination state. .

[0142] If the determination result is yes, it indicates that all concurrent operation tasks currently carried by the system have converged and completed. The host computer node 110 stops status polling, releases system memory, and sends a global task completion signal. If the determination result is no, it indicates that there are still chips in the system that are in the execution or suspension waiting stage, and the scheduling module 111 maintains the status polling mechanism. The execution flow jumps back to the active state transition admission evaluation step, and the system enters a new round of dynamic scheduling and time-division multiplexing loop until all physical slots have completed state convergence.

[0143] To more clearly illustrate the collaborative working principle of the surge prevention phase-shifting scheduling and gap injection mechanism in this invention, and to verify its technical effect in a real industrial environment, the following uses a high-density programming system containing 16 concurrent physical channels (N=16) for specific numerical deduction and experimental comparison analysis.

[0144] 1. Initialization and parameter setting (S10 stage):

[0145] After the system is powered on, a channel set is established. And bind the first 16 consecutive prime numbers in sequence. Set the transient power consumption safety capacity limit for the multi-dimensional resource token bucket. =100 normalized units, for example, representing a system's maximum safe supply of 10A transient current, where 1 unit = 0.1A). Define the characteristic resource request vector:

[0146] Firmware programming write status ( High-power requests, weight =30; Low bandwidth request, weight =10 MB / s.

[0147] Comparison verification status ( Low-power requests, weight =2; High bandwidth requests, weight =100MB / s.

[0148] 2. Discrete derivative triggering and phase-out delay calculation (S20-S30 stage):

[0149] Assuming at time The system is extremely idle; the real-time remaining power consumption capacity of the multi-dimensional resource token bucket is [data missing]. .

[0150] In the next sampling window Internal, physical slots The corresponding chip simultaneously meets the state transition conditions and requests to enter the high-power programming / writing state. ).

[0151] The token module atomically deducts resources: .

[0152] The derivative monitoring module calculates the discrete derivative of transient resource consumption: (unit Preset security threshold Since 9 > 5, the system determines that there is an extremely high risk of transient surge. The system's dynamic tuning reference clock spread factor (assuming minimum analytical delay) is used. (Gain coefficient K=1.5) .

[0153] By combining the prime numbers specific to each channel, the phase delay is calculated (with a global effective waiting window limit set). : aisle

[0154] aisle mod50

[0155] aisle

[0156] See attached document Figure 8 ,like Figure 8As shown, the broken line above visually illustrates the process of the step decrease in the remaining capacity of the multidimensional resource token, and the discrete derivative calculated from it. Exceeding the security threshold The trigger point. Combined with Figure 8 As shown in the timing diagram below, through the above dynamic calculation, the original polling mechanism, which tended to distribute the data at the same time, has been improved. The three high-power startup instructions, which occurred in rapid succession, were deterministically broken down into... , , The system executes at three discrete moments in a stepped manner. As a result, the system actively avoids concurrent surges, smoothing out the current step rate rise at its physical source.

[0157] 3. Interval injection during idle time slots (stage 540):

[0158] The channel that is executed first in the above queue Taking the waiting time as an example, the communication bus 130 forms a length of [missing information] on the microscopic time axis. The minimum idle time interval. At this time, the system addresses the channel. In comparison and verification state ( (This requires loading benchmark verification data.)

[0159] Set inherent protocol overhead Arbitration and wake-up protection time Calculate the actual dynamic net load time slot: Given the current physical transmission rate of the bus. MB / s, long-distance transmission efficiency conversion factor The system calculates the maximum micro-data slice size that can be injected without loss during this tiny idle time gap: =⌊3μs×100MB / s×0.9⌋=⌊270Bytes⌋=270 bytes.

[0160] The system then generates a 270-byte chained access descriptor, precisely "inserting" the verification data into it. During the waiting period. As time progresses to At the exact moment, the data injection operation was completed, the communication bus 130 seamlessly switched back, and data was transmitted to the channel on time. The originally planned high-power command was issued.

[0161] 4. Experimental verification and effect comparison:

[0162] To verify the actual performance of the above solution, a hardware testbed was built using a high-precision oscilloscope, logic analyzer, and bus protocol analysis platform. The scheduling mechanism of this invention (experimental group) was compared with the traditional polling concurrent scheduling mechanism (control group). The test conditions were as follows: on a 16-channel high-density programming hardware, a full-chip erase, firmware programming, and comparison verification process was simultaneously performed on 16 256MB high-capacity NOR Flash memory chips.

[0163] (1) Verification of the effect of transient surge current suppression in power supply network:

[0164] A precision current detection circuit is connected to the main power supply channel of the system to continuously collect the dynamic current response characteristics during the burning process.

[0165] See attached document Figure 9 , combined Figure 9 As can be seen from the control group curves, when concurrent large-area page programming is performed, the curve exhibits an extremely high and sharp pulse peak due to the simultaneous activation of the internal charge pumps in all 16 channels within a very short time. The measured instantaneous peak current surged to 14.2A, exceeding the 12A overcurrent protection threshold of the motherboard's DC-DC regulator module, directly causing a severe instantaneous voltage drop in the system.

[0166] In contrast, the curve in the embodiment of this invention exhibits a significant "peak shaving and valley filling" characteristic. Before the system triggers a high-power task, the scheduling system keenly detects the sharp increase in the discrete derivative and implements coprime phase-shifting delay intervention. For example... Figure 9 As shown, the ramp-up slope of the total system current is significantly smoothed, and the curve is transformed into multiple continuous wide pulses with gentle fluctuations. The highest peak current is strictly clamped at 7.8A (far below the hardware safety limit). Experiments show that this invention reduces the peak-to-peak value of the supply voltage ripple by approximately 65%, completely eliminating power supply interference and the risk of system crashes from adjacent chips on the same board.

[0167] (2) Verification of communication bus time slot utilization:

[0168] By capturing the transaction layer time slot allocation logs of the communication bus using a low-level protocol analyzer, the effective payload transmission density during the entire burning cycle can be analyzed.

[0169] See attached document Figure 10 ,like Figure 10 As shown in the timing distribution of the control group in the upper half, the traditional mechanism has a typical "intermittent" congestion problem. That is, the bus is busy when the command is issued, but during the time when the underlying chip takes several milliseconds to perform physical operations, the bus leaves a large blank area (idle waiting area). The measured average effective utilization rate of bus bandwidth is only 41%.

[0170] like Figure 10The timing distribution of this invention in the lower half shows that, thanks to the gap injection module's extreme extraction of the waiting time caused by phase misalignment delays and the fragmented idle time during chip execution, a large amount of verification data used for low-level comparison is sliced, packaged, and dynamically addressed and injected. These densely packed tiny rectangular blocks (corresponding to the aforementioned deduction) The payload slicing effectively fills the original communication gaps. Actual measurements show that the average bandwidth utilization of the communication bus of this invention jumps to 86%, exhibiting highly dense and continuous data flow scheduling characteristics.

[0171] Comprehensive performance statistics show that, under the same hardware and chip load, this invention achieves deep overlap between the data verification and comparison process and the chip physical solidification process on the macroscopic time axis. The average time to complete the entire 16-channel 256MB process is reduced from 45.2 seconds in the control group to 36.8 seconds in the invention group, resulting in an overall system production efficiency increase of approximately 18.6%. Experimental data fully demonstrates that this solution breaks through the performance bottleneck of concurrent communication systems while ensuring extremely high physical layer security.

[0172] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A parallel task adaptive scheduling system for high-density chip cluster programming, characterized in that, include: The host computer node and the programmable gate array are connected via a communication bus; The host computer node is equipped with a scheduling module and a token module; The programmable gate array is connected to the chip to be programmed in the physical slot via an end bus. The scheduling module abstracts the chip to be programmed into a finite state machine configured with a feature resource request vector, and obtains the state transition request. The token module constructs a multi-dimensional resource token bucket, performs admission adjudication based on the feature resource request vector and the remaining capacity of the multi-dimensional resource token bucket, assigns the instruction to the execution subset and deducts the corresponding capacity; The scheduling module calculates the misphase delivery delay time for the instructions within the execution subset and dispatches instructions to the programmable gate array according to this delay. The programmable gate array controls the chip to be programmed to perform physical operations and report hardware status update messages. The scheduling module parses the hardware state update message to advance the logical pointer of the finite state machine; the token module performs capacity reclamation of the multidimensional resource token bucket.

2. The parallel task adaptive scheduling system for high-density chip cluster programming according to claim 1, characterized in that: The feature resource request vector is a two-dimensional array variable containing nominal power consumption weights and nominal communication bandwidth weights; The multidimensional resource token bucket includes a transient power consumption safety capacity limit parameter and a maximum concurrent throughput bandwidth parameter; the token module sets the initial value of the real-time remaining capacity of the multidimensional resource token bucket to the transient power consumption safety capacity limit parameter and the maximum concurrent throughput bandwidth parameter.

3. The parallel task adaptive scheduling system for high-density chip cluster programming according to claim 1, characterized in that, The host computer node also includes a derivative monitoring module; The derivative monitoring module is used to maintain a time sampling window within the system and extract the capacity change of the multidimensional resource token bucket in order to calculate the discrete derivative of transient resource consumption. The derivative monitoring module is also used to compare the discrete derivative value of the transient resource consumption with the safety judgment threshold, and dynamically calculate the reference clock expansion coefficient of the current scheduling cycle in combination with the preset minimum instruction parsing delay, tuning gain coefficient and maximum allowable delay limit.

4. The parallel task adaptive scheduling system for high-density chip cluster programming according to claim 3, characterized in that, The scheduling module calculates the misphase delivery delay time for instructions within the execution subset, specifically including: The scheduling module retrieves the dedicated prime number statically bound to the corresponding physical slot, multiplies the dedicated prime number with the reference clock extension coefficient, and performs modulo-limiting processing in combination with the global effective waiting window limit to generate an independent discrete phase misalignment instruction issuance delay time. When the delay times calculated from multiple physical slots fall within the same hardware minimum timing resolution range, or when the time interval between the issuance of adjacent instructions is less than the minimum protection interval, the scheduling module performs a secondary offset on the subsequent channels according to the channel order to generate the actual issuance delay time after collision resolution.

5. The parallel task adaptive scheduling system for high-density chip cluster programming according to claim 1, characterized in that, The host computer node also includes a gap injection module; The gap injection module is used to read the remaining countdown time of each instruction to be issued that is in a delayed waiting state in the timed transmission queue, and select the minimum value among them to determine the idle time gap length of the communication bus. The gap injection module is also used to traverse the physical slot set, locate the chip whose current state machine pointer is in the comparison and verification state, establish it as the target data injection node, and perform micro data slice injection to the target data injection node within the length of the idle time gap.

6. The parallel task adaptive scheduling system for high-density chip cluster programming according to claim 5, characterized in that, The gap injection module performs a validity determination on the idle time gap before performing micro-data slice injection, specifically including: The fixed time loss required for the communication bus to initiate a non-continuous data burst transmission is obtained and calibrated as a protocol overhead constant. Determine whether the length of the idle time slot is sufficient to cover the sum of the protocol overhead constant and the minimum net payload transmission time threshold; if not, the gap injection module abandons the current idle time slot.

7. The parallel task adaptive scheduling system for high-density chip cluster programming according to claim 6, characterized in that, The gap injection module performs micro-data slice injection to the target data injection node, specifically including: Subtract the protocol overhead constant from the idle time slot length, and deduct the bus arbitration protection time and the timed send queue wake-up protection time to obtain the dynamic net payload time slot; The maximum data slice length upper limit is calculated by combining the physical transmission rate of the communication bus, the upper limit of the data buffer depth of the target channel, the bus transmission efficiency conversion factor, and the length of the remaining verification data that the target chip has not yet sent, together with the dynamic net load time slot.

8. The parallel task adaptive scheduling system for high-density chip cluster programming according to claim 7, characterized in that: The gap injection module generates micro data slices by truncating them according to the upper limit boundary of the maximum data slice length, and constructs a chained access descriptor in the main memory that includes the base address of the slice data source, the base address of the target buffer on the programmable gate array side, and the transmission length. The gap injection module submits the chained access descriptor to the underlying system bus control terminal, wakes up the access controller in the programmable gate array, and temporarily occupies the communication bus to transmit the micro data slice before the phase delay waiting time expires.

9. The parallel task adaptive scheduling system for high-density chip cluster programming according to claim 1, characterized in that, The programmable gate array contains a state machine array; The state machine array is used to monitor the physical pin levels, status registers and feedback flags on each end bus, and generates the hardware status update message after confirming the status change. The scheduling module configures an independent operation timeout timer for the channel that is performing physical operations. The timer starts from the moment the instruction is actually sent and completed. If the hardware status update message is not received within the timeout threshold, the scheduling module advances the corresponding chip logic pointer to the fault termination state and triggers the resource forced reclamation process.

10. The high-density chip cluster programming parallel task adaptive scheduling system according to claim 1, characterized in that, The token module performs capacity reclamation of the multi-dimensional resource token bucket, specifically including: The token module applies a mutex lock to the multidimensional resource token bucket, extracts the feature resource request vector of the corresponding logical state node, performs a minimum value clamping protection in combination with the preset global limit capacity parameter, restores the real-time remaining capacity of the multidimensional resource token bucket through reverse accumulation operation, and then releases the mutex lock.

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