Laser driver circuit, method, system and electronic device under modulation depth variation

Abstract

The application belongs to the technical field of laser radar, and discloses a laser driver circuit, method, system and electronic equipment under variable modulation depth. The circuit comprises a low-speed precision digital-to-analog converter for detecting a modulation depth mode and generating a corresponding analog setting signal; a high-speed digital-to-analog converter, an input end of which receives a full-range digital waveform code stream and dynamically configures a full-range output current according to the analog setting signal; and a transimpedance conversion circuit, a transimpedance resistance value of which is fixedly set and used for converting a modulation current signal into a voltage signal to drive a subsequent laser. When switching to a smaller modulation depth mode, the analog setting signal is reduced to reduce the full-range output current, and the high-speed digital-to-analog converter receives the full-range digital code stream. The application can reduce the driving amplitude, suppress the analog current noise of the voltage drop source, stabilize the quantization accuracy, eliminate the double penalty effect, and improve the beat signal quality under the small modulation depth mode.

Description

Technical Field

[0001] This application relates to the field of frequency modulated continuous wave lidar system technology, and more specifically, to a laser driving circuit, method, system, and electronic device with variable modulation depth. Background Technology

[0002] Frequency-modulated continuous wave (FM-CHW) lidar is a detection technology that uses linearly modulated laser signals to obtain target distance and velocity information by measuring the beat frequency of the echo signal and a local reference light. In an FM-CHW lidar system, the laser linewidth directly determines the system's coherence length and signal-to-noise ratio (SNR), making it one of the system's core performance indicators. With the rapid development of lidar technology, the market is placing higher demands on multi-scenario adaptability. For example, the same lidar system needs to support different detection ranges, including short-range high-resolution modes (e.g., 10 GHz modulation depth) and long-range modes (e.g., 15 GHz modulation depth). This variable modulation depth application places extremely stringent requirements on the noise performance of the laser drive circuitry.

[0003] Currently, existing frequency-modulated continuous-wave lidar systems typically employ a high-speed digital-to-analog converter (DAC) architecture with a fixed full-scale current to drive the laser. In this approach, the transimpedance of the current-to-voltage conversion circuit must be fixed in hardware design according to the limiting voltage swing required for the maximum modulation depth. However, when the system switches to a lower modulation depth mode, this traditional architecture faces a fundamental flaw. Since the transimpedance cannot dynamically change with the modulation depth, the system can only achieve a smaller current output by significantly reducing the digital code value input to the high-speed DAC. This approach leads to a decrease in the effective number of bits, resulting in severe code value waste and quantization noise degradation. Furthermore, the baseline current noise floor fails to decrease with the full-scale current, causing a sharp deterioration in the signal-to-noise ratio, creating a double penalty effect. This disconnect between static testing and practical applications results in dynamic noise being superimposed on the modulation signal, causing problems such as laser linewidth degradation and weakened beat frequency spikes, making it difficult to meet the requirements of high-precision detection in multiple scenarios. Summary of the Invention

[0004] This application provides a laser driving circuit, method, system, and electronic device for variable modulation depth, which is used to solve the noise degradation problem of the driving link in variable modulation depth applications and to achieve consistent optimization of system linewidth under different modulation depth modes.

[0005] This application provides a laser driving circuit with variable modulation depth, including a low-speed precision digital-to-analog converter (DAC), a high-speed DAC, and a transimpedance conversion circuit. The low-speed precision DAC generates a corresponding analog setting signal based on the currently set modulation depth detection mode. The high-speed DAC receives a full-scale digital waveform stream at its digital input terminal. The full-scale current adjustment pin of the high-speed DAC is connected to the output terminal of the low-speed precision DAC, dynamically configuring the full-scale output current of the high-speed DAC according to the analog setting signal. The input terminal of the transimpedance conversion circuit is connected to the current output terminal of the high-speed DAC, converting the modulation current signal output by the high-speed DAC into a voltage signal to drive the subsequent laser. The transimpedance value of the transimpedance conversion circuit is fixedly set according to the voltage swing corresponding to the maximum modulation depth supported by the system. When the system switches to a smaller modulation depth mode, the low-speed precision DAC reduces the analog setting signal output to the high-speed DAC, decreasing the amplitude of the full-scale output current, while the high-speed DAC maintains its operation of receiving the full-scale digital waveform stream.

[0006] Furthermore, the low-speed precision digital-to-analog converter includes an internal configuration register and a precision current source network. The internal configuration register receives modulation depth mode control commands issued by an external main control unit, and the precision current source network outputs a DC bias current with a preset amplitude as the analog setting signal according to the modulation depth mode control commands. The full-scale current adjustment pin of the high-speed digital-to-analog converter is connected in series with a first reference resistor R. The DC bias current flows through the first reference resistor R to establish a reference voltage Vref. The high-speed digital-to-analog converter internally includes a current mirror circuit. The current mirror circuit scales the source tail current of each internal current switching unit according to the reference voltage Vref, limiting the dynamic configuration range of the full-scale output current.

[0007] Furthermore, the current noise density (Inoise) at the output of the high-speed digital-to-analog converter (DAC) exhibits a physical square root positive correlation with the amplitude of the full-scale output current controlled by the reference voltage (Vref). When the system switches to the lower modulation depth mode, the low-speed precision DAC reduces the output DC bias current according to a system-set ratio, causing the established reference voltage (Vref) to decrease synchronously. This triggers the high-speed DAC to reduce the current noise density (Inoise) at the output source while simultaneously reducing the output full-scale output current. The transimpedance switching circuit employs a fixed passive network without analog RF switching devices, ensuring that the transimpedance value remains constant in both the lower and maximum modulation depth modes, thus cutting off the physical path for the switching impedance network to introduce additional switching distortion and thermal noise.

[0008] Furthermore, the laser driving circuit also includes a nonlinear predistortion compensation module. The signal output terminal of the nonlinear predistortion compensation module is connected to the digital input terminal of the high-speed digital-to-analog converter. The nonlinear predistortion compensation module uses digital predistortion model coefficients to perform predistortion correction on the initial swept frequency waveform digital sequence and generates the full-range digital waveform code stream input to the high-speed digital-to-analog converter.

[0009] Furthermore, the nonlinear predistortion compensation module is equipped with a coefficient lookup table and an interpolation unit. The coefficient lookup table stores reference digital predistortion model coefficients corresponding to multiple full-scale current discrete ranges. The interpolation unit obtains the current setting parameters of the low-speed precision digital-to-analog converter. When the current current setting parameters deviate from the multiple full-scale current discrete ranges, it uses the reference digital predistortion model coefficients of adjacent ranges to perform interpolation calculations, synchronously generating target digital predistortion model coefficients that match the current full-scale output current, thus compensating for frequency modulation nonlinearity physical errors under different drive current swings.

[0010] This application also provides a laser driving method under variable modulation depth, applied to a laser driving circuit under variable modulation depth, including acquiring the currently set detection modulation depth mode. A corresponding analog setting signal is generated by the low-speed precision digital-to-analog converter (DAC) according to the detection modulation depth mode. The analog setting signal is input to the full-scale current adjustment pin of the high-speed DAC to dynamically configure the full-scale output current of the high-speed DAC. A full-scale digital waveform stream is input to the digital input terminal of the high-speed DAC, and the high-speed DAC is controlled to output a modulation current signal. The modulation current signal is converted into a voltage signal by the transimpedance conversion circuit and used to drive the subsequent laser. The transimpedance value of the transimpedance conversion circuit is fixedly set according to the voltage swing corresponding to the maximum modulation depth supported by the system. When the system is detected to switch to a smaller modulation depth mode, the low-speed precision DAC is controlled to reduce the generated analog setting signal to decrease the amplitude of the full-scale output current, while the high-speed DAC is controlled to maintain the operation of receiving the full-scale digital waveform stream.

[0011] Further, the step of generating a corresponding analog setting signal by the low-speed precision digital-to-analog converter according to the detection modulation depth mode includes parsing the externally input mode switching command and extracting the target full-scale current value parameter corresponding to the current detection modulation depth mode. The corresponding low-speed digital control word parameter is determined by looking up the digital-to-analog conversion mapping lookup table pre-stored in the storage medium based on the target full-scale current value parameter. The low-speed digital control word parameter is written into the internal register of the low-speed precision digital-to-analog converter, triggering the built-in current source array of the low-speed precision digital-to-analog converter to output a DC setting voltage proportional to the target full-scale current value parameter as the analog setting signal.

[0012] Further, the step of inputting a full-range digital waveform stream to the digital input terminal of the high-speed digital-to-analog converter includes calling a nonlinear predistortion compensation module during the synchronization period of writing the low-speed digital control word parameters to obtain dynamic digital predistortion model coefficients corresponding to the low-speed digital control word parameters. An initial digital sequence of the set waveform is input to a polynomial predistortion filter, and amplitude pre-compensation and phase inverse offset operations are performed in conjunction with the obtained dynamic digital predistortion model coefficients to generate a target waveform sequence corrected by distortion compensation. The target waveform sequence is then pushed as the full-range digital waveform stream to the digital input terminal of the high-speed digital-to-analog converter, ensuring that the high-speed digital-to-analog converter maintains a full-range mapping state of the effective number of bits at each set full-range output current level.

[0013] This application also provides a lidar system, including a laser and a laser driving circuit under the variable modulation depth mode. The output terminal of the laser driving circuit under the variable modulation depth mode is connected to the laser and provides a modulation driving voltage signal under the variable modulation depth mode.

[0014] This application also provides an electronic device, including a memory and a processor. The memory stores computer-readable instructions, which, when read and executed by the processor, implement the laser driving method under variable modulation depth. Attached Figure Description

[0015] Figure 1 This is a block diagram of the logic structure of the laser driver circuit provided in the embodiments of this application.

[0016] Figure 2 This is a flowchart of a laser driving method provided in an embodiment of this application.

[0017] Figure 3 This is a system architecture block diagram provided in the embodiments of this application.

[0018] Figure 4This is a data interaction timing diagram provided in the embodiments of this application.

[0019] Figure 5 This is a signal processing data flow diagram provided in an embodiment of this application.

[0020] Figure 6 This is a schematic diagram of a high-speed digital-to-analog converter circuit provided in an embodiment of this application.

[0021] Figure 7 This is a circuit schematic diagram of a low-speed precision digital-to-analog converter provided in an embodiment of this application.

[0022] Figure 8 This is a system block diagram provided in the embodiments of this application.

[0023] In the diagram: 100 - Laser driver circuit with variable modulation depth, 101 - Low-speed precision digital-to-analog converter, 102 - High-speed digital-to-analog converter, 103 - Transimpedance conversion circuit, 104 - System main control microcontroller platform, 105 - Multi-track power supply network, 106 - Nonlinear predistortion compensation module, 300 - LiDAR system, 301 - Laser, 400 - Electronic equipment, 401 - Processor, 402 - Memory. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0025] In Example 1, a laser driving circuit with variable modulation depth is introduced.

[0026] like Figure 1 As shown, this application provides a laser driving circuit 100 with variable modulation depth, applied in a frequency-modulated continuous wave lidar system, to achieve precise driving of the laser at variable modulation depth and eliminate quantization and current noise degradation. The circuit mainly consists of a low-speed precision digital-to-analog converter 101, a high-speed digital-to-analog converter 102, a transimpedance converter circuit 103, a system main control microcontroller platform 104, a multi-track power supply network 105, and a nonlinear predistortion compensation module 106. The system main control microcontroller platform 104 connects the low-speed precision digital-to-analog converter 101 and the high-speed digital-to-analog converter 102 via a digital bus and is responsible for overall timing scheduling. The multi-track power supply network 105 provides low-noise DC power to all the above modules.

[0027] In terms of system architecture, the analog signal output terminal of the low-speed precision digital-to-analog converter 101 is connected to the full-scale current adjustment pin of the high-speed digital-to-analog converter 102, forming a cascaded control architecture. The low-speed precision digital-to-analog converter 101 receives configuration instructions from the system's main microcontroller platform 104 and generates a corresponding analog setting signal according to the currently set detection modulation depth mode. This analog setting signal remains constant within a single frequency modulation continuous wave sweep cycle (typically on the millisecond level), so its quantization error only manifests as a quasi-static DC bias and does not constitute dynamic AC noise superimposed on the modulation signal. By adopting a cascaded control architecture, the low-speed precision digital-to-analog converter 101 can dynamically set the full-scale output current of the high-speed digital-to-analog converter 102 from the outside. It should be noted that those skilled in the art can also use a dedicated power management chip with a high-precision programmable reference output to replace the low-speed precision digital-to-analog converter 101, as long as it can achieve the static precise bias adjustment function.

[0028] The high-speed digital-to-analog converter 102 receives a full-range digital waveform code stream from the digital baseband at its digital input terminal, and generates an analog modulated current signal at its output terminal. In terms of specific hardware selection, the high-speed digital-to-analog converter 102 uses a high-speed conversion chip with a resolution of 14-bit or 16-bit, such as the AD973x, AD9117, or AD9744 series. In a preferred embodiment, the AD9744ARU chip with a 14-bit resolution is used. The full-scale code value range of the high-speed digital-to-analog converter 102 is 0 to 16383. In any modulation depth mode, the high-speed digital-to-analog converter 102 always operates at near-full-scale output (100% utilization), completely unaffected by changes in the modulation depth. The current output terminal of the high-speed digital-to-analog converter 102 is connected to the subsequent transimpedance conversion circuit 103. The transimpedance conversion circuit 103 receives the modulated current signal and converts it into a voltage signal, which is ultimately used to drive the subsequent laser. The equivalent transimpedance value inside the transimpedance conversion circuit 103 is fixed according to the voltage swing corresponding to the maximum modulation depth supported by the system. It does not contain analog RF switching devices or relays, and maintains a stable conduction state of a completely passive structure.

[0029] During operation, the system supports multiple modulation depth modes for different application scenarios. For example, in long-distance mode, the system operates at its maximum modulation depth, with the modulation depth parameter set to 15 GHz. In this mode, the analog setting signal configured in the low-speed precision digital-to-analog converter 101 causes the full-scale current IFS of the high-speed digital-to-analog converter 102 to reach its maximum standard, set to 20 mA. The fixed impedance of the transimpedance conversion circuit 103, under these conditions, can provide the limiting voltage swing sufficient for 15 GHz modulation.

[0030] When the system switches to short-range high-resolution mode, the corresponding smaller modulation depth is set to 10GHz. At this time, the system's main control microcontroller platform 104 triggers underlying hardware adjustments. The low-speed precision digital-to-analog converter 101 reduces the analog setting signal it generates. Meanwhile, the full-scale current IFS of the high-speed digital-to-analog converter 102 is dynamically compressed, decreasing from 20mA to approximately 13.3mA. Simultaneously, the digital baseband continues to input a full-range digital waveform code stream covering the range of 0 to 16383 to the high-speed digital-to-analog converter 102, maintaining full-range full-code value drive.

[0031] The core innovation of this embodiment lies in its deep decoupling mechanism based on physical noise laws. Specifically, the system utilizes the square root proportionality between current noise density and full-scale current to achieve source noise reduction. Specifically, the system performs noise prediction and hardware adaptation based on proportional calculations, and the aforementioned physical relationship follows the following physical law formula: in∝IFS Wherein represents the current noise density at the output of the high-speed digital-to-analog converter, and IFS represents the full-scale output current set by the low-speed precision digital-to-analog converter.

[0032] According to this formula, in 15GHz mode, the system's current noise density baseline is 50pA / Hz. When switching to 10GHz mode and reducing the IFS to approximately 13.3mA, the current noise density automatically decreases to approximately 41pA / Hz based on the square root ratio attenuation (some actual measurements show it to be between 35pA / Hz and 41pA / Hz).

[0033] Based on the unchanged physical characteristics of the transimpedance switching circuit 103, the system's output voltage noise depends entirely on the source current noise. Specifically, the system's output voltage noise density is derived using the following formula: en=in×RT Where en represents the output voltage noise density driving the subsequent laser, in represents the current noise density at the output of the aforementioned converter, and RT represents the fixed transimpedance gain of the transimpedance conversion circuit.

[0034] Since RT is constant, when the source current noise density in drops from 50pA / Hz to about 41pA / Hz, the system's output voltage noise density decreases proportionally, resulting in a decrease in the fixed full-scale transimpedance current noise density of about 18%.

[0035] At the quantization noise level, the system maintains a full code value input, thus keeping the number of effective bits unchanged. Specifically, the quantization characteristics of the digital waveform by the system follow the following formula: Q∝1 / 2N Where Q represents the system quantization noise amplitude during the digital-to-analog conversion process, and N represents the number of effective input digits actually used by the high-speed digital-to-analog converter.

[0036] Since this application always maintains full-range digital code stream input, the effective number of bits N is stable at the nominal 14-bit precision level, eliminating the problem of deterioration of the effective number of bits (approximately reduced to 13.1 bits) caused by code value waste under smaller modulation depth, and the quantization noise Q reaches the theoretical minimum extreme value of this hardware platform.

[0037] To clearly demonstrate the data improvement brought about by the dynamic architecture, the measured comparison parameters of the system using the traditional fixed architecture and the dynamic architecture of this embodiment in the 10GHz short-range mode are shown in Table 1 below: Table 1 shows a performance comparison between the fixed full-scale architecture and the dynamic full-scale architecture.

[0038]

[0039] By introducing dynamic full-scale configuration and noise decoupling mechanism, this embodiment enables the system to reduce the signal drive amplitude while simultaneously proportionally reducing the analog current noise at the source and stabilizing the quantization accuracy, thereby eliminating the double penalty effect and improving the quality of beat frequency signal spikes in the small modulation depth mode.

[0040] Furthermore, to address the differences in laser thermal Joule effect caused by changes in full-scale current, this embodiment also incorporates a nonlinear predistortion compensation module 106 in conjunction with a dynamic configuration architecture. The signal output of the nonlinear predistortion compensation module 106 is connected to the digital input of the high-speed digital-to-analog converter 102. The system's main control microcontroller platform 104 transmits synchronization commands to the nonlinear predistortion compensation module 106 based on the configuration parameters of the currently invoked low-speed precision digital-to-analog converter 101. The nonlinear predistortion compensation module 106 utilizes its built-in interpolation unit to synchronously generate digital predistortion model coefficients at the corresponding depth, correcting the initial waveform and rectifying the frequency modulation nonlinearity degradation caused by changes in the drive current swing, ensuring consistent scanning linearity across different modes. Through a closed-loop system of digital predistortion and dynamic current adjustment, this solution achieves a balance between low noise and high linearity—two core performance indicators.

[0041] In Example 2, a micro-topology extension of the driving circuit is described in conjunction with specific figures.

[0042] This embodiment combines Figure 6 , Figure 7 and Figure 8 The circuit connection relationships of the core components in the above embodiments are discussed in detail at the microscopic level.

[0043] Combination Figure 6As shown, the high-speed digital-to-analog converter (AD9744ARU) includes a core current configuration network and a high-speed output network in its pin layout. Control signals from the low-speed precision digital-to-analog converter are introduced to pin 18 (Full Scale Adjust, FSADJ) of the high-speed digital-to-analog converter via the network node VDAREF. This pin network is connected in series with a first reference resistor R (R42 in the diagram, 4.7KΩ, with a low temperature drift of 25ppm). The incoming control bias current flows through the first reference resistor R and establishes a precise reference voltage Vref. The AD9744 chip internally includes a current mirror circuit composed of multiple parallel transistor arrays. This current mirror circuit scales the source tail current of each internal current switching unit based on the reference voltage Vref, establishing the dynamic configuration range of the full-scale output current at the output. The high-speed frequency-modulated current signal is then output differentially via pins 21 (IOUTB) and 22 (IOUTA). Furthermore, Figure 6 The system's multi-rail power supply network was demonstrated, including a 3.3V power rail providing low-noise energy for both the digital positive power supply (DVDD) and the analog positive power supply (AVDD), with multiple levels of bypass decoupling capacitors connected in parallel at the power supply pins. These bypass decoupling capacitors filter out high-frequency switching noise, ensuring glitches-free output during the digital-to-analog conversion process.

[0044] Combination Figure 7 As shown, a low-speed precision digital-to-analog converter (selected as AD5623RBRMZ-3, with 16-bit resolution) serves as the system's instruction conversion node. Its external digital communication interface consists of pin 6 (SDACS2, chip select), pin 7 (SDACLK2, clock), and pin 8 (SDAIN2, data input), conforming to the standard SPI digital communication protocol. Upon receiving the duty cycle command from the external master module, the resistor ladder network inside the AD5623R activates, outputting a continuous and smooth analog voltage to the outside through pin 2 (VOA, voltage output pin). This analog voltage is used as a control quantity to apply to the bias adjustment pin (or FSADJ pin) of the subsequent high-speed digital-to-analog converter, thereby dynamically controlling its full-scale output current. This analog voltage then becomes... Figure 6 The VDAREF signal source is located at pin 3. To ensure the stability of the analog reference, an external reference power supply of 1.25V (+1.25VREF) is connected to pin 3, forming a local energy storage and high-frequency bypass array. By adopting this microarchitecture, a microsecond-level smooth transition of the bias setting is ensured when the modulation depth is switched.

[0045] Combination Figure 8The system's overall physical signal flow block diagram shows that a reference signal set by a low-speed precision digital-to-analog converter (DAC) is injected into a high-speed DAC to adjust its internal DAC current noise characteristics and output a modulated current signal. This signal then enters a transimpedance converter circuit, converting it into an AC voltage signal with a certain swing. Following this, a summing network node is included in the system to perform analog algebraic summation on this AC voltage signal, along with an additional static DC bias signal and a phase-locked loop (PLL) signal used for frequency stabilization. The resulting composite voltage signal is finally input to a voltage-to-current converter (VDC) drive circuit, generating a physical injection current that enters the semiconductor laser diode cavity. This hierarchical synthesis and multi-path independent hybrid signal conditioning architecture controls dynamic noise suppression at the amplitude modulation front end while preserving a high-purity control window for the back-end closed-loop PLL.

[0046] In Example 3, a laser driving method with variable modulation depth is introduced.

[0047] like Figure 2 As shown, this application also provides a laser driving method with variable modulation depth based on the above hardware architecture. This method is mainly coordinated and executed by a main control unit or a field-programmable gate array, and specifically includes the following control flow steps: Step S201: Obtain the currently set detection modulation depth mode. During the initialization phase of each scan cycle, the system reads the scene configuration message sent by the host computer, extracts the long-range or short-range detection task tags that the radar system needs to perform, and then determines the corresponding detection modulation depth mode.

[0048] Step S202 involves generating a corresponding analog setting signal based on the detection modulation depth mode using a low-speed precision digital-to-analog converter (DAC). Specifically, the system main controller parses the externally input mode switching command and extracts the target full-scale current value parameter corresponding to the current detection modulation depth mode. Subsequently, the system software uses this target full-scale current value parameter to look up the digital-to-analog conversion mapping table pre-stored in the system storage medium to determine the corresponding low-speed digital control word parameter. The system writes the low-speed digital control word parameter into the internal register of the low-speed precision DAC via the SPI bus. This write operation triggers the DAC's built-in current source array to switch operating modes, ultimately smoothly outputting a DC setting voltage proportional to the target full-scale current value parameter as the analog setting signal.

[0049] Step S203: Dynamically configure the full-scale output current of the high-speed digital-to-analog converter. The generated analog setting signal is input to the full-scale current adjustment pin of the high-speed digital-to-analog converter via physical traces, changing the reference node voltage of the internal transistor mirror tail current source, forcing the upper limit voltage of the output envelope of the high-speed digital-to-analog converter to drop to the expected level that matches the modulation depth.

[0050] Step S204: A full-range digital waveform stream is input to the digital input of the high-speed digital-to-analog converter (DAC) using the nonlinear predistortion model. During the synchronization period of writing the low-speed digital control word parameters, the system calls the nonlinear predistortion compensation module to obtain the dynamic digital predistortion model coefficients corresponding to the low-speed digital control word parameters. If the current setting parameter deviates from the pre-stored discrete range, the system uses the reference digital predistortion model coefficients of adjacent ranges to perform Lagrange polynomial interpolation calculations. The system inputs the initial digital sequence of the set waveform into the polynomial predistortion filter, and performs amplitude pre-compensation and phase inverse offset operations based on the obtained dynamic digital predistortion model coefficients to generate the target waveform sequence corrected by distortion compensation. The system then pushes the target waveform sequence as a full-range digital waveform stream to the digital input of the high-speed DAC.

[0051] Step S205: Output the modulated current signal and perform transimpedance conversion. Control the high-speed digital-to-analog converter to generate an analog modulated current signal. Through a fixed transimpedance conversion circuit without RF switches, the modulated current signal is converted into a voltage signal and drives the subsequent laser. The transimpedance value of the transimpedance conversion circuit is always fixed according to the voltage swing corresponding to the maximum modulation depth supported by the system, maintaining the high bandwidth characteristics of the physical path.

[0052] Step S206, Dual-channel sustain control logic. When the system detects that it has switched to a smaller modulation depth mode, the system controls the low-speed precision digital-to-analog converter to reduce the generated analog setting signal to reduce the amplitude of the full-scale output current; on the other hand, it forces the high-speed digital-to-analog converter to ignore amplitude changes and maintain the working state of receiving the full-bias full-scale digital waveform code stream, and prohibits amplitude clipping in the digital domain.

[0053] This method employs a dual-track parallel scheduling at the digital command level. One track reduces analog low-level current noise while the other ensures high-precision full-scale drive of the digital front-end, and incorporates adaptive predistortion interpolation correction. This achieves zero-hardware physical contact switching when changing between different detection ranges and maintains the radar sweep waveform at a high signal-to-noise ratio.

[0054] Combination Figure 4 The data interaction timing diagram shown illustrates the signal timing interaction process during modulation depth switching in this embodiment of the invention. For example... Figure 4As shown, when the system switches modulation depth modes, the microcontroller platform issues a modulation depth mode control command, which is received by the low-speed precision digital-to-analog converter (DAC). Triggered by the clock edge, the low-speed precision DAC outputs an analog setting signal of the corresponding amplitude to the full-scale current adjustment pin of the high-speed DAC. Simultaneously, the high-speed DAC continuously receives the full-scale digital waveform stream and, combined with the analog setting signal received by its full-scale current adjustment pin, dynamically adjusts and outputs the corresponding modulation current signal. Subsequently, the transimpedance converter circuit converts this modulation current signal into a voltage signal and drives the subsequent laser. Throughout the entire data interaction process, the digital input of the high-speed DAC consistently receives the full-scale digital waveform stream, ensuring high quantization accuracy on the time axis.

[0055] Combination Figure 5 The signal processing data flow diagram shown illustrates the signal flow process in an embodiment of the present invention. Figure 5 As shown, the full-range digital waveform stream generated by the digital front end first passes through a nonlinear predistortion compensation module to correct and compensate for nonlinear distortions such as amplitude and phase, generating a corrected digital waveform stream which is then injected into the digital input of the high-speed digital-to-analog converter (DAC). Simultaneously, the probe modulation depth mode command generated by the microcontroller platform is transferred to a low-speed precision DAC, where it is converted into an analog setting signal and used as the bias or full-scale configuration reference for the high-speed DAC. Under the fusion of the two signals, the high-speed DAC outputs a modulated current signal with dynamic amplitude, which is finally converted into a voltage drive signal by a transimpedance converter circuit and flows to the laser, effectively combining analog control of the signal drive amplitude with the maintenance of digital quantization accuracy.

[0056] In Example 4, the system and electronic equipment are described.

[0057] Combination Figure 3 The system architecture diagram shown illustrates a lidar system 300 provided in this embodiment. The system integrates a laser 301, including a tunable semiconductor laser, and a laser driving circuit 100 with variable modulation depth as described in Embodiments 1 and 2. The output of the laser driving circuit 100 with variable modulation depth is connected to the laser 301, providing a modulation drive voltage signal in variable modulation depth mode to its internal gain cavity and tuning section. By incorporating this driving circuit, the entire lidar system can handle switching between multiple ranging scenarios. Through precise driving, the system can narrow the laser output linewidth, improve the coherence contrast of the far-field beat frequency signal, and thus enhance the spatial resolution of point cloud generation.

[0058] This embodiment also provides an electronic device 400. The device includes an internally interconnected processor 401 and a memory 402. The memory 402 stores a sequence of computer-readable instructions. When these instructions are read and executed by the processor 401, they can drive a connected hardware bus and perform various data processing and parameter scheduling steps in the laser driving method with variable modulation depth as described in Embodiment 3. The device may have an external bus interface to receive scene macro instructions issued by a host computer.

[0059] In Example 5, an extended alternative and its comparison mechanism are introduced.

[0060] This embodiment discusses two alternative extension schemes that may exist in the same application scenario and their working principles.

[0061] Alternative solution one is a variable gain transimpedance amplifier architecture. In this architecture, the system changes the transimpedance by adding a multiplexed RF switch and a precision feedback resistor matrix network to the analog signal transmission path. When at a relatively low modulation depth of 10 GHz, the system sends a switching signal to control the RF relay to engage, switching the feedback network to a branch with a smaller transimpedance value; at this time, the high-speed digital-to-analog converter still outputs a fixed 20mA current, obtaining the reduced target voltage swing through the smaller transimpedance. This solution requires truncating the analog RF signal and introducing a solid-state switching network with parasitic capacitance. This physical switching network introduces additional switching insertion loss, transient spike distortion, and additional resistor thermal noise. In contrast, the main embodiment of this application maintains a completely passive design for the transimpedance network, ensuring the continuity of the microwave transmission line impedance.

[0062] Alternative solution two is a multi-channel digital-to-analog converter (DAC) switching architecture. In this architecture, the system is configured with two or more independent high-speed DAC channels with parallel hardware structures. For example, channel A has a fixed hardware output of 20mA full-scale drive, while channel B is configured at the factory with a fixed feedback resistor output of 13.3mA full-scale drive. The host computer uses digital logic to control the RF multiplexing switch for signal path routing at the front end. The microscopic inconsistencies in the silicon wafer manufacturing process between the two independent DAC cores in this solution can lead to uncalibrated phase jumps and DC baseline drift during mode switching. In contrast, the main embodiment of this application utilizes a cascaded approach to reuse the same high-speed core base, achieving parameter switching without increasing the complexity of the high-speed clock domain.

Claims

1. A laser driving circuit with variable modulation depth, characterized in that, The system includes a low-speed precision digital-to-analog converter (DAC), a high-speed DAC, and a transimpedance conversion circuit. The low-speed precision DAC generates a corresponding analog setting signal based on the currently set detection modulation depth mode. The digital input terminal of the high-speed DAC receives the full-range digital waveform stream, and the full-range current adjustment pin of the high-speed DAC is connected to the output terminal of the low-speed precision DAC, dynamically configuring the full-range output current of the high-speed DAC according to the analog setting signal. The input terminal of the transimpedance conversion circuit is connected to the current output terminal of the high-speed DAC, converting the modulation current signal output by the high-speed DAC into a voltage signal to drive the subsequent laser. The transimpedance value of the transimpedance conversion circuit is fixedly set according to the voltage swing corresponding to the maximum modulation depth supported by the system. When the system switches to a smaller modulation depth mode, the low-speed precision DAC reduces the analog setting signal output to the high-speed DAC, reducing the amplitude of the full-range output current, while the high-speed DAC maintains the operation of receiving the full-range digital waveform stream.

2. The laser driving circuit with variable modulation depth as described in claim 1, characterized in that, The low-speed precision digital-to-analog converter includes an internal configuration register and a precision current source network. The internal configuration register receives modulation depth mode control commands issued by an external main control unit. The precision current source network outputs a DC setting voltage with a preset amplitude as the analog setting signal according to the modulation depth mode control commands. The full-scale current adjustment pin of the high-speed digital-to-analog converter is connected in series with a first reference resistor R. The DC bias current flows through the first reference resistor R to establish a reference voltage Vref. The high-speed digital-to-analog converter includes a current mirror circuit. The current mirror circuit scales the source tail current of each internal current switching unit according to the reference voltage Vref to limit the dynamic configuration range of the full-scale output current.

3. The laser driving circuit with variable modulation depth as described in claim 2, characterized in that, The current noise density Inoise at the output of the high-speed digital-to-analog converter is positively correlated with the amplitude of the full-scale output current under the control of the reference voltage Vref, showing a physical square root positive correlation. When the system switches to the lower modulation depth mode, the low-speed precision digital-to-analog converter reduces the output DC bias current according to the system set ratio, causing the established reference voltage Vref to drop synchronously. This causes the high-speed digital-to-analog converter to reduce the current noise density Inoise at the output source while outputting a reduced full-scale output current. The transimpedance switching circuit is constructed using a fixed passive network that does not contain analog RF switching devices, ensuring that the transimpedance value remains constant in both the lower modulation depth mode and the maximum modulation depth mode. This avoids the physical path of introducing additional switching distortion and thermal noise into the switching impedance network.

4. The laser driving circuit with variable modulation depth as described in claim 1, characterized in that, The laser driving circuit further includes a nonlinear predistortion compensation module. The signal output terminal of the nonlinear predistortion compensation module is connected to the digital input terminal of the high-speed digital-to-analog converter. The nonlinear predistortion compensation module uses digital predistortion model coefficients to perform predistortion correction on the initial swept frequency waveform digital sequence and generates the full-range digital waveform code stream input to the high-speed digital-to-analog converter.

5. The laser driving circuit with variable modulation depth as described in claim 4, characterized in that, The nonlinear predistortion compensation module is equipped with a coefficient lookup table and an interpolation unit. The coefficient lookup table stores reference digital predistortion model coefficients corresponding to multiple full-scale current discrete ranges. The interpolation unit obtains the current setting parameters of the low-speed precision digital-to-analog converter. When the current current setting parameters deviate from the multiple full-scale current discrete ranges, it uses the reference digital predistortion model coefficients of adjacent ranges to perform interpolation calculations and synchronously generates target digital predistortion model coefficients that match the current full-scale output current to compensate for frequency modulation nonlinear physical errors under different drive current swings.

6. A laser driving method with variable modulation depth, applied to the laser driving circuit with variable modulation depth as described in claim 1, characterized in that, The process includes: acquiring the currently set detection modulation depth mode; generating a corresponding analog setting signal based on the detection modulation depth mode using the low-speed precision digital-to-analog converter (DAC); inputting the analog setting signal to the full-scale current adjustment pin of the high-speed DAC to dynamically configure the full-scale output current of the high-speed DAC; inputting a full-scale digital waveform stream to the digital input terminal of the high-speed DAC and controlling the high-speed DAC to output a modulation current signal; converting the modulation current signal into a voltage signal through the transimpedance conversion circuit and driving the subsequent laser, wherein the transimpedance value of the transimpedance conversion circuit is fixedly set according to the voltage swing corresponding to the maximum modulation depth supported by the system; when the system is detected to switch to a smaller modulation depth mode, controlling the low-speed precision DAC to reduce the generated analog setting signal to decrease the amplitude of the full-scale output current, while controlling the high-speed DAC to maintain the working state of receiving the full-scale digital waveform stream.

7. The laser driving method under variable modulation depth as described in claim 6, characterized in that, The step of generating a corresponding analog setting signal by means of the low-speed precision digital-to-analog converter according to the detection modulation depth mode includes parsing the externally input mode switching command and extracting the target full-scale current value parameter corresponding to the current detection modulation depth mode. The target full-scale current value parameter is used to look up the digital-to-analog conversion mapping table stored in the storage medium and determine the corresponding low-speed digital control word parameter; the low-speed digital control word parameter is written into the internal register of the low-speed precision digital-to-analog converter, and the built-in current source array of the low-speed precision digital-to-analog converter is triggered to output a DC setting voltage proportional to the target full-scale current value parameter as the analog setting signal.

8. The laser driving method with variable modulation depth as described in claim 7, characterized in that, The step of inputting a full-range digital waveform code stream to the digital input terminal of the high-speed digital-to-analog converter includes calling a nonlinear predistortion compensation module during the synchronization period of writing the low-speed digital control word parameters to obtain dynamic digital predistortion model coefficients corresponding to the low-speed digital control word parameters; inputting the initial digital sequence of the set waveform into a polynomial predistortion filter; and performing amplitude pre-compensation and phase inverse offset operations in combination with the obtained dynamic digital predistortion model coefficients to generate a target waveform sequence corrected by distortion compensation. The target waveform sequence is pushed as the full-range digital waveform code stream to the digital input terminal of the high-speed digital-to-analog converter, so that the high-speed digital-to-analog converter maintains the full-range mapping state of the effective number of bits of the digital input terminal under each set full-range output current level.

9. A lidar system, characterized in that, It includes a laser and a laser driving circuit under variable modulation depth as described in claim 1, wherein the output terminal of the laser driving circuit under variable modulation depth is connected to the laser and provides a modulation driving voltage signal in the variable modulation depth mode.

10. An electronic device, characterized in that, It includes a memory and a processor, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are read and executed by the processor, the laser driving method under variable modulation depth as described in claim 6 is implemented.

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