A scalable multi-layer stacked cluster computing chip system and implementation method thereof

Abstract

The application discloses a multi-layer stacked cluster computing chip system capable of constrained expansion and an implementation method thereof, three-dimensional stacked integrated circuit technology, adopts a central radiation architecture, controls and manages multi-layer stacked units in a central control hub, realizes constrained expansion through signal retiming compensation, and controls transmission delay. Physical isolation composite bus integrates data, clock and power supply signals, and suppresses crosstalk. The central integrated synchronization, routing and power consumption control module dynamically optimizes clock and scheduling efficiency; Manhattan shortest path is adopted for data forwarding to ensure linear growth of computing power. The stacked unit is designed in a partition mode and reinforced with through silicon via coupling defects, is adapted to multiple CMOS processes, and meets the requirements of AI, high-performance computing, aerospace and edge scenarios. Compared with traditional chips, the computing power density, energy efficiency and adaptability are improved, the attenuation in the expansion range is low, and the stability is enhanced.

Description

Technical Field

[0001] This invention belongs to the fields of semiconductor integrated circuits, three-dimensional stacked chips, and large-scale heterogeneous parallel computing technology. Specifically, it relates to a cluster computing chip system with constrained expansion capability and collaborative radiation resistance of stacked architecture, as well as its fabrication process. It is suitable for application scenarios with high requirements for computing power density, timing synchronization accuracy, cluster expansion capability, and adaptability to extreme environments, such as artificial intelligence inference operations, general high-performance computing, aerospace data processing, and edge terminal computing devices. Background Technology

[0002] With the rapid development of artificial intelligence, deep space exploration, and satellite communication industries, the demand for comprehensive computing power of chips in civilian, industrial, and aerospace fields continues to rise. Traditional planar chips are limited by substrate area, and the number of computing units that can be integrated on a single chip has a physical upper limit, making it difficult to break through the space for improving computing power. When multiple planar chips are networked, the data transmission latency between chips is relatively high, signal crosstalk problems occur frequently, and the overall computing power utilization rate is difficult to reach the ideal level.

[0003] Conventional 3D stacked chips mostly only implement storage medium stacking or mixed storage and logic stacking, without a unified global control center. When multiple units are networked, the timing clock deviation is large, failing to meet the requirements for low-latency collaborative computing. Simultaneously, the interlayer through-silicon via (TSV) structure is highly susceptible to radiation coupling effects, significantly increasing the probability of single-event upsets. Existing chip architectures have weak process compatibility, unable to adapt to multiple generations of mature CMOS processes, making overall manufacturing cost control difficult.

[0004] Conventional cluster chip expansion lacks physical boundary constraints, making it difficult to effectively manage signal attenuation and timing offset issues as the cluster size increases. Furthermore, in extreme environments such as aerospace with strong radiation and wide temperature ranges, general hardening solutions cannot adapt to the inherent defects of stacked chips, resulting in high modification costs and poor operational stability. To address these shortcomings of existing technologies, this invention designs a centrally radial multi-layer stacked cluster architecture, coupled with an isolated bus, collaborative hardening circuitry, and a constrained expansion mechanism, thus overcoming the deficiencies of existing technologies. Summary of the Invention

[0005] Purpose of the invention This invention aims to overcome the shortcomings of existing technologies, such as limited computing power density, poor cluster timing synchronization, high data transmission latency, lack of physical boundaries for expansion, single process adaptability, and insufficient stability in extreme environments. It provides a multi-layer stacked cluster computing chip system with constrained expansion and its implementation method. It improves computing power per unit area by relying on a vertical stacking structure, achieves full-domain timing and task management with a unified central hub, sets up standardized interfaces to achieve controllable scale expansion, optimizes the radiation-resistant structure to adapt to the inherent defects of stacking, is compatible with multiple generations of mature processes, and comprehensively broadens the applicable scenarios of the chip. Technical solution

[0006] The first aspect of this invention provides a multi-layer stacked cluster computing chip system with constrained scalability. The system adopts a central radial topology architecture, with a single central control hub located at the geometric center of the cluster. Multi-layer stacked computing units are arranged in an array around the periphery, and the number of units can be reasonably expanded within the bus delay tolerance. A three-way physically isolated composite bus is used to uniformly transmit data, clock, and power supply signals, thereby avoiding signal interference at the structural level.

[0007] The central control hub integrates three major global management modules: dual-mode time synchronization combined with local crystal oscillator to ensure clock timing consistency, and calibration algorithm to optimize synchronization accuracy; the routing module determines forwarding paths based on Manhattan distance and dynamically allocates computing tasks to achieve load balancing; the power module collects global operating status, divides multiple working modes, and dynamically adjusts voltage and frequency to match the power consumption requirements of different load conditions.

[0008] The stacked cells are internally divided into multiple dedicated computing regions to meet diverse data processing needs. Redundant voting timing is optimized to address the radiation coupling problem of interlayer through-silicon vias (TSVs), and the voting path is designed according to the chip feature size ratio, adaptable to chips of different specifications and processes. Standardized high-speed interconnect interfaces are configured on the outside of the cluster, along with signal retiming circuitry to compensate for long-distance transmission losses, ensuring linear growth of computing power within a defined range.

[0009] The second aspect of this invention provides a method for implementing a multi-layer stacked cluster computing chip system with constrained scalability. First, the semiconductor substrate undergoes electromagnetic field annealing to reduce lattice defects. A single-layer logic functional layer is fabricated using CMOS technology, and multi-layer stacking is completed through bonding, with inter-layer conductive lines laid out. Bus lines, a central control module, and interconnect expansion interfaces are then assembled sequentially. Radiation-hardened structures are selected according to the application scenario. After the entire system is assembled, full-project performance testing is conducted. Finally, multi-cluster cascading expansion is achieved through interfaces, verifying the overall operating performance under constrained scalability. Beneficial effects

[0010] The architecture is reasonably scalable and controllable: It abandons the design of unlimited expansion and relies on the signal retiming circuit to compensate for transmission loss. It can expand the cluster size within the physical tolerance range. The upper limit of the size is determined by the bus delay characteristics. The computing power attenuation of large-scale cluster operation is low and the practicality of engineering implementation is strong.

[0011] Excellent timing synchronization accuracy: Adopting a central unified timing calibration mode, combined with phase optimization algorithm and redundant clock backup, the overall timing consistency of the cluster is far superior to that of multi-master network chips, meeting the requirements of high-precision collaborative computing.

[0012] The data scheduling logic is clear: the forwarding is based on the physical Manhattan distance, the data forwarding level is limited, the routing table is updated regularly to optimize the path, effectively reducing cross-unit transmission latency and improving task processing efficiency.

[0013] Stacked radiation resistance has unique advantages: the hardening circuit is optimized for the unique radiation coupling defects of stacked silicon vias, which is different from general chip hardening solutions. At the same time, the voting path is adapted to multiple processes, which greatly reduces the probability of failure in extreme environments.

[0014] Wide adaptability to process and cost: The architecture is not bound to a single manufacturing process and can be adapted to multiple generations of mature CMOS processes such as 28nm, 56nm, and 65nm. The manufacturing scheme can be flexibly selected according to computing power and cost requirements, and the mass production control is easy.

[0015] Adaptive power consumption adjustment: Automatically switches operating levels based on real-time load, dynamically adjusts power supply and operating frequency, effectively reduces useless power consumption under light load conditions, and significantly improves the overall energy efficiency of the machine.

[0016] High versatility: The basic architecture meets the common scenarios of civilian artificial intelligence and edge computing. With the addition of a collaborative reinforcement structure, it can be adapted to the extreme working conditions of strong radiation and wide temperature range in aerospace, greatly expanding the scope of application of the equipment. Attached Figure Description

[0017] Figure 1 Overall cluster topology diagram Figure 2. Layered structure diagram of a single nine-layer vertical stacked unit. Figure 3 Schematic diagram of internal functional zoning of a single layer Figure 4. Schematic diagram of inter-layer connection of integrated composite bus Figure 5. Schematic diagram of cluster inter-chip interconnection expansion structure Figure 6. Schematic diagram of dynamic power consumption control logic for load grading Detailed Implementation

[0018] Those skilled in the art can complete the overall manufacturing and performance testing based on the technical solution in this document. The following provides a detailed description of the solution in conjunction with actual implementation parameters, test conditions, and two sets of application examples. Equivalent modifications that do not depart from the core architecture of this invention all fall within the protection scope of this invention. Basic general technical parameters (reference values ​​for implementation)

[0019] The thickness of a single stacking unit is set to 50μm, and the overall stacking thickness of nine layers is 530μm. Copper-copper hybrid bonding process is used between layers, the bonding layer thickness is 10μm, and the on-resistance is controlled within 0.05Ω. The diameter of the through-silicon via is 20μm, and the center-to-center spacing between the vias is not less than 40μm.

[0020] The integrated composite bus has a data path width of 2048 bits and a base transmission rate of 32Gbps; the isolation impedance between the three isolated lines is not less than 1000Ω; the interconnect interface adopts the CXL3.0 high-speed protocol, is configured with 200 pairs of differential pins, and the interface impedance is matched to 50Ω.

[0021] The clock module uses a 100MHz temperature-controlled crystal oscillator, and the timing communication protocol is NMEA-0183. The signal sampling frequency range is 5Hz~10Hz. When the sampling frequency is 8Hz or higher, the cluster clock synchronization deviation can be controlled within 0.2ps, and the optimal operating condition deviation at 10Hz is ≤0.1ps.

[0022] The load levels are divided according to the load percentage: light load range 0%~35%, optimal range 0%~30%; normal range 30%~70%; full load range 70%~100%; corresponding power supply voltages 0.8V, 0.9V, 1.0V, and operating frequencies 1.2GHz, 1.8GHz, 2.5GHz.

[0023] Substrate annealing process parameters: electromagnetic field frequency fixed at 2.45 GHz, field strength controllable range of 8 kV / m~12 kV / m, optimal value of 10 kV / m; vacuum degree of processing chamber 1×10^-3 Pa, constant temperature processing time 30 min, and lattice defect density controlled within 100 defects / cm² after cooling.

[0024] Radiation testing conditions: A control test was conducted using a radiation dose of 50 MeV·cm² / mg, and 100 stacked chips of the same specifications were selected as test samples; the upper limit of the redundancy voting path was set to 0.5 times the feature size of a single-layer chip, which is compatible with mainstream 28nm and 65nm processes, and a path length of 2mm is preferred in engineering practice.

[0025] Cluster expansion test: Within the range of 0 to 100 units, signal loss can be effectively compensated by the retiming circuit, and the cluster computing power attenuation is ≤5%; after the number of units exceeds 100, the bus delay exceeds the physical tolerance and the linear computing power growth characteristic cannot be guaranteed.

[0026] Overall cluster architecture (corresponding to Figure 1) Label 1 is the central control hub, serving as the sole core for overall management and control; Label 2 represents nine vertically stacked computing units, with a base configuration of 81 units and a maximum stable expansion capacity of 100 units; Label 3 is the array layout area; Label 4 is the integrated composite bus, equipped with signal retiming compensation circuitry; Label 5 is the inter-chip interconnection expansion interface, which cannot be stably expanded beyond 100 units due to bus latency constraints. All unit commands, clocks, and power are centrally managed. A single nine-layer stacked structure (corresponding to Figure 2)

[0027] Numbered 10-18 represent logic functional layers one through nine, each with a thickness of 50 μm; numbered 19 represents a copper-copper hybrid bonding structure with interlayer silicon via diameters of 20 μm. Based on radiation measurement results, differentiated timing designs were implemented for inner-layer circuit redundancy to address interlayer coupling defects. Simultaneously, voting path lengths were constrained according to process specifications to offset inherent radiation defects in the stacked structure. Single-layer internal functional zoning (corresponding to Figure 3)

[0028] Number 21 is the single-layer central control area, and 22 to 29 are the eight major categories of computing function areas. Each area is matched with the corresponding circuit according to the computing type. The storage, computing and control areas operate independently and complete data interaction in conjunction with the quantization forwarding rules. Integrated composite bus connection (see Figure 4)

[0029] Number 30 is the main bus port, and 31-33 are three physically isolated paths. The bus is equipped with a signal compensation node to correct the attenuation signal in real time during the expansion process and maintain the rated transmission rate. 34 is the branch line and 35 is the impedance node to ensure stable signal transmission between layers. Inter-chip interconnection and capacity expansion within the cluster (corresponding to Figure 5)

[0030] Label 40 represents the existing cluster core; 41 represents the CXL3.0 interconnect interface with built-in retiming circuitry; 42 represents the unit connection line; and 43 represents the newly added stacking unit. The computing power linearly decreases by ≤5% within the expansion range of 0~100 groups; beyond this scale, the hardware cannot compensate for timing losses. Dynamic power consumption control based on load grading (corresponding to Figure 6)

[0031] The 50-pin load acquisition port uses 10Hz high-frequency sampling; the 51-pin judgment module is divided into levels according to 0~35% (preferably 30%), 30%~70%, and 70%~100%; 52~54 are three-level control branches; and 55 outputs voltage and frequency regulation parameters, with the threshold selected based on the results of energy efficiency comparison experiments. Example 1: 28nm Process Civil AI Inference Cluster

[0032] This embodiment uses a mature 28nm CMOS process without additional radiation-hardening structures. It is mainly used in real-time AI inference scenarios in data centers. The cluster is based on 81 nine-layer stacked units, which can be stably expanded to a maximum of 100 units.

[0033] The unit is internally configured with a 32-bit integer arithmetic area, a 64-bit floating-point arithmetic area, a 256MB high-speed cache area, an INT8 / FP16 quantization conversion area, and a 256-bit wide memory control area; the clock module is connected to the Beidou timing signal by default, operates at a 10Hz sampling frequency, and the global timing synchronization deviation is stably controlled within 0.1ps. When the signal is abnormal, it automatically switches to local crystal oscillator backup power supply.

[0034] Tasks are divided into four priority levels. Data is forwarded according to the Manhattan shortest path, with ≤1 hop count for single-layer forwarding and ≤3 hop count for cross-unit forwarding. The routing table is dynamically updated at a frequency of 1Hz. The load priority adopts the optimal light load threshold of 0%~30%, which reduces the idle power consumption by 40% under light load conditions. The energy efficiency ratio of the whole machine in INT8 mode can reach 16TOPS / W.

[0035] Expansion test data: 50 units saw a 1.1% decrease in computing power, 81 units saw a 2.8% decrease, and 100 units saw a 4.2% decrease; cross-unit data transmission latency was ≤10ns, and overall computing power utilization was ≥92%, meeting the needs of large-scale commercial inference computing power. Example 2: 65nm process spaceborne processing cluster

[0036] This embodiment uses a 65nm high-stability CMOS process, which is suitable for aerospace satellite radar and remote sensing data processing scenarios. It has a base configuration of 9 stacked units and can be expanded to a maximum of 20 units.

[0037] The entire device is equipped with a stacked collaborative radiation hardening circuit, the computing circuit is configured with a three-modal redundancy structure, the power supply circuit is equipped with an anti-latch-up protection module, the storage area is equipped with an EDAC single-event error correction algorithm, and the clock line is covered with a high-permeability shielding layer; the voting path is constrained by 0.5 times the feature size, and the inter-layer timing is optimized to avoid radiation interference periods.

[0038] After testing with a radiation dose of 50MeV・cm² / mg, the optimized interlayer single-event upset amplification was reduced from 30% to 3%, and the chip can operate stably in a wide temperature range of -55℃ to 125℃; the clock sampling frequency is 9Hz, and the synchronization deviation is ≤0.18ps, meeting the high-precision timing requirements of aerospace; the load threshold is relaxed to 35% to adapt to space load fluctuations, and the computing power attenuation is ≤3% in extreme environments. Complete machine manufacturing and testing process

[0039] Substrate pretreatment: The silicon-based semiconductor substrate is placed in an electromagnetic field cavity and annealed and repaired according to predetermined frequency, field strength and vacuum parameters. After cooling, the lattice defects are tested and found to be qualified. Single-layer fabrication: 28nm / 65nm CMOS process is used to etch the circuit, divide various functional areas, and cut individual monomers after completing electrical performance testing; Stacked bonding: Nine single layers are stacked sequentially, fixed using a hybrid bonding process, and silicon via conductive lines are laid out. The aerospace version synchronously optimizes redundant timing paths. Bus and hub assembly: Deploy isolated composite bus and debug line impedance; assemble three types of control modules in the cluster center and complete joint module debugging; Interface and ruggedized assembly: High-speed interconnect interfaces are assembled on the outside of the array to test connectivity; aerospace models are equipped with radiation protection structures. Full performance testing: Clock synchronization, power consumption adjustment, task scheduling, environmental adaptability, and expansion stability tests were completed sequentially; Cascaded networking: Expand the cluster size through standard interfaces and verify various operating indicators of the whole machine within the constraints.

[0040] Sampling frequency - clock accuracy relationship: 5Hz: maximum synchronization deviation 0.35ps; 8Hz: maximum 0.2ps; 10Hz: maximum 0.1ps. 8Hz is determined as the minimum acceptable sampling frequency, and 10Hz is the optimal operating condition.

[0041] Expansion scale - computing power attenuation relationship: Group 50: attenuation 1.1%; Group 81: 2.8%; Group 100: 4.2%; Group 110: 8.7%, verifying that Group 100 is the stable expansion limit.

[0042] Power consumption threshold energy efficiency comparison: 30% threshold: optimal energy efficiency gain; 35% threshold: gain decreases by 4.8%; 40% threshold: gain decreases by 9.2%, proving the rationality of the 30% optimal value.

[0043] Radiation hardening control test conditions: radiation dose 50 MeV·cm² / mg, 100 stacked chip test samples, planar chips of the same process as the control group; General hardening circuit: the flip-flop rate affected by coupling of the stacked layer is increased by 30%; The collaborative optimization circuit of this invention: the flip-flop rate increase is reduced to 3%, effectively adapting to the unique defects of the stacked architecture.

[0044] Adaptability to different process paths: Under the mainstream processes of 28nm and 65nm, the voting path is set according to 0.5 times the feature size. The circuit operates stably and there is no significant difference in anti-interference performance, and the design has universality. Performance comparison data

[0045] Compared with traditional high-end planar chips of the same power consumption, the core indicators of the two sets of embodiments of the present invention are compared as follows:

[0046] Computing density: 2.3 TOPS / mm² Global clock synchronization deviation: controlled within ≤0.1ps. Computing power at a scale of 100 groups: only 4.2% Energy efficiency ratio (INT8 operating mode): 16 TOPS / W Interlayer single-event upset amplification: No additional amplification (without radiation hardening).

[0047] Computing density: 1.8 TOPS / mm² Global clock synchronization deviation: ≤0.18ps Interlayer single-particle flip-flop amplification: only 3% after synergistic hardening. Energy efficiency ratio (INT8 operating mode): 12 TOPS / W Computing power attenuation at a scale of 100 groups: No actual measured data (because ultra-large-scale clusters are not typically used in aerospace scenarios).

Claims

1. A multi-layer stacked cluster computing chip system with constrained scalability, characterized in that, include: A central control hub is located at the geometric center of the cluster; Several groups of nine-layer vertically stacked computing units are arranged in an array around the central control hub. The array has a base arrangement of 81 groups. With the addition of a signal retiming circuit, the cluster can flexibly expand the number of units within the physical tolerance of bus delay. An integrated composite bus runs through the central control hub and all stacked computing units, and is used to independently transmit data signals, reference clock signals, and power supply signals. Several inter-chip interconnection expansion interfaces are arranged on the outside of the array and connected to the integrated composite bus for accessing new stacking units to expand the cluster size; The central control hub includes: a global clock synchronization module, a global data routing and scheduling module, and a global dynamic power management module; The global clock synchronization module has a built-in dual-mode time synchronization subunit, a local constant temperature crystal oscillator, and a clock calibration algorithm unit; the global data routing and scheduling module has a built-in load balancing unit, a task priority determination unit, and a distance addressing routing table; the global dynamic power management module has a built-in load acquisition unit, a gear determination unit, and a voltage and frequency regulation drive unit. Each logical function layer is configured with a single-layer central control area and several computing function areas; the integrated composite bus is divided into three physically isolated transmission paths, and isolation protection structures are set between the lines to avoid mutual interference between different signals. A scalable, multi-layer stacked cluster computing chip system, characterized by comprising: a central control hub located at the geometric center of the cluster; several groups of nine-layer vertically stacked computing units arranged in an array around the central control hub, the array having a base arrangement of 81 groups, and after incorporating a signal retiming circuit, the cluster can flexibly expand the number of units within the physical tolerance of bus delay; an integrated composite bus that runs through the central control hub and all stacked computing units, used for independently transmitting data signals, base clock signals, and power supply signals; and several inter-chip interconnection expansion interfaces arranged on the outside of the array and connected to the integrated composite bus, used to access new stacked units to expand the cluster size; The central control hub includes: a global clock synchronization module, a global data routing and scheduling module, and a global dynamic power management module; the global clock synchronization module has a built-in dual-mode time synchronization subunit, a local constant temperature crystal oscillator, and a clock calibration algorithm unit; the global data routing and scheduling module has a built-in load balancing unit, a task priority determination unit, and a distance-based routing table; the global dynamic power management module has a built-in load acquisition unit, a gear determination unit, and a voltage and frequency regulation drive unit; Each logical function layer is configured with a single-layer central control area and several computing function areas; the integrated composite bus is divided into three physically isolated transmission paths, and isolation protection structures are set between the lines to avoid mutual interference between different signals.

2. The scalable, multi-layered stacked cluster computing chip system according to claim 1, characterized in that, The nine-layer vertically stacked computing unit comprises multiple layers of sequentially stacked logic function layers, which are fixed together by bonding structures. Through-silicon vias (TSVs) are set between the layers to achieve interlayer electrical interconnection. To address the interlayer radiation coupling problem caused by TSVs, the computing circuit is equipped with a redundant voting timing optimization structure to reduce the failure risk caused by single-event upsets.

3. The scalable, multi-layered stacked cluster computing chip system according to claim 1, characterized in that, The computational function area includes at least one of the following: integer arithmetic area, floating-point arithmetic area, model loading area, activation arithmetic area, cache area, quantization conversion area, on-chip interconnect transceiver area, and memory read / write control area. Different function areas are matched with corresponding working circuits to complete corresponding data processing tasks.

4. The scalable, multi-layered stacked cluster computing chip system according to claim 1, characterized in that, The global clock synchronization module can access external time signals to resolve standard time and combine with a local temperature-controlled crystal oscillator to achieve clock redundancy backup; the built-in phase calibration algorithm can compensate for phase deviations caused by transmission, and the system clock synchronization accuracy is optimized synchronously as the signal sampling frequency increases, meeting the unified timing operation requirements of large-scale clusters.

5. The scalable, multi-layered stacked cluster computing chip system according to claim 1, characterized in that, The global data routing and scheduling module collects the cluster load status in real time and pre-divides multi-level task priorities; it uses the Manhattan distance of physical coordinates as the basis for data forwarding determination, and completes data interaction within a single layer, across layers within the same unit, and between adjacent units in hierarchical order. The routing table is updated periodically to maintain cluster load balance.

6. The scalable, multi-layered stacked cluster computing chip system according to claim 1, characterized in that, The global dynamic power management module collects cluster operating current, computing load and temperature data in real time, and divides multiple working modes according to the load ratio; it adjusts the power supply voltage and operating frequency according to the corresponding mode, and is configured with a dual-circuit power supply structure, which can automatically switch power supply lines to ensure uninterrupted operation in the event of a fault.

7. The scalable, multi-layered stacked cluster computing chip system according to claim 1, characterized in that, The inter-chip interconnection expansion interface uses a high-speed interconnection protocol to configure differential signal pins. The interface is equipped with a signal retiming circuit to compensate for the rate loss caused by long-distance data transmission and ensure the overall transmission stability after the expansion unit is connected.

8. The scalable, multi-layered stacked cluster computing chip system according to claim 2, characterized in that, The system is equipped with radiation-hardened circuitry adapted to the stacked architecture, which is arranged in the arithmetic circuit, storage circuit, and clock circuit. It includes redundant arithmetic circuitry, latch-up protection circuitry, single-event error correction circuitry, and clock shielding structure. The redundant voting path is set according to the single-layer feature size ratio, with an engineering preferred value of ≤2mm. The majority voting logic is used to output the calculation results. A control test was completed under a radiation dose of 50MeV・cm² / mg. The interlayer silicon vias can increase the local single-event flip rate by 30%. This circuit has optimized the timing logic to offset the negative effects of radiation.

9. A method for implementing a constrained scalability multi-layer stacked cluster computing chip system according to any one of claims 1 to 8, characterized in that, Includes the following steps: Step 1: Perform defect repair treatment on the semiconductor substrate using an annealing pretreatment process; Step 2: Based on the design layout, fabricate a single-layer logic functional layer using CMOS technology, and after completing functional testing, cut it into independent computing units; Step 3: Stack and bond single-layer functional layers to form a nine-layer stacked computing unit, lay out interlayer silicon vias to provide conductive lines, optimize circuit timing for radiation coupling effect, and constrain voting path length according to process size. Step 4: Arrange several groups of nine-layer stacked computing units in an array form, route the integrated composite bus through all stacked computing units and the central control hub, and complete bus impedance debugging and signal compensation circuit configuration; Step 5: Arrange the global clock synchronization module, the global data routing and scheduling module, and the global dynamic power management module at the central control hub, and complete the joint debugging of functional modules; Step 6: Arrange inter-chip interconnection expansion interfaces on the periphery of the array, complete the connectivity test between the interfaces and the integrated composite bus, and equip a retiming circuit to adapt to cluster capacity expansion; Step 7: For radiation-hardened chips, add triple modular redundancy circuits, latch-up protection circuits, and single event flip error correction circuits to each stacked computing unit, strictly control the length of the voting path, and arrange a clock circuit shielding layer; Step 8: Perform global clock synchronization test, load scheduling test, power consumption test, capacity expansion stability test, and environmental adaptability test on the assembled chip system; Step 9: Cascading multiple groups of chip systems through inter-chip interconnection expansion interfaces, and verify the cluster computing power stability and data transmission delay indicators within the physical tolerance range.

10. The method for implementing a constrained scalability multi-layer stacked cluster computing chip system according to claim 9, characterized in that, The high-frequency electromagnetic field pretreatment process further comprises: Place the wafer substrate into a high-frequency electromagnetic field processing chamber, and set the chamber vacuum degree to 1×10^-3Pa; Adjust the electromagnetic field frequency to 2.45GHz, the preferred range of field strength is 8~12kV / m, and the optimal value is 10kV / m. When the field strength exceeds 12kV / m, the defect repair efficiency tends to be saturated; Keep the chamber temperature at 500°C, and the continuous processing duration is 30min; After the processing is completed, naturally cool the wafer substrate to room temperature in a nitrogen environment, and it is qualified if the lattice defect density of the wafer substrate is detected to be ≤100 pieces / cm².

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