Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device; the display panel comprises a display area and a non-display area, the non-display area comprises a gate drive circuit area and a winding area, the winding area is arranged between the gate drive circuit area and the display area, the display panel comprises a data line and a first light shielding pattern, the data line is arranged in the winding area and the display area, and the first light shielding pattern is arranged in the non-display area; in the top view, the first light shielding pattern is located outside the winding area, and the first light shielding pattern is arranged at intervals with the part of the data line located in the winding area, so that the light shielding pattern does not overlap with the data line in the winding area, thereby reducing the risk of static electricity burn between the light shielding pattern and the data line, and improving the yield of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] OLED (Organic Light-Emitting Diode) displays are widely used in various fields due to their advantages such as lightweight, wide viewing angle, low power consumption, fast response, low-temperature resistance, high luminous efficiency, and the ability to fabricate flexible displays. To reduce costs and the number of driver chips, OLED displays employ Demux (Demultiplexer) technology. While OLED displays incorporate light-shielding patterns, electrostatic discharge (ESD) damage has been observed between these patterns and data lines or Demux circuitry during actual use, leading to OLED display failure.

[0003] Therefore, existing OLED display devices have a technical problem where electrostatic discharge damage can occur between the light-shielding pattern and other traces and circuits. Summary of the Invention

[0004] This application provides a display panel and a display device to solve the technical problem of electrostatic discharge damage between the light-shielding pattern and other traces and circuits in existing OLED display devices.

[0005] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, the display panel including a display area and a non-display area, the non-display area including a gate driving circuit area and a winding area, the winding area being disposed between the gate driving circuit area and the display area; The display panel includes a data cable and a first light-shielding pattern. The data cable is disposed in the winding area and the display area, and the first light-shielding pattern is disposed in the non-display area. In the top view, the first light-shielding pattern is located outside the winding area, and the first light-shielding pattern is spaced apart from the portion of the data line located in the winding area.

[0006] According to a second aspect of this application, a display device is provided, the display device including a display panel as described in any of the above embodiments.

[0007] This application provides a display panel and a display device. The display panel includes a display area and a non-display area. The non-display area includes a gate driving circuit area and a winding area. The winding area is disposed between the gate driving circuit area and the display area. The display panel includes a data line and a first light-shielding pattern. The data line is disposed within the winding area and the display area, and the first light-shielding pattern is disposed within the non-display area. In a top view, this application arranges the first light-shielding pattern outside the winding area, and the first light-shielding pattern and the data line are partially spaced apart in the winding area. This prevents the light-shielding pattern from overlapping with the data line in the winding area, thereby reducing the risk of electrostatic discharge damage between the light-shielding pattern and the data line and improving the yield of the display panel.

[0008] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0010] Figure 1 This is a schematic diagram of a comparison display device provided in an embodiment of this application.

[0011] Figure 2 This is a plan view of the display panel provided in an embodiment of this application.

[0012] Figure 3 This is a schematic diagram of the cross-sectional area of ​​the film layer of the display panel provided in an embodiment of this application.

[0013] Figure 4 for Figure 2 An enlarged view of area A of the display panel.

[0014] Figure 5 for Figure 4 An enlarged view of area B of the display panel.

[0015] Figure 6 A plan view of the light-shielding pattern in the display area of ​​the display panel provided in the embodiments of this application.

[0016] Figure 7 A comparison diagram of the light-shielding pattern of the comparative display device provided in the embodiments of this application and the light-shielding pattern in this application.

[0017] Figure 8 The first plan view of the light-shielding pattern of the gate driving circuit area and the corresponding via provided in the embodiments of this application.

[0018] Figure 9 The second plan view of the light-shielding pattern of the gate drive circuit area and the corresponding via provided in the embodiments of this application.

[0019] Figure 10 A schematic diagram of the cross-section of the light-shielding pattern and the high-potential power line in the display area provided in the embodiments of this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0021] To illustrate the principle behind the technical problems in the embodiments of this application, a contrast display device is provided. It should be understood that this contrast display device cannot be considered prior art in the embodiments of this application. Figure 1 As shown, the comparison display device includes a display area 101 and a gate circuit area 102. In order to improve the anti-static capability, the comparison display device provides light-shielding metal 11 in the display area 101 and the gate circuit area 102, and then connects the first light-shielding metal 111 of the display area 101 and the second light-shielding metal 113 of the gate circuit area 102 through a third light-shielding metal 112.

[0022] Meanwhile, in order to reduce the number of driver chips, comparison display devices often employ demux technology, such as... Figure 1 As shown, a demultiplexing circuit 13 is set at the lower bezel and lower rounded corner of the contrast display device, and the data trace 12 in the contrast display device needs to be wound at the lower rounded corner. This results in the third light-shielding metal 112 overlapping with the data trace 12 and the demultiplexing circuit 13 at the lower rounded corner. Since the third light-shielding metal 112 is an independent trace, the overlap area between the third light-shielding metal 112 and the transistors in the data trace 12 and demultiplexing circuit 13 is small, making it prone to capacitor breakdown and electrostatic discharge (ESD) damage. Although some contrast display devices reduce the frequency of ESD damage by decreasing the amount of light-shielding metal, the problem of light-shielding metal overlapping with large-area traces still exists, leading to ESD damage. Therefore, existing OLED display devices have a technical problem of ESD damage occurring between the light-shielding pattern and other traces and circuits.

[0023] This application provides a display panel and a display device to address the aforementioned technical problems.

[0024] like Figure 2 As shown, this application embodiment provides a display panel 2, which includes a display area 201 and a non-display area 202. Sub-pixels can be set in the display area 201, and structures such as gate driving circuits, multiplexing circuits, and bonding terminals can be set in the non-display area 202.

[0025] Specifically, Figure 2 The example described uses a non-display area 202 surrounding a display area 201, but this embodiment is not limited to this. The non-display area 202 can be located on one, two, or three sides of the display area 201. Furthermore, when the display panel in this embodiment needs to accommodate under-display sensors (e.g., an under-display camera), a punch-hole area can be provided within the display area 201 or at the boundary between the display area 201 and the non-display area 202. This punch-hole area may or may not be displayed. When the display panel in this embodiment uses a full-screen display, the non-display area 202 can be bent or folded to the back of the display panel 2.

[0026] Specifically, such as Figure 2 As shown, the non-display area 202 may include a left border area 202a, a right border area 202b, a top border area 202d, a bottom border area 202c, a first corner area 202e, a second corner area 202f, a third corner area 202g, and a fourth corner area 202h, respectively disposed on the left, right, top, bottom, lower left, lower right, upper left, and upper right sides of the display area 201. The left border area 202a and the right border area 202b are disposed on both sides of the display area along a first direction X, and the top border area 202d and the bottom border area 202c are disposed on both sides of the display area along a second direction Y. The angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees.

[0027] Specifically, such as Figure 2 As shown, the first corner area 202e is the area connecting the left border area 202a and the bottom border area 202c; the second corner area 202f is the area connecting the right border area 202b and the bottom border area 202c; the third corner area 202g is the area connecting the left border area 202a and the top border area 202d; and the fourth corner area 202h is the area connecting the right border area 202b and the top border area 202d.

[0028] Specifically, a bonding terminal can be set within the lower frame area 202c for bonding the driver chip.

[0029] Specifically, such as Figure 2As shown, the non-display area 202 may include a gate drive circuit area 203, a winding area 204, a multiplexing circuit area 205, and a transfer area 206. A gate drive circuit 36 ​​may be housed in the gate drive circuit area 203, a portion of a data line 33 may be housed in the winding area 204, and a multiplexing circuit 32 may be housed in the multiplexing circuit area 205. The multiplexing circuit reduces the number of source driver chips; specifically, it allows one input port to be connected to two or more data lines via a multiplexed transistor, thereby reducing the number of input ports and the number of source driver chips. The transfer area 206 may house the transfer line between the gate drive circuit 36 ​​and the pixel drive circuit in the display area 201.

[0030] Specifically, such as Figure 2 As shown, in the above embodiments, the non-display area is divided according to orientation and function. It is understood that the areas divided in different ways may overlap. For example, the gate drive circuit area 203 may overlap with the left border area 202a. Similarly, the relationship between other areas can be determined.

[0031] Specifically, such as Figure 2 As shown, the gate driving circuit region 203 may include a first gate circuit region 203a and a second gate circuit region 203b. Correspondingly, gate driving circuits may be provided in both the first gate circuit region 203a and the second gate circuit region 203b. However, the embodiments of this application are not limited to this. The gate driving circuit region 203 may be provided only on one side of the display area 201, and the gate driving circuit may be provided only on one side of the display area.

[0032] Specifically, such as Figure 2 As shown, when the gate driving circuit region 203 includes a first gate circuit region 203a and a second gate circuit region 203b, the transfer line region 206 can include a first transfer line region 206a and a second transfer line region 206b. The first transfer line region 206a is disposed between the first gate circuit region 203a and the display region 201, and the second transfer line region 206b is disposed between the second gate circuit region 203b and the display region 201.

[0033] Specifically, Figure 2 The example given is that the gate drive circuit region 203 overlaps with the third corner region 202g and the fourth corner region 202h. However, the embodiments of this application are not limited to this. The gate drive circuit region 203 may not overlap with the third corner region 202g and the fourth corner region 202h.

[0034] Specifically, it is understood that the film layer of the portion of data line 33 disposed within the display area 201 is different from that disposed within the winding area 204. The portion of data line 33 disposed within the display area 201 and the portion disposed within the winding area 204 are connected through a cable replacement hole. Therefore, when the display panel 2 includes a multiplexing circuit area 205, the data line 33 will pass through the multiplexing circuit area 205. The position of the cable replacement hole corresponding to the data line 33 can be determined according to actual needs. It can be at the edge of the display area 201 near the winding area 204, at the edge of the winding area 204 near the display area 201, or in the multiplexing circuit area 205. This application embodiment does not limit this.

[0035] Specifically, Figure 2 The example given is that the winding area 204 overlaps with the first corner area 202e, the second corner area 202f and the lower border area 202c. However, the embodiments of this application are not limited to this. The winding area 204 may overlap only with the first corner area 202e and the second corner area 202f.

[0036] Specifically, the display area 201 is provided with multiple pixels, each of which may include a first sub-pixel unit, a second sub-pixel unit, and a third sub-pixel unit with different emission colors. The emission color of one of the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit is one of red, green, and blue. The emission color of another of the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit is one of the remaining three sub-pixel units. For example, the emission colors of the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit are red, green, or blue, respectively.

[0037] Specifically, when the emission colors of the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit are different, the emission colors of the emission parts of the light-emitting material layer corresponding to each sub-pixel can be the same or different. When the emission colors of the emission parts of the light-emitting material layer corresponding to each sub-pixel are the same, different emission colors of each sub-pixel unit can be achieved by setting color resistance. When the emission colors of the emission parts of the light-emitting material layer corresponding to each sub-pixel are different, color resistance can still be set to improve the color purity of each sub-pixel unit.

[0038] Specifically, multiple first sub-pixel units, multiple second sub-pixel units, and multiple third sub-pixel units can form multiple pixels. However, the embodiments of this application do not limit the arrangement of each sub-pixel unit. For example, the sub-pixel units adopt the realRGB pixel arrangement, that is, the sub-pixel units can be alternately set along the row direction, and the sub-pixel units in the same column have the same emission color. Or the sub-pixel units adopt the SPR pixel arrangement, that is, the red sub-pixel units and blue sub-pixels are alternately set along the row direction and the column direction, the row where the green sub-pixel is located is alternately set with the row where the red sub-pixel is located, and the column where the green sub-pixel is located is alternately set with the column where the red sub-pixel is located.

[0039] Specifically, each sub-pixel unit can be connected to a corresponding pixel driving circuit, which is equipped with a pixel driving transistor.

[0040] like Figure 3 As shown, this application embodiment provides a display panel, which includes a substrate 21 and a driving circuit layer.

[0041] Specifically, such as Figure 3 As shown, the driving circuit layer may include a light-shielding layer 221, a first insulating layer 222, an active layer 223, a first gate insulating layer 224, a gate layer 24, a second insulating layer 25, a source-drain layer 229, and a passivation layer 231.

[0042] Specifically, such as Figure 3 As shown, the gate layer 24 includes a first gate layer 225 and a second gate layer 227, and the second insulating layer 25 includes a second gate insulating layer 226 and an interlayer insulating layer 228.

[0043] Specifically, Figure 3 The present invention uses one structure of the driving circuit layer as an example for illustration, but the embodiments of this application are not limited thereto. The driving circuit layer may have only one gate layer or three gate layers; the driving circuit layer may have two or more source and drain layers; the driving circuit layer may not have a passivation layer 231; the driving circuit layer may include an active layer and a semiconductor layer. The active layer is formed using silicon semiconductor, and the semiconductor layer is formed using metal oxide semiconductor, such as indium gallium zinc oxide, which will not be described in detail here.

[0044] Specifically, when using active layers and semiconductor layers in the driving circuit layer, the transistors in the gate driving circuit can use active layers to form channels, while the transistors in the pixel driving circuit can use semiconductor layers to form channels. Alternatively, some transistors in the pixel driving circuit can use active layers to form channels, while others can use semiconductor layers to form channels. The transistors in the gate driving circuit can all use active layers to form channels, or some transistors can use active layers to form channels, while others can use semiconductor layers to form channels.

[0045] Specifically, when the display panel is an organic light-emitting diode display panel, the display panel 2 may also include a light-emitting functional layer, which may include a pixel electrode layer, a pixel definition layer, a light-emitting material layer, and a common electrode layer.

[0046] like Figures 2 to 10 As shown in the figure, this application embodiment provides a display panel 2, which includes a display area 201 and a non-display area 202. The non-display area 202 includes a gate driving circuit area 203 and a winding area 204. The winding area 204 is disposed between the gate driving circuit area 203 and the display area 201. The display panel 2 includes a data line 33 and a light-shielding pattern 31. The data line 33 is disposed within the winding area 204 and the display area 201, and the light-shielding pattern 31 is disposed within the gate driving circuit area 203 and the display area 201. The orthographic projection of the light-shielding pattern 31 is located outside the winding area 204, and there is a gap between the orthographic projection of the portion of the data line 33 located in the winding area 204.

[0047] like Figures 2 to 10 As shown, this application embodiment provides a display panel 2, which includes a display area 201 and a non-display area 202. The non-display area 202 includes a gate driving circuit area 203 and a winding area 204, with the winding area 204 disposed between the gate driving circuit area 203 and the display area 201. The display panel 2 includes a data line 33 and a first light-shielding pattern 311, with the data line 33 disposed within the winding area 204 and the display area 201, and the first light-shielding pattern 311 disposed within the non-display area 202. In the top view, the first light-shielding pattern 311 is located outside the winding area 204, and the first light-shielding pattern 311 and the data line 33 are spaced apart in the winding area 204.

[0048] This application provides a display panel in which, in a top view, the orthographic projection of the first light-shielding pattern 311 is located outside the winding area 204, and the first light-shielding pattern 311 and the data line 33 are partially spaced apart in the winding area 204. This prevents the light-shielding pattern 31 from overlapping with the data line 33 in the winding area 204, thereby reducing the risk of electrostatic discharge damage between the light-shielding pattern 31 and the data line 33 and improving the yield of the display panel.

[0049] Specifically, such as Figure 7 As shown, Figure 7Image (a) shows the structure of the light-shielding metal 11 in the comparative display device. It can be seen that a third light-shielding metal 112 is provided in the winding area and the demultiplexing circuit area. Multiple third light-shielding metals 112 are spaced apart, causing each third light-shielding metal 112 to overlap with the data trace 12 and the demultiplexing circuit. The overlap area is small, making capacitor breakdown more likely. Figure 7 As shown in (b) of this application embodiment, the light-shielding pattern 31 is disposed outside the winding area 204 and the multiplexing circuit area 205. The light-shielding pattern 31 will not overlap with the data line 33 in the winding area 204, nor with the multiplexing circuit in the multiplexing circuit area 205, thereby reducing the risk of electrostatic discharge injury.

[0050] Within the display area, the light-shielding pattern 31 overlaps with the data line 33. However, the second light-shielding pattern 312 within the display area 201 has a mesh design, which facilitates the diffusion of static electricity, reducing the risk of electrostatic discharge (ESD) damage. Furthermore, the data line 33 within the display area 201 is formed using a source-drain layer, increasing the distance between it and the second light-shielding pattern 312, further reducing the risk of ESD damage. Additionally, within the gate drive circuit area 203, the first light-shielding pattern 311 also has a mesh design, facilitating the diffusion of static electricity and reducing the risk of ESD damage to the display panel.

[0051] In some embodiments, such as Figures 2 to 10 As shown, the non-display area 202 also includes a multiplexed circuit area 205, which is disposed between the winding area 204 and the display area 201. In the top view, the first light-shielding pattern 311 is located outside the multiplexed circuit area 205. By positioning the orthographic projection of the first light-shielding pattern 311 outside the multiplexed circuit area 205, the light-shielding pattern 31 will not overlap with the multiplexed circuit 32 in the multiplexed circuit area 205, thus avoiding electrostatic discharge damage caused by the overlap of the light-shielding pattern 31 and the multiplexed circuit 32, and improving the yield of the display panel.

[0052] Specifically, a multiplexing circuit 32 can be set within the multiplexing circuit area 205, and the multiplexing circuit 32 can contain multiplexing transistors and multiplexing signal lines. In the comparison display device, the third light-shielding metal 112 passes through the multiplexing circuit area 205, causing the third light-shielding metal 112 to overlap with the active pattern of the multiplexing transistor, the gate of the multiplexing transistor, and the multiplexing signal lines. The active pattern of the multiplexing transistor is located on the active layer, and the gate of the multiplexing transistor and the multiplexing signal lines are located on the gate layer. The distance between the light-shielding metal 112 and the light-shielding layer is relatively small, which easily leads to capacitor breakdown and electrostatic discharge damage. In this embodiment, by making the light-shielding pattern 31 avoid the multiplexing transistors and multiplexing signal lines in the multiplexing circuit 32, the overlap between the light-shielding pattern 31 and the multiplexing circuit 32 is avoided, thus preventing electrostatic discharge damage and improving the yield of the display panel.

[0053] Specifically, Figures 2 to 10 The following description uses a display panel 2 including a multiplexed circuit area 205 as an example; however, the embodiments of this application are not limited to this. The display panel 2 may not have a multiplexed circuit, and correspondingly, the multiplexed circuit area 205 will not exist. In some embodiments, such as Figure 4 , Figure 5 As shown, the light-shielding pattern 31 includes a first light-shielding pattern 311, which is disposed within the gate driving circuit region 203. The display panel 2 also includes a high-potential power bus 34. Within the winding region 204, the orthographic projection of the high-potential power bus 34 overlaps with the orthographic projection of the data line 33. The high-potential power bus 34 is connected to the first light-shielding pattern 311. By setting the high-potential power bus 34 within the winding region 204, allowing the high-potential power bus 34 to overlap with the data line 33, no additional space is required. Furthermore, the connection between the high-potential power bus 34 and the first light-shielding pattern 311 ensures a stable signal input to the first light-shielding pattern 311, preventing unstable potential of the first light-shielding pattern 311 from affecting other signals.

[0054] Specifically, such as Figure 4 , Figure 5 As shown, the display panel 2 also includes a high-potential power bus 34. In the winding area 204, in the top view, the high-potential power bus 34 overlaps with the data line 33. The high-potential power bus 34 is connected to the first light-shielding pattern 311.

[0055] Specifically, since the first light-shielding pattern 311 and the second light-shielding pattern 312 located in the first corner area are not connected, in order to make the potential on the first light-shielding pattern 311 more stable and to prevent the first light-shielding pattern 311 from affecting the stability of other signals, the high-potential power bus 34 can be connected to the first light-shielding pattern 311 to input a high-potential power signal to the first light-shielding pattern 311, thereby preventing the first light-shielding pattern 311 from affecting other signals.

[0056] Specifically, the high-potential power bus 34 can be set on the source-drain layer, and the portion of the data line 33 located in the winding region 204 can be set on the gate layer, so that the high-potential power bus 34 and the data line 33 can overlap without short-circuiting, and will not occupy additional space, thus avoiding an excessively large bezel.

[0057] Specifically, it is understood that the signal of the high-potential power line needs to be input through the driver chip. Therefore, there will be a high-potential power bus between the driver chip and the high-potential power line to transmit the high-potential power signal. In this embodiment, the high-potential power bus is connected to the first light-shielding pattern 311 without the need for additional input signals or additional space, thus stabilizing the signal of the first light-shielding pattern 311.

[0058] Specifically, such as Figure 4 As shown, since the high-potential power bus 34 is located above the data line 33, therefore, Figure 4 The data line 33 is not visible, and the portion of the first light-shielding pattern 311 that connects to the high-potential power bus 34 is also blocked. Figure 4 To illustrate the first light-shielding pattern 311, it is shown on the high-potential power bus 34; however, in practice, the high-potential power bus 34 is positioned above the first light-shielding pattern 311. Meanwhile, to illustrate the position of the data line 33, Figure 5 The high-potential power bus 34 has been removed, which is understandable. Figure 5 In the middle, there is a high-potential power bus 34 above the data line 33.

[0059] In some embodiments, such as Figure 4 , Figure 5 As shown, a gate driving circuit 36 ​​is provided in the gate driving circuit region 203. The gate driving circuit 36 ​​includes a gate driving transistor 361. The first light-shielding pattern 311 includes a light-shielding part 311a, a bridging part 311b, and a connecting part 311c. The bridging part 311b connects the light-shielding part 311a and the connecting part 311c. The light-shielding part 311a is correspondingly disposed to the gate driving transistor 361. The connecting part 311c is connected to the high-potential power bus 34. By connecting the connecting part 311c to the high-potential power bus 34, the high-potential power bus 34 will not short-circuit with the signal lines in the gate driving circuit, thereby improving the yield of the display panel.

[0060] Specifically, a gate driving circuit 36 ​​is provided in the gate driving circuit region 203. The gate driving circuit 36 ​​is provided with a gate driving transistor 361 and a signal line. The light-shielding part 311a is arranged opposite to the gate driving transistor 361, which can block light and improve the stability of the gate driving transistor 361. The multiple light-shielding parts 311a can be understood to form a mesh, which improves the anti-static performance of the gate driving circuit region 203.

[0061] Specifically, such as Figure 4 , Figure 5 As shown, the bridging portion 311b is positioned opposite to the signal line in the gate drive circuit region 203. In the comparison display device, the bridging portion 311b is part of the third light-shielding metal 112, which is equivalent to the bridging portion 311b being directly connected to the first light-shielding metal 111. However, in this embodiment, the bridging portion 311b is connected to the connecting portion 311c and does not cross the winding region 204 and the multiplexing circuit region 205. This avoids the bridging portion 311b overlapping with the data line 33 and the multiplexing circuit 32, which could cause electrostatic discharge damage and improve the yield of the display panel.

[0062] Specifically, such as Figure 4 , Figure 5 As shown, the bridging portion 311b extends along the gate drive circuit region 203 toward the display region 201, and the connecting portion 311c extends along the extension direction of the first corner region.

[0063] Specifically, the connection portion 311c can be disposed on the edge of the gate drive circuit region 203 near the winding region 204. The connection portion 311c does not overlap with the signal lines in the gate drive circuit at least partially, and the high-potential power bus 34 does not overlap with the signal lines in the gate drive circuit.

[0064] In some embodiments, such as Figures 3 to 10 As shown, the display panel 2 includes a substrate 21, a light-shielding layer 221, a first insulating layer 222, a gate layer 24, a second insulating layer 25, and a source-drain layer 229. The light-shielding layer 221 is disposed on one side of the substrate 21 and includes the first light-shielding pattern 311. The first insulating layer 222 is disposed on the side of the light-shielding layer 221 away from the substrate 21. The gate layer 24 is disposed on the side of the first insulating layer 222 away from the light-shielding layer 221 and includes the portion of the data line 33 located in the winding region 204. The second insulating layer 25 is disposed on the side of the gate layer 24 away from the first insulating layer 222. The source-drain layer 229 is disposed on the side of the second insulating layer 25 away from the gate layer 24 and includes the high-potential power bus 34. The first insulating layer 222 has a first via 222a at the position corresponding to the connection portion 311c, and the second insulating layer 25 has a second via 226a at the position corresponding to the connection portion 311c. The high-potential power bus 34 passes through the second via 226a and the first via 222a and connects to the connection portion 311c.

[0065] Specifically, such as Figure 3 , Figure 5 As shown, the data line 33 is formed using a source-drain layer 229 within the display area 201. In the winding area 204, the data line 33 needs to be switched to the gate layer 24. Therefore, the distance between the portion of the data line 33 in the winding area 204 and the light-shielding pattern is shortened. Furthermore, if the light-shielding pattern is located in the winding area, the line width is relatively narrow, and the overlap area between the light-shielding pattern and the data line is small, making it prone to capacitor breakdown and electrostatic discharge (ESD) damage. Therefore, this embodiment of the application avoids the data line 33 by making the light-shielding pattern 31 avoid overlap between the two in the area between the gate drive circuit area 203 and the display area 201, thereby reducing the risk of ESD damage.

[0066] Specifically, such as Figure 3As shown, the gate layer 24 includes a first gate layer 225 and a second gate layer 227, the second insulating layer 25 includes a second gate insulating layer 226 and an interlayer insulating layer 228, the display panel 2 also includes an active layer 223 and a first gate insulating layer 224, and the high-potential power bus 34 passes through the vias of the interlayer insulating layer 228, the second gate insulating layer 226, the first gate insulating layer 224 and the first insulating layer 222 and is connected to the connection portion 311c.

[0067] Specifically, when the display panel has other structures, the high-potential power bus 34 can be connected to the connection part 311c through the corresponding via. For example, if the display panel includes two source-drain layers and the high-potential power bus 34 is disposed in the upper source-drain layer, the high-potential power bus 34 can be connected to the light-shielding pattern through multiple insulating layers in the lower layer.

[0068] Specifically, such as Figure 5 As shown, the portion of the data line 33 located in the winding region 204 includes a first data portion 331 and a second data portion 332. One of the first data portion 331 and the second data portion 332 is disposed on the first gate layer 225, and the other is disposed on the second gate layer 227, thereby reducing the space occupied by the data line 33.

[0069] Specifically, one of the first data portion 331 and the second data portion 332 is disposed on the first gate layer 225, and the other is disposed on the second gate layer 227. This arrangement, where the first data portion 331 and the second data portion 332 are disposed on different film layers, reduces the spacing between them, thereby reducing the space occupied. Alternatively, the first data portion 331 and the second data portion 332 can be staggered.

[0070] In some embodiments, such as Figure 5 , Figure 8 As shown, the first insulating layer 222 includes a plurality of first vias 222a, which are spaced apart; the second insulating layer 25 includes a plurality of second vias 226a, which are spaced apart; the orthographic projections of the first vias 222a and the second vias 226a overlap. Specifically, the spacing between any two adjacent first vias 222a is equal, and the spacing between any two adjacent second vias 226a is equal. By ensuring that the spacing between any two adjacent first vias 222a and any two adjacent second vias 226a is equal, stress concentration is avoided, reducing the risk of display panel failure.

[0071] Specifically, the first vias 222a and the second vias 226a can be set at equal intervals to disperse stress, avoid stress concentration caused by multiple first vias 222a concentrating in one area, and avoid stress concentration caused by multiple second vias 226a concentrating in one area, thereby reducing the risk of display panel failure.

[0072] Specifically, the vias of the first gate insulating layer can overlap with the first via 222a and the second via 226a, and can be set at equal intervals.

[0073] Specifically, the first via 222a and the second via 226a can be two parts of a single via, or they can be two independent vias.

[0074] In some embodiments, such as Figure 9 As shown, the first via 222a extends from one end of the connecting portion 311c to the other end of the connecting portion 311c, and the second via 226a extends from one end of the connecting portion 311c to the other end of the connecting portion 311c. By making the first via 222a and the second via 226a extend from one end of the connecting portion 311c to the other end of the connecting portion 311c, the first via 222a and the second via 226a form an elongated shape, which facilitates the connection of the high-potential power bus 34 to the first light-shielding pattern.

[0075] In some embodiments, such as Figure 2 As shown, the display panel further includes a second light-shielding pattern 312, which is disposed within the display area 201. The non-display area 202 further includes a transition area 206, which is disposed between the display area 201 and the gate driving circuit area 203. The transition area 206 has a connecting pattern 313, and the first light-shielding pattern 311 and the second light-shielding pattern 312 are connected through the connecting pattern 313. By connecting the first light-shielding pattern 311 and the second light-shielding pattern 312 through the connecting pattern 313, the first light-shielding pattern 311 and the second light-shielding pattern 312 can have the same potential, stabilizing the potential of the light-shielding pattern 31. Furthermore, the grid-like structure of the light-shielding pattern 31 facilitates the release of static electricity.

[0076] Specifically, in the display panel 2, since some signal lines in the gate driving circuit 36 ​​and some signal lines in the pixel driving circuit are located on different film layers but need to be connected, there is a line-swapping area between the gate driving circuit 36 ​​and the pixel driving circuit to connect the signal lines in the gate driving circuit 36 ​​and the signal lines in the pixel driving circuit. In this embodiment, the connection pattern 313 is set in this area, so that the first light-shielding pattern 311 and the second light-shielding pattern 312 are connected. This area does not contain the data line 33 and the multiplexing circuit, so there will be no electrostatic discharge damage.

[0077] Specifically, in the transition area 206, the connecting pattern 313 can extend along the direction from the gate drive circuit area 203 to the display area 201. The portions of the first light-shielding pattern 311 located in the left and right frame areas may not have a connecting portion 311c, but can be connected to the connecting pattern 313 through a bridging portion 311b, thereby connecting the first light-shielding pattern 311 and the second light-shielding pattern 312.

[0078] Specifically, the connecting pattern 313 may not be provided in the transition area 206, so that the part of the first light-shielding pattern 311 located in the left and right frame areas includes the connecting part 311c, and a trace for transmitting high-potential power signals, such as a high-potential power bus, is provided to connect the first light-shielding pattern 311 through the high-potential power bus.

[0079] In some embodiments, such as Figure 6 , Figure 10 As shown, the display panel 2 also includes a high-potential power line 35, which is connected to the high-potential power bus 34. The high-potential power line 35 is disposed within the display area 201 and connected to the second light-shielding pattern 312. By connecting the high-potential power line 35 to the second light-shielding pattern 312, the signal of the second light-shielding pattern 312 is stabilized, preventing the second light-shielding pattern 312 from affecting other signals. Furthermore, the impedance of the high-potential power line 35 is reduced, improving the electrical performance of the display panel.

[0080] Specifically, such as Figure 4 , Figure 6 As shown, the second light-shielding pattern 312 is arranged in a mesh pattern within the display area, and the second light-shielding pattern 312 is positioned opposite to the pixel driving transistor in the pixel driving circuit. Figure 10 As shown, the second light-shielding pattern 312 is connected to the high-potential power line 35, which can stabilize the signal of the second light-shielding pattern 312 and prevent the second light-shielding pattern 312 from affecting other signals.

[0081] Specifically, when setting the light-shielding pattern 31, the light-shielding pattern 31 may include a first light-shielding pattern 311 located in the gate driving circuit region 203 and a second light-shielding pattern 312 located in the display region 201. The structure of the first light-shielding pattern 311 in the left and right frame regions may be the same as or different from the structure of the first light-shielding pattern 311 in the first and second corner regions. For example, the portion of the first light-shielding pattern 311 in the left and right frame regions may only include a light-shielding part 311a and a bridging part 311b, and the bridging part 311b is connected to the second light-shielding pattern 312 through a connecting pattern 313. The portion of the first light-shielding pattern 311 in the first and second corner regions includes a light-shielding part 311a, a bridging part 311b, and a connecting part 311c. Alternatively, the first light-shielding pattern 311 may include a light-shielding part 311a, a bridging part 311b, and a connecting part 311c in the left frame area, the right frame area, the first corner area, and the second corner area, but the light-shielding pattern 31 is not disposed in the area between the gate drive circuit area 203 and the display area 201.

[0082] Specifically, in the first corner region 202e and the second corner region 202f, the light-shielding pattern 31 can be excluded from the area between the gate drive circuit region 203 and the display region 201.

[0083] Specifically, the above embodiments have provided a detailed description of the display panel from aspects such as the film layer structure of the display panel, the specific design of each film layer, and the specific design of each structure. It is understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the non-display area also includes a multiplexed circuit area, which is disposed between the winding area and the display area. The orthographic projection of the light-shielding pattern is located outside the multiplexed circuit area. The light-shielding pattern includes a first light-shielding pattern, which is disposed within the gate driving circuit area. The display panel also includes a high-potential power bus. Within the winding area, the orthographic projection of the high-potential power bus overlaps with the orthographic projection of the data line. The high-potential power bus is connected to the first light-shielding pattern, which will not be elaborated further here.

[0084] Meanwhile, this application provides a display device, which includes a display panel as described in any of the above embodiments.

[0085] Specifically, the display device may also include a power supply, a housing, and other structures.

[0086] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0087] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0088] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0089] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, It includes a display area and a non-display area, wherein the non-display area includes a gate driving circuit area and a winding area, and the winding area is disposed between the gate driving circuit area and the display area; The display panel includes a data cable and a first light-shielding pattern. The data cable is disposed in the winding area and the display area, and the first light-shielding pattern is disposed in the non-display area. In the top view, the first light-shielding pattern is located outside the winding area, and the first light-shielding pattern is spaced apart from the portion of the data line located in the winding area.

2. The display panel according to claim 1, characterized in that, The non-display area also includes a multiplexed circuit area, which is disposed between the winding area and the display area; In the top view, the first light-shielding pattern is located outside the multiplexing circuit area.

3. The display panel according to claim 1 or 2, characterized in that, The display panel also includes a high-potential power bus. In the winding area, in a top view, the high-potential power bus overlaps with the data line, and the high-potential power bus is connected to the first light-shielding pattern.

4. The display panel according to claim 3, characterized in that, The gate driving circuit area is provided with a gate driving circuit, which includes a gate driving transistor. The first light-shielding pattern includes a light-shielding part, a bridging part, and a connecting part. The bridging part connects the light-shielding part and the connecting part. The light-shielding part is correspondingly arranged with the gate driving transistor. The connecting part is connected to the high-potential power bus.

5. The display panel according to claim 4, characterized in that, The display panel includes: Substrate; A light-shielding layer is disposed on one side of the substrate, and the light-shielding layer includes the first light-shielding pattern; A first insulating layer is disposed on the side of the light-shielding layer away from the substrate; A gate layer is disposed on the side of the first insulating layer away from the light-shielding layer, and the gate layer includes the portion of the data line located in the winding region; A second insulating layer is disposed on the side of the gate layer away from the first insulating layer; A source-drain layer is disposed on the side of the second insulating layer away from the gate layer, and the source-drain layer includes the high-potential power bus; The first insulating layer has a first via at the position corresponding to the connection part, and the second insulating layer has a second via at the position corresponding to the connection part. The high-potential power bus passes through the second via and the first via and connects to the connection part.

6. The display panel according to claim 5, characterized in that, The first insulating layer includes a plurality of first vias, which are spaced apart; the second insulating layer includes a plurality of second vias, which are spaced apart; the orthographic projections of the first vias and the second vias overlap. The spacing between any two adjacent first vias is equal, and the spacing between any two adjacent second vias is equal.

7. The display panel according to claim 5, characterized in that, The first through hole extends from one end of the connecting portion to the other end of the connecting portion, and the second through hole extends from one end of the connecting portion to the other end of the connecting portion.

8. The display panel according to claim 3, characterized in that, The display panel further includes a second light-shielding pattern, which is disposed within the display area; The non-display area also includes a transition area, which is disposed between the display area and the gate driving circuit area. The transition area is provided with a connection pattern, and the first light-shielding pattern and the second light-shielding pattern are connected by the connection pattern.

9. The display panel according to claim 8, characterized in that, The display panel also includes a high-potential power line, which is connected to the high-potential power bus. The high-potential power line is disposed within the display area and connected to the second light-shielding pattern.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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