Integrated photonic platform and circuit and method of manufacture

Abstract

The invention provides a method for manufacturing an integrated photonic platform, comprising: providing a substrate; depositing a lower cladding made of a first material on the substrate; depositing a photonic layer made of a second material on the lower cladding; and patterning the photonic layer to form a waveguide portion and an etch stop portion, wherein the waveguide portion is formed to guide a defined optical mode substantially inside the second material, wherein the etch stop portion is formed as a defined region of the photonic layer. The invention further provides a method for manufacturing an integrated photonic platform, comprising: etching a portion of an upper cladding made of the first material on the photonic layer by using a second etchant to at least partially expose the etch stop portion of the photonic layer, thereby forming a cavity; and etching the exposed portion of the etch stop portion of the photonic layer by using a first etchant to expose the lower cladding. Furthermore, the invention also provides a corresponding integrated photonic platform and a corresponding integrated photonic circuit.

Description

Technical Field

[0001] This invention relates to integrated photonic platforms and integrated photonic circuits, as well as corresponding methods for manufacturing such integrated photonic platforms and integrated photonic circuits. Background Technology

[0002] To integrate active components onto a photonic platform, minimizing any potential spatial misalignment between optical modes traveling through waveguides on the platform and other optical modes traveling in and out of active sub-components integrated on the photonic substrate is crucial. For efficient coupling of optical modes to the waveguides, the active components need to be precisely positioned relative to the waveguides on the photonic platform to minimize coupling losses. For the in-plane orientation, masks and other techniques are typically used precisely for the active components on the platform. However, control in the vertical direction (i.e., the direction towards the depth of the substrate) remains challenging for this placement.

[0003] Therefore, the object of the present invention is to provide an improved method for placing active components on an integrated photonic platform. Summary of the Invention

[0004] According to the invention, this problem is addressed in each case by the subject matter of the independent claims.

[0005] According to a first aspect of the present invention, a method for manufacturing an integrated photonic platform is provided. The method includes: providing a substrate; depositing a lower cladding layer made of a first material on the substrate; depositing a photonic layer made of a second material on the lower cladding layer; and patterning the photonic layer to form waveguide portions and etch-stop portions, wherein the waveguide portions are formed to guide defined optical patterns substantially within the second material, and wherein the etch-stop portions are formed as defined regions of the photonic layer.

[0006] According to a second aspect of the invention, a method for manufacturing an integrated photonic circuit is provided. The method includes providing an integrated photonic platform, particularly by means of the method of the invention, which includes a waveguide structure disposed on a substrate. The waveguide structure includes a lower cladding layer made of a first material disposed on the substrate, a photonic layer made of a second material disposed on the lower cladding layer, and an upper cladding layer made of the first material disposed on the photonic layer. The photonic layer includes a waveguide portion and an etch-stop portion, wherein the waveguide portion is configured to guide defined optical modes substantially within the second material. The etch-stop portion is configured as a defined region of the photonic layer. The first material is configured as an etch stop for a first etchant, and the second material is configured as an etch stop for a second etchant. The method further includes forming a cavity by etching a portion of the upper cladding layer using the second etchant to at least partially expose the etch-stop portion of the photonic layer; and exposing the lower cladding layer by etching the exposed portion of the etch-stop portion of the photonic layer using the first etchant.

[0007] According to a third aspect of the present invention, an integrated photonic platform is provided. The integrated photonic platform includes a substrate, a lower cladding layer made of a first material disposed on the substrate, and a photonic layer made of a second material disposed on the lower cladding layer. The photonic layer includes a waveguide portion and an etch-stop portion. The waveguide portion is configured to guide defined optical modes substantially within the second material. The etch-stop portion is a defined region of the photonic layer.

[0008] According to a fourth aspect of the present invention, an integrated photonic circuit is provided. The integrated photonic platform includes a waveguide structure disposed on a substrate. The waveguide structure includes a lower cladding layer made of a first material disposed on the substrate, a photonic layer made of a second material disposed on the lower cladding layer, and an upper cladding layer made of the first material disposed on the photonic layer. The photonic layer has a waveguide portion configured to guide defined optical modes substantially within the second material, wherein the second material is configured as an etch stop layer for a second etchant. A cavity is formed in the waveguide structure, extending into the upper cladding layer and the photonic layer to expose the lower cladding layer.

[0009] The basic idea of ​​this invention is to use a portion of the photonic layer as an etch stop for etching down to a well-defined depth in the first etch step, which would otherwise be difficult due to variations in the thickness of the upper cladding. By using a second etch step with a different etchant, only the etch stop portion of the photonic layer with a well-defined thickness is etched, allowing the etching to stop precisely at the lower cladding.

[0010] The basic concept of this invention is to define a portion or a portion of a photonic layer that serves as an etch stop when etching a cavity in the upper cladding. This portion can be used to expose a defined portion of a waveguide within the photonic layer. This may be necessary, for example, in biosensing applications, where the method can be applied to remove most of the upper cladding to expose a second waveguide beneath an etch stop portion containing biomolecules, thereby enabling biosensing applications.

[0011] The etch stop portion can also be used, at least partially, as a placeholder for subsequent placement of optical components after the etch stop portion itself has been removed by a second etch step. This etch stop portion of the photonic layer is positioned adjacent to the waveguide, such that by placing the optical components in place, optical modes can be coupled from the active component into the waveguide, and vice versa.

[0012] A particular advantage of the solution according to one aspect of the invention is that the depth of the etching process can be controlled with exceptionally high precision. Therefore, it is highly efficient to couple active components, such as lasers, into the waveguide portion of the photonic layer. Thus, the photonic layer serves both as a photonic waveguide and as an etch stop for integration, thereby allowing the integration of external sub-components into a cavity with virtually zero vertical misalignment.

[0013] It should be understood that a "layer" can consist of multiple sublayers, and a layer disposed on a substrate or another layer can relate to other layers between these layers. A photonic layer can therefore include multiple waveguide portions defining multiple waveguide cores. These can also be arranged adjacent to each other or above or below each other in a layer stack comprising multiple cladding layers. Multiple such photonic layers can also be provided. It should also be understood that the naming of photonic devices (i.e., integrated photonic platforms and integrated photonic circuits) has been chosen, such as "platform" indicating a device prior to any local etching process of the cladding. Therefore, an integrated photonic platform is provided for fabricating integrated photonic circuits by applying local etching processes using first and second etchants, as described in the corresponding method according to the second aspect of the invention.

[0014] To fabricate integrated photonic circuits suitable for this application, it is important that a first material is selected as the etch stop for a first etchant, and a second material is selected as the etch stop for a second etchant. In the method of this invention, these properties of the two materials are selected to selectively etch a defined region to a defined depth. A typical first etchant would be, for example, hydrofluoric acid (HF) or selective dry etching, such as dry plasma etching, using CH4, CHF3, SF6, etc., or combinations thereof, while a typical second etchant would be, for example, phosphoric acid (H3PO4) or combinations thereof. The first and second etchants may also include similar portions or components.

[0015] According to an embodiment of the first aspect of the invention, the etch stop portion is formed as a defined region configured as a placeholder for integrating optical components. Therefore, in this case, the etch stop portion is not limited to a waveguide for a specific defined pattern, but can be an area to be etched subsequently. The optical components can be passive optical components (such as microlenses or micromirrors) or active components (such as lasers or detectors). Active components typically have an active region that needs to be coupled to a waveguide portion of the photonic layer, as will be further described below.

[0016] According to an embodiment of the first aspect of the invention, the first material is silicon dioxide (SiO2), and the second material is silicon nitride (SiN). These two materials provide good refractive index contrast for optical modes propagating in the photonic layer with low loss.

[0017] According to an embodiment of the first aspect of the invention, the method further includes annealing the waveguide portion at a temperature greater than or equal to 900 degrees Celsius. A key technical aspect of this disclosure stems from this annealing process. When annealing at high temperatures, the typical etch stop layer is annealed, which usually results in relatively high roughness of the exposed surface. However, particularly by using a SiN layer as the photonic etch stop portion, the annealing step has the dual or synergistic advantage of reducing propagation losses in the silicon nitride material (i.e., by exhausting residual hydrogen) and preventing mixing with adjacent layers such as the silicon dioxide cladding. Therefore, this process allows the exposed surface to maintain very low surface roughness after post-annealing, which is desirable for bonding and reduced propagation losses.

[0018] According to an embodiment of a first aspect of the invention, the method further includes depositing an upper cladding layer made of a first material on the photonic layer to define a waveguide structure comprising a lower cladding layer, a photonic layer, and an upper cladding layer. Compared to an air-top surface, control over optical modes propagating substantially within the photonic layer can be improved.

[0019] According to an embodiment of a second aspect of the invention, the method further includes etching the cavity portion of the lower cladding to a predetermined depth using a first etchant. This is necessary, for example, for active components having an active region within a stack of layers, wherein the active region is within the stack and not necessarily immediately above the lowest cladding. The active region, which should be coupled to the waveguide portion, therefore requires a certain depth in the lower cladding to achieve effective optical coupling, which may be referred to in the literature as butt coupling or edge coupling. This etching process allows for very precise control of the depth, thereby achieving effective edge coupling at virtually any height of the active region of the active component.

[0020] According to an embodiment of the second aspect of the invention, when the upper cladding is etched using a second etchant, the upper cladding is etched on the portion of the photonic layer that has been removed, such that a portion of the lower cladding is exposed adjacent to the etch stop portion and the waveguide portion. The exposed portion of the lower cladding may be arranged on the lateral side of the portion of the waveguide exposed after the upper cladding has been etched using the second etchant. This supports alignment of the etch stop portion perpendicular to the waveguide portion (or at a predetermined angle to reduce reflection).

[0021] According to an embodiment of the second aspect of the invention, when the etch stop portion is etched, a waveguide tip suitable for optical edge coupling is formed in the cavity. The waveguide tip thus represents an interface for optical modes propagating from the waveguide portion of the photonic layer to the active region of the active component, or vice versa.

[0022] According to an embodiment of a second aspect of the invention, the method further includes bonding an optical component having an active region to the surface of the exposed lower cladding layer, such that an optical mode from the waveguide portion is optically coupled to the active region of the active component. The optical component may be a passive optical component, such as a microlens or micromirror, or it may be an active component, such as a laser, an electro-optic modulator, or any other photonic component, such as a detector, a filter, etc.

[0023] According to an embodiment of the second aspect of the invention, the active region of the active component is optically coupled to the waveguide portion through a waveguide tip formed at the edge of the cavity.

[0024] According to an embodiment of a third aspect of the present invention, the integrated photonic platform further includes an upper cladding layer made of a first material on the photonic layer, the upper cladding layer defining a waveguide structure including a lower cladding layer, a photonic layer, and an upper cladding layer.

[0025] The first material is silicon dioxide (SiO2), and the second material is preferably silicon nitride (SiN). As mentioned above, these two materials provide good refractive index contrast for optical modes propagating in the photonic layer with low loss.

[0026] According to an embodiment of the fourth aspect of the invention, the cavity extends into the lower cladding at a predetermined depth. As mentioned above, this is necessary, for example, for active components having an active region within a stack of layers, where the active region is not the bottommost layer in the stack. Therefore, the active region that should be coupled into the waveguide portion requires a certain depth in the lower cladding to achieve effective coupling. This etching process allows for very precise control of the depth, thereby achieving effective coupling of the active region of the active component at virtually any height.

[0027] According to an embodiment of a fourth aspect of the invention, the integrated photonic circuit further includes optical components bonded to the surface of the exposed lower cladding. As described above, the optical components can be passive or active optical components. In the latter case, the active component includes an active region optically coupled to the waveguide portion. The active component can be a laser, an electro-optic modulator, or any other photonic component, such as a detector, an active filter, etc.

[0028] If appropriate and technically meaningful, the above embodiments and further modifications can be combined with each other as needed. In particular, all features of the methods for manufacturing integrated photonic platforms and circuits can be transferred to the integrated photonic platforms and circuits, and vice versa. Other possible aspects, further modifications, and implementations of the invention include combinations of features of the invention described above or below with respect to examples of embodiments not explicitly mentioned. In particular, those skilled in the art will also add various aspects as improvements or additions to the corresponding basic forms of the invention.

[0029] Advantageous implementation schemes and further improvements emerge from the description with reference to the accompanying drawings. Attached Figure Description

[0030] The invention is explained in more detail below based on exemplary embodiments indicated in the schematic diagrams, wherein:

[0031] Figure 1 A flowchart illustrating a method for manufacturing an integrated photonic platform and integrated photonic circuits according to an embodiment of the present invention is shown;

[0032] Figures 2a to 2b A schematic diagram showing a side view and a top view of an integrated photonic platform according to an embodiment of the present invention is provided;

[0033] Figures 3a to 3b A schematic diagram showing a side view and a top view of an integrated photonic platform according to an embodiment of the present invention is provided;

[0034] Figures 4a to 4b A schematic diagram showing a side view and a top view of an integrated photonic circuit according to an embodiment of the present invention is provided;

[0035] Figures 5a to 5b A schematic diagram showing a side view and a top view of an integrated photonic circuit according to an embodiment of the present invention is provided;

[0036] Figures 6a to 6b A schematic diagram showing a side view and a top view of an integrated photonic circuit according to an embodiment of the present invention is provided; and

[0037] Figures 7a to 7b Schematic diagrams of a side view and a top view of an integrated photonic circuit according to an embodiment of the present invention are shown.

[0038] The accompanying drawings are intended to convey a further understanding of embodiments of the invention. They illustrate embodiments and are used in conjunction with the description to explain the principles and concepts of the invention. Other embodiments and numerous advantages are presented with reference to the drawings. Elements in the drawings are not necessarily shown to scale relative to each other. Directional designations such as “at the top,” “at the bottom,” “on the left,” “on the right,” “above,” “below,” “horizontally,” “vertically,” “in front,” “in rear,” and similar statements are for illustrative purposes only and are not intended to limit the generality to the specific configuration shown in the figures.

[0039] In the accompanying drawings, unless otherwise specified, identical elements, features, and parts that have the same function and effect are each given the same reference numerals. Detailed Implementation

[0040] Figure 1 A flowchart illustrating a method for manufacturing an integrated photonic platform and integrated photonic circuits according to an embodiment of the present invention is shown.

[0041] The method for manufacturing the integrated photonic platform 1 includes the step of providing an M11 substrate 4. The substrate can be any suitable material, such as silicon of any crystal type from the corresponding wafer.

[0042] In the next step, a lower cladding layer 3 made of a first material, M12, is deposited on the substrate 4. Furthermore, a photonic layer 2 made of a second material, M13, is deposited on the lower cladding layer 3. In a preferred embodiment, the first material is silicon dioxide (SiO2), and the second material is silicon nitride (SiN). Therefore, the second material has a higher refractive index than the first material, allowing it to be used as a waveguide core for optical modes that propagate substantially within the photonic layer 2.

[0043] In a further step, photonic layer 2 is patterned M14 to form waveguide portion 21 and etch stop portion 22. This means that a portion of photonic layer 2 is removed to form two portions 21, 22. This can be done by an etching process or other means, such as laser ablation. Waveguide portion 21 is formed to guide defined optical modes substantially within a second material. Waveguide portion 21 thus represents the core of a functional photonic circuit to guide defined modes through the waveguide. The defined modes can be purely optical modes, or they can be a defined superposition of optical modes, such as a few-mode waveguide. Etch stop portion 22 is formed as a defined region of photonic layer 2. In some embodiments that may be relevant to biosensing applications, it may be necessary to remove most of the upper cladding to expose biomolecules in the second waveguide beneath etch stop portion 21. This can be used to enable biosensing applications that detect the activation of specific biomolecules in waveguide portion 21.

[0044] In some embodiments, the etch stop portion may be configured as a placeholder for integration of the optical component 8. In some embodiments, the optical component 8 is a passive optical component, such as a microlens or micromirror, and is configured to couple light into or decouple light from a waveguide portion of the photonic layer. In some embodiments, the optical component 8 is configured as an active component 8. In the following examples, the etch stop portion 22 has a rectangular or square shape in a top view of the integrated photonic platform 1 to match the coverage area of ​​the passive or active component 8. The etch stop portion 22 should be etched and is not intended to guide a defined optical pattern.

[0045] In a preferred embodiment, the method further includes an annealing step of the waveguide portion 21 at a temperature greater than or equal to 900 degrees Celsius. Figure 1 (Not shown in the image). Due to the annealing process, the propagation loss of waveguide section 21 will be reduced to enable hydrogen diffusion and prevent mixing with the lower cladding layer 3. In addition, low surface roughness of photonic layer 2 and lower cladding layer 3 will be ensured, which may be advantageous for subsequent bonding steps.

[0046] In a preferred embodiment of the method for manufacturing an integrated photonic platform, an upper cladding layer 5 made of a first material is deposited on the photonic layer 2 as M15. This defines a waveguide structure 6 comprising a lower cladding layer 3, the photonic layer 2 (particularly excluding the etch stop portion 22), and the upper cladding layer 5.

[0047] Thus, an integrated photonic platform 1 is provided via step M1. To fabricate the final integrated photonic circuit 10 usable in this application, it is important that a first material is selected as the etch stop for a first etchant, and a second material is selected as the etch stop for a second etchant. In a further step of the method, these properties of the two materials are selected to selectively etch a defined region to a defined depth. A typical first etchant would be, for example, hydrofluoric acid (HF) or selective dry etching, such as dry plasma etching using CH4, CHF3, SF6, etc., or combinations thereof, while a typical second etchant would be, for example, phosphoric acid (H3PO4) or combinations thereof. Although the first etchant differs from the second etchant, both the first and second etchants may include similar portions or components.

[0048] Therefore, in the following steps, a first etching is performed. A portion of the cladding 5 on M2 is etched using a second etchant to at least partially expose the etch stop portion 22 of the photonic layer 2, thereby forming the cavity 7.

[0049] In some embodiments, when the upper cladding 5 of M2 is etched using a second etchant, the upper cladding 5 is etched on the removed portion of the photonic layer 2, exposing a portion 31 of the lower cladding 3 adjacent to the etch stop portion 22 and the waveguide portion 21. In some of these embodiments, the exposed portion 31 of the lower cladding 3 is disposed on the lateral side of a portion 211 of the waveguide portion 211 exposed after the upper cladding 5 has been etched using a first etchant. This portion 211 later forms a waveguide tip 212, which allows optical modes to be coupled from another optical component 8 into and from the waveguide portion 21 to another optical component 8. The waveguide tip 212 is suitable for optical edge coupling, also known as butt coupling. The exposed portion 31 of the lower cladding 3 can be used to ensure alignment of the waveguide portion 211 with at least one of the sidewalls of the cavity 7.

[0050] Then, a second etching of M3 is performed using another first etchant. The exposed portion of the etch stop portion 22 of the photonic layer 2 of M3 is etched by using the first etchant to expose the lower cladding 3. As previously described, in a preferred embodiment, when the etch stop portion 22 of M3 is etched, a waveguide tip 212 is formed in the cavity 7. The waveguide tip 212 serves as an interface between the waveguide portion 21 and the active region 81 of the active component 8, which serves as an optical component 8 to be placed in the cavity 7.

[0051] In a preferred embodiment, a portion of the lower cladding 3 within the cavity 7 is further etched to a predetermined depth D using a second etchant. The depth D can be controlled very precisely through this third etching process. This is often necessary for optical components (particularly active components 8, whose active regions are not located at the bottom of component 8).

[0052] In subsequent steps of these embodiments, the optical component 8 having the active region 81 is bonded to the exposed surface 32 of the lower cladding 3. In some embodiments, the optical component 8 is an active component 8 having the active region 81. The active component 8 is bonded M5 such that optical modes from the waveguide portion 21 are optically coupled to the active region 81 of the optical component 8. Known bonding techniques can be applied to form a strong bond between the optical component 8 and the surface 32 of the lower cladding 3.

[0053] In some embodiments, the active component 8 is a laser that includes a gain region as the active region 81. In other embodiments, the active component 8 is an electro-optic modulator, such as including a Pockels cell as the active region 81. In still other embodiments, the active component 8 is a detector.

[0054] In these embodiments, the active region 81 of the component 8 is typically optically coupled to the waveguide portion 21 via a waveguide tip 212 formed in the cavity 7.

[0055] Figures 2a to 2b A schematic diagram showing a side view and a top view of an integrated photonic platform 1 according to an embodiment of the present invention is provided.

[0056] Figure 2a A side view of the integrated photonic platform 1 is shown, i.e., a cross-sectional view in the XY plane. Figure 2b A top view of the integrated photonic platform 1 in the XZ plane is shown. The illustrated embodiment of the integrated photonic platform 1 is based on and compatible with the method for manufacturing the integrated photonic platform 1 as described above.

[0057] Figure 2a and Figure 2b The integrated photonic platform 1 shown includes a substrate 4. As previously mentioned, a suitable substrate may be silicon. The integrated photonic platform 1 includes a lower cladding layer 3 made of a first material disposed on the substrate 4. Furthermore, the integrated photonic platform 1 includes a photonic layer 2 made of a second material disposed on the lower cladding layer 4. In a preferred embodiment, the first material is silicon dioxide (SiO2), and the second material is silicon nitride (SiN).

[0058] The photonic layer 2 includes a waveguide portion 21 and an etch-stop portion 22, wherein the waveguide portion 21 is configured to guide a defined optical mode substantially within a second material, and the etch-stop portion 22 is a defined region of the photonic layer 2. In some embodiments, the etch-stop portion is configured as a placeholder for the optical component 8. In the illustrated embodiment, the etch-stop portion 22 is shown in a top view (i.e., Figure 2b In the XZ plane, it is rectangular or square. The waveguide section 21 is represented as a waveguide, which can be... Figure 2b The YZ plane has a cross-sectional area suitable for a defined mode (such as a single mode).

[0059] Figures 3a to 3b A schematic diagram showing a side view and a top view of an integrated photonic platform 1 according to an embodiment of the present invention is provided.

[0060] Figure 3a A side view of the integrated photonic platform 1 is shown, i.e., a cross-sectional view in the XY plane. Figure 3b A top view of the integrated photonic platform 1 in the XZ plane is shown. The illustrated embodiment of the integrated photonic platform 1 is based on and compatible with the method for manufacturing the integrated photonic platform 1 as described above.

[0061] The integrated photonic platform 1 also includes an upper cladding layer 5, which is made of a first material and deposited on the photonic layer 2. The resulting structure thus defines a waveguide structure 6 comprising a lower cladding layer 3, the photonic layer 2, and the upper cladding layer 5.

[0062] As described above, in the preferred embodiment, the first material is preferably silicon dioxide (SiO2), and the second material is preferably silicon nitride (SiN). Furthermore, upon exposure, SiN can be annealed at a temperature of approximately 900 degrees Celsius or higher. This results in the depletion of residual hydrogen from the material, thereby reducing propagation losses in the SiN waveguide portion 21. It further reduces surface roughness, limiting intermingling with adjacent SiO2 layers, which is desirable for further bonding processes.

[0063] Figures 4a to 4b A schematic diagram showing a side view and a top view of an integrated photonic circuit 10 according to an embodiment of the present invention is provided.

[0064] Figure 4a A side view of the integrated photonic circuit 10 is shown, i.e., a cross-sectional view in the XY plane. Figure 4b A top view of the integrated photonic circuit 10 in the XZ plane is shown. The illustrated embodiment of the integrated photonic circuit 10 is based on and compatible with the method for manufacturing the integrated photonic circuit 10 as described above.

[0065] The integrated photonic circuit 10 shown is based on, as in the reference... Figure 2a and Figure 2b ,as well as Figure 3a and Figure 3b The described integrated photonic platform 1. The integrated photonic circuit 10 includes a waveguide structure 6 disposed on a substrate 4. The waveguide structure 6 includes a lower cladding layer 3 made of a first material disposed on the substrate 4, a photonic layer 2 made of a second material disposed on the lower cladding layer 3, and an upper cladding layer 5 made of the first material disposed on the photonic layer 2. As in a previous embodiment, the photonic layer 2 has a waveguide portion 21 configured to guide a defined optical mode substantially within the second material. According to the previously described method for manufacturing such an integrated photonic circuit, the second material is configured as an etch stop layer for a second etchant.

[0066] exist Figure 4a The diagram illustrates the formation of a cavity 7 within the waveguide structure 6. The cavity can be formed via the method step M2 described above, wherein M2 is etched through a portion of the upper cladding 5 using a second etchant to at least partially expose the etch stop portion 22 of the photonic layer 2. The resulting cavity 7 extends within the upper cladding 5. Figure 4a The cavity 7 shown can be formed by performing an etching step M2. Therefore, Figure 4a and Figure 4b The integrated photonic circuit 10 shown represents an intermediate product after the above-described method step M2 has been performed.

[0067] It should be noted that when the upper cladding 5 of M2 is etched using the second etchant, the upper cladding 5 is etched on the removed portion of the photonic layer 2, exposing a portion 31 of the lower cladding 3 adjacent to the etch stop portion 22 and the waveguide portion 21. In this embodiment, the exposed portion 31 of the lower cladding 3 is arranged on the lateral side of portion 211 of the waveguide portion 21, which is exposed after the upper cladding 5 is etched using the second etchant.

[0068] Figures 5a to 5b A schematic diagram showing a side view and a top view of an integrated photonic circuit 10 according to an embodiment of the present invention is provided.

[0069] Figure 5a A side view of the integrated photonic circuit 10 is shown, i.e., a cross-sectional view in the XY plane. Figure 5b A top view of the integrated photonic circuit 10 in the XZ plane is shown. The illustrated embodiment of the integrated photonic circuit 10 is based on and compatible with the method for manufacturing the integrated photonic circuit 10 as described above.

[0070] Figure 5a and Figure 5b The integrated photonic circuit 10 shown represents an intermediate product after the above-described method step M3 has been performed. Here, the exposed portion of the etch stop portion 22 of the M3 photonic layer 2 is etched using a first etchant to expose the surface 32 of the lower cladding layer 3.

[0071] It should also be noted that not all etch-stop portions 22 have been etched in the second etch step M3; instead, the embedded portions 222 remain below the upper cladding 5 adjacent to the cavity 7. This ensures that the predetermined depth D of the exposed surface 32 of the lower cladding 3 can be uniformly formed in the subsequent etch steps M3 and, optionally, M4.

[0072] Figures 6a to 6b A schematic diagram showing a side view and a top view of an integrated photonic circuit 10 according to an embodiment of the present invention is provided.

[0073] Figure 6a A side view of the integrated photonic circuit 10 is shown, i.e., a cross-sectional view in the XY plane. Figure 6b A top view of the integrated photonic circuit 10 in the XZ plane is shown. The illustrated embodiment of the integrated photonic circuit 10 is based on and compatible with the method for manufacturing the integrated photonic circuit 10 as described above.

[0074] Figure 6a and Figure 6b The integrated photonic circuit 10 shown represents an intermediate product after the optional method step M4 described above has been performed. Whether step M4 (i.e., the third etching using the second etchant) is performed depends on the location of the active region 81 of the active component 8 to be placed in the cavity 7 on the exposed surface 32, as follows: Figure 7a and Figure 7b As described in [the document]. However, in most applications, the active region is within the layer stack, thus typically requiring an etching step M4.

[0075] As can be seen, in this embodiment, cavity 7 extends into the lower cladding 3 at a predetermined depth D. Such a depth can be etched in the order of several μm with an accuracy of less than 100 nm, preferably less than 20 nm.

[0076] Figures 7a to 7b A schematic diagram showing a side view and a top view of an integrated photonic circuit 10 according to an embodiment of the present invention is provided.

[0077] Figure 7a A side view of the integrated photonic circuit 10 is shown, i.e., a cross-sectional view in the XY plane. Figure 7b A top view of the integrated photonic circuit 10 in the XZ plane is shown. The illustrated embodiment of the integrated photonic circuit 10 is based on and compatible with the method for manufacturing the integrated photonic circuit 10 as described above.

[0078] therefore, Figure 7a and Figure 7b The integrated photonic circuit 10 following step M5 of the method described above is shown. Here, an active component 8 is bonded to the exposed surface 32 of the lower cladding 3. The active component 8 includes an active region 81 optically coupled to the waveguide portion 21. In a further embodiment, instead of the active component 8, a passive component 8, such as a microlens or micromirror, may be bonded to the exposed surface 32 of the lower cladding or to the waveguide portion 21 of the photonic layer 2.

[0079] In some embodiments, the active component 8 is a laser that includes a gain region as the active region 81. In other embodiments, the active component 8 is an electro-optic modulator, such as including a Pockels cell as the active region 81. In still other embodiments, the active component 8 is a detector.

[0080] In the detailed description above, various features have been combined in one or more examples to improve the rigor of the illustrations. However, it should be clear in this context that the above description is merely illustrative and not restrictive. It is intended to cover all alternatives, modifications, and equivalents of the various features and exemplary embodiments. Many other examples will immediately and directly become apparent to those skilled in the art in light of the above description and their knowledge in the art.

[0081] Exemplary embodiments have been selected and described to present the basic principles of the invention and its practical applications in the best possible manner. Therefore, those skilled in the art can optimally modify and utilize the invention and its various exemplary embodiments with respect to their intended uses. In the claims and specification, the terms "including" and "having" are used as neutral linguistic concepts corresponding to the term "comprising." Furthermore, the use of the terms "a," "an," and "one" should not, in principle, exclude multiple features and components described in this manner.

[0082] While at least one exemplary embodiment of the invention has been disclosed herein, it should be understood that modifications, substitutions, and alternatives will be apparent to those skilled in the art and can be made without departing from the scope of this disclosure. This disclosure is intended to cover any modifications or variations of the exemplary embodiments. Furthermore, in this disclosure, the terms “comprise” or “comprising” do not exclude other elements or steps, the terms “a” or “an” do not exclude a plural, and the term “or” means either one or both. Moreover, unless otherwise stated in this disclosure or the context, features or steps already described may also be used in combination with other features or steps in any order. This disclosure is made herein by reference to the full disclosure of any patent or application in which its claims or priorities are incorporated.

[0083] List of reference numerals used

[0084] 1 Integrated Photonic Platform

[0085] 2 Photon layer

[0086] 4 substrate

[0087] 5. Upper cladding

[0088] 6 Waveguide Structure

[0089] 7. The cavity obtained

[0090] 7 cavities

[0091] 8. Optical (passive or active) components

[0092] 10 Integrated Photonic Circuits

[0093] 21 SiN waveguide section

[0094] 21 Waveguide Section

[0095] 22 Etching Stop Section

[0096] 31 Part of the lower cladding

[0097] 32 Exposed surfaces

[0098] 32 Surface of the lower cladding

[0099] 81 Active Area

[0100] 211 Part of the waveguide section

[0101] 212 Waveguide tip

[0102] 222 Embedded Part

[0103] D. Predetermined depth.

Claims

1. A method for manufacturing an integrated photonic platform (1), comprising: Provide (M11) substrate (4); A lower cladding layer (3) made of a first material is deposited (M12) on the substrate (4); A photonic layer (2) made of a second material is deposited (M13) on the lower cladding layer (3); and The photonic layer (2) is patterned (M14) to form a waveguide portion (21) and an etch stop portion (22), wherein the waveguide portion (21) is formed to guide a defined optical pattern substantially within the second material, and wherein the etch stop portion (22) is formed as a defined region of the photonic layer (2).

2. The method according to claim 1, wherein, The etch stop portion (22) is formed as a defined area configured as a placeholder for integrating optical components (8).

3. The method according to claim 1 or 2, wherein, The first material is silicon dioxide (SiO2), and the second material is silicon nitride (SiN), and / or The method further includes annealing the waveguide portion (21) at a temperature greater than or equal to 900 degrees Celsius.

4. The method according to any one of the preceding claims further includes: An upper cladding (5) made of the first material is deposited (M15) on the photonic layer (2) to define a waveguide structure (6) including the lower cladding (3), the photonic layer (2) and the upper cladding (5).

5. A method for manufacturing integrated photonic circuits (10), An integrated photonic platform (1) is provided (M1), particularly by means of the method according to claim 4, the integrated photonic platform (1) comprising a waveguide structure (6) disposed on a substrate (4), wherein the waveguide structure (6) comprises a lower cladding layer (3) made of a first material disposed on the substrate (4), a photonic layer (2) made of a second material disposed on the lower cladding layer (3), and an upper cladding layer (5) made of the first material disposed on the photonic layer (2), wherein the photonic layer (2) comprises a waveguide portion (21) and an etch stop portion (22), wherein the waveguide portion (21) is configured to guide a defined optical mode substantially within the second material, wherein the etch stop portion (22) is configured as a defined region of the photonic layer (2), wherein the first material is configured for etch stop for a first etchant, and the second material is configured for etch stop for a second etchant. A cavity (7) is formed by etching (M2) a portion of the upper cladding (5) using the second etchant to at least partially expose the etch stop portion (22) of the photonic layer (2); and The exposed portion of the etch stop portion (22) of the photonic layer (2) is etched (M3) by using the first etchant to expose the lower cladding layer (3).

6. The method according to claim 5, further comprising: By using the second etchant, a portion of the lower cladding (3) inside the cavity (7) is etched (M4) to a predetermined depth (D).

7. The method according to claim 5 or 6, wherein, When the upper cladding (5) is etched (M2) using the second etchant, the upper cladding (5) is etched on the removed portion of the photonic layer (2), such that a portion (31) of the lower cladding (3) is exposed adjacent to the etch stop portion (22) and the waveguide portion (21). The exposed portion (31) of the lower cladding (3) is specifically arranged on the lateral side of a portion (211) of the waveguide portion (21), which is exposed after the upper cladding (5) is etched using the second etchant.

8. The method according to any one of claims 5 to 7, wherein, When etching (M3) the etch stop portion (22), a waveguide tip (212) suitable for optical edge coupling is formed in the cavity (7).

9. The method according to any one of claims 5 to 8, further comprising: An optical component (8) having an active region (81) is bonded (M5) to the surface (32) of the exposed lower cladding (3) such that an optical mode from the waveguide portion (21) is optically coupled to the active region (81) of the optical component (8), wherein the optical component (8) is particularly an active component (8), preferably a laser or an electro-optic modulator.

10. The method according to claim 8 or 9, wherein, The active region (81) of the optical component (8) is optically coupled to the waveguide portion (21) through the waveguide tip (212) formed in the cavity (7).

11. An integrated photonic platform (1), comprising: base plate (4), A lower cladding layer (3) made of a first material is disposed on the substrate (4), and A photonic layer (2) made of a second material is disposed on the lower cladding layer (4), wherein the photonic layer (2) includes a waveguide portion (21) and an etch stop portion (22), wherein the waveguide portion (21) is configured to guide a defined optical pattern substantially within the second material, and wherein the etch stop portion (22) is a defined region of the photonic layer (2).

12. An integrated photonic platform, further comprising: An upper cladding (5) made of a first material on the photonic layer (2) defines a waveguide structure (6) comprising a lower cladding (3), the photonic layer (2) and the upper cladding (5), wherein the first material is preferably silicon dioxide (SiO2) and the second material is preferably silicon nitride (SiN).

13. An integrated photonic circuit (10), particularly an integrated photonic circuit (10) manufactured using the method according to claim 5, comprising: An integrated photonic platform (1), particularly the integrated photonic platform according to claim 12, wherein the integrated photonic platform (1) comprises: A waveguide structure (6) disposed on a substrate (4) includes a lower cladding layer (3) made of a first material disposed on the substrate (4), a photonic layer (2) made of a second material disposed on the lower cladding layer (3), and an upper cladding layer (5) made of the first material disposed on the photonic layer (2). The photonic layer (2) has a waveguide portion (21) configured to guide defined optical modes substantially within the second material, wherein the second material is configured as an etch stop layer for a second etchant. A cavity (7) is formed in the waveguide structure (6), and the cavity (7) extends into the upper cladding (5) and the photonic layer (2) to expose the lower cladding (3).

14. The integrated photonic circuit according to claim 13, wherein, The cavity (7) extends into the lower cladding (3) at a predetermined depth (D).

15. The integrated photonic circuit according to claim 13 or 14, further comprising: Optical components (8) bonded to the surface (32) of the exposed lower cladding (3), wherein the optical components (8) are specifically configured as active components (8) including an active region (81) which is optically coupled to the waveguide portion (21). The active component (8) is preferably a laser or an electro-optic modulator.

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