A method for verifying a multiple-sim DUT arrangement from a test program

Abstract

This invention relates to the field of semiconductor testing technology and discloses a method for verifying the arrangement of multiple device-under-test (DUT) devices from a test program. The test program calls the channel layout file and translates it into relative coordinates of each DUT relative to the first DUT1. During mass production testing, the test machine acquires the relative coordinates of the first DUT1 in each jump returned by the probe station and assigns absolute coordinates to the other DUTs in the current jump based on these relative coordinates. The absolute coordinates of each DUT are converted into a feature value using the formula X*M+Y and stored in an array. The array is compared to check for duplicate feature values; if duplicate values ​​are detected, the DUT arrangement is deemed abnormal and the test is stopped. This invention achieves effective separation of DUT arrangement parameters from the test program by placing the channel layout file outside the test program and defining it in a standardized manner.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing technology, and in particular to a method for verifying the arrangement of multiple DUTs (Device Under Test) from a test procedure. Background Technology

[0002] In semiconductor manufacturing, wafer-level testing typically employs multi-site testing (MST) technology to improve throughput efficiency. An accurate wafer map is fundamental for subsequent ink dot marking and dicing processes. Errors in the map can directly lead to good products being incorrectly marked and scrapped, or defective products being missed, resulting in significant economic losses and quality risks.

[0003] In existing technologies, the layout definition of multiple DUTs for simultaneous testing is usually hard-coded directly into the test program or manually configured by process engineers based on the pincard layout. Typical definitions include the number of DUTs in the X and Y directions, the position of DUT1 (top left / bottom left / top right / bottom right), the stepping direction of DUT2 relative to DUT1 (X or Y direction), and the die spacing between adjacent DUTs. However, this manual definition method has significant drawbacks: test engineers may inadvertently set incorrect DUT arrangement order, quantity, or spacing parameters when writing the program; process engineers may also cause mapping errors due to parameter input deviations when creating the ProberMap. For example, with a 2x4 pincard layout, if the adjacent spacing in the X direction is incorrectly set to 2 in the program, the coordinates of all DUTs will be displaced erratically, resulting in a stretched or shifted map that does not match the actual die positions. Furthermore, for non-standard pincard layouts, the DUT distribution is often irregular, further increasing the probability of errors in manual definition.

[0004] Therefore, how to verify the correctness of the arrangement of multiple DUTs in a standardized manner from the test program, and proactively intercept human-caused errors and parameter configuration errors before generating error maps, has become a pressing technical problem in this field. Developing an effective DUT arrangement verification mechanism has significant practical value for improving the accuracy of test maps and reducing economic losses caused by map errors. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a method for verifying the arrangement of multiple DUTs from a test program, comprising the following steps: A channel layout file defined in a standard format is placed outside the test program. The test program calls the channel layout file and translates it into the relative coordinates of each DUT relative to the first DUT1. During mass production testing, the test machine obtains the relative coordinates of the first DUT1 in each jump returned by the probe station, and assigns absolute coordinates to the other DUTs in the current jump based on the relative coordinates of the first DUT1. The absolute coordinates of each chip under test (DUT) are converted into a feature value using the formula X*M+Y, and this feature value is stored in an array, where X is the x-coordinate of the chip, Y is the y-coordinate, and M is a constant greater than the maximum value of the X coordinate. The array is compared to see if there are duplicate feature values. If duplicate values ​​are detected, the DUT layout is determined to be abnormal and the test is stopped.

[0006] Furthermore, the standard format of the channel layout file includes two types: the standard regular format Case1 and the free-defined format Case2. The standard regular format is used to handle regular DUT matrix arrangements, while the free-defined format is used to handle irregular special arrangement requirements.

[0007] Furthermore, the standard rule format Case1 is SaabbLUYIddee, where: the first 'S' represents the standard rule format; the second and third 'aa' represent the number of DUTs in the X direction; the fourth and fifth 'bb' represent the number of DUTs in the Y direction; the sixth and seventh 'b' represent the position of DUT1; the eighth 'b' represents the arrangement direction of DUT2 relative to DUT1; the tenth and eleventh 'dd' represent the interval between adjacent DUTs in the X direction plus 1; and the twelfth and thirteenth 'ee' represent the interval between adjacent DUTs in the Y direction plus 1.

[0008] Furthermore, the basic format of Case1 uses two digits to represent aa, bb, dd, and ee, and supports a maximum arrangement of 99×99. When the number of tests exceeds 99, three or more digits are used to represent them to meet the needs of large-scale parallel testing.

[0009] Furthermore, the free-definition format Case2 is FXaaabbbcccddd…… / FYaaabbbcccddd……, where: the first F character represents the free-definition format; and each subsequent three characters represent the coordinate position of the corresponding DUT relative to DUT1. This format allows users to flexibly configure it according to the actual pin layout and is suitable for non-standard DUT arrangements.

[0010] Furthermore, when translating the channel layout file into relative coordinates, the test program, based on the maximum testing capability of the test machine, forcibly assigns a value of 0 to the relative positions of the DUTs not defined in the channel layout file, in order to avoid anomalies caused by undefined coordinates.

[0011] Furthermore, the constant M is initially set to 10000; if the number of X-direction coordinates exceeds 10000, the value of the constant M is increased accordingly to ensure that the uniqueness of the feature value is not affected by the increase in the number of coordinates.

[0012] Furthermore, when the DUT layout is determined to be abnormal and the test is stopped, the test program will remind the user to check the DUT layout settings or probe station parameter settings through a pop-up window so that the user can correct the erroneous parameters in time.

[0013] Furthermore, the test program adjusts the logical coordinate mapping of the DUT in real time by changing the external channel layout file according to the test requirements, without modifying the test program source code, thus improving the system's flexibility and maintainability.

[0014] Furthermore, the method is applied to the multi-test autorun mode of MOSFET products, and prevents test map anomalies by checking for duplicate values ​​in the array, thus ensuring the accuracy and reliability of the test results.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: By placing the channel layout file outside the test program and defining it in a standardized manner, the DUT layout parameters are effectively separated from the test program. This design eliminates the need for test engineers and process engineers to perform complex parameter configurations within the test program; they only need to maintain the external channel layout file. At the same time, the standardized file format significantly reduces the possibility of errors during manual configuration, improving the accuracy and consistency of the DUT layout definition.

[0016] By converting absolute coordinates into feature values ​​and storing them in an array for duplicate detection, DUT (Device Under Test) layout errors can be proactively detected before the test map is generated. When duplicate feature values ​​exist, it indicates that multiple DUTs are mapped to the same physical location, and the generated map will inevitably be incorrect. Performing this verification before testing effectively avoids problems such as incorrect rejection of good products or missed detection of defective products due to map errors, significantly reducing the risk of economic losses caused by test map errors.

[0017] The method of this invention has wide applicability. It can be applied not only to the autorun mode of multiple simultaneous tests of MOSFET products, but also extended to the testing of other types of semiconductor devices, and has good versatility and scalability. Attached Figure Description

[0018] Figure 1 A flowchart provided for an embodiment of the present invention. Detailed Implementation

[0019] The terms first, second, third, fourth, etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms include or have, and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0020] A method for verifying the arrangement of multiple DUTs from a test procedure, such as Figure 1 As shown, it includes the following steps: A channel layout file is defined using a standard format and placed outside the test program. The test program calls the channel layout file and translates it into the relative coordinates of each DUT relative to the first DUT1. During mass production testing, the test machine obtains the relative coordinates of the first DUT1 in each jump returned by the probe station and assigns absolute coordinates to the other DUTs in the current jump based on the relative coordinates of the first DUT1. The absolute coordinates of each chip under test (DUT) are converted into a feature value using the formula X*M+Y and stored in an array, where X is the x-coordinate of the chip, Y is the y-coordinate, and M is a constant greater than the maximum value of X. The array is compared to see if there are duplicate feature values. If duplicate values ​​are detected, the DUT layout is determined to be abnormal and the test is stopped.

[0021] Specifically as follows: Creating a standard format channel layout file: In this invention, the channel layout file is defined using a standard format and placed outside the test program. This design separates the DUT layout information from the test program, facilitating independent management and maintenance of the layout parameters by process engineers. The standard format of the channel layout file includes two types: the standard regular format Case1 and the freely defined format Case2. These two formats are suitable for different types of pin tack layout requirements, respectively.

[0022] case 1, SaabbLUYIddee case2, FXaaabbbcccddd…… / FYaaabbbcccddd…… Case 1 uses the encoding format SaabbLUYIddee for characterization, where each bit has the following meaning: The first character, 'S', indicates that the current format type is a standard regular format. When the parsing module reads the encoding starting with the character 'S', it determines that the channel layout file is defined using a standard regular format. The second and third characters, 'aa', indicate the number of DUTs in the X direction. For example, when 'aa' is 04, it means there are 4 DUTs arranged in the X direction. The fourth and fifth characters, 'bb', indicate the number of DUTs in the Y direction. For example, when 'bb' is 03, it means there are 3 DUTs arranged in the Y direction. The sixth and seventh characters represent the position information of DUT1, which is used to determine... The first device under test (DUT1) is positioned as the reference point in the overall layout. The 8th bit uses a single character to represent the arrangement direction of DUT2 relative to DUT1. This direction includes four modes: increasing in the X direction (represented by the character X), decreasing in the X direction (represented by the character x), increasing in the Y direction (represented by the character Y), and decreasing in the Y direction (represented by the character y). These four modes can describe the conventional row and column arrangement. The 10th and 11th bits, dd, are used to represent the interval between adjacent DUTs in the X direction plus 1. For example, when dd is 02, it means that the actual interval between adjacent DUTs in the X direction is 1 unit. The 12th and 13th bits, ee, are used to represent the interval between adjacent DUTs in the Y direction plus 1, and their meanings are similar to dd.

[0023] Case 2 uses the encoding format FXaaabbbcccddd…… / FYaaabbbcccddd……, where: the first character 'F' indicates that the current format type is a free-defined format. When the parsing module reads the encoding starting with the character 'F', it determines that the channel layout file is defined using a free-defined format; the second character indicates the initial direction, 'X' indicates that the definition starts from the X direction, and 'Y' indicates that the definition starts from the Y direction; the subsequent three characters represent the coordinate position of the corresponding DUT relative to DUT1, and arbitrary layout forms are defined by combining the X-direction offset and the Y-direction offset. This free-defined format can meet the needs of non-standard regular pin layout definition and has a wide range of applications.

[0024] In practical applications, channel layout files are typically stored as text files in a designated directory of the testing system. The filenames can follow a standardized naming convention for easy identification and reading by the testing program. Process engineers can choose to define the layout using either Case 1 or Case 2 format based on the actual pin layout, or create multiple channel layout files when using different pin specifications in the same batch of tests to accommodate varying testing requirements.

[0025] Calling and translating channel layout files: When the test program starts, it first reads the channel layout file stored outside the test program through the parsing module. There is a direct data reading relationship between the parsing module and the channel layout file. The parsing module is responsible for opening the channel layout file at the specified path and reading the encoded content within it. During the reading process, the parsing module first determines whether the current format type is a standard regular format or a free-defined format based on the first character of the encoding, and then parses the encoding according to different format rules.

[0026] The specific translation process is as follows: For Case1 format encoding, the parsing module extracts key information such as aa, bb, position information, direction information, and interval parameters in sequence according to the definition of the encoding format, and then calculates the relative coordinates of each DUT with respect to DUT1 based on this information.

[0027] During the translation process, the test program, based on the test machine's maximum simultaneous testing capability, forcibly assigns specific values ​​to the relative positions of DUTs not defined in the channel layout file, ensuring that all DUT channels have valid coordinate values. This mechanism ensures system robustness; even if the definitions in the channel layout file are incomplete, the test program can still run normally without errors due to missing coordinate information. The coordinate calculation module is responsible for performing the specific coordinate calculations. The parsing module passes the parsed parameters to the coordinate calculation module, which then completes the conversion calculation from encoding to relative coordinates.

[0028] Allocation of absolute coordinates: During mass production testing, the probe station is responsible for moving the chips on the wafer sequentially to the test positions and returning the position information of each test to the test machine. The test machine obtains the relative coordinate information of the first device under test (DUT1) in each hop returned by the probe station. This coordinate information includes the X-direction position parameters and Y-direction position parameters of DUT1, denoted as the DUT1 coordinates.

[0029] After receiving the coordinates of DUT1, the coordinate calculation module assigns absolute coordinates to the other DUTs currently being jumped to, based on the translated relative coordinate information. The specific assignment method is as follows: the absolute coordinates of DUT1 are superimposed with the relative coordinates of each DUT to obtain the absolute coordinates of each DUT.

[0030] The coordinate calculation module communicates with the probe station. The probe station provides real-time physical position information, and the coordinate calculation module combines this physical position information with relative coordinates to generate absolute coordinates for test positioning. The test machine uses these absolute coordinates to control the test probes to precisely contact each DUT, thus completing the parallel testing function.

[0031] Eigenvalue transformation and storage: After obtaining the absolute coordinates of each DUT, the feature value conversion module is responsible for converting the absolute coordinates of each chip under test (DUT) into a feature value using the formula X×M+Y, and storing the feature value in an array storage unit. In a specific embodiment of the present invention, the constant M is initially set to a value of 10000; if the number of coordinates in the X direction exceeds 10000, the value of the constant M is increased accordingly to ensure the uniqueness of the feature value.

[0032] A data writing relationship exists between the feature value conversion module and the array storage unit. After completing the conversion calculation, the feature value conversion module sequentially stores the calculated feature values ​​into the array storage unit. Throughout the testing process, the array storage unit continuously records the feature values ​​of each chip under test (DUT), forming a complete sequence of positional feature values. This feature value setting is one of the key innovations of this invention. By converting two-dimensional coordinates into one-dimensional feature values, duplicate value detection can be easily performed. When the coordinates of two DUTs are exactly the same, their feature values ​​will also be the same, thus enabling rapid identification of coordinate overlap anomalies.

[0033] Duplicate value detection and anomaly assessment: During the test program's execution, the duplicate value detection module iterates through and compares the feature values ​​stored in the array storage unit to detect whether duplicate feature values ​​exist. The duplicate value detection module sequentially reads each feature value in the array storage unit, compares the current feature value with all previously stored feature values, and if a duplicate feature value is found, it determines that the DUT arrangement is abnormal.

[0034] When the duplicate value detection module detects a duplicate value, the exception handling module immediately triggers the exception handling process, and the test program immediately stops testing and exits the current test process. There is a control relationship between the exception handling module and the pop-up notification interface. When the DUT layout is determined to be abnormal and the test stops, the test program displays a notification message through the pop-up notification interface, allowing the user to check the DUT layout settings or probe station parameter settings based on the notification message.

[0035] The anomaly detection mechanism in this step effectively prevents test map anomalies caused by incorrect DUT layout parameters. When DUT coordinates overlap, it indicates an error in the DUT layout parameters. The test program can promptly stop the test and remind the user to check, avoiding the generation of erroneous maps and thus preventing good products from being mistakenly marked as scrap or defective products from being missed.

[0036] Dynamic adjustment function: The dynamic adjustment function provided by this invention allows the test program to adjust the logical coordinate mapping relationship of the DUT in real time according to test requirements by changing the external channel layout file, without modifying the internal code of the test program. When the DUT layout needs to be adjusted, the process engineer only needs to modify the coding content in the channel layout file. The test program will automatically read the updated channel layout file on the next startup and calculate the DUT coordinates according to the new layout rules.

[0037] This dynamic adjustment mechanism significantly improves production efficiency, especially in scenarios requiring frequent pin changes or test scheme adjustments. Users do not need to rewrite test programs; they can simply modify the external channel layout file to adjust the DUT layout. This method is particularly suitable for the multi-test autorun mode of MOSFET products, preventing test map anomalies by checking for duplicate values ​​in the array.

[0038] To enable those skilled in the art to fully understand and implement this invention, the specific implementation principles of this invention are further supplemented below with a specific application scenario.

[0039] Step 1: Creating and parsing the channel layout file Before starting wafer-level testing, process engineers first need to create a channel layout file based on the actual pin layout used. The engineers open the test system configuration file directory and create the channel layout file using either the standard Case1 format or the custom-defined Case2 format. The parsing module automatically scans the specified directory when the test program starts, identifies the channel layout file, and loads it into memory. The parsing module reads the first character of the channel layout file, determines the current format type based on the character 'S' or 'F', and then parses the file content according to the corresponding encoding rules. Taking the standard Case1 format as an example, the parsing module sequentially extracts the number of DUTs in the X direction (2nd and 3rd positions), the number of DUTs in the Y direction (4th and 5th positions), the DUT1 position information (6th and 7th positions), the DUT2 arrangement direction (8th position), the X-direction spacing parameters (10th and 11th positions), and the Y-direction spacing parameters (12th and 13th positions). The parsing module passes these parameters to the coordinate calculation module, which generates the relative coordinate sequence for this test based on these parameters. The test program completes the conversion from external files to internal data structures through the parsing module.

[0040] Step 2: Probe station positioning and absolute coordinate calculation The wafer is placed on the probe station's working platform, and the probe station begins the first round of chip positioning. The probe station's precision motion mechanism drives the probes to precisely move to the position of the first chip under test (DUT) on the wafer, which serves as the DUT. The coordinate information of this position is acquired by the probe station in real time and sent to the testing machine. After receiving the position information returned by the probe station, the testing machine records it as the DUT1 coordinates. The coordinate calculation module, after obtaining the DUT1 coordinates, superimposes the relative coordinates of each DUT to calculate the absolute coordinates corresponding to each DUT. The coordinate calculation module transmits the calculated absolute coordinates to the testing machine, which uses these absolute coordinates to control the probes of each test channel to simultaneously contact the corresponding chip, achieving parallel testing.

[0041] Step 3: Feature value transformation and array storage After the test machine completes the parallel testing of the current jump, the feature value conversion module begins to convert the feature values ​​of each tested chip. The feature value conversion module receives the absolute coordinates output by the coordinate calculation module and extracts the X and Y coordinates of each chip. The feature value conversion module calculates the feature value according to the formula X×M+Y, where M is a constant of 10000. The feature value conversion module stores the calculated feature value in the corresponding position of the array storage unit. When storing the feature value of each chip, the array storage unit simultaneously records the DUT number corresponding to that feature value for subsequent tracking of anomaly locations. This conversion mechanism, which transforms two-dimensional coordinates into one-dimensional feature values, simplifies the complex detection process that originally required comparing two coordinate values ​​to a comparison of a single numerical value, significantly improving detection efficiency.

[0042] Step 4: Duplicate Value Detection and Anomaly Judgment After the array storage unit completes the storage of all DUT feature values ​​for the current jump, the duplicate value detection module begins executing the duplicate value detection program. The duplicate value detection module iterates through each feature value in the array storage unit, comparing the current feature value with all previously stored feature values ​​one by one. Internally, the duplicate value detection module maintains a detection pointer. When the detection pointer points to the second feature value, it compares it with the first feature value; as the pointer continues to move down, it compares the current feature value with all previously stored historical feature values. When the duplicate value detection module detects a duplicate value, it immediately sends an exception signal to the exception handling module, triggering the exception handling process. Upon receiving the exception signal, the exception handling module immediately stops the current test process and displays a warning message through a pop-up notification interface. This real-time duplicate value detection mechanism can proactively intercept DUT arrangement anomalies before error mapping occurs, avoiding the problem of good products being mistakenly scrapped or defective products being missed due to mapping errors.

[0043] Step 5: Dynamic Adjustment and Testing Recovery Following the prompts on the pop-up notification interface, the process engineers opened the channel layout file for inspection and discovered that the X-direction spacing parameter was incorrectly set to 00. After correcting the parameter to the correct 01, the process engineers saved the channel layout file. The test program restarted, and the parsing module read the updated channel layout file, obtaining the correct X-direction spacing parameter. The coordinate calculation module recalculated the relative coordinates of each DUT based on the corrected parameters. At this point, the offset of DUT2 relative to DUT1 was (1, 0), no longer the original (0, 0). The probe station performed chip positioning again. After the test machine obtained the correct DUT1 coordinates, the coordinate calculation module superimposed the relative coordinates to obtain the absolute coordinates of each DUT. The feature value conversion module converted these absolute coordinates into feature values ​​and stored them in the array storage unit. The duplicate value detection module traversed the array storage unit. Since the coordinates of the DUTs no longer overlapped, the detection passed, and the test program resumed normal operation. This process of adjusting the DUT layout logic by modifying the external channel layout file requires no modification to the test program's source code, significantly improving production efficiency.

[0044] Step Six: Complete Wafer Testing Process With the aforementioned verification mechanism functioning correctly, the test program executes a complete test procedure on the entire wafer. The probe station moves sequentially to the test position for each jump. After the tester acquires the coordinates of the DUT1 for each jump, the coordinate calculation module calculates the absolute coordinates of all DUTs for that jump. The feature value conversion module converts the absolute coordinates of each chip into feature values ​​and stores them in an array storage unit. The duplicate value detection module simultaneously performs duplicate value detection. The number of feature values ​​in the array storage unit increases accordingly after each test jump is completed. When the entire wafer test is complete, the array storage unit records the positional feature value information of all tested chips on the wafer. This information can be used by the tester to generate the final test Map file, which records the test results and physical position of each chip, providing important guidance for subsequent ink dot marking and dicing processes. This invention effectively ensures the accuracy of the final generated test Map by continuously verifying the correctness of the DUT arrangement during the testing process, providing reliable data support for product quality assessment.

[0045] All contents not described in detail in the specification are existing technologies known to those skilled in the art, and the model parameters of each electrical appliance are not specifically limited; conventional equipment can be used. Electrical control components not mentioned in this technical solution are not shown in the figures because they are existing technologies, and will not be described here.

[0046] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for verifying the arrangement of multiple identically tested DUTs from a test program, characterized in that, Includes the following steps: Define the channel layout file using a standard format and place it outside the test program; The test program calls the channel layout file and translates it into the relative coordinates of each DUT with respect to the first device under test, DUT1; During mass production testing, the test machine obtains the relative coordinates of the first device under test (DUT1) in each hop returned by the probe station, and assigns absolute coordinates to the other DUTs in the current hop based on the relative coordinates of the first DUT1. The absolute coordinates of each chip under test (DUT) are converted into a feature value using the formula X*M+Y, and the feature value is stored in an array, where X is the horizontal coordinate of the chip, Y is the vertical coordinate, and M is a constant greater than the maximum value of the X coordinate. Compare whether there are duplicate feature values ​​in the array. If duplicate values ​​are detected, the DUT arrangement is determined to be abnormal and the test is stopped.

2. The method for verifying the arrangement of multiple DUTs from a test program according to claim 1, characterized in that: The standard formats of the channel layout file include the standard regular format Case1 and the freely defined format Case2.

3. The method for verifying the arrangement of multiple DUTs from a test program according to claim 2, characterized in that: The standard rule format Case1 is SaabbLUYIddee, where: The first S character represents the standard regularity format; The second and third 'aa' characters represent the number of DUTs in the X direction; The 4th and 5th bb represent the number of DUTs in the Y direction; The 6th and 7th bits represent the position of DUT1; The 8th position indicates the orientation of DUT2 relative to DUT1; The 10th and 11th bits dd represent the increment of the interval between adjacent DUTs in the X direction by 1; The 12th and 13th ee bits represent the interval between adjacent DUTs in the Y direction plus 1.

4. The method for verifying the arrangement of multiple DUTs from a test program according to claim 3, characterized in that: The basic format of Case 1 uses two digits to represent aa, bb, dd, and ee, and supports a maximum arrangement of 99×99; when the number of identical samples exceeds 99, it uses three or more digits to represent them.

5. A method for verifying the arrangement of multiple DUTs from a test program according to claim 2, characterized in that: The freely defined format Case2 is FXaaabbbcccddd…… / FYaaabbbcccddd……, where: The first F character represents a freely defined format; The subsequent three characters represent the coordinates of the corresponding DUT relative to DUT1.

6. The method for verifying the arrangement of multiple DUTs from a test program according to claim 1, characterized in that: When translating the channel layout file into relative coordinates, the test program forces the relative positions of DUTs not defined in the channel layout file to be 0, based on the maximum simultaneous testing capability of the test machine.

7. The method for verifying the arrangement of multiple DUTs from a test program according to claim 1, characterized in that: The constant M is initially set to 10000; if the number of X-direction coordinates exceeds 10000, the value of the constant M is increased accordingly.

8. The method for verifying the arrangement of multiple DUTs from a test program according to claim 1, characterized in that: When the DUT layout is determined to be abnormal and the test is stopped, the test program will remind the user to check the DUT layout settings or probe station parameter settings through a pop-up window.

9. A method for verifying the arrangement of multiple DUTs from a test program according to claim 1, characterized in that: The test program adjusts the logical coordinate mapping of the DUT in real time by changing the external channel layout file according to the test requirements.

10. A method for verifying the arrangement of multiple DUTs from a test program according to claim 1, characterized in that: The method is applied to the multi-test autorun mode of MOSFET products, and prevents test map anomalies by checking for duplicate values ​​in the array.

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