A one-time programmable diode and diode array

Abstract

The application relates to the field of semiconductor technology and discloses a one-time programmable diode and a diode array, which comprises an N well region, a P-type silicon substrate is taken as a base to inject low-dose phosphorus ions to form the N well region; an N+ well region, high-dose phosphorus ions are injected into the formed N well region to form the N+ well region; a gate oxide layer, the gate oxide layer is arranged above the N+ well region; a polysilicon layer, the polysilicon layer is formed above the gate oxide layer through an LPCVD technology; and a metal titanium layer, the metal titanium layer is deposited above the polysilicon layer through a magnetron sputtering process. The application can effectively reduce the device programming voltage of the programmable diode, reduce the layout area of a storage unit and an array, widen a storage window, realize high-density one-time programmable array storage, and is completely compatible with a standard CMOS process without needing to add any additional process steps, thereby providing a low-cost, high-compatibility programmable diode device for high-density one-time programmable (OTP) storage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a one-time programmable diode and diode array. Background Technology

[0002] One-time programmable diodes (IPDs) are antifuse PN junction diodes with one-time irreversible electrical programming characteristics, and are widely used in automotive electronics, security chips, and other fields requiring high-density non-volatile memory. However, traditional IPDs often employ independent device architecture designs in their cell structure, without optimization for CMOS process layout. They lack high-density integration design concepts such as shared wells and shared gates, resulting in a large area ratio for individual memory cells, making it difficult to achieve compact and arrayed arrangement of memory cells. Furthermore, when these memory devices perform programming operations, they must simultaneously achieve the breakdown of the silicon dioxide insulating layer and the intrinsic PN junction, directly leading to a high programming voltage and consequently, significant power consumption.

[0003] The two major problems of large memory cell area and high power consumption due to high programming voltage severely restrict the large-scale integration and application of this type of memory device in advanced large-scale CMOS memory circuits.

[0004] For one-time programmable diodes, existing research has proposed various technical solutions to reduce their programming voltage and shrink the area of ​​memory cells. However, these solutions are mostly achieved through iterative innovation of material systems, optimization of advanced semiconductor processes, and matching design of peripheral auxiliary circuit architectures. Not only are they not compatible with standard CMOS processes, but they also introduce additional process steps. At the same time, the addition of peripheral auxiliary circuits makes it difficult to further reduce and optimize the overall area occupied by memory cells, and cannot meet the high-density integration requirements of advanced processes. Summary of the Invention

[0005] This invention addresses the problems of high power consumption caused by the large area occupied by one-time programmable diode memory cells and the high programming voltage in the prior art by providing a one-time programmable diode, a diode array, and an array read / write method.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: A one-time programmable diode, comprising: P-type silicon substrate, The N-well region is formed by implanting a low dose of phosphorus ions onto a P-type silicon substrate. N+ well region: A high dose of phosphorus ions is injected into an existing N-well region to form an N+ well region. Gate oxide layer, a gate oxide layer placed above the N+ well region; Polycrystalline silicon layer, formed above the gate oxide layer using LPCVD technology; The titanium layer is a titanium layer deposited on top of a polycrystalline silicon layer using a magnetron sputtering process.

[0007] Preferably, the low-dose phosphorus ion dose is 1×10¹² cm⁻¹. -2 ~1×10¹⁴cm -2 The high dose of phosphate ions is 1×10¹⁷ cm⁻¹. -2 ~1×10¹⁹cm -2 .

[0008] Preferably, the oxide layer placed above the N+ well region is grown using a dry oxygen thermal growth process to grow the gate oxide layer.

[0009] Preferably, the temperature of the dry oxygen thermal growth process is 750℃~800℃, and the growth thickness of the gate oxide layer is 2nm~10nm.

[0010] Preferably, a polycrystalline silicon layer is formed above the gate oxide layer using LPCVD technology, and the thickness of the polycrystalline silicon layer is 200nm~240nm.

[0011] Preferably, the gases used in LPCVD technology are SiH4 gas and N2 gas, with a flow rate of 180~220 Sccm for SiH4 gas and a flow rate of 950~1050 Sccm for N2 gas.

[0012] As a preferred method, a titanium layer is deposited using magnetron sputtering. Under an argon atmosphere, the argon gas flow rate is 10-15 Sccm, the sputtering rate is 5-6 nm / min, the sputtering time is controlled at 9-10 min, and the thickness of the sputtered titanium layer is 45-60 nm.

[0013] To address the aforementioned technical problems, the present invention also provides a one-time programmable diode array, wherein the diode array comprises 2n*2n one-time programmable diodes; Programmable diodes include a P-type silicon substrate. The N-well region is formed by implanting a low dose of phosphorus ions onto a P-type silicon substrate. N+ well region: A high dose of phosphorus ions is injected into an existing N-well region to form an N+ well region. Gate oxide layer, a gate oxide layer placed above the N+ well region; Polycrystalline silicon layer, formed above the gate oxide layer using LPCVD technology; The titanium layer is a titanium layer deposited on top of a polycrystalline silicon layer using a magnetron sputtering process.

[0014] Preferably, for a 2n*2n programmable diode array, programmable diodes in the same column share the same well, and programmable diodes in the same row share the same gate.

[0015] Preferably, the low-dose phosphorus ion dose is 1×10¹² cm⁻¹. -2 ~1×10¹⁴cm -2 The high dose of phosphate ions is 1×10¹⁷ cm⁻¹. -2 ~1×10¹⁹cm -2 .

[0016] This invention, by adopting the above technical solutions, has significant technical effects: The one-time programmable diode designed in this invention has an additional N+ well structure and its shared well and shared gate structure design and operation method in the array, which reduces the programming voltage, reduces the cell and array area, and expands the memory window, enabling one-time programmable high-density array memory. This invention provides a one-time programmable diode and array that are fully compatible with standard CMOS processes and require no additional process steps to achieve high-density memory.

[0017] This invention can effectively reduce device programming voltage, reduce the layout area of ​​memory cells and arrays, and widen the memory window, enabling high-density one-time programmable array memory. At the same time, this solution is fully compatible with standard CMOS processes, requiring no additional process steps, providing low cost and high compatibility for high-density one-time programmable (OTP) memory. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the N-well region structure formed in this invention.

[0019] Figure 2 This is a schematic diagram of the N+ well region structure formed in this invention.

[0020] Figure 3 This is a schematic diagram of the structure of the present invention, in which a gate oxide layer and a polysilicon layer are provided in the N+ well region.

[0021] Figure 4 This is a schematic diagram of the programmable diode structure of the present invention.

[0022] Figure 5 This is a flowchart of the present invention.

[0023] Figure 6 This is a schematic diagram of a 2x2 programmable array structure.

[0024] Figure 7 This is a schematic diagram of a 2n*2n programmable array structure.

[0025] Figure 8It is a current-voltage curve of a one-time programmable diode with a programming voltage of 5~8V.

[0026] Figure 9 It is a current-voltage curve of a one-time programmable diode with a read voltage of 1~3V.

[0027] Figure 10 This is a statistical distribution chart of the programming voltage and burn-out voltage of 35 one-time programmable diodes.

[0028] Figure 11 This is a test current-voltage curve graph written to cell A.

[0029] Figure 12 This is the test current-voltage curve written to cell B.

[0030] Figure 13 It is a test current-voltage curve graph written to cell C.

[0031] Figure 14 This is a test current-voltage curve graph written to cell D.

[0032] Figure 15 It reads the test current and voltage curve of unit A.

[0033] Figure 16 It reads the test current and voltage curve of cell B.

[0034] Figure 17 It reads the test current and voltage curve of cell C.

[0035] Figure 18 It reads the test current and voltage curve of cell D.

[0036] Among them, 100 is a P-type silicon substrate layer, 101 is an N-well region, 102 is an N+ well region, 103 is a gate oxide layer, 104 is a polysilicon layer, and 105 is a titanium metal layer. Detailed Implementation

[0037] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0038] Example 1 A one-time programmable diode, Figure 4 It includes: P-type silicon substrate, N-well region, Figure 1 A low dose of phosphorus ions is implanted into a P-type silicon substrate to form an N-well region; N+ well region, Figure 2 In the process of injecting a high dose of phosphorus ions into the already formed N-well region to form an N+ well region; Gate oxide layer, a gate oxide layer placed above the N+ well region; Polycrystalline silicon layer, Figure 3 A polycrystalline silicon layer is formed above the gate oxide layer using LPCVD technology. The titanium layer is a titanium layer deposited on top of a polycrystalline silicon layer using a magnetron sputtering process.

[0039] The low dose of phosphate ions is 1×10 12 cm -2 ~1×10 14 cm -2 The high dose of phosphate ions is 1×10⁻⁶. 17 cm -2 ~1×10 19 cm -2 .

[0040] The oxide layer placed above the N+ well region is grown using a dry oxygen thermal growth process. The dry oxygen thermal growth process is carried out at a temperature of 750℃~800℃, and the thickness of the gate oxide layer is 2nm~10nm.

[0041] A polycrystalline silicon layer is formed above the gate oxide layer using LPCVD technology, with a thickness of 200nm~240nm.

[0042] The gases used in LPCVD technology are SiH4 gas and N2 gas. The flow rate of SiH4 gas is 180~220 Sccm; the flow rate of N2 gas is 950~1050 Sccm.

[0043] Example 2

[0044] Based on Example 1, Figure 5 This is a process flow diagram of the method for improving the size and programming voltage of a one-time programmable diode by modifying the device structure according to the present invention. The method for improving the size and programming voltage of a one-time programmable diode by modifying the device structure includes the following steps: Step S1: Using a P-type silicon substrate as the base, an N-well region is fabricated using a low-dose phosphorus ion implantation process, with an implantation dose of 1×10⁻⁶. 12 ~1×10 14 cm -2 Low doping concentration allows for precise control of the N-well depletion layer width, optimizes band bending under gate voltage, concentrates the programming voltage on the gate oxide antifuse layer, significantly reduces silicon substrate lattice damage, reduces the repair pressure of subsequent high-temperature annealing, ensures the interface quality of 800℃ ultrathin gate oxide (2~10nm), eliminates gate oxide leakage defects, and improves device yield.

[0045] Step S2: Within the already formed N-well region, a heavily doped N+ well region is prepared using a high-dose phosphorus ion implantation process, with an implantation dose of 1×10⁻⁶.17 ~1×10 19 cm -2 The combination of highly doped N+ ions and a lightly doped N-well high-resistivity substrate further widens the resistance difference between the high-resistivity and low-resistivity states of the device, effectively reducing the programming voltage of the one-time programmable diode, thus enabling the device to exhibit a resistance of 10. 5 Large-scale storage window.

[0046] Step S3 involves growing a gate oxide layer using a dry oxygen thermal growth process at a temperature of 750℃~800℃, with a growth thickness of 2~10nm. This ultra-thin thickness of 2~10nm is the optimal range for soft breakdown (anti-fuse) of the gate oxide layer. Under compliant current, the gate voltage can induce the directional aggregation of oxygen vacancies, rapidly forming a low-resistance conductive channel and completing the programming switch from high to low resistance. Excessive thickness can lead to excessively high programming voltage and failure, while excessive thinness can easily cause spontaneous breakdown and misprogramming. The oxygen vacancy defect density of the oxide layer grown at a low temperature of 750~800℃ is controllable, ensuring the defect sources required for programming while avoiding excessive defects that could lead to initial leakage.

[0047] Step S4 employs LPCVD technology at a temperature of 600℃~620℃ and a working pressure of 30~50 Pa. The gases used are high-purity SiH4 and N2, with flow rates of 180~220 Sccm and 950~1050 Sccm, respectively. Simultaneously, PH3 is introduced for in-situ N-type doping at a flow rate of 2~5 Sccm. The deposition rate is 10~15 nm / min, resulting in a polycrystalline silicon thickness of 200~240 nm. This temperature is significantly lower than the high-temperature oxidation / annealing temperature, completely avoiding secondary growth of the ultrathin gate oxide, interface degradation, and oxygen vacancy runaway, thus protecting the device from antifuse soft breakdown. 5 The core physical basis of ultra-large memory window; simultaneously eliminating gate oxide pinhole leakage, ensuring initial high-resistivity stability, and preventing N-well and N-well contamination. + The lateral / vertical diffusion of phosphorus ions in the heavily doped region maintains the vertical doping gradient and PN junction barrier of the device, ensuring the unidirectional rectification characteristics of the diode after programming and suppressing reverse leakage current and array latent current.

[0048] Step S5 involves depositing a titanium layer using magnetron sputtering. Under an argon atmosphere, the argon gas flow rate is 10–15 sccm, the sputtering rate is 5–6 nm / min, and the sputtering time is controlled at 9–10 min. The sputtered titanium layer thickness is 45–60 nm. This low argon flow rate creates a low-energy, mild sputtering environment, preventing damage from high-energy ion bombardment. This perfectly protects the 2–10 nm ultrathin dry oxide gate oxide layer, avoiding gate oxide pinholes, interface state surges, and initial leakage current, ensuring the device's initial high-resistivity state and 10 nm high-resistivity state. 5 With an ultra-large storage window, medium- and low-speed sputtering suppresses coarse Ti film grains, pores, and stress concentration. The prepared metal film has high density and extremely strong adhesion, with no delamination or peeling from the polycrystalline silicon gate / dielectric layer. It can withstand the thermal shock of 17V high-voltage programming and is suitable for working scenarios where the conductive filament in the fused state melts.

[0049] Step S6 involves a high-temperature rapid thermal annealing process under a nitrogen atmosphere to complete the electroactivation and lattice damage repair of the implanted ions. The temperature is 1040℃~1060℃, and the time is 10s~15s. This temperature range is suitable for phosphorus ions (Nt, Nt). + The optimal window for electro-activation (in-situ PH3 doping of polycrystalline silicon) is achieved; a short annealing of 10-15 seconds can achieve nearly 100% doping activation rate, maximizing carrier concentration; simultaneously, it can rapidly repair ion implantation (N-well, N-well...) + The method significantly reduces the interface state density and substrate leakage current for defects such as lattice dislocations and vacancies caused by P-type silicon substrates; it uses inert N2 to isolate oxygen, avoids the high-temperature oxidation of Ti electrodes and polycrystalline silicon surfaces to form high-resistivity oxides, ensures stable metal-semiconductor contact resistance, and has no additional electrical losses.

[0050] Step S7 involves fabricating the top electrode pattern using photolithography and dry etching processes. Photolithography and dry etching are standard microfabrication methods for 0.18μm advanced CMOS processes, enabling submicron-level pattern resolution and linewidth control. This results in nearly 90° vertical electrode sidewalls, free from side etching and burrs, avoiding electric field distortion and localized electric field concentration at the electrode edges. This ensures a uniform programming electric field on the gate oxide layer, precisely inducing the formation of oxygen vacancy conductive channels and improving the controllability of antifuse / fuse dual-state switching. Photolithography and dry etching are purely dry processes, eliminating particulate contamination, water residue, and electrochemical corrosion associated with wet cleaning. This meets the cleanliness requirements of ultra-small devices, significantly reducing the probability of array short circuits and open circuit failures, and improving mass production yield.

[0051] The novel device structure design miniaturizes the size of the one-time programmable diode and significantly reduces the programming voltage of the one-time programmable diode by adding only one additional ion implantation without the need for additional supporting circuitry.

[0052] Example 3

[0053] Based on Example 1, this example is a one-time programmable diode array, which includes 2n*2n one-time programmable diodes. The programmable diodes include: a P-type silicon substrate, N-well region, Figure 1 A low dose of phosphorus ions is implanted into a P-type silicon substrate to form an N-well region; N+ well region, Figure 2 In the process of injecting a high dose of phosphorus ions into the already formed N-well region to form an N+ well region; Gate oxide layer, a gate oxide layer placed above the N+ well region; Polycrystalline silicon layer, Figure 3 A polycrystalline silicon layer is formed above the gate oxide layer using LPCVD technology. The titanium layer is a titanium layer deposited on top of a polycrystalline silicon layer using a magnetron sputtering process.

[0054] The low dose of phosphate ions is 1×10 12 cm -2 ~1×10 14 cm -2 The high dose of phosphate ions is 1×10⁻⁶. 17 cm -2 ~1×10 19 cm -2 .

[0055] exist Figure 7 In a 2n*2n programmable diode array, programmable diodes in the same column share the same well, and programmable diodes in the same row share the same gate.

[0056] In this embodiment, Figure 6 The array uses a 2*2 programmable diode array. Programmable diode unit A and programmable diode unit C share well 1; programmable diode unit B and programmable diode unit D share well 2; programmable diode unit A and programmable diode unit B share gate 1; and programmable diode unit C and programmable diode unit D share gate 2.

[0057] Example 4

[0058] Based on the above embodiments, this embodiment is a one-time programmable diode array read / write method, which includes the following steps for reading and writing the one-time programmable diode array: When a programming or reading operation is performed on the one-time programmable diode of any target cell in the array, a zero potential is applied to the programmable diode that shares the well with the target cell, and a programming voltage or a reading voltage is applied to the corresponding programmable diode.

[0059] Figure 8 The programming voltage of a one-time programmable diode is 5~8V, and the switching ratio reaches 105. Figure 9 The voltage to be read is 1~3V. Figure 10 The figure shows the statistical distribution of programming voltage and burn-out voltage of 35 one-time programmable diodes. It can be seen from the figure that the programming voltage of the one-time programmable diode proposed in this invention is 5~8V and the burn-out voltage is 15~19V.

[0060] Figures 11 to 14 and Figures 15 to 18 The test results of programming and reading operations performed on the one-time programmable diodes of four units A, B, C, and D in the array are shown respectively. The test results verify that the one-time programmable diodes provided by the present invention can be applied to large-scale memory arrays and reliably realize data storage and reading functions.

Claims

1. A one-time programmable diode, characterized in that, include: P-type silicon substrate, The N-well region is formed by implanting a low dose of phosphorus ions onto a P-type silicon substrate. The N+ well region is formed by injecting a high dose of phosphorus ions into an existing N-well region; and the depth of the N+ well region is less than the depth of the N-well region. Gate oxide layer, a gate oxide layer placed above the N+ well region; Polycrystalline silicon layer, formed above the gate oxide layer using LPCVD technology; The titanium layer is a titanium layer deposited on top of a polycrystalline silicon layer using a magnetron sputtering process.

2. The one-time programmable diode according to claim 1, characterized in that, The low dose of phosphate ions is 1×10 12 cm -2 ~1×10 14 cm -2 The high dose of phosphate ions is 1×10⁻⁶. 17 cm -2 ~1×10 19 cm -2 .

3. A one-time programmable diode according to claim 1, characterized in that, The oxide layer placed above the N+ well region is grown using a dry oxygen thermal growth process to grow the gate oxide layer.

4. A one-time programmable diode according to claim 3, characterized in that, The temperature of the dry oxygen thermal growth process is 750℃~800℃, and the thickness of the gate oxide layer is 2nm~10nm.

5. A one-time programmable diode according to claim 1, characterized in that, A polycrystalline silicon layer is formed above the gate oxide layer using LPCVD technology, with a thickness of 200nm~240nm.

6. A one-time programmable diode according to claim 1, characterized in that, The gases used in LPCVD technology are SiH4 gas and N2 gas. The flow rate of SiH4 gas is 180~220 Sccm; the flow rate of N2 gas is 950~1050 Sccm.

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