Structure and fabrication method of PIP multilayer capacitors in ETOX Flash

Abstract

The application discloses a method for optimizing PIP stacked capacitors in an ETOX Flash, the PIP stacked capacitors are integrated in the Flash, and an active region of the PIP stacked capacitors is a plurality of comb-shaped strips arranged in a row; a first plate of the PIP stacked capacitors is formed by a floating gate polysilicon of a PIP stacked capacitor region, and an active region below an outgoing end of the first plate is kept in a block shape and is combined; the first plate of the PIP stacked capacitors formed by the floating gate polysilicon is arranged alternately with STIs and has a height difference, and a plurality of STIs isolate the floating gate polysilicon to form a plurality of parallel strip arrangements; a 3D appearance in a wave type fluctuation of a second dielectric layer serving as a capacitor dielectric layer increases a surface area of the second dielectric layer in a limited horizontal projection area, and increases a capacitance; above the second dielectric layer is a part of a second plate formed by a control gate polysilicon, which is connected with the active region of the PIP stacked capacitor region through an interconnection structure, and forms the second plate of the PIP stacked capacitors together; and the first dielectric layer is between the floating gate polysilicon of the PIP stacked capacitor region and the active region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device design and manufacturing, and in particular to a method for optimizing the PIP stacked capacitance in ETOX Flash. Background Technology

[0002] In storage devices, reading, writing, and erasing memory cells all involve different operating voltages, especially the erase operation, where the programming voltage is often higher than the voltage provided by the power supply. A pump circuit, also known as a switched-capacitor voltage converter, is a DC-DC converter that uses "flying" or "pumping" capacitors (not inductors or transformers) to store energy. It generates high voltage through the accumulation of charge by the capacitor, causing current to flow from a low potential to a high potential. Simply put, it charges the capacitor, removes it from the charging circuit to isolate the charged charge, and then connects it to another circuit to transfer the isolated charge. In FLASH devices, its function is to use the "pumping capacitor" to boost the power supply voltage to the required erase / write voltage. FLASH products require a charge pump charging circuit to provide the power for erasing and writing. The pump circuit in FLASH devices uses multiple capacitors to boost the voltage; commonly used capacitors include MIM capacitors, MOM capacitors, and PIP capacitors.

[0003] The high-voltage charge pump circuit for programming operations in the 48nm ETOX (tunneling oxide) NOR Flash Cell employs a POLY / Inter-dielectric / POLY (PIP) stacked capacitor. The floating gate (FG) in the ETOX flash bit fabrication process serves as plate 1 of the PIP capacitor. The substrate active region (AA) and control gate (CG) are located below and above the floating gate FG, respectively, forming plate 2 of the PIP capacitor. Figure 1 and Figure 2 As shown, it can be fabricated using a process that integrates with memory arrays. Because it has a tunnel oxide layer (tunox) and an ONO layer as the intermediate dielectric layer, the PIP capacitor has the advantages of both high voltage withstand capability and large capacitance.

[0004] During the fabrication of Flash memory array cells, floating gate (FG) planarization is achieved through grinding. Due to unavoidable loading effects, while ensuring the required FG height (~70nm) for densely patterned cell array bit areas (line width 0.06um, space spacing 0.06um), large-area blocky PIP (~20um*10um per unit) FGs are over-ground, leaving only about 48nm of remaining thickness. These excessively thin PIP capacitor FG plates are prone to burn-through failure under prolonged high-voltage operating conditions, affecting product reliability.

[0005] Currently, the thickness requirements for PIP capacitors (FG) result in a relatively small process window. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a method for optimizing the PIP stacked capacitance in ETOX Flash.

[0007] To solve the above problems, the present invention provides a method for optimizing the PIP stacked capacitance in ETOX Flash, comprising: Step 1: Provide a semiconductor substrate, and deposit a first dielectric layer as a floating gate dielectric layer in the active region of the device area on the semiconductor substrate; then etch multiple trenches and deposit and fill a layer of STI dielectric layer to form STI; The first dielectric layer is etched back to expose the first dielectric layer on the surface of the active region, and the STI dielectric layer in the STI region protrudes from the surface of the active region to form a certain height. A first polysilicon layer for fabricating the floating gate is deposited, the thickness of which needs to completely cover the STI dielectric layer; the first polysilicon layer is then ion-implanted and doped. Step 2: Perform a grinding process on the first polysilicon layer to remove the excess thickness of the first polysilicon layer; the remaining first polysilicon layer in the PIP stacked capacitor region serves as the first electrode of the PIP stacked capacitor. Step 3: Open the PIP stacked capacitor region of the active area using photolithography, and perform back etching of the STI dielectric layer. Part of the STI dielectric layer protruding above the active area surface above the STI trench is etched back to form a recessed area that is downward relative to the current active area surface. Multiple STI trenches form multiple recessed areas, and the surface of the PIP stacked capacitor region forms a periodic undulating morphology. Step 4: A thin film is deposited in the active region PIP stacked capacitor region to form a second dielectric layer and then etched back to form a second dielectric layer covering the surface of the first polysilicon layer. Then, the second dielectric layer is etched back to remove the first polysilicon layer as the second dielectric layer outside the first electrode. The second dielectric layer with the completed morphology etching is attached to the surface morphology of the active region to form a wave-like morphology with periodic undulations. This three-dimensional morphology can increase the surface area of ​​the second dielectric layer with a limited horizontal projection area. Step 5: Deposit a second polysilicon layer for fabricating the control gate and etch it to form the control gate. Etch the remaining second polysilicon layer in the PIP stacked capacitor region as the second electrode of the PIP stacked capacitor. Open the active region AA by etching back the second polysilicon layer. By simultaneously etching back the gate polysilicon of the flash memory, a portion of the second polysilicon layer of the PIP stacked capacitor region is etched away, and the etching stops on the second dielectric layer, forming an outgoing channel for the first electrode of the PIP stacked capacitor.

[0008] The semiconductor substrate includes a silicon substrate, a germanium-silicon substrate, a gallium arsenide substrate, a gallium nitride substrate, and a silicon carbide substrate.

[0009] In step one, the first dielectric layer is a tunneling oxide (TUNOX), and the STI dielectric layer is silicon oxide or silicon nitride.

[0010] In step two, the grinding process adopts the CMP process. After grinding is completed, the wafer surface is flat, and the STI dielectric layer protruding above the active area has a certain height.

[0011] In step four, the third dielectric layer is an ONO layer; the surface area of ​​the intermediate insulating dielectric layer of the capacitor is increased by multiple undulating surface morphologies, thereby increasing the capacitance.

[0012] The process method also includes step six, which involves performing subsequent steps according to the conventional ETOX Flash cell fabrication process, including sidewall Spacer / SAB / interlayer dielectric ILD deposition process, whereby the second dielectric layer above the first polysilicon layer will be opened during the sidewall Spacer / SAB etching process.

[0013] The contact hole etching process simultaneously brings out the control gate, floating gate, and active region. The control gate and active region are connected together through the first metal layer to form the second plate of the PIP stacked capacitor.

[0014] This invention provides a structure for a PIP stacked capacitor in an ETOX Flash, wherein the PIP stacked capacitor is integrated in the Flash, and the active area of ​​the PIP stacked capacitor is a series of comb-shaped strips. The floating gate polysilicon in the PIP stacked capacitor region forms the first electrode plate, and the active region below its lead-out terminal remains in a block-shaped merging. The first plate of the PIP stacked capacitor, which is composed of floating gate polysilicon, is alternately arranged with an STI and has a height difference. Multiple STIs isolate the floating gate polysilicon to form multiple parallel strips. The second dielectric layer, which serves as the capacitor dielectric layer, has a wavy 3D morphology, which increases the surface area of ​​the second dielectric layer within a limited horizontal projected area, thereby increasing the capacitance. Above the second dielectric layer is a part of the second electrode plate formed by control gate polysilicon, which is connected to the active region of the PIP stacked capacitor region through an interconnect structure to form the second electrode plate of the PIP stacked capacitor together. The first dielectric layer is located between the floating gate polysilicon and the active region in the PIP stacked capacitor region.

[0015] Furthermore, the comb-shaped active region optimizes the consistency of pattern density, improves the load effect during the planarization process of floating gate polysilicon grinding, and the first plate of the PIP stacked capacitor is formed by synchronous grinding of the floating gate polysilicon in the flash cell region, which is consistent with the thickness of the floating gate, optimizes the high voltage long-term performance of the capacitor, and increases the process window.

[0016] Furthermore, the ratio of the active region of the PIP stacked capacitor to the area of ​​the STI is adjustable, thereby achieving fine-tuning of the equivalent capacitance ratio of the optimized floating gate dielectric layer and ONO dielectric layer.

[0017] Furthermore, the thicknesses of the first dielectric layer and the second dielectric layer remain consistent with those of existing structures.

[0018] Furthermore, the height difference between the first plate of the PIP stacked capacitor and the STI is achieved by etching back the thickness of the STI dielectric layer, thereby reducing the height of the STI.

[0019] The structure of the PIP stacked capacitor in the ETOX Flash described in this invention optimizes the PIP stacked capacitor structure by changing the active region morphology to a comb-like shape, improving the load effect during the flattening process of the floating gate polysilicon, ensuring that the thickness of the floating gate polysilicon is consistent with the pattern density of the Flash Cell array bit region, optimizing the capacitor's high-voltage long-term performance, and increasing the process window. The active region below the floating gate polysilicon lead-out terminal of the PIP stacked capacitor remains block-shaped and merged to ensure the first electrode is connected, and the capacitor lead-out method remains consistent with that before optimization. The second dielectric layer of the PIP stacked capacitor is adjusted from a traditional planar morphology to a 3D wave morphology to increase the surface area of ​​the second dielectric layer and increase the capacitance. The adjustable active region / STI area ratio yields the optimized equivalent capacitance ratio of the first and second dielectric layers, increasing the capacitance within the existing process window. The withstand voltage of the comb-shaped first and second dielectric layers is basically the same as that of the block structure, and the high-voltage withstand performance is the same after structural optimization. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the planar structure of an existing PIP (Polypropylene In-line Capacitor).

[0021] Figure 2 This is a schematic diagram of the cross-sectional structure of an existing PIP (Polypropylene In-line Capacitor).

[0022] Figure 3 This is a schematic diagram of the planar structure of the PIP stacked capacitor of the present invention.

[0023] Figure 4 This is a schematic cross-sectional view of the PIP stacked capacitor of the present invention.

[0024] Figures 5-10 This is a schematic diagram of each step in the process method of the present invention.

[0025] 1 is the FG plate of the PIP capacitor, 2-1 is the AA plate of the PIP capacitor, 2-2 is the CG plate of the PIP capacitor, 11 is the first dielectric layer (tunox tunneling dielectric layer), 12 is the second dielectric layer (ONO layer), 13 is the first polysilicon layer (floating gate polysilicon FG), 14 is the second polysilicon layer (control gate CG), and 15 is the interlayer dielectric ILD. Detailed Implementation

[0026] The following detailed description, in conjunction with the accompanying drawings, provides specific embodiments of the present invention and clearly and completely describes the technical solutions of the present invention. However, the present invention is not limited to the following embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise ratios, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] It should be understood that the present invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated, and the same reference numerals denote the same elements throughout. It should be understood that when an element or layer is referred to as “on,” “adjacent to,” “connected to,” or “coupled to” other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part.

[0028] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below with reference to specific illustrations.

[0029] The present invention describes a PIP stacked capacitor and its manufacturing process in an ETOX Flash memory. Firstly, its structure is referenced... Figure 4The diagram shown is a cross-sectional schematic of the PIP (Polymer In-line Package) multilayer capacitor of this invention. This PIP capacitor is integrated into the flash memory device and shares the same process as the flash device. Therefore, the structure of this invention uses the same descriptive methods as the flash cell array bit region, such as floating gate and control gate, which are synchronous material films used in the storage cell region. The floating gate polysilicon and control gate polysilicon are used to fabricate the plates of the PIP multilayer capacitor. In this invention, the PIP multilayer capacitor has a tunneling oxide layer (tunox) on the surface of the active region substrate AA as a floating gate dielectric layer; the active region substrate contains multiple parallel STI trenches; the STI trenches are filled with a dielectric layer, the filling height of which exceeds the opening of the STI trench, forming a tooth-like STI dielectric layer protruding from the substrate plane at the opening.

[0030] Specifically, the surface of the active region substrate has a first dielectric layer as a floating gate dielectric layer, typically a tunneling oxide (TURN) layer. Above the floating gate dielectric layer is another layer of floating gate conductive material, typically polysilicon. After etching, a polysilicon floating gate (FG) is formed. The floating gate is higher than the tooth-shaped STI structure and is not covered by the STI dielectric layer, thus forming a trench above the STI trench.

[0031] The floating gate and its STI trench have an ONO layer on their sidewalls and the STI trench, covering the floating gate and the STI trench. A control gate conductive material, typically polysilicon, is then coated on the ONO layer to form the control gate CG.

[0032] from Figure 4 The cross-section shown reveals a comb-like interlocking relationship between the floating gate and the control gate, separated by an ONO layer. This wavy ONO layer, compared to existing planar structures, provides a larger actual surface area within a limited horizontal projected area, thus increasing the capacitance as the dielectric layer of the capacitor. Combined with... Figure 3 As can be seen from the plan view (perspective structure), the floating gate FG and control gate CG in the active region are arranged in multiple parallel strip structures.

[0033] The control gate CG is then covered with an interlayer dielectric ILD, and contact holes are etched to bring out each electrode, forming a PIP stacked capacitor.

[0034] This invention optimizes the structure of block-shaped PIP (Polymerized In-line Package) multilayer capacitors by transforming the active region AA of the PIP capacitor into a comb-like dense stripe shape similar to the active region AA of the Flash Cell array. This improves the load effect during the planarization process of the floating gate (FG), ensuring that the thickness of the floating gate FG is consistent with the Flash Cell array bit area, optimizing the stability of the capacitor during long-term high-voltage operation, and increasing the process window. Its main structural features are as follows: 1. The AA below the floating gate FG lead of the PIP stacked capacitor remains in a block-like merge to ensure the connection of the plates, and the capacitor lead-out method is consistent with the existing structure.

[0035] 2. After the floating gate FG is ground flat, the PIP capacitor needs to be re-etched with STI trench filling dielectric to modify its morphology and form a three-dimensional morphology with a wavy profile, so as to increase the surface area of ​​the insulating dielectric layer between the FG and CG plates, that is, to increase the capacitance.

[0036] 3. Optimize the structure's dielectric layer and tunnel oxide layer according to design calculations (capacitance approximately 3.4 fF / um). 2 The area will become 0.5 times larger, and the ONO dielectric layer (capacitance approximately 2.5 fF / um) will be affected. 2 The area will become 1.67 times the original, and the total capacitance will be basically the same as the existing structure. Considering that the width ratio of the active region AA / shallow trench isolation STI is >1 in the actual fabrication process, the capacitance will be larger after structural optimization.

[0037] 4. The ratio of AA / STI in the active region can be adjusted to obtain a fine-tuned equivalent capacitance ratio of the optimized floating gate dielectric layer and ONO dielectric layer. The capacitance can be increased by approximately 10% within the process window.

[0038] 5. The withstand voltage of the comb-shaped floating gate dielectric layer and ONO dielectric layer is basically the same as that of the block structure. After structural optimization, the high voltage withstand performance is the same.

[0039] The manufacturing method of the above structure is illustrated by an embodiment of the present invention as follows: Step 1, as follows Figure 5 As shown, a wafer is provided. A first dielectric layer, namely a tunneling oxide (TUNOX), is deposited in the active region (AA) of the device area on the wafer. Then, multiple trenches are etched and a solid-state dielectric (STI) layer is deposited and filled to form the STI. The STI is formed by etching trenches in the active region and then filling them with the STI dielectric layer. The STI dielectric layer is generally made of silicon oxide, but in some scenarios, silicon nitride may be used. The first dielectric layer is etched back to expose the TUNOX on the surface of the active region, and the first dielectric layer in the STI region protrudes from the surface of the active region to a certain height.

[0040] A first polysilicon layer for fabricating the Floating Gate (FG) is deposited, the thickness of which needs to completely cover the first dielectric layer. The first polysilicon layer is then ion-implanted and doped. Step two involves performing a CMP planarization polishing process on the first polysilicon layer, such as... Figure 6 As shown, the excess polysilicon layer is ground away. After grinding, the wafer surface is smooth, and the STI dielectric layer protruding above the active region has a certain height.

[0041] Step 3: The PIP capacitor region in the active area is opened, and the STI dielectric layer is etched back. A portion of the STI dielectric layer protruding above the tunneling oxide (TUNOX) surface in the active area is etched back, forming a downward-facing recessed region. Multiple STI trenches form multiple recessed regions, resulting in a periodic undulating morphology on the surface of the entire PIP capacitor region, such as... Figure 7 As shown. The purpose of this step is to increase the area of ​​the subsequent second dielectric layer, ONO, which will be explained in detail later.

[0042] Step four: An ONO layer is deposited in the PIP capacitor region of the active area and etched back to form a second dielectric layer, i.e., the ONO layer, covering the surface of the active area AA. The ONO layer is then etched back to remove the ONO thin film layer outside the lower electrode of FG. The formed ONO film layer adheres to the surface morphology of the active area, forming a wave-like morphology with periodic undulations, such as... Figure 8 As shown, this morphology can increase the surface area of ​​the ONO film layer with a limited horizontal area occupied, which in turn increases the area of ​​the intermediate insulating dielectric layer of the capacitor formed by FG / ONO / CG, thereby increasing the capacitance.

[0043] Step 5: Deposit a second polysilicon layer for fabricating the Control Gate (CG). CG serves as the PIP capacitor plate 2-2. The active region AA (PIP capacitor plate 2-1, active region AA) is opened by etching back the second polysilicon layer (CG_ET).

[0044] The CG region of the PIP capacitor is etched open using a gate polysilicon etch-back (GPL_ET) process, with the etching stopping at the ONO thin film layer, preparing for the FG lead-out (PIP capacitor plate 1) and forming the lead-out channel; as shown... Figure 9 and Figure 10 As shown.

[0045] Step six: Proceed with the subsequent steps according to the conventional ETOX Flash cell fabrication process, including sidewall spacer / SAB / interlayer dielectric (ILD) processes. The ONO above the FG will be opened during the sidewall spacer / SAB etching process.

[0046] The CT_ET contact hole etching process simultaneously brings out CG, FG, and AA, and connects capacitor plates 2-1 and 2-2 through metal layer M1, ultimately forming the device as shown. Figure 4 As shown.

[0047] This invention optimizes the process of AA / Tunox / FG / ONO / CG stacked capacitors in 48nm ETOX NOR Flash technology. Addressing the drawback of the FG layer in planar capacitors being prone to thinning during processing, a denser AA / STI pattern is used to improve the FG CMP process window. STI is resolved during the CRS process to increase the FG / ONO / CG capacitor area, resulting in a slightly larger overall capacitance. Thickening the polysilicon of the FG terminal plate avoids the risk of FG breakdown during etching CT or gate oxide breakdown during high-voltage pump circuit testing due to excessive FG thickness, thus preventing related reliability failures.

[0048] The above are merely preferred embodiments of the present invention and are not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A manufacturing process for PIP stacked capacitors in an ETOX Flash memory, characterized in that: Include: Step 1: Provide a semiconductor substrate, and deposit a first dielectric layer as a floating gate dielectric layer in the active region of the device area on the semiconductor substrate; then etch multiple trenches and deposit and fill a layer of STI dielectric layer to form STI; The first dielectric layer is etched back to expose the first dielectric layer on the surface of the active region, and the STI dielectric layer in the STI region protrudes from the surface of the active region to form a certain height. A first polysilicon layer for fabricating the floating gate is deposited, the thickness of which needs to completely cover the STI dielectric layer; the first polysilicon layer is then ion-implanted and doped. Step 2: Perform a grinding process on the first polysilicon layer to remove the excess thickness of the first polysilicon layer; The remaining first polysilicon layer in the PIP stacked capacitor region serves as the first electrode of the PIP stacked capacitor. Step 3: Open the PIP stacked capacitor region of the active area using photolithography, and perform back etching of the STI dielectric layer. Part of the STI dielectric layer protruding above the active area surface above the STI trench is etched back to form a recessed area that is downward relative to the current active area surface. Multiple STI trenches form multiple recessed areas, and the surface of the PIP stacked capacitor region forms a periodic undulating morphology. Step 4: A thin film is deposited in the active region PIP stacked capacitor region to form a second dielectric layer and then etched back to form a second dielectric layer covering the surface of the first polysilicon layer. Then, the second dielectric layer is etched back to remove the first polysilicon layer as the second dielectric layer outside the first electrode. The second dielectric layer with the completed morphology etching is attached to the surface morphology of the active region to form a wave-like morphology with periodic undulations. This three-dimensional morphology can increase the surface area of ​​the second dielectric layer with a limited horizontal projection area. Step 5: Deposit a second polysilicon layer for fabricating the control gate and etch it to form the control gate. Etch the remaining second polysilicon layer in the PIP stacked capacitor region as the second electrode of the PIP stacked capacitor. Open the active region AA by etching back the second polysilicon layer. By simultaneously etching back the gate polysilicon of the flash memory, a portion of the second polysilicon layer of the PIP stacked capacitor region is etched away, and the etching stops on the second dielectric layer, forming an outgoing channel for the first electrode of the PIP stacked capacitor.

2. The process method for PIP stacked capacitors in ETOX Flash as described in claim 1, characterized in that: The semiconductor substrate includes a silicon substrate, a germanium-silicon substrate, a gallium arsenide substrate, a gallium nitride substrate, and a silicon carbide substrate.

3. The process method for PIP stacked capacitors in ETOX Flash as described in claim 1, characterized in that: In one of the steps, the first dielectric layer is a tunneling oxide (TUNOX), and the STI dielectric layer is silicon oxide or silicon nitride.

4. The process method for PIP stacked capacitors in ETOX Flash as described in claim 1, characterized in that: In step two, the grinding process adopts the CMP process. After grinding is completed, the wafer surface is flat, and the STI dielectric layer protruding above the active area has a certain height.

5. The process method for PIP stacked capacitors in ETOX Flash as described in claim 1, characterized in that: In step four, the second dielectric layer is an ONO layer; the surface area of ​​the intermediate insulating dielectric layer of the capacitor is increased by multiple undulating surface morphologies, thereby increasing the capacitance.

6. The process method for PIP stacked capacitors in ETOX Flash as described in claim 1, characterized in that: The process method also includes step six, which involves performing subsequent steps according to the conventional ETOX Flash cell fabrication process, including sidewall Spacer / SAB / interlayer dielectric ILD deposition process, whereby the second dielectric layer above the first polysilicon layer will be opened during the sidewall Spacer / SAB etching process.

7. The contact hole etching process simultaneously brings out the control gate, floating gate, and active region. The control gate and active region are connected together through the first metal layer to form the second plate of the PIP stacked capacitor.

8. A structure of PIP stacked capacitors in an ETOX Flash, characterized in that: The PIP stacked capacitor is integrated in the Flash memory, and the active area of ​​the PIP stacked capacitor consists of multiple comb-shaped strips. The floating gate polysilicon in the PIP stacked capacitor region forms the first electrode plate, and the active region below its lead-out terminal remains in a block-shaped merging. The first plate of the PIP stacked capacitor, which is composed of floating gate polysilicon, is alternately arranged with an STI and has a height difference. Multiple STIs isolate the floating gate polysilicon to form multiple parallel strips. The second dielectric layer, which serves as the capacitor dielectric layer, has a wavy 3D morphology, which increases the surface area of ​​the second dielectric layer within a limited horizontal projected area, thereby increasing the capacitance. Above the second dielectric layer is a part of the second electrode plate formed by control gate polysilicon, which is connected to the active region of the PIP stacked capacitor region through an interconnect structure to form the second electrode plate of the PIP stacked capacitor together. The first dielectric layer is located between the floating gate polysilicon and the active region in the PIP stacked capacitor region.

9. The structure of the PIP stacked capacitor in the ETOX Flash as described in claim 7, characterized in that: The comb-shaped active region optimizes the consistency of pattern density and improves the load effect during the planarization process of floating gate polysilicon grinding. The first plate of the PIP stacked capacitor is formed by synchronous grinding of the floating gate polysilicon in the flash cell region, which is consistent with the thickness of the floating gate, optimizes the high voltage long-term performance of the capacitor, and increases the process window.

10. The structure of the PIP stacked capacitor in the ETOX Flash as described in claim 7, characterized in that: The ratio of the active region to the area of ​​the STI in the PIP stacked capacitor is adjustable, thereby achieving fine-tuning of the equivalent capacitance ratio of the first and second dielectric layers after optimization.

11. The structure of the PIP stacked capacitor in the ETOX Flash as described in claim 7, characterized in that: The thicknesses of the first and second dielectric layers are consistent with those of the existing structure.

12. The structure of the PIP stacked capacitor in the ETOX Flash as described in claim 7, characterized in that: The height difference between the first plate of the PIP stacked capacitor and the STI is achieved by etching back the thickness of the STI dielectric layer, thereby reducing the height of the STI.

13. The structure of the PIP stacked capacitor in the ETOX Flash as described in any one of claims 7 to 11, characterized in that: The first dielectric layer is a tunneling oxide layer, and the second dielectric layer is an ONO layer.

Images