Manufacturing method of semiconductor device
By forming a polycrystalline silicon layer on a semiconductor substrate and performing ion implantation and oxide layer protection, the problem of depression caused by density differences in the patterned area is solved, thereby improving the reliability of semiconductor devices and the flexibility of the process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-14
- Publication Date
- 2026-04-14
AI Technical Summary
In the prior art, the problem of indentation after grinding caused by the density difference in the patterned area affects the reliability of PIP capacitors.
A polysilicon layer is formed on a semiconductor substrate and ion implantation is performed. After forming an oxide layer, the oxide layers in different patterned areas are protected and etched. Chemical mechanical polishing is then used to ensure that the polysilicon layer thickness is consistent.
It improves the reliability of semiconductor devices, and the process is simple, flexible, and easy to implement.
Smart Images
Figure CN121865620A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device. Background Technology
[0002] PIP (Poly-insulator-poly) capacitors are parasitic capacitors provided by floating-gate memory technology platforms. They combine the capacitance of the inter-gate dielectric layer and the capacitance of the tunneling oxide layer in parallel to provide a high-capacitance capacitor. Existing PIP capacitors are planar capacitors, primarily used in charge pump boost circuits or filter circuits. Please refer to... Figures 1a-1c as well as Figure 2 ,in, Figures 1a-1c This is a cross-sectional view of the semiconductor structure corresponding to the semiconductor device fabrication process in related technologies. Figure 2 The diagram illustrates the impact of pitting on the reliability of semiconductor devices, using a PIP capacitor as an example. This planar structure, in its fabrication process, such as... Figure 1a The diagram shown is a cross-sectional view of a first patterned region 110 and a second patterned region 120 on a semiconductor substrate 100, where multiple isolation structures 500 are formed, and an insulating layer 600 and a first polysilicon layer 210 are stacked. Figure 1b The diagram shown is a cross-sectional view of an ultrathin oxide layer 300 formed on the first polycrystalline silicon layer 210; as shown... Figure 1c The image shown is a cross-sectional schematic diagram after chemical mechanical polishing of the oxide layer 300 and the first polysilicon layer 210. However, as... Figure 1c and Figure 2 As shown, due to the significant difference in pattern density between the array region (i.e., the first pattern region 110) and the PIP capacitor region (i.e., the second pattern region 120), the FG CMP (FG: Floating Gate, CMP: Chemical Mechanical Polishing) grinding process produces a large dishing 211 in the PIP region, resulting in a thinner floating gate (FG) thickness in this region. Figure 2 As shown, in severe cases, it can affect the reliability of the PIP capacitor (for example, the second polysilicon layer 220 and the first polysilicon layer 210 may become conductive).
[0003] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0004] The purpose of this invention is to address the problem in the prior art where low-density patterned areas become concave after grinding due to different pattern densities in various patterned regions during semiconductor device fabrication. This invention provides a method for fabricating semiconductor devices that ensures consistent polysilicon layer thickness in regions with different pattern densities, thereby improving the reliability of semiconductor devices. Furthermore, the process is simple, convenient, highly flexible, and easy to implement.
[0005] To achieve the above objectives, the present invention provides the following technical solution: a method for fabricating a semiconductor device, comprising:
[0006] A semiconductor substrate is provided, and a first polysilicon layer is formed on the semiconductor substrate by floating gate polysilicon deposition; wherein the semiconductor substrate includes a first patterned region and a second patterned region, and the pattern density of the first patterned region is greater than the pattern density of the second patterned region;
[0007] Ion implantation is performed on the first polysilicon layer, and an oxide layer is formed on the top surface of the first polysilicon layer;
[0008] The oxide layer of the second patterned region is protected and the oxide layer of the first patterned region is etched.
[0009] Chemical mechanical polishing is performed on the first polysilicon layer in the first patterned region and the oxide layer and the first polysilicon layer in the second patterned region.
[0010] The semiconductor device is generated based on the first polycrystalline silicon layer after chemical mechanical polishing.
[0011] Optionally, the method for fabricating the semiconductor device includes forming the oxide layer on the top surface of the first polycrystalline silicon layer using a thermal oxidation method.
[0012] Optionally, the thickness of the oxide layer is
[0013] Optionally, protecting the oxide layer of the second patterned region includes: superimposing a protective layer on the top surface of the oxide layer of the second patterned region.
[0014] Optionally, the protective layer includes a photoresist layer.
[0015] Optionally, etching the oxide layer of the first patterned region includes removing the oxide layer of the first patterned region using wet etching.
[0016] Optionally, the oxide layer in the first patterned region is removed by wet etching with hydrofluoric acid. Optionally, the semiconductor device is generated based on the first polysilicon layer after chemical mechanical polishing, comprising:
[0017] At least an insulating dielectric layer and a second polysilicon layer are formed on the top surface of the first polysilicon layer, and the first polysilicon layer, the insulating dielectric layer and the second polysilicon layer are selectively etched to generate the semiconductor device.
[0018] Optionally, a PIP capacitor is generated in the second patterned region, wherein the second polysilicon layer and the first polysilicon layer serve as the upper and lower plates of the PIP capacitor, respectively.
[0019] Optionally, a memory array structure is generated in the first patterned region, wherein the second polysilicon layer and the first polysilicon layer serve as the control gate and floating gate of the unit of the memory array structure, respectively.
[0020] Optionally, before depositing floating-gate polysilicon on the semiconductor substrate to form a first polysilicon layer, the fabrication method further includes:
[0021] An insulating layer is formed on the semiconductor substrate, and a plurality of isolation structures are formed on the side of the semiconductor substrate near the insulating layer, wherein the top surface of the isolation structures is higher than the top surface of the insulating layer.
[0022] The step of depositing floating-gate polysilicon on the semiconductor substrate to form a first polysilicon layer includes:
[0023] A first polysilicon layer is formed by depositing floating gate polysilicon on the top surface of the insulating layer, wherein the top surface of the first polysilicon layer is higher than the top surface of the isolation structure.
[0024] Compared with the prior art, the method for fabricating a semiconductor device provided by the present invention has the following advantages:
[0025] The method for fabricating a semiconductor device provided by this invention firstly deposits floating-gate polysilicon on a semiconductor substrate to form a first polysilicon layer, laying the foundation for forming polysilicon electrodes (such as PIP capacitors) and high-resistivity polysilicon according to the structure of the semiconductor device. Then, by ion implantation, the conductivity, permeability, and other properties of the first polysilicon layer can be changed, thereby laying the foundation for further improving the performance of the semiconductor device. Furthermore, by forming an oxide layer on the top surface of the first polysilicon layer, not only can contaminants be prevented from damaging the surface of the first polysilicon layer, thus protecting the first polysilicon layer, but it also facilitates the smooth progress of subsequent processes. Furthermore, by protecting the oxide layer in the second patterned region and etching the oxide layer in the first patterned region (exemplarily, removing the oxide layer in the first patterned region and retaining the oxide layer in the second patterned region), it is possible to fully utilize the polishing slurry to polish the oxide layer when performing chemical mechanical polishing on the first polysilicon layer in the first patterned region and the oxide layer and the first polysilicon layer in the second patterned region. Although the oxide layer is polished away slowly, a certain removal ratio is still achieved. After the oxide layer is polished away, the polishing rate increases due to the loading effect of the second patterned region. Ultimately, the thickness of the first polysilicon layer in the first patterned region and the second patterned region is kept consistent, thereby improving the reliability of the semiconductor device. Moreover, the process is simple, convenient, flexible, and easy to implement. Attached Figure Description
[0026] Figures 1a-1c This is a cross-sectional view of the semiconductor structure corresponding to the semiconductor device fabrication process in related technologies;
[0027] Figure 2 A schematic diagram illustrating the impact of denting on the reliability of semiconductor devices is given, using a PIP capacitor as an example.
[0028] Figure 3 This is a schematic diagram of the overall process of a method for fabricating a semiconductor device according to one embodiment of the present invention;
[0029] Figures 4a-4d A cross-sectional view of the semiconductor structure corresponding to the relevant steps of the semiconductor device fabrication method provided by the present invention.
[0030] The reference numerals in the attached figures are as follows:
[0031] Semiconductor substrate-100, first patterned area-110, second patterned area-120;
[0032] First polysilicon layer - 210, second polysilicon layer - 220, recess - 211, oxide layer - 300, protective layer - 400, isolation structure - 500, insulating layer - 600. Detailed Implementation
[0033] The following detailed description, in conjunction with the accompanying drawings, provides a further detailed explanation of a method for fabricating a semiconductor device according to the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, intended only to facilitate and clearly illustrate the embodiments of the present invention. Please refer to the drawings to make the objectives, features, and advantages of the present invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes and to enable those skilled in the art to understand and read them, and are not intended to limit the implementation conditions of the present invention. Any modifications to the structure, changes in proportions, or adjustments to the size, provided they produce the same or similar effects and achieve the same objectives as the present invention, should still fall within the scope of the technical content disclosed in the present invention. Specific design features of the present invention disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific application and usage environment. Furthermore, in the embodiments described below, the same reference numerals are sometimes used across different drawings to denote the same parts or parts having the same function, omitting repeated descriptions. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it need not be discussed further in subsequent figures. Furthermore, if the methods described herein involve a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, some of the described steps may be omitted and / or other steps not described herein may be added to the method.
[0034] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The singular forms “a,” “an,” and “the” include plural objects. The term “or” is generally used to mean “and / or,” the term “several” is generally used to mean “at least one,” and the term “at least two” is generally used to mean “two or more.” Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.
[0035] The core idea of this invention is to provide a method for manufacturing semiconductor devices. This invention can ensure that the thickness of the polysilicon layer is consistent in regions with different pattern densities, thereby improving the reliability of semiconductor devices. Moreover, the process is simple, convenient, flexible, and easy to implement.
[0036] For example, please see Figure 3 as well as Figures 4a-4d ,in, Figure 3 This is a schematic diagram of the overall process of a method for fabricating a semiconductor device according to one embodiment of the present invention; Figures 4a-4d Cross-sectional views of the semiconductor structure corresponding to the steps in the fabrication method of the semiconductor device provided by this invention. From Figure 3 As can be seen, the method for fabricating a semiconductor device provided by the present invention includes:
[0037] S100: A semiconductor substrate 100 is provided, and a first polysilicon layer 210 is formed on the semiconductor substrate 100 by floating gate polysilicon deposition; wherein, the semiconductor substrate 100 includes a first patterned region 110 and a second patterned region 210, and the pattern density of the first patterned region 110 is greater than the pattern density of the second patterned region 210.
[0038] S200: Ion implantation is performed on the first polysilicon layer 210, and an oxide layer 300 is formed on the top surface of the first polysilicon layer 210.
[0039] S300: Protect the oxide layer 300 of the second patterned region 210 and etch the oxide layer 300 of the first patterned region 110;
[0040] S400: Perform chemical mechanical polishing on the first polysilicon layer 210 of the first patterned region 110 and the oxide layer 300 and the first polysilicon layer 210 of the second patterned region 210.
[0041] S500: The semiconductor device is generated based on the first polycrystalline silicon layer 210 after chemical mechanical polishing.
[0042] The method for fabricating a semiconductor device provided by the present invention firstly deposits floating-gate polysilicon on the semiconductor substrate 100 to form a first polysilicon layer 210, laying the foundation for forming polysilicon electrodes (such as PIP capacitors) and high-resistivity polysilicon according to the structure of the semiconductor device; then, by ion implantation, the conductivity, permeability and other properties of the first polysilicon layer 210 can be changed, thereby laying the foundation for further improving the performance of the semiconductor device; furthermore, by forming an oxide layer 300 on the top surface of the first polysilicon layer 210, not only can contaminants be prevented from damaging the surface of the first polysilicon layer 210, thus protecting the first polysilicon layer 210, but it also facilitates the smooth progress of subsequent processes. Furthermore, by protecting the oxide layer 300 of the second patterned region 210 and etching the oxide layer 300 of the first patterned region 110 (exemplarily, removing the oxide layer 300 of the first patterned region 110 while retaining the oxide layer 300 of the second patterned region 210), it is possible to fully utilize the polishing slurry to polish the oxide layer 300 during chemical mechanical polishing of the first polysilicon layer 210 of the first patterned region 110 and the oxide layer 300 and the first polysilicon layer 210 of the second patterned region 210. Although the polishing is slow, a certain removal ratio is still achieved. After the oxide layer 300 is polished away, the polishing rate increases due to the loading effect of the second patterned region 210. Ultimately, the thickness of the first polysilicon layer 210 of the first patterned region 110 and the second patterned region 210 remains consistent, thereby improving the reliability of the semiconductor device. Moreover, the process is simple, convenient, flexible, and easy to implement.
[0043] Exemplarily, in step S100 above, the provided semiconductor substrate 100 can be any suitable substrate known in the art, such as at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or it can be a double-sided polished wafer (DSP), or a ceramic substrate such as alumina, quartz, or glass substrate. Exemplarily, in this embodiment, the semiconductor substrate 100 is, for example, a silicon wafer. Exemplarily, the first patterned region 110 of the semiconductor substrate 100 is used to form a semiconductor memory, and the second patterned region 210 is used to form a PIP capacitor. The first patterned region 110 and the second patterned region 210 may be adjacent or non-adjacent, that is, they can be divided according to the layout design of the wafer or chip, and their specific positional relationship and connection relationship are subject to the actual needs of the product. It should be noted that, as those skilled in the art will understand, the above description of the first patterned region 110 of the semiconductor substrate 100 being used to form a semiconductor memory and the second patterned region 210 being used to form a PIP capacitor is merely illustrative. The first patterned region 110 and the second patterned region 210 in this document are only schematic illustrations of their respective uses to form different semiconductor devices to achieve different device functions. This invention does not impose excessive limitations on the specific types of the semiconductor devices. Furthermore, since the key innovation of the fabrication method in this embodiment lies in steps S100-S300, therefore... Figures 4a-4d Only the parts related to the innovative aspects of this invention are drawn.
[0044] For example, please see Figure 4a , Figure 4a This is a cross-sectional view of the semiconductor structure after step S100 (FG Poly dep, polysilicon layer deposition). Preferably, in some exemplary embodiments, before step S100, floating gate polysilicon deposition is performed on the semiconductor substrate 100 to form the first polysilicon layer 210, the fabrication method further includes:
[0045] An insulating layer 600 is formed on the semiconductor substrate 100, and a plurality of isolation structures 500 are formed on the side of the semiconductor substrate 100 near the insulating layer 600, wherein the top surface of the isolation structure 500 is higher than the top surface of the insulating layer 600.
[0046] The step of depositing floating-gate polysilicon on the semiconductor substrate 100 to form a first polysilicon layer 210 includes:
[0047] A floating gate polysilicon deposition is performed on the top surface of the insulating layer 600 to form the first polysilicon layer 210, and the top surface of the first polysilicon layer is higher than the top surface of the isolation structure 500.
[0048] Therefore, by forming an insulating layer 600 and a plurality of isolation structures 500 on the semiconductor substrate 100, with the top surface of the isolation structures 500 higher than the top surface of the insulating layer 600, not only can the individual semiconductor devices be isolated to prevent leakage and other issues, but stress can also be relieved, helping to protect subsequently formed semiconductor devices from damage. For example, as... Figures 4a-4b As shown, the density of the isolation structure 500 in the first graphic region 110 is greater than the density of the isolation structure 500 in the second graphic region 210, thereby ensuring that the graphic density of the first graphic region 110 is greater than the graphic density of the second graphic region 210.
[0049] It should be noted that, as those skilled in the art will understand, the present invention does not impose excessive limitations on the material and formation method of the isolation structure 500. For example, it can be formed by first depositing, patterning, and etching silicon using a silicon nitride mask to create a trench, and then filling the trench with deposited oxide. For more detailed information on how to form the isolation structure 500, please refer to relevant technologies known to those skilled in the art; this will not be elaborated upon herein. Similarly, the present invention does not impose excessive limitations on the material and formation method of the insulating layer 600. For example, the insulating layer 600 can be formed by depositing an OX / SIN / OX(ONO) thin film, a SIN / OX / SIN / OX / SIN(NONON) thin film, or any other high-k (or high-dielectric-constant) dielectric thin film. Furthermore, in some embodiments, other film layer structures can also be formed on the semiconductor substrate 100; the present invention does not limit this.
[0050] For example, please see Figure 4b , Figure 4b This is a cross-sectional view of the semiconductor structure after step S200 (FG Poly RTO, thermal oxidation to form oxide layer 300). Further, the formation of oxide layer 300 on the top surface of the first polysilicon layer 210 in step S200 includes forming the oxide layer 300 on the top surface of the first polysilicon layer 210 using a thermal oxidation method. Therefore, a high-quality, ultra-thin oxide layer 300 can be obtained through rapid thermal oxidation (RTO), which not only prevents contaminants from damaging the surface of the first polysilicon layer 210, thus protecting the first polysilicon layer 210, but also facilitates the smooth progress of subsequent processes.
[0051] It is understood that the formation of the oxide layer 300 on the top surface of the first polycrystalline silicon layer 210 using a rapid heating oxidation method is merely an exemplary description of a preferred embodiment and not a limitation of the present invention. The present invention does not impose excessive limitations on the material of the oxide layer 300 or its formation method. Exemplarily, in some embodiments, the material of the oxide layer 300 may be silicon dioxide. Besides the rapid heating oxidation method, methods including, but not limited to, wet oxidation or chemical vapor deposition may also be used.
[0052] Preferably, in some exemplary embodiments, the thickness of the oxide layer 300 is [missing information]. Therefore, by setting the thickness of the oxide layer 300 to... This not only protects the first polysilicon layer 210, but also facilitates the subsequent removal of the oxide layer 300. Understandably, the present invention does not impose excessive limitations on the specific thickness of the oxide layer 300; its specific thickness can be selected based on the thickness of the first polysilicon layer 210, the required polishing thickness, and / or the polishing process.
[0053] For example, protecting the oxide layer 300 of the second patterned region 210 in step S300 includes: depositing a protective layer 400 on the top surface of the oxide layer 300 of the second patterned region 210. Thus, by depositing a protective layer 400 on the top surface of the oxide layer 300 of the second patterned region 210, a foundation is laid for ensuring that the thickness of the first polysilicon layer 210 of the first patterned region 110 and the second patterned region 210 remains consistent during subsequent polishing.
[0054] Preferably, in some of the exemplary embodiments, such as Figure 4cAs shown, the protective layer 400 includes a photoresist layer. It is understood that the present invention does not impose excessive limitations on the formation method of the photoresist layer. Exemplarily, an existing photomask (PH) can be used to form the photoresist layer using chemical vapor transport (CVT), thereby exposing the oxide layer 300 of the first patterned region 110 and masking the oxide layer 300 of the second patterned region 210, so as to retain the oxide layer 300 of the second patterned region 210 when etching the oxide layer 300 of the first patterned region 110. Furthermore, the present invention does not impose excessive limitations on the material of the protective layer 400, preferably using a photoresist-based etching material. Exemplarily, the protective layer 400 (e.g., using photoresist as the protective layer 400) can be a thin film formed by chemical vapor deposition of a novel polymer material using photoresist etching. Therefore, when the oxide layer 300 of the first patterned region 110 is subsequently removed, the protective layer 400 possesses excellent mechanical properties and chemical corrosion resistance, effectively protecting the oxide layer 300 of the second patterned region 210. Exemplarily, in some exemplary embodiments, the etching of the oxide layer 300 of the first patterned region 110 in step S300 includes removing the oxide layer 300 of the first patterned region 110 using wet etching. Thus, by removing the oxide layer 300 of the first patterned region 110 while retaining the oxide layer 300 of the second patterned region 210 through wet etching, a good foundation is laid for subsequent chemical mechanical polishing to select different polishing ratios for the oxide layer 300 and the first polysilicon layer 210, thereby utilizing the different polishing rates of the oxide layer 300 and the first polysilicon layer 210, as well as the loading effect between the first patterned region 110 and the second patterned region 210, to achieve complementary polishing.
[0055] Exemplary examples, in some exemplary embodiments, the removal of the oxide layer 300 of the first patterned region 110 by wet etching includes removing the oxide layer of the first patterned region by hydrofluoric acid wet etching. Thus, by using hydrofluoric acid as the primary chemical carrier, not only can the oxide layer 300 of the first patterned region 110 be removed more economically and effectively, but it also exhibits weaker corrosivity to the protective layer 400 located in the second patterned region 210, which is more beneficial for the protective layer 400 to protect the oxide layer 300 of the second patterned region 210.
[0056] It should be noted that the use of hydrofluoric acid (HF) as the main chemical carrier for wet etching in this article is merely an exemplary description of a preferred embodiment and not a limitation of the present invention. The present invention does not impose excessive limitations on the specific wet etching process; the material of the oxide layer 300 can be reasonably selected when implementing the present invention. For example, in some preferred embodiments, phosphoric acid can also be used as the main chemical carrier for wet etching. Furthermore, the present invention does not impose excessive limitations on the etching method of the oxide layer 300 in the first patterned region 110. For example, in some other embodiments, dry etching can also be used to remove the oxide layer 300. For more detailed information on wet etching and dry etching, please refer to etching-related content known to those skilled in the art; this will not be elaborated upon here.
[0057] For example, please see Figure 4c , Figure 4c This is a cross-sectional view of the semiconductor structure after step S300 (forming a photoresist layer in the second patterned region 210 and etching away the oxide layer 300, i.e., CVT PH and HF, in the first patterned region 110).
[0058] Further, please see Figure 4d , Figure 4d This is a cross-sectional view of the semiconductor structure after step S400 chemical mechanical polishing (CMP). By comparison... Figure 4d and Figure 1c It is not difficult to see that, using the semiconductor device fabrication method provided by the present invention, after the grinding process, the thickness of the first polysilicon layer 210 of the first patterned region 110 and the second patterned region 210 is basically the same, and there is no problem that the second patterned region 210 (such as the PIP capacitor region) is too thin, which can effectively ensure the reliability of the semiconductor device subsequently fabricated.
[0059] Preferably, after etching away the oxide layer 300 of the first patterned region 110 and after performing chemical mechanical polishing (CMP) on the first polysilicon layer 210 of the first patterned region 110 and the oxide layer 300 and the first polysilicon layer 210 of the second patterned region 210 in step S400, a cleaning process can be performed to improve the quality of the semiconductor device.
[0060] For example, step 500, which involves generating the semiconductor device based on the first polycrystalline silicon layer 210 after chemical mechanical polishing, includes:
[0061] At least an insulating dielectric layer and a second polysilicon layer are formed on the top surface of the first polysilicon layer 210, and the first polysilicon layer 210, the insulating dielectric layer and the second polysilicon layer 220 are selectively etched to generate the semiconductor device.
[0062] It should be noted that the present invention does not impose excessive limitations on the specific formation method of the semiconductor device. Preferably, in some preferred embodiments, a PIP capacitor is formed in the second patterned region 210, wherein the second polysilicon layer and the first polysilicon layer 210 serve as the upper and lower electrodes of the PIP capacitor, respectively. Thus, by using the first polysilicon layer 210 of the second patterned region 210 with a flat top surface as the lower electrode of the PIP capacitor, the reliability of the PIP capacitor can be guaranteed.
[0063] Preferably, in some preferred embodiments, a memory array structure is formed in the first patterned region 110, wherein the second polysilicon layer and the first polysilicon layer 210 serve as the control gate and floating gate of the units of the memory array structure, respectively. Therefore, by forming the memory array structure in the first patterned region 110 and using the second polysilicon layer and the first polysilicon layer 210 as the control gate and floating gate of the units of the memory array structure, it is more conducive to forming PIP capacitors in the second patterned region 210, improving the fabrication efficiency of the semiconductor device and ensuring its performance.
[0064] In summary, compared with the prior art, the method for fabricating a semiconductor device provided by the present invention has the following beneficial effects:
[0065] The method for fabricating a semiconductor device provided by this invention firstly deposits floating-gate polysilicon on a semiconductor substrate to form a first polysilicon layer, laying the foundation for forming polysilicon electrodes (such as PIP capacitors) and high-resistivity polysilicon according to the structure of the semiconductor device. Then, by ion implantation, the conductivity, permeability, and other properties of the first polysilicon layer can be changed, thereby laying the foundation for further improving the performance of the semiconductor device. Furthermore, by forming an oxide layer on the top surface of the first polysilicon layer, not only can contaminants be prevented from damaging the surface of the first polysilicon layer, thus protecting the first polysilicon layer, but it also facilitates the smooth progress of subsequent processes. Furthermore, by protecting the oxide layer in the second patterned region and etching the oxide layer in the first patterned region (exemplarily, removing the oxide layer in the first patterned region and retaining the oxide layer in the second patterned region), it is possible to fully utilize the polishing slurry to polish the oxide layer when performing chemical mechanical polishing on the first polysilicon layer in the first patterned region and the oxide layer and the first polysilicon layer in the second patterned region. Although the oxide layer is polished away slowly, a certain removal ratio is still achieved. After the oxide layer is polished away, the polishing rate increases due to the loading effect of the second patterned region. Ultimately, the thickness of the first polysilicon layer in the first patterned region and the second patterned region is kept consistent, thereby improving the reliability of the semiconductor device. Moreover, the process is simple, convenient, flexible, and easy to implement.
[0066] The above description is merely a preferred embodiment of a method for manufacturing a semiconductor device provided by the present invention, and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure are within the protection scope of the present invention. Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the present invention and its equivalents, the present invention also intends to include these modifications and variations.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor substrate is provided, and a first polysilicon layer is formed on the semiconductor substrate by floating gate polysilicon deposition; wherein the semiconductor substrate includes a first patterned region and a second patterned region, and the pattern density of the first patterned region is greater than the pattern density of the second patterned region; Ion implantation is performed on the first polysilicon layer, and an oxide layer is formed on the top surface of the first polysilicon layer; The oxide layer of the second patterned region is protected and the oxide layer of the first patterned region is etched. Chemical mechanical polishing is performed on the first polysilicon layer in the first patterned region and the oxide layer and the first polysilicon layer in the second patterned region. The semiconductor device is generated based on the first polycrystalline silicon layer after chemical mechanical polishing.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, This includes forming the oxide layer on the top surface of the first polycrystalline silicon layer using a heating oxidation method.
3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The thickness of the oxide layer is 4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The method of protecting the oxide layer of the second patterned region includes: superimposing a protective layer on the top surface of the oxide layer of the second patterned region.
5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The protective layer includes a photoresist layer.
6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The etching of the oxide layer in the first patterned region includes removing the oxide layer in the first patterned region using wet etching.
7. The method for fabricating a semiconductor device according to claim 6, characterized in that, This includes removing the oxide layer from the first patterned area using a hydrofluoric acid wet etching process.
8. The method for fabricating a semiconductor device according to claim 1, characterized in that, The semiconductor device is generated from the first polycrystalline silicon layer after chemical mechanical polishing, comprising: At least an insulating dielectric layer and a second polysilicon layer are formed on the top surface of the first polysilicon layer, and the first polysilicon layer, the insulating dielectric layer and the second polysilicon layer are selectively etched to generate the semiconductor device.
9. The method for fabricating a semiconductor device according to claim 8, characterized in that, A PIP capacitor is generated in the second patterned region, wherein the second polysilicon layer and the first polysilicon layer serve as the upper and lower plates of the PIP capacitor, respectively.
10. The method for fabricating a semiconductor device according to claim 8, characterized in that, A memory array structure is generated in the first patterned region, wherein the second polysilicon layer and the first polysilicon layer serve as the control gate and floating gate of the unit of the memory array structure, respectively.
11. A method for fabricating a semiconductor device according to any one of claims 1 to 10, characterized in that, Before depositing a floating-gate polysilicon layer on the semiconductor substrate to form a first polysilicon layer, the fabrication method further includes: An insulating layer is formed on the semiconductor substrate, and a plurality of isolation structures are formed on the side of the semiconductor substrate near the insulating layer, wherein the top surface of the isolation structures is higher than the top surface of the insulating layer. The step of depositing floating-gate polysilicon on the semiconductor substrate to form a first polysilicon layer includes: A first polysilicon layer is formed by depositing floating gate polysilicon on the top surface of the insulating layer, wherein the top surface of the first polysilicon layer is higher than the top surface of the isolation structure.