Intelligent drive control circuit and control method of adaptive valve body impedance

Abstract

The application discloses an intelligent driving control circuit and method of self-adaptive valve body impedance, and relates to the technical field of valve body driving control. The encoding signal generation unit converts a single-channel switch signal into a double-channel differential encoding signal; the logic decoding and interlocking unit outputs a driving trigger signal when the decoding result is a driving enabled state, and blocks the output in a non-driving safety state, and single-line flipping does not change the blocking state; the impedance detection unit applies a detection electric signal lower than the minimum action threshold of the valve body to the valve body load in a non-driving period and obtains an impedance value; the driving parameter self-adaptive adjustment unit matches the driving parameter according to the comparison result of the impedance value and a preset threshold value; and the power output stage outputs driving power according to the driving trigger signal and the driving parameter. The application can automatically distinguish the electromagnetic valve and the electric explosion valve and match the differentiated driving parameters, prevents the mis-triggering through the double-channel differential encoding interlocking, and detects the load state on line in the non-driving period, so that the safety is high and the adaptability is strong.

Description

Technical Field

[0001] This invention relates to the field of valve body drive control technology, specifically to an intelligent drive control circuit and method that can automatically match drive parameters according to the valve body load impedance and detect the load status online during non-drive periods, and particularly to an intelligent drive control circuit and control method that adapts to valve body impedance. Background Technology

[0002] In fields such as fire protection systems, industrial automation, and aerospace, solenoid valves and electric explosion valves are two commonly used actuators. Solenoid valve coils typically have an impedance of tens to hundreds of ohms and require continuous energization to maintain their opening. Electric explosion valves achieve rapid opening by igniting the explosive charge with a low-impedance heating wire (usually a few ohms), requiring only a pulse of a few milliseconds. Continuous energization can burn out the heating wire or even lead to accidental detonation.

[0003] Chinese patent application CN112576803A discloses an adaptive drive system for a power solenoid valve, which detects static resistance during startup and adjusts the drive voltage accordingly. This solution achieves adaptive drive for the solenoid valve, but it has the following shortcomings: it only targets solenoid valves and cannot identify or distinguish low-impedance loads such as explosion-proof valves, posing a risk of accidental detonation if incorrectly connected; it uses a single control signal, which can easily lead to accidental switching of the power switch due to long lines or strong interference environments; impedance detection is only performed once during startup, lacking online monitoring capabilities during non-drive periods, making it impossible to detect potential problems such as loose cables in a timely manner; and the wiring mode is fixed, not supporting common positive / common negative switching.

[0004] Chinese patent CN204088194U discloses a safety output control circuit that employs a dual-pulse interlock scheme. Two independent microprocessors generate synchronous pulse signals, triggering the relay only when both signals are synchronized, thus preventing false triggering due to single-point failures. However, this scheme only addresses relay output control and does not cover valve body load impedance detection or adaptive load type identification.

[0005] In summary, existing valve body drive circuits suffer from problems such as poor load type adaptability, susceptibility to interference and false triggering in single-channel control, lack of online detection capability during non-drive periods, and inflexible wiring modes. Summary of the Invention

[0006] The purpose of this invention is to provide an intelligent drive control circuit and control method that adapts to valve body impedance, so as to solve the problems mentioned in the background art.

[0007] To achieve the above objectives, this invention provides an intelligent drive control circuit and control method for adaptive valve body impedance, employing the following technical solution:

[0008] An intelligent drive control circuit for adaptive valve body impedance includes an encoded signal generation unit for converting a single-channel switch control signal into a dual-channel differential encoded signal, wherein the dual-channel differential encoded signal includes a drive enable state and multiple non-drive safety states; a logic decoding and interlocking unit for decoding the dual-channel differential encoded signal, outputting a drive trigger signal only when the decoding result is the drive enable state, and blocking the drive output in the non-drive safety state; an impedance detection unit connected between the drive output port and the valve body load, for applying a detection electrical signal lower than the minimum action threshold of the valve body to the valve body load during non-drive periods, and obtaining the impedance detection value of the valve body load based on the feedback signal; an interlocking control mechanism is provided between the impedance detection unit and the power output stage, the interlocking control mechanism being configured to ensure that the detection circuit and the drive circuit do not conduct simultaneously based on the output state of the logic decoding and interlocking unit and a preset timing logic; a drive parameter adaptive adjustment unit for automatically matching and outputting corresponding drive parameters based on the comparison result of the impedance detection value and the preset threshold; and a power output stage for outputting drive power to the valve body load based on the drive trigger signal and the drive parameters.

[0009] By adopting the above technical solution, this invention injects a micro-current into the valve body load to detect impedance during non-driving periods. Based on the impedance value, it automatically distinguishes between solenoid valves and electric explosion valves and matches the corresponding driving voltage, current, and pulse width parameters, thus avoiding false driving caused by incorrect load type identification. At the same time, it uses dual-channel differential coded signals to replace single-channel switching signals. The two signal lines must simultaneously meet a specific level relationship to allow power output. If a single signal line is interfered with and flips, or if both signal lines are simultaneously subjected to common-mode interference, it will not cause false triggering, significantly improving the safety of drive control.

[0010] Preferably, the dual-path differential coded signal includes a first logic signal line and a second logic signal line; the drive enable state is a state where the first logic signal line is at a high level and the second logic signal line is at a low level; the non-drive safe state includes: a state where the first logic signal line is at a low level and the second logic signal line is at a high level, a state where both lines are at a high level, and a state where both lines are at a low level.

[0011] By adopting the above technical solution, the drive enable state adopts a clear differential state with the first line high and the second line low. It has at least two signal line level differences with the three non-drive safety states, which increases the transition conditions from the non-drive state to the drive enable state and reduces the probability of false triggering.

[0012] Preferably, during the initial power-on period or non-driving period, the encoding signal generation unit forcibly sets the dual-channel differential encoding signal to a state completely opposite to the drive enable state, and the logic decoding and interlocking unit accordingly causes the power output stage to enter a strong shutdown state. In the strong shutdown state, the level flip of a single signal line does not change the state. The power output stage only starts outputting when both signal lines flip to the drive enable state simultaneously. The transition from the strong shutdown state to the drive enable state requires the dual signal lines to complete the level transition in opposite directions simultaneously within the same control cycle. The control cycle is the program loop cycle of the encoding signal generation unit.

[0013] By adopting the above technical solution, the power output stage is in a strongly shut-off state during the initial power-on and normal non-driving periods. Even if a single output line of the encoding signal generation unit flips due to interference, as long as the other line maintains the correct level, the logic decoding and interlocking unit will still maintain the blocked output, thus avoiding malfunctions caused by single-line interference.

[0014] Preferably, when the dual-channel differential encoded signals simultaneously transition to both lines being high or both lines being low, the logic decoding and interlocking unit determines it as common-mode interference, maintains the non-drive safe state, and blocks the drive output.

[0015] By adopting the above technical solution, when two signal lines are simultaneously subjected to interference of the same polarity due to electromagnetic coupling, the levels of the two lines will simultaneously become high or simultaneously become low. The logic decoding and interlocking unit recognizes this as an interference state rather than a valid drive command, and continues to block the output, thereby further improving the anti-interference capability of the system.

[0016] Preferably, the detection electrical signal is a detection current lower than the minimum operating current of the valve body load, with an amplitude of 5mA to 20mA. A voltage clamping circuit is provided in the detection circuit to clamp the detection voltage within a safe voltage range of no more than 3.3V, which is lower than the minimum operating voltage of the valve body load. The impedance detection is periodically activated during the non-drive period of the power output stage or activated in response to a host computer command.

[0017] By adopting the above technical solution, the detection current amplitude is much lower than the minimum operating current of the valve body load (usually above 50mA for solenoid valves and above 100mA for electric explosion valves), and a voltage clamping circuit is provided in the detection circuit to limit the detection voltage within a safe range, ensuring that the detection process will not cause the valve body to malfunction.

[0018] Preferably, the adaptive adjustment unit for drive parameters is preset with a first threshold, a second threshold, a third threshold, a fourth threshold, and a fifth threshold, wherein the first threshold > the second threshold > the third threshold > the fourth threshold, and the fifth threshold > the first threshold; when the impedance detection value is ≥ the first threshold and < the fifth threshold, it is determined to be a solenoid valve type load, high-voltage drive parameters are matched, and current limiting is enabled; when the impedance detection value is ≥ the second threshold and < the first threshold, it is determined to be a low-power solenoid valve type load, medium-voltage drive parameters are matched, and current limiting is enabled; when the impedance detection value is ≥ the third threshold and < the second threshold, it is determined to be a low-power solenoid valve type load. For valve-type loads, narrow pulse drive parameters are matched, and an independent overcurrent protection threshold is enabled. When the impedance detection value is ≥ the fourth threshold and < the third threshold, it is determined to be an extremely low impedance load, the output is blocked, and a fault alarm is output. When the impedance detection value is < the fourth threshold, it is determined to be a short circuit fault, the output is blocked, and a short circuit alarm is output. When the impedance detection value is ≥ the fifth threshold, it is determined to be an open circuit fault, and an open circuit alarm is output. Further, the first threshold is 30Ω, the second threshold is 10Ω, the third threshold is 0.5Ω, the fourth threshold is 0.05Ω, and the fifth threshold is 1MΩ.

[0019] By adopting the above technical solution, the impedance detection value is divided into six continuous intervals, covering six states: solenoid valve, low-power solenoid valve, electric explosion valve, low impedance, short circuit, and open circuit. Each interval corresponds to a clear judgment result and driving strategy. Solenoid valve loads are driven by high voltage continuously with current limiting protection, while electric explosion valve loads are driven by low voltage or narrow pulse to prevent overdrive. Short circuit and open circuit faults directly block the output and trigger an alarm.

[0020] Preferably, the power output stage includes a high-side drive switch and a low-side drive switch. By configuring the on / off state combinations of the high-side drive switch and the low-side drive switch, it adapts to the common positive or common negative wiring mode of the valve body load. The on / off state combinations include three combinations: the high-side drive switch is on and the low-side drive switch is controlled; the low-side drive switch is on and the high-side drive switch is controlled; and both the high-side drive switch and the low-side drive switch are off. The on / off state of the high-side drive switch and the low-side drive switch is configured by at least one of hardware jumpers and DIP switches.

[0021] By adopting the above technical solution, the power output stage can be configured to common positive or common negative mode via hardware jumpers or DIP switches without replacing the driver module, thus adapting to the wiring requirements of different systems.

[0022] This invention also provides an intelligent drive control method that adapts to valve body impedance, applied to the intelligent drive control circuit described in any of the above technical solutions, comprising the following steps:

[0023] S1: After power-on, the dual differential coded signals are locked in the non-drive safe state, causing the power output stage to enter a strong shutdown state;

[0024] S2: Apply a detection electrical signal below the minimum action threshold to the valve body load during non-drive periods to obtain the impedance detection value;

[0025] S3: Match the corresponding driving parameters according to the impedance detection value;

[0026] When the impedance detection value is greater than or equal to the first threshold and less than the fifth threshold, it is determined to be a solenoid valve type load, and high voltage drive parameters are matched and current limiting is enabled.

[0027] When the impedance detection value is greater than or equal to the second threshold and less than the first threshold, it is determined to be a low-power solenoid valve type load, and the medium voltage drive parameters are matched and current limiting is enabled.

[0028] When the impedance detection value is greater than or equal to the third threshold and less than the second threshold, it is determined to be an electric explosion valve type load, and the narrow pulse drive parameters are matched and an independent overcurrent protection threshold is enabled.

[0029] When the impedance detection value is greater than or equal to the fourth threshold and less than the third threshold, it is determined to be an extremely low impedance load, the output is blocked and an alarm is triggered;

[0030] When the impedance detection value is less than the fourth threshold, it is determined to be a short circuit fault, the output is blocked and an alarm is triggered;

[0031] When the impedance detection value is greater than or equal to the fifth threshold, it is determined to be an open circuit fault and an alarm is triggered.

[0032] S4: Receive external switch commands, convert them into dual-channel differential coded signals, and decode them;

[0033] S5: When the decoding result is in the drive enabled state, output drive power according to the matched drive parameters; when the decoding result is in the non-drive safe state, keep the output blocked.

[0034] By adopting the above technical solutions, the method of the present invention achieves full-process safety control of valve body driving through power-on forced interlocking, online detection during non-driving periods, adaptive matching of load types, and differential decoding drive.

[0035] Preferably, in step S2, the impedance detection is performed once during power-on initialization, or repeatedly performed at a preset cycle during non-driving periods.

[0036] When the impedance detection value changes from the current impedance range to another impedance range during periodic detection, return to step S3 to rematch the driving parameters. The first threshold, the second threshold, and the third threshold are all equipped with hysteresis, which is 10% of the absolute value of the threshold.

[0037] Specifically: when crossing the first threshold (30Ω) from high impedance to low impedance, the trigger threshold is 27Ω; when crossing the first threshold from low impedance to high impedance, the trigger threshold is 33Ω; the second threshold (10Ω) corresponds to 9Ω / 11Ω; and the third threshold (0.5Ω) corresponds to 0.45Ω / 0.55Ω. Rematching is triggered only after the impedance detection value crosses the hysteresis boundary to avoid frequent parameter switching caused by boundary jitter.

[0038] By adopting the above technical solution, an impedance detection is performed once upon power-up to detect wiring errors in a timely manner; periodic detection can monitor changes in load status during operation (such as increased contact resistance due to loose cables), and once an impedance change across the threshold is detected, the drive parameters are automatically rematched, improving the system's adaptability.

[0039] This invention achieves full-process safe control of valve body driving through dual-channel differential coding interlock, online impedance detection during non-driving periods, and adaptive drive parameter matching based on load type. It effectively avoids the risk of mis-driving caused by incorrect load type identification, signal interference, and load failure, and has the advantages of high safety, strong adaptability, and flexible wiring. Attached Figure Description

[0040] Figure 1 This is a block diagram of the intelligent drive control circuit for adaptive valve body impedance in an embodiment of the present invention.

[0041] Figure 2 This is a circuit diagram of the encoding signal generation unit and the logic decoding and interlocking unit in an embodiment of the present invention.

[0042] Figure 3 This is a circuit diagram of the impedance detection unit in an embodiment of the present invention.

[0043] Figure 4 This is a circuit schematic diagram of the power output stage in an embodiment of the present invention. Detailed Implementation

[0044] The following is in conjunction with the appendix Figure 1 To be continued Figure 4 The present invention will be described in further detail below.

[0045] Example 1

[0046] like Figure 1 As shown, this embodiment provides an intelligent drive control circuit that adapts to valve body impedance, applied to the drive control of valve body load in a fire control system. Commonly used valves in fire protection systems include solenoid valves and electric explosion valves.

[0047] The "non-driving period" as described in this invention refers to the time interval during which both the high-side and low-side drive switches in the power output stage are in the off state, and there is no drive voltage output between the drive output port and the valve body load. This excludes the switching cycle turn-off gap in PWM modulation. Impedance detection is only initiated during the complete non-driving period; detection is not performed during the turn-off gap of PWM modulation.

[0048] like Figure 1 As shown, the encoded signal generation unit uses an MCU microcontroller (model: STM32F103C8T6). The first GPIO output and the second GPIO output of the MCU microcontroller output the first logic signal line S1 and the second logic signal line S2, respectively. When an external switch command requests to drive the valve body, the MCU microcontroller sets the first GPIO output to a high level (3.3V) and the second GPIO output to a low level (0V), forming a drive enable state with the first line high and the second line low. When an external switch command requests to disable the drive, the MCU microcontroller sets both the first and second GPIO outputs to a low level (0V), forming a non-drive safe state with both lines low. During power-on initialization, the MCU microcontroller sets the first GPIO output to a low level and the second GPIO output to a high level, forming a non-drive safe state with the first line low and the second line high, which is the complete opposite of the drive enable state.

[0049] The first logic signal line S1 is grounded through a 10kΩ pull-down resistor, and the second logic signal line S2 is connected to a 3.3V power supply through a 10kΩ pull-up resistor. When the MCU is not powered on or the program crashes, causing the GPIO pins to be in a high-impedance state, S1 is fixed at a low level and S2 is fixed at a high level. The logic decoding and interlocking unit is forced into a strong shutdown state, and the power output stage remains blocked, ensuring that the drive output will not be accidentally turned on when the MCU fails.

[0050] like Figure 2 As shown, the logic decoding and interlocking unit includes a first RS flip-flop, a second RS flip-flop, a first NOT gate, a second NOT gate, and an interlocking AND gate. Both the first and second RS flip-flops are active-high RS flip-flops (composed of NOR gates), and their logic characteristics are as follows: when the set input S is high, the output Q is set to 1; when the reset input R is high, the output Q is reset to 0; when both the set and reset inputs are low, the output Q retains its previous state; when both the set and reset inputs are high, it is an illegal state, and the output Q is forced to 0.

[0051] The set input S of the first RS flip-flop is connected to the first logic signal line S1, and the reset input R is connected to the second logic signal line S2. The set input S of the second RS flip-flop is connected to the second logic signal line S2 after being inverted by the first NOT gate, meaning the set input S of the second RS flip-flop is active when the second logic signal line S2 is low. The reset input R of the second RS flip-flop is connected to the first logic signal line S1 after being inverted by the second NOT gate, meaning the reset input R of the second RS flip-flop is active when the first logic signal line S1 is low. The outputs Q1 of the first RS flip-flop and Q2 of the second RS flip-flop are respectively connected to the two inputs of an interlocked AND gate.

[0052] In this embodiment, both the first and second RS flip-flops are R-priority type RS flip-flops (composed of NOR gates; when S and R are both high, the output is forcibly reset to 0), ensuring that the output is always low in illegal states and does not oscillate. Simultaneously, the output of the interlocked AND gate is connected to a Schmitt trigger shaping circuit to ensure a steep edge on the drive trigger signal; or an RC filter is set at the input of the preceding logic gate, while no series RC filter is used in the power output stage gate drive circuit.

[0053] The logical relationships under each working state are as follows:

[0054] (1) Drive enable state (S1 is high level, S2 is low level): The first RS flip-flop is set, Q1=1; the second logic signal line S2 is high level after being inverted by the first NOT gate, the first logic signal line S1 is low level after being inverted by the second NOT gate, the second RS flip-flop is set, Q2=1; the interlock AND gate outputs high level (drive trigger signal is valid), and the power output stage starts output.

[0055] (2) Strong shutdown state / power-on initial state (S1 is low level, S2 is high level): The first RS flip-flop is reset, Q1=0; the second logic signal line S2 is low level after being inverted by the first NOT gate, the first logic signal line S1 is high level after being inverted by the second NOT gate, the second RS flip-flop is reset, Q2=0; the interlock AND gate outputs a low level (the drive trigger signal is invalid), and the power output stage enters the strong shutdown state.

[0056] (3) In the strong shutdown state, the single S1 flips (S1 changes from low to high, S2 remains high): the set and reset terminals of the first RS flip-flop are both high, entering the illegal state, and Q1=0; the set and reset terminals of the second RS flip-flop are both low, entering the holding state, and Q2 remains unchanged at 0; the interlock AND gate still outputs a low level, the power output stage remains blocked, and the flipping of a single signal line will not cause false triggering.

[0057] (4) In the strong shutdown state, the single S2 flips (S1 remains low and S2 changes from high to low): the set and reset terminals of the first RS flip-flop are both low, entering the holding state, and Q1 remains unchanged at 0; the set and reset terminals of the second RS flip-flop are both high, entering the illegal state, and Q2=0; the interlock AND gate still outputs a low level, the power output stage remains blocked, and the flipping of a single signal line will not cause false triggering.

[0058] (5) Common-mode interference: both lines jump high at the same time (S1 and S2 are high at the same time): the set and reset terminals of the first RS flip-flop are both high, entering an illegal state, and Q1=0; the set and reset terminals of the second RS flip-flop are both low, entering a hold state, and Q2 remains unchanged from the previous state; the interlocked AND gate outputs a low level, the power output stage remains blocked, and common-mode interference will not cause false triggering.

[0059] (6) Common-mode interference: both lines jump low at the same time (S1 and S2 are low at the same time): the set and reset terminals of the first RS flip-flop are both low, entering the holding state, and Q1 remains unchanged from the previous state; the set and reset terminals of the second RS flip-flop are both high, entering the illegal state, and Q2=0; the interlocked AND gate outputs a low level, the power output stage remains blocked, and common-mode interference will not cause false triggering.

[0060] The common-mode interference determination described above is non-latching type. That is, when the dual signal lines exit the common-mode state (both lines are high or both are low) and return to a valid differential level combination, the logic decoding and interlocking unit automatically restores the corresponding output state without requiring a reset operation. However, it should be noted that when transitioning from the strong off state (S1=low, S2=high) to the drive enable state (S1=high, S2=low), the time difference between the transitions of S1 and S2 must not exceed half of the MCU program loop cycle (1ms in this embodiment), i.e., 500μs. If this value is exceeded, the system will trigger common-mode interference determination in the intermediate state (S1=high, S2=high) and maintain the blockage. At this time, both signal lines need to be pulled back to the non-drive safe state simultaneously before initiating the transition again.

[0061] The aforementioned strong shutdown state and common-mode interference detection are two parallel safety mechanisms, each addressing different sources of interference: the strong shutdown state handles individual signal line switching due to inductive coupling or cable damage, ensuring that a single line switching does not unlock the drive output; the common-mode interference detection handles situations where two signal lines simultaneously undergo unidirectional switching due to strong electromagnetic field coupling, ensuring that the system remains blocked even when both lines are simultaneously disturbed. Both mechanisms work together to ensure the output safety of the system under various interference modes. Furthermore, "simultaneous switching" refers to both signal lines undergoing unidirectional level switching within the same control cycle (the control cycle is the program loop cycle of the MCU microcontroller, 1ms in this embodiment).

[0062] like Figure 3 As shown, the impedance detection unit includes a controllable constant current source, a sampling resistor, an analog switch, and an ADC (analog-to-digital converter). The controllable constant current source outputs a constant detection current with an amplitude of 10mA, which is injected into the valve body load through the analog switch. The sampling resistor (100Ω) is connected in series in the detection circuit. The ADC detects the voltage drop across the valve body load and calculates the impedance detection value of the valve body load according to Ohm's law. The analog switch is controlled by an MCU (microcontroller unit) and is turned on only when the power output stage is not in a driving period.

[0063] Before the MCU microcontroller controls the analog switch to turn on, it first confirms that the power output stage is in a strongly off state by checking the output state of the logic decoding and interlocking unit, and waits for 2ms for the output capacitor to discharge before starting impedance detection. Before starting the drive output, it first turns off the analog switch and waits for 1ms before outputting the drive enable state to the logic decoding and interlocking unit. The detection circuit and the drive circuit do not conduct simultaneously.

[0064] In this embodiment, the detection current of 10mA is much lower than the minimum operating current of the solenoid valve, which is 50mA. The detection voltage is calculated as 10mA × load impedance. For a solenoid valve with a maximum impedance of 100Ω, the detection voltage is only 1V, which is far below the valve body's operating threshold, ensuring that the detection process will not cause the valve body to malfunction. The detection current ranges from 5mA to 20mA, with the upper limit of 20mA determined by the lower limit of the minimum operating current of various valve body loads (the minimum operating current of common valve body loads is generally higher than 20mA), and the lower limit of 5mA determined by the ADC analog-to-digital converter. The detection resolution and maximum detection impedance of the converter are jointly determined (for a solenoid valve with a maximum impedance of 100Ω, the voltage drop across the valve body load caused by a 5mA detection current is 0.5V, which is higher than the minimum resolvable voltage of the ADC analog-to-digital converter in this embodiment, which is 10mV); the third threshold of 0.5Ω is determined by the sum of the on-state resistances of the high-side drive switch (IRF9540, on-state resistance approximately 0.2Ω) and the low-side drive switch (IRF540, on-state resistance approximately 0.04Ω), combined with the comprehensive margin of the connecting cables and contact resistance. The above thresholds can be adjusted according to the actual circuit parameters in different application scenarios.

[0065] It should be noted that the amplitude of the detection current can be selected within the range of 5mA to 20mA, depending on the type of valve body load. For low-impedance electric explosion valves (impedance approximately 3Ω), a detection current of 5mA can be used, corresponding to a detection voltage of only 15mV, far below the detonation threshold. For high-impedance solenoid valves (impedance approximately 50Ω to 100Ω), a detection current of 15mA can be used, corresponding to a detection voltage of 0.75V to 1.5V, which, while ensuring ADC sampling accuracy, is still far below the valve body operating voltage. All of the above detection current amplitudes are lower than the minimum operating current of the valve body load and will not cause malfunction of the valve body.

[0066] like Figure 4 As shown, the power output stage includes a high-side drive switch and a low-side drive switch. The high-side drive switch uses a P-channel MOSFET (model: IRF9540), and the low-side drive switch uses an N-channel MOSFET (model: IRF540). The gate of the high-side drive switch is connected to the drive power supply (24V) via a pull-up resistor, and the gate of the low-side drive switch is grounded via a pull-down resistor. A clamping circuit consisting of a 15V Zener diode and a series current-limiting resistor is provided between the gate and source of the high-side drive switch to clamp the gate-source voltage at -15V, preventing the gate-source voltage from exceeding the MOSFET's maximum rating (±20V). The drive trigger signal is connected to the MOSFET gate via a gate driver (input compatible with 3.3V logic level, output providing 12V gate drive voltage) to ensure the power MOSFET is fully turned on. Hardware jumper JP1 is used to configure the on / off combination of the high-side drive switch and the low-side drive switch: When hardware jumper JP1 is shorted to pins 1-2, the high-side drive switch is normally on, and the low-side drive switch is controlled by the drive trigger signal, and the power output stage operates in common negative mode (low-side switch control); when hardware jumper JP1 is shorted to pins 2-3, the low-side drive switch is normally on, and the high-side drive switch is controlled by the drive trigger signal, and the power output stage operates in common positive mode (high-side switch control); when hardware jumper JP1 is in the middle position with no pins shorted or in a poor contact state, the gate of the high-side drive switch is connected to the drive power supply (24V) through a pull-up resistor, and the gate of the low-side drive switch is grounded through a pull-down resistor. Both drive switches are in the off state, and the power output stage defaults to a double off state where both the high-side drive switch and the low-side drive switch are blocked, ensuring that no drive power is output when the wiring configuration is abnormal. The double off state is a hardware-level forced shutdown, which has a higher priority than the strong shutdown state of the logic decoding and interlocking unit output.

[0067] A freewheeling diode D1 (model: 1N5822, reverse withstand voltage 40V, forward current 3A) is connected in parallel across the valve body load. The cathode is connected to the output terminal of the high-side drive switch, and the anode is connected to the output terminal of the low-side drive switch. This is used to discharge the reverse induced electromotive force generated by the inductive load when the low-side drive switch is turned off, thus protecting the MOSFET from breakdown.

[0068] The adaptive adjustment unit for drive parameters is integrated within the MCU microcontroller, using a software lookup table to match impedance to drive parameters. The MCU microcontroller compares the impedance detected by the ADC analog-to-digital converter with preset thresholds (first threshold 30Ω, second threshold 10Ω, third threshold 0.5Ω, fourth threshold 0.05Ω, fifth threshold 1MΩ) to determine the load type and match the corresponding drive parameters.

[0069] When the impedance detection value is greater than or equal to the first threshold (30Ω) and less than the fifth threshold, it is determined to be a solenoid valve type load. The power output stage outputs 24V voltage and enables 1.5A current limiting, and continues to output until the external switch command is released.

[0070] When the impedance detection value is greater than or equal to the second threshold (10Ω) and less than the first threshold (30Ω), it is determined to be a low-power solenoid valve type load, and the power output stage outputs 24V voltage and enables 0.3A current limiting;

[0071] When the impedance detection value is ≥ the third threshold (0.5Ω) and < the second threshold (10Ω), it is determined to be an electric explosion valve type load. The power output stage outputs a 5V voltage and a narrow pulse with a pulse width of 3ms (the current is determined by the load impedance, typically 1A~5A). The output is immediately blocked after the pulse ends. At the same time, the drive circuit has an independent hardware overcurrent comparator, and the current limiting protection threshold is set to 5A by default. When the circuit current exceeds this threshold, the hardware forcibly shuts off the output. These drive parameters correspond to common electric explosion valve models with bridge wire resistance of 1Ω~5Ω. If the actual valve body specifications exceed this range, the user can configure the drive voltage (3V~12V), pulse width (1ms~10ms), and current limiting value (500mA~5A) through the serial port of the MCU microcontroller via the host computer. The adaptive adjustment unit of the drive parameters takes priority over the user-configured value. To reduce the risk of accidental detonation, the MCU microcontroller needs to receive two independent external switch commands (with an interval of 100ms to 500ms between the two commands) before executing the electric explosion valve drive. The drive pulse will only be output after the two confirmations are consistent; no output will be made if a single command or two commands are inconsistent.

[0072] When the impedance detection value is ≥ the fourth threshold (0.05Ω) and < the third threshold (0.5Ω), it is determined to be an extremely low impedance load, the output is blocked and a fault alarm is output;

[0073] When the impedance detection value is less than the fourth threshold (0.05Ω), it is determined to be a short circuit fault, the output is blocked, and a short circuit alarm is sent to the host computer through the serial port of the MCU microcontroller;

[0074] When the impedance detection value is greater than or equal to the fifth threshold (1MΩ), it is determined to be an open circuit fault, the output is blocked, and an open circuit alarm is sent to the host computer via the serial port.

[0075] The working process of this embodiment is as follows:

[0076] (1) After the MCU microcontroller is powered on, it sets the first GPIO output to low level and the second GPIO output to high level. The logic decoding and interlocking unit outputs a low level, and the power output stage enters a strong shutdown state. Then the MCU microcontroller controls the analog switch to turn on, injecting a 10mA detection current into the valve body load. The ADC analog-to-digital converter samples and calculates the impedance detection value.

[0077] (2) If the power-on detection determines that the circuit is open (≥1MΩ), the system will not immediately shut down, but will retry the detection once per second for 30 seconds. If a normal load is detected within 30 seconds, the system will enter standby mode. After the timeout, an open circuit fault will be reported and the system will shut down. If the power-on detection determines that the circuit is short (<0.05Ω) or a very low impedance load (0.05Ω~0.5Ω), the system will shut down directly and trigger an alarm, without retrying. If the load is determined to be normal, the system will enter standby mode and wait for an external switch command.

[0078] (3) When an external switch command requires the valve body to be driven, the MCU microcontroller sets the first GPIO output to high level and the second GPIO output to low level. The logic decoding and interlocking unit outputs high level, and the power output stage outputs driving power to the valve body load according to the matched driving parameters.

[0079] (4) During the non-drive period of the power output stage, the MCU microcontroller controls the analog switch to turn on once every 1 second to perform impedance detection. If the impedance detection value is detected to change from the current impedance range to another impedance range (i.e., it crosses any one of the first threshold of 30Ω, the second threshold of 10Ω, or the third threshold of 0.5Ω, such as changing from 3Ω to 50Ω, indicating that the valve body load has been changed from an electric explosion valve to a solenoid valve), the MCU microcontroller automatically rematches the drive parameters.

[0080] Example 2

[0081] The difference between this embodiment and Embodiment 1 is that the high and low side switch configurations of the power output stage are different.

[0082] In this embodiment, a DIP switch is used instead of the hardware jumper JP1 to configure the on / off combination of the high-side drive switch and the low-side drive switch. The DIP switch has two positions. The first position controls whether the gate of the high-side drive switch is connected to the drive trigger signal, and the second position controls whether the gate of the low-side drive switch is connected to the drive trigger signal. When the first position is ON and the second position is OFF, the high-side drive switch is controlled and the low-side drive switch is always on, operating in common positive mode; when the first position is OFF and the second position is ON, the low-side drive switch is controlled and the high-side drive switch is always on, operating in common negative mode; when both positions are OFF, both the high-side drive switch and the low-side drive switch are blocked, and the power output stage enters a dual shutdown state, which can be used as an emergency stop configuration.

[0083] The remaining structure and parameters are the same as in Example 1, and will not be repeated here.

[0084] The above are all preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Therefore, all equivalent changes made in accordance with the structure, shape and principle of the present invention should be covered within the scope of protection of the present invention.

Claims

1. An intelligent drive control circuit that adapts to valve body impedance, characterized in that, It includes an encoding signal generation unit for converting a single-channel switch control signal into a dual-channel differential encoded signal, wherein the dual-channel differential encoded signal includes a drive enable state and multiple non-drive safety states; The logic decoding and interlocking unit is used to decode the dual-channel differential coded signal, and outputs the drive trigger signal only when the decoding result is the drive enable state, and blocks the drive output in the non-drive safe state; An impedance detection unit is connected between the drive output port and the valve body load. It is used to apply a detection electrical signal lower than the minimum action threshold of the valve body to the valve body load during non-drive periods, and obtain the impedance detection value of the valve body load according to the feedback signal. An interlock control mechanism is provided between the impedance detection unit and the power output stage. The interlock control mechanism is configured to ensure that the detection circuit and the drive circuit do not conduct at the same time according to the logic decoding, the output state of the interlock unit and the preset timing logic. The adaptive adjustment unit for driving parameters is used to automatically match and output the corresponding driving parameters according to the impedance detection value. The power output stage is used to output drive power to the valve body load according to the drive trigger signal and the drive parameters.

2. The intelligent drive control circuit for adaptive valve body impedance according to claim 1, characterized in that: The dual-path differential coded signal includes a first logic signal line and a second logic signal line; The drive enable state is a state where the first logic signal line is at a high level and the second logic signal line is at a low level; The non-driven safe state includes: a state where the first logic signal line is low and the second logic signal line is high, a state where both lines are high, and a state where both lines are low.

3. The intelligent drive control circuit for adaptive valve body impedance according to claim 2, characterized in that: During the initial power-on period or non-driving period, the encoding signal generation unit forces the dual-channel differential encoding signal to be set to a state completely opposite to the driving enable state, and the logic decoding and interlocking unit thereby causes the power output stage to enter a strong shutdown state. In the strong off state, the level flip of a single signal line does not change the state. The power output stage only starts to output when both signal lines flip to the drive enable state at the same time. The transition from the strong off state to the drive enable state requires the two signal lines to complete the level transition in opposite directions at the same control cycle. The control cycle is the program loop cycle of the encoded signal generation unit.

4. The intelligent drive control circuit for adaptive valve body impedance according to claim 1, characterized in that: When the dual-channel differential encoded signal simultaneously transitions to either a state where both lines are at a high level or a state where both lines are at a low level, the logic decoding and interlocking unit determines it as common-mode interference, maintains the non-drive safe state, and blocks the drive output.

5. The intelligent drive control circuit for adaptive valve body impedance according to claim 1, characterized in that: The detection electrical signal is a detection current lower than the minimum operating current of the valve body load, with an amplitude of 5mA to 20mA; The upper limit of the detection current amplitude of 20mA is lower than the lower limit of the minimum operating current of various valve body loads. The lower limit of the detection current amplitude of 5mA is determined by the detection resolution and maximum detection impedance of the ADC analog-to-digital converter. A voltage clamping circuit is provided in the detection circuit to clamp the detection voltage within a safe voltage range of no more than 3.3V, which is lower than the minimum operating voltage of the valve body load. The impedance detection is periodically activated during the non-driving period of the power output stage or in response to a host computer command.

6. The intelligent drive control circuit for adaptive valve body impedance according to claim 5, characterized in that: The adaptive adjustment unit for driving parameters is preset with a first threshold, a second threshold, a third threshold, a fourth threshold, and a fifth threshold, wherein the first threshold > the second threshold > the third threshold > the fourth threshold, and the fifth threshold > the first threshold; When the impedance detection value is greater than or equal to the first threshold and less than the fifth threshold, it is determined to be an electromagnetic valve type load, and high voltage drive parameters are matched and current limiting is enabled. When the impedance detection value is greater than or equal to the second threshold and less than the first threshold, it is determined to be a low-power solenoid valve type load, and the medium voltage drive parameters are matched and the current limiting is enabled. When the impedance detection value is greater than or equal to the third threshold and less than the second threshold, it is determined to be an electric explosion valve type load, the narrow pulse drive parameters are matched, and an independent overcurrent protection threshold is enabled. When the impedance detection value is greater than or equal to the fourth threshold and less than the third threshold, it is determined to be an extremely low impedance load, the output is blocked and a fault alarm is output. When the impedance detection value is less than the fourth threshold, it is determined to be a short circuit fault, the output is blocked and a short circuit alarm is output. When the impedance detection value is greater than or equal to the fifth threshold, it is determined to be an open circuit fault, and an open circuit alarm is output. Furthermore, the first threshold is 30Ω, the second threshold is 10Ω, the third threshold is 0.5Ω, the fourth threshold is 0.05Ω, and the fifth threshold is 1MΩ.

7. The intelligent drive control circuit for adaptive valve body impedance according to claim 1, characterized in that: The power output stage includes a high-side drive switch and a low-side drive switch. By configuring the on / off state combination of the high-side drive switch and the low-side drive switch, it can adapt to the common positive or common negative wiring mode of the valve body load. The on / off states of the high-side drive switch and the low-side drive switch are configured by at least one of hardware jumpers and DIP switches.

8. An intelligent drive control method for adaptive valve body impedance, applied to the intelligent drive control circuit as described in any one of claims 1 to 7, characterized in that, Includes the following steps: S1: After power-on, the dual differential coded signals are locked in the non-drive safe state, causing the power output stage to enter a strong shutdown state; S2: Apply a detection electrical signal below the minimum action threshold to the valve body load during non-drive periods to obtain the impedance detection value; S3: Match the corresponding driving parameters according to the impedance detection value; When the impedance detection value is greater than or equal to the first threshold and less than the fifth threshold, it is determined to be a solenoid valve type load, and high voltage drive parameters are matched and current limiting is enabled. When the impedance detection value is greater than or equal to the second threshold and less than the first threshold, it is determined to be a low-power solenoid valve type load, and the medium voltage drive parameters are matched and current limiting is enabled. When the impedance detection value is greater than or equal to the third threshold and less than the second threshold, it is determined to be an electric explosion valve type load. The narrow pulse drive parameters are matched and an independent overcurrent protection threshold is enabled. When the impedance detection value is greater than or equal to the fourth threshold and less than the third threshold, it is determined to be an extremely low impedance load, the output is blocked and an alarm is triggered; When the impedance detection value is less than the fourth threshold, it is determined to be a short circuit fault, the output is blocked and an alarm is triggered; When the impedance detection value is greater than or equal to the fifth threshold, it is determined to be an open circuit fault and an alarm is triggered; S4: Receive external switch commands, convert them into dual-channel differential coded signals, and decode them; S5: When the decoding result is in the drive enabled state, output drive power according to the matched drive parameters; when the decoding result is in the non-drive safe state, keep the output blocked.

9. The intelligent drive control method for adaptive valve body impedance according to claim 8, characterized in that: In step S2, the impedance detection is performed once during power-on initialization, or repeatedly during non-driving periods according to a preset cycle. When the impedance detection value changes from the current impedance range to another impedance range during periodic detection, return to step S3 to rematch the driving parameters. The first threshold, the second threshold, and the third threshold are all equipped with hysteresis, which is 10% of the absolute value of the threshold. Specifically: when crossing the first threshold (30Ω) from high impedance to low impedance, the trigger threshold is 27Ω; when crossing the first threshold from low impedance to high impedance, the trigger threshold is 33Ω; the second threshold (10Ω) corresponds to 9Ω / 11Ω; and the third threshold (0.5Ω) corresponds to 0.45Ω / 0.55Ω. Rematching is triggered only after the impedance detection value crosses the hysteresis boundary to avoid frequent parameter switching caused by boundary jitter.

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