Semiconductor device, high-speed interface circuit, and memory system

Abstract

The application discloses a semiconductor device, a high-speed interface circuit and a storage system, and relates to the technical field of storage systems.The semiconductor device comprises a packaging substrate, a high-speed interface chip and a transmission path communication circuit.When the first chip side surface of the high-speed interface chip is arranged to face away from the device mounting area, the transmission path communication circuit is connected with the first signal input end and the first signal output end, and is connected with the second signal input end and the second signal output end; and / or when the first chip side surface of the high-speed interface chip is arranged to face the device mounting area, the transmission path communication circuit is connected with the first signal input end and the second signal output end, and is connected with the second signal input end and the first signal output end.The application can realize the compatibility of the same packaging substrate to two different high-speed interface chip mounting orientations by introducing a configurable transmission path communication circuit into the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of storage system technology, and in particular to a semiconductor device, a high-speed interface circuit, and a storage system. Background Technology

[0002] In high-speed interface chip design, there are various interconnection methods between the chip and the package, commonly including Wire Bonding and Flip-Chip. In Wire Bonding, the chip I / O pads are connected to the package pins via gold wires. Due to package layout limitations, the I / O signals on the left and right sides of the chip are usually connected in a predetermined order. However, in some packaging solutions, when using Flip-Chip or when the package structure is flipped, the positions of the left and right signals may be interchanged. For example, a signal originally located on the left may be connected to a pin on the right side of the package, and vice versa. This signal position reversal causes the signal order received by the internal circuitry of the chip to be inconsistent with the signal order defined in the design, thus affecting the normal operation of the chip. Therefore, it is necessary to modify the internal signal connection structure of the chip, readjust the chip layout, or modify the pin definitions on the package substrate, making the package substrate incompatible with the two chip packages. Summary of the Invention

[0003] The main objective of this invention is to propose a semiconductor device, a high-speed interface circuit, and a storage system, which aims to introduce a configurable transmission path connectivity circuit into the semiconductor device to achieve compatibility of two different high-speed interface chip mounting orientations on the same package substrate.

[0004] To achieve the above objectives, the present invention provides a semiconductor device, the semiconductor device comprising: The packaging substrate has a device mounting area and a first device connection fixing part and a second device connection fixing part disposed opposite to each other. A high-speed interface chip is disposed in the device mounting area; the first chip side surface of the high-speed interface chip has two signal lead-out areas disposed opposite to each other; the high-speed interface chip includes a first signal transmission pad and a second signal transmission pad, which are respectively disposed in the two signal lead-out areas of the high-speed interface chip; A transmission path connection circuit is provided, comprising a first signal input terminal, a second signal input terminal, a first signal output terminal, and a second signal output terminal; the first signal input terminal is connected to a first signal transmission pad, and the second signal input terminal is connected to a second signal transmission pad; the first signal output terminal is connected to a first device connection fixing part, and the second signal output terminal is connected to a second device connection fixing part; wherein... When the transmission path connection circuit is disposed on the first chip-side surface of the high-speed interface chip facing away from the device mounting area, the transmission path connection circuit connects the first signal input terminal and the first signal output terminal, and connects the second signal input terminal and the second signal output terminal; and / or, When the first chip-side surface of the high-speed interface chip is positioned facing the device mounting area, the transmission path connection circuit connects the first signal input terminal and the second signal output terminal, and also connects the second signal input terminal and the first signal output terminal.

[0005] In one embodiment, the transmission path connection circuit includes: A first signal input switch circuit has a first controlled terminal and a second controlled terminal respectively connected to a first connection control signal and a second connection control signal. The first signal input terminal of the first signal input switch circuit is connected to the first signal input terminal, and the second signal input terminal of the first signal input switch circuit is connected to the second signal input terminal. The signal output terminal of the first signal input switch circuit is connected to both the first signal output terminal and the second signal input terminal. The second signal input switch circuit has its first controlled terminal and second controlled terminal respectively connected to a second connection control signal and a first connection control signal. The first signal input terminal of the second signal input switch circuit is connected to the first signal input terminal, and the second signal input terminal of the second signal input switch circuit is connected to the second signal input terminal. The signal output terminal of the second signal input switch circuit is connected to both the first signal output terminal and the second signal output terminal. When the first chip-side surface of the high-speed interface chip is disposed away from the device mounting area, the first signal input switch circuit and the second signal input switch circuit realize the transmission of the first transmission signal through the first signal input terminal and the first signal output terminal, and realize the transmission of the second transmission signal through the second signal input terminal and the second signal output terminal; When the first chip-side surface of the high-speed interface chip is disposed facing the device mounting area, the first signal input switch circuit and the second signal input switch circuit realize the transmission of the first transmission signal through the first signal input terminal and the second signal output terminal, and realize the transmission of the second transmission signal through the second signal input terminal and the first signal output terminal.

[0006] In one embodiment, the first signal input switch circuit includes a first pull-up controlled switch, a second pull-up controlled switch, a first transmission gate, a second transmission gate, a first pull-down controlled switch, a second pull-down controlled switch, and a first inverter. The first pull-up controlled switch, the first transmission gate, and the first pull-down controlled switch are connected in series. The controlled terminals of the first pull-up controlled switch and the first pull-down controlled switch are respectively connected to a first connection control signal and a second connection control signal. The input terminal of the first transmission gate is connected to the first signal input terminal of the first signal input switch circuit, and the output terminal of the first transmission gate is connected to the signal output terminal of the first signal input switch circuit via the first inverter. The second pull-up controlled switch, the second transmission gate, and the second pull-down controlled switch are connected in series. The controlled terminals of the second pull-up controlled switch and the second pull-down controlled switch are respectively connected to the second connection control signal and the first connection control signal. The input terminal of the second transmission gate is connected to the second signal input terminal of the first signal input switch circuit. The output terminal of the second transmission gate is connected to the signal output terminal of the first signal input switch circuit via the first inverter.

[0007] In one embodiment, the second signal input switch circuit includes a third pull-up controlled switch, a fourth pull-up controlled switch, a third transmission gate, a fourth transmission gate, a third pull-down controlled switch, a fourth pull-down controlled switch, and a second inverter. The third pull-up controlled switch, the third transmission gate, and the third pull-down controlled switch are connected in series. The controlled terminals of the third pull-up controlled switch and the third pull-down controlled switch are respectively connected to a second connection control signal and a first connection control signal. The input terminal of the third transmission gate is connected to the first signal input terminal of the second signal input switch circuit, and the output terminal of the third transmission gate is connected to the signal output terminal of the second signal input switch circuit via the second inverter. The fourth pull-up controlled switch, the fourth transmission gate, and the fourth pull-down controlled switch are connected in series. The controlled terminals of the fourth pull-up controlled switch and the fourth pull-down controlled switch are respectively connected to the first connection control signal and the second connection control signal. The input terminal of the fourth transmission gate is connected to the second signal input terminal of the second signal input switch circuit. The output terminal of the fourth transmission gate is connected to the signal output terminal of the second signal input switch circuit via the second inverter.

[0008] In one embodiment, the semiconductor device further includes: An input buffer circuit is provided, wherein the two input terminals of the input buffer circuit are respectively connected to the first signal input terminal and the second signal input terminal, and the two output terminals of the input buffer circuit are respectively connected to the signal input terminals of the first signal input switch circuit and the second signal input switch circuit.

[0009] In one embodiment, the semiconductor device further includes: An output buffer circuit is provided, wherein the two input terminals of the output buffer circuit are respectively connected to the signal output terminals of the first signal input switch circuit and the second signal input switch circuit, and the two output terminals of the output buffer circuit are respectively connected to the first signal output terminal and the second signal output terminal.

[0010] In one embodiment, the semiconductor device further includes a controller disposed in the device mounting area. The control terminal of the controller is connected to the controlled terminal of the transmission path communication circuit. The controller is used to acquire the packaging mode information of the semiconductor device. When it is determined from the packaging mode information that the first chip-side surface of the high-speed interface chip is disposed away from the device mounting area, the controller controls the first signal input switch circuit to connect the first signal input terminal and the first signal output terminal; and controls the second signal input switch circuit to connect the second signal input terminal and the second signal output terminal. When the packaging mode information determines that the first chip-side surface of the high-speed interface chip is oriented toward the device mounting area, the first signal input switch circuit is controlled to connect the first signal input terminal and the second signal output terminal; and the second signal input switch circuit is controlled to connect the second signal input terminal and the first signal output terminal.

[0011] In one embodiment, when the first chip-side surface of the high-speed interface chip is disposed away from the device mounting area, the first signal transmission pad is bonded to the first signal input terminal via a lead, and the second signal transmission pad is bonded to the second signal input terminal via a lead. When the first chip-side surface of the high-speed interface chip is disposed facing the device mounting area, the first signal transmission pad is connected to the first signal input terminal through circuit wiring disposed on the packaging substrate, and the second signal transmission pad is connected to the second signal input terminal through circuit wiring disposed on the packaging substrate.

[0012] The present invention also proposes a high-speed interface circuit, comprising the semiconductor device described above.

[0013] The present invention also proposes a storage system comprising the semiconductor device described above; and / or, the high-speed interface circuit described above.

[0014] This invention provides a semiconductor device that achieves compatibility between two different high-speed interface chip mounting orientations on the same package substrate by introducing a configurable transmission path connection circuit. This eliminates the need for separate substrate design for each orientation, reducing R&D and manufacturing costs, decreasing the types of materials required, and enabling signal path adjustment without modifying the internal circuit structure of the chip. It also adapts to the left-right flipping of input signals caused by changes in package structure, avoiding the need for redesigning the chip layout or re-fabrication due to package structure changes. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the circuit structure of a semiconductor device according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the circuit structure of one embodiment of the semiconductor device of the present invention in through-mode; Figure 3 This is a schematic diagram of the circuit structure of an embodiment of the semiconductor device of the present invention in switching mode; Figure 4 for Figure 1 A schematic diagram of the circuit structure of an embodiment of the transmission path connection circuit; Figure 5 This is a schematic diagram of the structure of one embodiment of the semiconductor device of the present invention using wire bonding packaging; Figure 6 This is a schematic diagram of one embodiment of the semiconductor device of the present invention using flip-chip packaging.

[0017] Explanation of icon numbers: 10. High-speed interface chip; 11. First signal transmission pad; 12. Second signal transmission pad; 20. Packaging substrate; 21. First device connection fixing part; 22. Second device connection fixing part; 30. Transmission path connection circuit; 31. First signal input switch circuit; 311. First transmission gate; 32. Second signal input switch circuit; 312. Second transmission gate; 40. Controller; 50. Input buffer circuit; 60. Output buffer circuit; P1, First pull-up controlled switch; N1, First pull-down controlled switch; P2, Second pull-up controlled switch; N2, Second pull-down controlled switch; INV1, First inverter; P3, Third pull-up controlled switch; 321, Third transmission gate; 322, Fourth transmission gate; N3, Third pull-down controlled switch; P4, Fourth pull-up controlled switch; N4, Fourth pull-down controlled switch; INV2, Second inverter; IO11, first signal input terminal; IO12, second signal input terminal; IO21, first signal output terminal; IO22, second signal output terminal; S1, First connection control signal; S2, Second connection control signal; CK_T, First transmission signal; CK_C, Second transmission signal.

[0018] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0021] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0022] In this article, the term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0023] This invention proposes a semiconductor device for use in a storage system, which may include multiple storage devices and a data bus. The storage devices may be dynamic random access memory (DRAM), and a DRAM chip has multiple memory cells. A high-speed interface chip can be placed between the CPU and the DRAM to resolve the speed mismatch between the two, ensuring stable and high-speed data flow. For example, it can provide clock signals, chip select instructions, command address instructions, and data to the selected DRAM memory address within the storage system.

[0024] Semiconductor devices specifically refer to high-speed interface semiconductors, such as DRAM interface, Flash interface, or CXL interface chips, used to achieve high-bandwidth, low-latency data transmission between the memory controller and the memory medium. In the packaging process of high-speed interface semiconductor devices in existing memory systems, the mounting orientation of the high-speed interface chip directly determines the connection path between the chip pads and the package substrate circuitry. Currently, the industry mainly uses two packaging and mounting methods for high-speed interface chips: Wire Bonding and Flip-chip. In Wire Bonding packaging, the chip is mounted with its front side facing away from the package substrate. The chip's I / O pads are connected to pins on the package substrate via metal wires such as gold wires, achieving electrical connection between the substrate and external circuitry, or connected to the package substrate and then electrically connected to external circuitry via a solder ball array on the other side of the package substrate. Furthermore, the I / O signals on the left and right sides of the chip are typically connected in a predetermined order. In flip-chip packaging, the chip is mounted with its front side facing the packaging substrate. The chip's pads are fixed to the substrate using solder or similar materials. These pads are connected to pins on the packaging substrate via wiring on the substrate, achieving electrical connection between the substrate and external circuitry. Alternatively, the chip can be connected to the packaging substrate and then electrically connected to external circuitry via a solder ball array on the other side of the packaging substrate. Compared to wire bonding, when the chip's front side is flipped relative to the substrate, the left and right signal positions may be interchanged. For example, a signal originally on the left side might need to be connected to a right-side package pin, and vice versa. This signal position reversal can cause the signal order received by the chip's internal circuitry to deviate from the designed signal order, affecting the chip's normal operation. Due to the fixed layout of the chip pads and the unchangeable wiring on the packaging substrate, different packaging substrate wiring designs are required for different chip orientations to ensure correct correspondence between the signal pads and the connection fixing parts on the substrate. These connection fixing parts include, but are not limited to, solder balls, pins, or gold fingers. If a general-purpose substrate is used, the signal transmission path needs to be crossed or misaligned. That is, the correspondence between the chip signal pads and the fixed connection points on the substrate will be mirrored and offset, which can easily lead to problems such as signal crossing and misalignment, signal transmission interruption, and differential signal matching abnormality.When signal flipping occurs during the packaging process, it is usually necessary to modify the internal signal connection structure of the chip. This may require redesigning the layout or even re-faking the chip, readjusting the chip layout, or modifying the package pin definitions to adapt to different chip mounting positions. This necessitates designing two different packaging substrates with different wiring structures, which not only significantly increases the costs of substrate molding, material inventory, and production control, but also leads to poor product versatility and low package compatibility, failing to meet the large-scale, standardized, and multi-scenario compatible production and use requirements of high-speed interface devices for storage systems. Furthermore, traditional high-speed interface semiconductor devices lack adaptive path adjustment structures. Once the chip mounting position changes, the signal transmission path cannot be adjusted synchronously, easily causing high-speed signal transmission distortion, impedance mismatch, communication failures, and other faults, severely affecting the data transmission stability and transmission rate of the storage system.

[0025] To solve the above problems, refer to Figure 1 In one embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: The packaging substrate 20 is provided with a device mounting area, and a first device connection fixing part 21 and a second device connection fixing part 22 disposed opposite to each other; A high-speed interface chip 10 is disposed in the device mounting area; the high-speed interface chip 10 has a first chip side surface and a second chip side surface disposed opposite to each other, and the first chip side surface of the high-speed interface chip 10 has two signal lead-out areas disposed opposite to each other; the high-speed interface chip 10 includes a first signal transmission pad 11 and a second signal transmission pad 12, which are disposed in the two signal lead-out areas of the high-speed interface chip 10 respectively. The transmission path connection circuit 30 has a first signal input terminal IO11, a second signal input terminal IO12, a first signal output terminal IO21, and a second signal output terminal IO22. The first signal input terminal IO11 is connected to a first signal transmission pad 11, and the second signal input terminal IO12 is connected to a second signal transmission pad 12. The first signal output terminal IO21 is connected to a first device connection fixing part 21, and the second signal output terminal IO22 is connected to a second device connection fixing part 22. When the high-speed interface chip 10 is disposed on the first chip-side surface facing away from the device mounting area, the transmission path connection circuit 30 connects the first signal input terminal IO11 and the first signal output terminal IO21, and connects the second signal input terminal IO12 and the second signal output terminal IO22; and / or, When the first chip-side surface of the high-speed interface chip 10 is positioned facing the device mounting area, the transmission path connection circuit 30 connects the first signal input terminal IO11 and the second signal output terminal IO22, as well as the second signal input terminal IO12 and the first signal output terminal IO21.

[0026] In this embodiment, the packaging substrate 20 serves as a carrier for the high-speed interface chip 10 and other devices. The packaging substrate 20 has a device mounting area for integrating and mounting core components such as the high-speed interface chip 10, the transmission path connection circuit 30, and the controller 40. The high-speed interface chip 10 has a first chip-side surface and a second chip-side surface arranged opposite to each other. When the first chip-side surface of the high-speed interface chip 10 faces away from the device mounting area, the second chip-side surface can be fixed to the device mounting area using solder, adhesive, etc. When the first chip-side surface of the high-speed interface chip 10 faces the device mounting area, the first chip-side surface can be fixed to the device mounting area using solder, adhesive, etc. The packaging substrate 20 also has two oppositely arranged connection and fixing parts, namely a first device connection and fixing part 21 and a second device connection and fixing part 22. These two connection and fixing parts are external signal interface ports for semiconductor devices, used to achieve signal interconnection and physical fixation with other hardware structures of the storage system. The packaging substrate 20 can be a glass substrate, an aluminum substrate, a ceramic substrate, etc. The high-speed interface chip 10 can have multiple pads, specifically configured according to the number of signals it needs to transmit. When multiple pads are used, they can be divided into two groups, located on opposite sides of the chip. These pads serve as the core lead-out points for high-speed signals from the high-speed interface chip 10, responsible for the internal and external transmission of these signals. The high-speed interface chip 10 can transmit signals from outside the system to other chip structures within the system, such as for data writing, command address instructions, chip select instructions, and clock signal transmission. It can also transmit signals from other chip structures within the system to the outside, such as for data reading. The following embodiments of this invention illustrate the transmission of signals from other chip structures within the system to the outside, where the high-speed interface chip 10 transmits the signal to be transmitted to other external circuits of the semiconductor device, such as a memory chip, via the transmission path connection circuit 30. The signals to be transmitted include, but are not limited to, clock signals.

[0027] The transmission path connection circuit 30 can be integrated into the high-speed interface chip 10, and / or it can also be encapsulated in the device mounting area of ​​the substrate 20, serving as the core functional circuit for adaptive signal path switching. The transmission path connection circuit 30 is configured with four signal ports: a first signal input terminal IO11, a second signal input terminal IO12, a first signal output terminal IO21, and a second signal output terminal IO22. The first signal input terminal IO11 and the second signal input terminal IO12 are signal input terminals, respectively connected one-to-one to the first signal transmission pad 11 and the second signal transmission pad 12 of the high-speed interface chip 10; the first signal output terminal IO21 and the second signal output terminal IO22 are signal output terminals, respectively connected one-to-one to the first device connection fixing part 21 and the second device connection fixing part 22 of the encapsulation substrate 20.

[0028] Reference Figure 5 In the direct transmission mode: When the first chip-side surface of the high-speed interface chip 10 is positioned away from the device mounting area (usually referring to the substrate body), the high-speed interface chip 10 is mounted in a forward-mounted manner. That is, the transmission path connection circuit 30, with the first chip-side surface facing away from the device mounting area of ​​the packaging substrate 20, executes the direct connection logic, connecting the first signal input terminal IO11 and the first signal output terminal IO21, and simultaneously connecting the second signal input terminal IO12 and the second signal output terminal IO22, realizing one-to-one forward transmission of chip pad signals without signal crossover offset. The first transmission signal CK_T output by the high-speed interface chip 10 travels from the first signal transmission pad 11 of the chip through the first signal input terminal IO11, and then directly connects to the first signal output terminal IO21 through the internal switch network of the transmission path connection circuit 30, finally reaching the first device connection fixing part 21 of the packaging substrate 20, and then being transmitted to the external circuit connected to the semiconductor device through the first device connection fixing part 21. Similarly, the second transmission signal CK_C output by the high-speed interface chip 10 is transmitted from the second signal transmission pad 12 of the chip through the second signal input terminal IO12, and then directly connected to the second signal output terminal IO22 through the internal switch network of the transmission path connection circuit 30, and finally reaches the second device connection fixing part 22 of the packaging substrate 20, and is then transmitted to the external circuit connected to the semiconductor device through the second device connection fixing part 22.

[0029] Reference Figure 6In the switching transmission mode: When the first chip-side surface of the high-speed interface chip 10 faces the device mounting area, the mounting posture is flipped, and the high-speed interface chip 10 is mounted in a flip-chip manner. The transmission path connection circuit 30 executes the switching connection logic, connecting the first signal input terminal IO11 with the second signal output terminal IO22, and simultaneously connecting the second signal input terminal IO12 with the first signal output terminal IO21. Due to the flip-chip mounting, the chip is mirrored on the horizontal plane, and the projection position of the pad that was originally physically located on the left side on the substrate may correspond to the electrical position of the original right-side pad. At this time, the transmission path connection circuit 30 connects the first signal input terminal IO11 to the second signal output terminal IO22, and connects the second signal input terminal IO12 to the first signal output terminal IO21. The first transmission signal CK_T output by the high-speed interface chip 10 travels from the chip's first signal transmission pad 11 through the first signal input terminal IO11, then directly to the second signal output terminal IO22 via the internal switch network of the transmission path connection circuit 30, and finally reaches the first device connection fixing part 21 of the packaging substrate 20. From there, it is transmitted to the external circuit connected to the semiconductor device. Similarly, the second transmission signal CK_C output by the high-speed interface chip 10 travels from the chip's second signal transmission pad 12 through the second signal input terminal IO12, then directly to the first signal output terminal IO21 via the internal switch network of the transmission path connection circuit 30, and finally reaches the second device connection fixing part 22 of the packaging substrate 20. From there, it is transmitted to the external circuit connected to the semiconductor device.

[0030] Although the physical pad order of the chip is reversed compared to the nominal order of the substrate mounting portion, through internal path cross-correction, the final signal order output to the mounting portion is exactly the same as in the through-through mode. This achieves seamless compatibility with the packaging substrate 20, avoids signal point mirror offset caused by chip flip mounting, corrects signal misalignment problems, and ensures normal signal connection and transmission. The transmission path connection circuit 30, as a reconfigurable switching network, can dynamically switch the internal signal routing based on the actual physical mounting orientation of the high-speed interface chip 10, or through firmware / hardware configuration. Thus, as... Figure 5 As shown, when the chip is mounted upright, the active side faces upwards and away from the substrate. The signal lead-out pads on the left and right sides of the chip are connected to the first signal input terminal IO11 and the second signal output terminal IO22 of the circuit via wire bonding. The circuit sends the signals to the corresponding substrate fixing parts in a direct-through manner. Figure 6As shown, when the chip is flip-chip mounted, with the active side facing down towards the substrate, the chip may undergo a mirror flip in the horizontal direction. Signals that were originally on the left side may appear in the physical position on the right. In this case, the circuit automatically or controllably routes the first input terminal to the second output terminal, thereby correcting the signal sequence without modifying the substrate wiring. Thus, the pads of the high-speed interface chip 10 and the device connection fixing parts of the package substrate 20 can both securely transmit the predetermined signals, without changing the definition of the pads or the connection fixing parts due to changes in the package form. The connection fixing parts include, but are not limited to, pins, solder balls, or gold fingers for connecting the chip to the outside world.

[0031] This invention enables the semiconductor device to achieve compatibility with two different mounting orientations of high-speed interface chips 10 on the same package substrate 20 by introducing a configurable transmission path connection circuit 30. This eliminates the need for separate substrate design for each orientation, reducing R&D and manufacturing costs and minimizing the types of materials required. Furthermore, this invention allows for signal path adjustment without modifying the internal circuitry of the chip, adapting to the left-right flipping of input signals caused by changes in package structure, and avoiding the need for redesigning the chip layout or re-fabrication due to package structure changes.

[0032] Reference Figures 2 to 4 In one embodiment, the transmission path connection circuit 30 includes a first signal input switch circuit 31 and a second signal input switch circuit 32, with the two sets of switch circuits working together to achieve dual-mode path switching. Specifically, the transmission path connection circuit 30 includes: The first signal input switch circuit 31 has its first controlled terminal and second controlled terminal respectively connected to the first connection control signal S1 and the second connection control signal S2. The first signal input terminal of the first signal input switch circuit 31 is connected to the first signal input terminal IO11, the second signal input terminal of the first signal input switch circuit 31 is connected to the second signal input terminal IO12, and the signal output terminal of the first signal input switch circuit 31 is connected to the first signal output terminal IO21 and the second signal input terminal IO12. The second signal input switch circuit 32 has its first controlled terminal and second controlled terminal respectively connected to the second connection control signal S2 and the first connection control signal S1. The first signal input terminal of the second signal input switch circuit 32 is connected to the first signal input terminal IO11, and the second signal input terminal of the second signal input switch circuit 32 is connected to the second signal input terminal IO12. The signal output terminal of the second signal input switch circuit 32 is connected to the first signal output terminal IO21 and the second signal output terminal IO22, respectively. When the first chip side surface of the high-speed interface chip 10 is set away from the device mounting area, the first signal input switch circuit 31 and the second signal input switch circuit 32 realize the transmission of the first transmission signal CK_T through the first signal input terminal IO11 and the first signal output terminal IO21, and the first signal input switch circuit 31 and the second signal input switch circuit 32 realize the transmission of the second transmission signal CK_C through the second signal input terminal IO12 and the second signal output terminal IO22. When the first chip side surface of the high-speed interface chip 10 is positioned facing the device mounting area, the first signal input switch circuit 31 and the second signal input switch circuit 32 transmit the first transmission signal CK_T through the first signal input terminal IO11 and the second signal output terminal IO22, and the first signal input switch circuit 31 and the second signal input switch circuit 32 transmit the second transmission signal CK_C through the second signal input terminal IO12 and the first signal output terminal IO21.

[0033] In this embodiment, the first signal input switch circuit 31 is configured with four controlled terminals. One set of two diagonally positioned controlled terminals are both connected to the first connection control signal S1, and the other set of two diagonally positioned controlled terminals are both connected to the second connection control signal S2, thus achieving controlled switching of the switch state. The first signal input terminal of the first signal input switch circuit 31 is connected to the first signal input terminal IO11 and is used to receive the output signal from the first signal transmission pad 11 of the high-speed interface chip 10. The second signal input terminal of the first signal input switch circuit 31 is connected to the second signal input terminal IO12 and is used to receive the output signal from the second signal transmission pad 12 of the high-speed interface chip 10. The signal output terminal of the first signal input switch circuit 31 is simultaneously connected to the first signal output terminal IO21 and the second signal output terminal IO22, allowing selection of the signal output path based on the control signal. The second signal input switch circuit 32 is symmetrically arranged with the first signal input switch circuit 31. Of the four controlled terminals of the second signal input switch circuit 32, two diagonally opposite terminals in one group are connected to the first connection control signal S1, and two diagonally opposite terminals in the other group are connected to the second connection control signal S2, achieving controlled switching of the switch state and realizing anti-phase synchronous control. The first signal input terminal of the second signal input switch circuit 32 is connected to the second signal input terminal IO12 to receive the output signal of the second signal transmission pad 12. The second signal input terminal of the second signal input switch circuit 32 is also connected to the second signal input terminal IO12 to receive the output signal of the second signal transmission pad 12 of the high-speed interface chip 10. Its signal output terminal is simultaneously connected to the first signal output terminal IO21 and the second signal output terminal IO22. By controlling the conduction direction of the first signal input switch circuit 31 and the second signal input switch circuit 32, and coordinating with the connection control signals connected to their respective controlled terminals (e.g., controlled by the first connection control signal S1 and the second connection control signal S2), path selection can be achieved. For example, when the logic of the first connection control signal S1 is "1" and the logic of the second connection control signal S2 is "0", the first signal input switch circuit 31 connects the second signal input terminal IO12 to the first signal output terminal IO21. The second transmission signal CK_C is output from the second signal input terminal IO12 to the inverter. After being inverted by the inverter, it is converted into the first transmission signal CK_T and transmitted by the first signal output terminal IO21. The second signal input switch circuit 32 connects the first signal input terminal IO11 to the second signal output terminal IO22. The second transmission signal CK_T is output from the first signal input terminal IO11 to the inverter. After being inverted by the inverter, it is converted into the second transmission signal CK_C and transmitted by the second signal output terminal IO22.

[0034] Therefore, the first transmission signal CK_T is input through the first signal input terminal IO11 and output through the first signal output terminal IO21, while the second transmission signal CK_C is input through the second signal input terminal IO12 and output through the second signal output terminal IO22.

[0035] When the logic of the first connection control signal S1 is "0" and the logic of the second connection control signal S2 is "1", the first signal input switch circuit 31 connects the second signal input terminal IO12 to the first signal output terminal IO21. The first transmission signal CK_T is output from the first signal input terminal IO11 to the inverter. After being inverted by the inverter, it is converted into the second transmission signal CK_C and transmitted by the first signal output terminal IO21. The second signal input switch circuit 32 connects the second signal input terminal IO12 to the second signal output terminal IO22. The second transmission signal CK_C is output from the second signal input terminal IO12 to the inverter. After being inverted by the inverter, it is converted into the first transmission signal CK_T and transmitted by the second signal output terminal IO22.

[0036] Therefore, it can be seen that the first transmission signal CK_T is input through the first signal input terminal IO11 and output through the second signal output terminal IO22, while the second transmission signal CK_C is input through the second signal input terminal IO12 and output through the first signal output terminal IO21.

[0037] The first signal input switch circuit 31 and the second signal input switch circuit 32 adopt complementary control logic to ensure that the two paths will not connect the same signal terminal to the same output terminal at the same time, thus avoiding conflict.

[0038] Optionally, when the high-speed interface chip 10 is mounted with its first chip-side surface facing away from the device mounting area, under the action of the first connection control signal S1 and the second connection control signal S2, the first signal input switch circuit 31 connects the second signal input terminal IO12 and the first signal output terminal IO21, and the second signal input switch circuit 32 connects the first signal input terminal IO11 and the second signal output terminal IO22, realizing direct signal transmission. When the high-speed interface chip 10 is mounted with its first chip-side surface facing the device mounting area, the levels of the first connection control signal S1 and the second connection control signal S2 are flipped. The first signal input switch circuit 31 connects the first signal input terminal IO11 and the first signal output terminal IO21, and the second signal input switch circuit 32 connects the second signal input terminal IO12 and the second signal output terminal IO22, realizing signal exchange transmission and adapting to the chip's flipped orientation. Through the coordinated operation of the two sets of switch circuits, signal path selection is achieved. The logic levels of the first connection control signal S1 and the second connection control signal S2 are also shown. For example, when the first connection control signal S1 is high and the second connection control signal S2 is low, a pass-through is selected; when the first connection control signal S1 is low and the second connection control signal S2 is high, a swap is selected, thus determining the internal connectivity of the switch. It can be understood that the first signal-introduced switch circuit 31 and the second signal-introduced switch circuit 32 switch the state of the entire signal network through simple digital logic control signals, such as those from the controller 40 or configuration pins on the substrate.

[0039] Reference Figure 4 In one embodiment, the first signal input switch circuit 31 includes a first pull-up controlled switch P1, a first transmission gate 311, a first pull-down controlled switch N1, and a first inverter INV1. The first pull-up controlled switch P1, the first transmission gate 311, and the first pull-down controlled switch N1 are connected in series. The controlled terminals of the first pull-up controlled switch P1 and the first pull-down controlled switch N1 are respectively connected to a first connection control signal S1 and a second connection control signal S2. The input terminal of the first transmission gate 311 is connected to the first signal input terminal of the first signal input switch circuit 31, and the output terminal of the first transmission gate 311 is connected to the signal output terminal of the first signal input switch circuit 31 via the first inverter INV1.

[0040] The first signal input switch circuit 31 further includes a second pull-up controlled switch P2, a second transmission gate 312, a second pull-down controlled switch N2, and a first inverter INV1. The second pull-up controlled switch P2, the second transmission gate 312, and the second pull-down controlled switch N2 are connected in series. The controlled terminals of the second pull-up controlled switch P2 and the second pull-down controlled switch N2 are respectively connected to the first connection control signal S1 and the second connection control signal S2. The input terminal of the second transmission gate 312 is connected to the second signal input terminal of the first signal input switch circuit 31, and the output terminal of the second transmission gate 312 is connected to the signal output terminal of the first signal input switch circuit 31 via the first inverter INV1.

[0041] The second signal input switch circuit 32 includes a third pull-up controlled switch P3, a fourth pull-up controlled switch P4, a third transmission gate 321, a fourth transmission gate 322, a third pull-down controlled switch N3, a fourth pull-down controlled switch N4, and a second inverter INV2. The third pull-up controlled switch P3, the third transmission gate 321, and the third pull-down controlled switch N3 are connected in series. The controlled terminals of the third pull-up controlled switch P3 and the third pull-down controlled switch N3 are respectively connected to the second connection control signal S2 and the first connection control signal S1. The input terminal of the third transmission gate 321 is connected to the first signal input terminal of the second signal input switch circuit 32, and the output terminal of the third transmission gate 321 is connected to the signal output terminal of the second signal input switch circuit 32 via the second inverter INV2. The fourth pull-up controlled switch P4, the fourth transmission gate 322, and the fourth pull-down controlled switch N4 are connected in series. The controlled terminals of the fourth pull-up controlled switch P4 and the fourth pull-down controlled switch N4 are respectively connected to the first connection control signal S1 and the second connection control signal S2. The input terminal of the fourth transmission gate 322 is connected to the second signal input terminal of the second signal input switch circuit 32. The output terminal of the fourth transmission gate 322 is connected to the signal output terminal of the second signal input switch circuit 32 via the second inverter INV2.

[0042] In this embodiment, the first pull-up controlled switch P1 can be implemented using a PMOS transistor, and the first pull-down controlled switch N1 can be implemented using an NMOS transistor. The PMOS transistor is controlled by the first connection control signal S1, and the NMOS transistor is controlled by the second connection control signal S2. The first transmission gate 311 can be implemented using a PMOS transistor and an NMOS transistor connected in series. The gates of the PMOS transistor and the NMOS transistor are respectively connected to the first transmission signal CK_T output by the high-speed interface chip 10. The first transmission signal CK_T can be a differential clock positive phase signal CK_T (Clock True, issued by the non-inverting input of the high-speed interface chip 10). The second pull-up controlled switch P2 can be implemented using a PMOS transistor, and the second pull-down controlled switch N2 can be implemented using an NMOS transistor. The PMOS transistor is controlled by the second connection control signal S2, and the NMOS transistor is controlled by the first connection control signal S1. The second transmission gate 312 can be implemented using a PMOS transistor and an NMOS transistor connected in series. The gates of the PMOS transistor and the NMOS transistor are respectively connected to the second transmission signal CK_C output by the high-speed interface chip 10. The second transmission signal CK_C can be a differential clock inverted signal CK_C (Clock Complement, issued by the complementary terminal of the high-speed interface chip 10).

[0043] In this embodiment, the third pull-up controlled switch P3 can be implemented using a PMOS transistor, and the third pull-down controlled switch N3 can be implemented using an NMOS transistor. The PMOS transistor is controlled by the second connection control signal S2, and the NMOS transistor is controlled by the first connection control signal S1. The third transmission gate 321 can be implemented using a PMOS transistor and an NMOS transistor connected in series. The gates of the PMOS transistor and the NMOS transistor are respectively connected to the first transmission signal CK_T output by the high-speed interface chip 10. The first transmission signal CK_T can be a differential clock positive phase signal CK_T (Clock True, issued by the non-inverting input of the high-speed interface chip 10). The fourth pull-up controlled switch P4 can be implemented using a PMOS transistor, and the fourth pull-down controlled switch N4 can be implemented using an NMOS transistor. The PMOS transistor is controlled by the first connection control signal S1, and the NMOS transistor is controlled by the second connection control signal S2. The fourth transmission gate 322 can be implemented using a PMOS transistor and an NMOS transistor connected in series. The gates of the PMOS transistor and the NMOS transistor are respectively connected to the second transmission signal CK_C output by the high-speed interface chip 10. The second transmission signal CK_C can be a differential clock inversion signal CK_C (Clock Complement, issued by the complementary terminal of the high-speed interface chip 10).

[0044] Optionally, such as Figure 2As shown, in normal pass-through mode, the level of the first connection control signal S1 is high (logic "1"), and the level of the second connection control signal S2 is low (logic "0"). The high level of the first connection control signal S1 is output to the first pull-up controlled switch P1 (the gate of the PMOS transistor is connected to the first connection control signal S1), causing the PMOS transistor to remain in the off state according to this high level, and thus not perform the pull-up function, thereby affecting the transmission of the first transmission signal CK_T. The low level of the second connection control signal S2 is output to the first pull-down controlled switch N1 (the gate of the NMOS transistor is connected to the second connection control signal S2). The NMOS transistor receives this low level and remains in the off state, thereby affecting the transmission of the first transmission signal CK_T. At this time, 311 remains in the non-operating state.

[0045] The low level of the second connection control signal S2 is output to the second pull-up controlled switch P2 (the gate of the PMOS transistor is connected to the second connection control signal S2). The PMOS transistor receives this low level and remains in the on state. At this time, the PMOS transistor is only turned on and connected to the power supply. The high level of the first connection control signal S1 is output to the second pull-down controlled switch N2 (the gate of the NMOS transistor is connected to the first connection control signal S1). The NMOS transistor remains in the on state and is grounded according to this high level, which acts as a pull-down, so that the high and low levels of the second transmission signal CK_C can be transmitted from the second transmission gate 312. The signal flow of the second transmission signal CK_C is as follows: the second transmission signal CK_C is output to the first inverter INV1 through the second transmission gate 312, and is inverted by the first inverter INV1 to become the first transmission signal CK_T, and then output from the first signal output terminal IO21.

[0046] The low level of the second connection control signal S2 is output to the third pull-up controlled switch P3 (the gate of the PMOS transistor is connected to the second connection control signal S2). The PMOS transistor receives this low level and remains in the conducting state. At this time, the PMOS transistor is only conducting and connected to the power supply. The third pull-down controlled switch N3 (the gate of the NMOS transistor is connected to the first connection control signal S1) makes the NMOS transistor remain in the conducting state according to this high level and grounded, which acts as a pull-down, so that the high and low levels of the first transmission signal CK_T can be transmitted from the third transmission gate 321. The signal flow of the first transmission signal CK_T is as follows: the first transmission signal CK_T is output to the second inverter INV2 through the third transmission gate 321, and is inverted by the second inverter INV2 to become the second transmission signal CK_C, and then output from the second signal output terminal IO22.

[0047] The high level of the first connection control signal S1 is output to the fourth pull-up controlled switch P4 (the gate of the PMOS transistor is connected to the first connection control signal S1), causing the PMOS transistor to remain in the off state according to this high level, and thus not perform the pull-up function, thereby affecting the transmission of the second transmission signal CK_C. The low level of the second connection control signal S2 is output to the fourth pull-down controlled switch N4 (the gate of the NMOS transistor is connected to the second connection control signal S2), and the NMOS transistor receives this low level and remains in the off state, thus affecting the transmission of the second transmission signal CK_C.

[0048] In summary, under normal pass-through mode, the first transmission signal CK_T is input through the first signal input terminal IO11 and output through the first signal output terminal IO21, while the second transmission signal CK_C is input through the second signal input terminal IO12 and output through the second signal output terminal IO22.

[0049] like Figure 3 As shown, in the switching mode, the level of the first connection control signal S1 is low (logic "0"), and the level of the second connection control signal S2 is high (logic "1"). The low level of the first connection control signal S1 is output to the first pull-up controlled switch P1 (the gate of the PMOS transistor is connected to the first connection control signal S1). The PMOS transistor is turned on at a low level, providing a pull-up path for the first connection signal CK_C, thus acting as a pull-up signal. The high level of the second connection control signal S2 is output to the first pull-down controlled switch N1 (the gate of the NMOS transistor is connected to the second connection control signal S2). The NMOS transistor is kept on and grounded according to this high level, acting as a pull-down signal, providing a pull-down path for CK_T, thereby enabling the high and low levels of the first transmission signal CK_T to be transmitted from the first transmission gate 311. The signal flow of the first transmission signal CK_T is as follows: the first transmission signal CK_T is output to the first inverter INV1 through the first transmission gate 311, inverted by the first inverter INV1 to become the second transmission signal CK_C, and output to the first signal output terminal IO21.

[0050] The high level of the second connection control signal S2 is output to the second pull-up controlled switch P2 (the gate of the PMOS transistor is connected to the second connection control signal S2), causing the PMOS transistor to remain off according to this high level, thus affecting the transmission of the second transmission signal CK_C. The low level of the second connection control signal S2 is output to the second pull-down controlled switch N2 (the gate of the NMOS transistor is connected to the second connection control signal S2), causing the NMOS transistor to remain off according to this low level, thus affecting the transmission of the second transmission signal CK_C. The high level of the second connection control signal S2 is output to the third pull-up controlled switch P3 (the gate of the PMOS transistor is connected to the second connection control signal S2), causing the PMOS transistor to remain off according to this high level and not provide a pull-up effect, thus affecting the transmission of the first transmission signal CK_T. The low level of the first connection control signal S1 is output to the third pull-down controlled switch N3 (the gate of the NMOS transistor is connected to the first connection control signal S1), causing the NMOS transistor to remain off according to this low level, thus affecting the transmission of the first transmission signal CK_T.

[0051] The low level of the first connection control signal S1 is output to the fourth pull-up controlled switch P4 (the gate of the PMOS transistor is connected to the first connection control signal S1). The PMOS transistor receives this low level and remains on. At this time, the PMOS transistor is only on and connected to the power supply. The fourth pull-down controlled switch N4 (the gate of the NMOS transistor is connected to the second connection control signal S2) causes the NMOS transistor to remain on according to this high level, acting as a pull-down switch, allowing the high and low levels of the second transmission signal CK_C to be transmitted from the fourth transmission gate 322. The signal flow of the second transmission signal CK_C is as follows: the second transmission signal CK_C is output to the second inverter INV2 through the fourth transmission gate 322, inverted by the second inverter INV2 to become the first transmission signal CK_T, and output to the second signal output terminal IO22.

[0052] In summary, in the switching mode, the first transmission signal CK_T is accessed by the first signal input terminal IO11 and sent to the output path (IO22) of the original second transmission signal CK_C. The second transmission signal CK_C is accessed by the second signal input terminal and sent to the path (IO21) of the original first transmission signal CK_T, thus realizing the switching.

[0053] This invention employs a "pull-up + transmission gate + pull-down" structure, which enhances signal driving capability, improves signal integrity, reduces rise / fall time, and suppresses noise. The transmission gate transmits digital signals without distortion, while the pull-up / pull-down switches, under the control of the signal, provide a defined level to the output node, for example, preventing the output from floating when the transmission gate is closed, thereby improving circuit reliability. By coordinating the levels of the upper and lower controlled switches, the conduction path of the transmission gate is controlled, enabling switching between pass-through and switching modes. The two sets of switching circuits adopt a symmetrical architecture to ensure consistent transmission impedance and transmission delay for the two high-speed signals, avoiding differential signal imbalance and ensuring high-speed transmission accuracy. This invention introduces a controllable MOS transistor network into the input signal path, enabling the input signal to switch between pass-through and switching modes, thereby adapting to the signal flipping problem caused by changes in package structure. The signal switching circuit structure based on the switching network composed of MOS transistors achieves dynamic switching of input signals by forming different conduction paths through control signals S1 and S2. This improves the chip's adaptability to different packaging structures. The structure is simple, requiring only a small number of MOS switching circuits, and is easy to implement in integrated circuits. At the same time, it can maintain the signal driving capability required by high-speed interface circuits.

[0054] Reference Figure 3 or Figure 4 In one embodiment, the semiconductor device further includes: The input buffer circuit 50 has two input terminals connected to the first signal input terminal IO11 and the second signal input terminal IO12, respectively, and two output terminals connected to the signal input terminals of the first signal input switch circuit 31 and the second signal input switch circuit 32, respectively.

[0055] The output buffer circuit 60 has two input terminals connected to the signal output terminals of the first signal input switch circuit 31 and the second signal input switch circuit 32, respectively, and two output terminals connected to the first signal output terminal IO21 and the second signal output terminal IO22, respectively.

[0056] In this embodiment, the input buffer circuit 50 amplifies and shapes the high-speed weak signal output by the high-speed interface chip 10, filters high-frequency noise and signal jitter generated during the packaging process, and simultaneously achieves input impedance matching to avoid signal reflection and crosstalk problems, thereby improving the signal integrity entering the switching circuit. The processed signal is then output to the first signal input switching circuit 31 and the second signal input switching circuit 32.

[0057] The output buffer circuit 60 can perform secondary shaping and noise reduction on the direct output or switched signal, stabilize the level amplitude and transmission impedance of the output signal, and output it to the subsequent circuit connected to the semiconductor device. The signal is driven by the output buffer circuit 60 to ensure that the signal is stably transmitted to the subsequent circuit of the external connection fixing part, and can stably drive the subsequent circuit to meet the high-speed and high-stability transmission requirements of the storage system.

[0058] Reference Figure 1 In one embodiment, the semiconductor device further includes a controller 40 disposed in the device mounting area. The control terminal of the controller 40 is connected to the controlled terminal of the transmission path communication circuit 30. The controller 40 is used to acquire the packaging mode information of the semiconductor device. When it is determined that the first chip side surface of the high-speed interface chip 10 is disposed away from the device mounting area according to the packaging mode information, the controller controls the first signal input switch circuit 31 to connect the first signal input terminal IO11 and the first signal output terminal IO21; and controls the second signal input switch circuit 32 to connect the second signal input terminal IO12 and the second signal output terminal IO22. When the first chip-side surface of the high-speed interface chip 10 is determined to be aligned with the device mounting area based on the packaging mode information, the first signal input switch circuit 31 is controlled to connect the first signal input terminal IO11 and the second signal output terminal IO22; and the second signal input switch circuit 32 is controlled to connect the second signal input terminal IO12 and the first signal output terminal IO21.

[0059] In this embodiment, the controller 40 can be a standalone microcontroller 40, logic circuit, or control logic integrated within the high-speed interface chip 10. The packaging mode information can be written once during the semiconductor device assembly and testing phase, for example, by programming efuse, or determined through physical connections (hardwired) on the substrate. After the device is powered on, the controller 40 automatically reads this information and configures the transmission path connection circuit 30 to achieve automatic adaptation. Alternatively, a configuration resistor can be set on the substrate, and the controller 40 can determine the current chip mounting orientation by detecting the configuration resistor R_cfg on the packaging substrate 20 or reading the internal OTP register. For example, R_cfg connected to power indicates "orthogonal mounting," and connected to ground indicates "flip-mounted." After power-on, the controller 40 reads this status and then outputs S1 and S2 (or a set of control buses) to the transmission path connection circuit 30 to complete the automatic configuration. This process requires no external intervention, improving the product's usability and reliability.

[0060] In some embodiments, the controller 40 can pre-store identification information of two packaging modes, acquire the packaging mode information of semiconductor devices in real time, and complete the mode determination by recognizing the chip mounting posture.

[0061] When it is determined that the first chip side surface of the high-speed interface chip 10 is set to face away from the device mounting area, the controller 40 outputs the corresponding control level to control the first signal input switch circuit 31 to make the first signal input terminal IO11 and the first signal output terminal IO21 conduct, and the second signal input switch circuit 32 to make the second signal input terminal IO12 and the second signal output terminal IO22 conduct, thus executing the pass-through transmission mode.

[0062] When it is determined that the first chip side surface of the high-speed interface chip 10 is facing the device mounting area, the controller 40 flips the control signal level to control the two sets of switching circuits to switch the path, so that the first signal input terminal IO11 is connected to the second signal output terminal IO22 and the second signal input terminal IO12 is connected to the first signal output terminal IO21, and the switching transmission mode is executed.

[0063] This invention enables the packaging substrate 20 to be compatible with two mounting orientations of high-speed interface chips 10. Through the coordination of a switching circuit and a controller 40, the controller 40 identifies the chip packaging and mounting mode, outputting corresponding connectivity control signals to drive two sets of symmetrical signals into the switching circuit to switch the transmission path. When the chip is mounted in the forward orientation, the switching circuit executes signal pass-through logic, ensuring one-to-one forward signal transmission. When the chip is mounted in the reverse orientation, the controller 40 controls the transmission path connectivity circuit 30 to automatically switch to signal exchange transmission logic, compensating for the mirror offset of the solder pads caused by the chip flip. The entire process requires no manual intervention, achieving intelligent adaptive adaptation. Simultaneously, the input and output buffer circuits 60 perform noise reduction, shaping, and impedance matching on the high-speed signals, ultimately achieving a single substrate adapting to two packaging modes. This ensures complete and stable transmission of high-speed signals under different mounting orientations, solving the problems of poor versatility and easy signal failure in traditional devices.

[0064] Reference Figure 5 and Figure 6 In one embodiment, when the first chip-side surface of the high-speed interface chip 10 is disposed away from the device mounting area, the first signal transmission pad 11 is bonded to the first signal input terminal IO11 via a lead, and the second signal transmission pad 12 is bonded to the second signal input terminal IO12 via a lead. When the first chip side surface of the high-speed interface chip 10 is arranged facing the device mounting area, the first signal transmission pad 11 is connected to the first signal input terminal IO11 through circuit wiring provided on the packaging substrate 20, and the second signal transmission pad 12 is connected to the second signal input terminal IO12 through circuit wiring provided on the packaging substrate 20.

[0065] When the first chip side surface of the high-speed interface chip 10 is set to face away from the device mounting area, the chip pads are suspended and facing outwards. Signal docking is achieved by using wire bonding technology. That is, the first signal transmission pad 11 and the second signal transmission pad 12 are respectively bonded to the first signal input terminal IO11 and the second signal input terminal IO12 through metal leads. The process is simple and highly adaptable.

[0066] When the first chip side surface of the high-speed interface chip 10 is set towards the device mounting area, the chip pads are attached to the substrate without wire bonding. Through the pre-set circuit wiring inside the packaging substrate 20, the electrical connection between the first signal transmission pad 11 and the first signal input terminal IO11, and the second signal transmission pad 12 and the second signal input terminal IO12 are directly realized, which meets the packaging process requirements and ensures the compact structure.

[0067] In the upright (back-facing) configuration, the chip is connected to the signal input terminal on the substrate via wire bonding, with the connection sequence directly corresponding. In the flip-chip (facing) configuration, the chip is connected to the signal input terminal via internal metal wiring (e.g., RDL layer or inner layer traces). Since the chip's projection position on the substrate is fixed during flip-chip configuration, the connection can be achieved using substrate wiring. Regardless of the connection method, the transmission path connection circuit 30 can correct the signal sequence ultimately output to the device connection fixing part (i.e., the external interface).

[0068] The present invention also proposes a high-speed interface circuit, comprising the semiconductor device described above.

[0069] The detailed structure of the semiconductor device can be referred to in the above embodiments, and will not be repeated here. It is understood that since the above semiconductor device is used in the high-speed interface circuit of the present invention, the embodiments of the high-speed interface circuit of the present invention include all the technical solutions of all the embodiments of the above semiconductor device, and the technical effects achieved are exactly the same, and will not be repeated here.

[0070] The present invention also proposes a storage system comprising the semiconductor device described above; and / or, the high-speed interface circuit described above.

[0071] This invention enables the application of the aforementioned semiconductor device or a high-speed interface circuit incorporating the device in storage systems, such as solid-state drives (SSDs), DDR DIMM memory modules, or CXL memory pool devices. In this storage system, the main control chip exchanges data with NAND flash memory or DRAM storage chips through the high-speed interface chip in the semiconductor device of this invention. Because the semiconductor device can adapt to chip orientation, the circuit board design of the storage system can be more flexible, and the same substrate can be used for various storage systems with different packaging processes, ensuring the complete and stable transmission of high-speed signals under different mounting orientations, and solving the problems of poor versatility and easy signal failure of traditional devices.

[0072] The above description is merely an optional embodiment of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: The packaging substrate has a device mounting area and a first device connection fixing part and a second device connection fixing part disposed opposite to each other. A high-speed interface chip is disposed in the device mounting area; the first chip-side surface of the high-speed interface chip has two signal lead-out areas disposed opposite to each other; the high-speed interface chip further includes a first signal transmission pad and a second signal transmission pad, respectively disposed in the two signal lead-out areas of the high-speed interface chip; and A transmission path connection circuit is provided, comprising a first signal input terminal, a second signal input terminal, a first signal output terminal, and a second signal output terminal; the first signal input terminal is connected to a first signal transmission pad, and the second signal input terminal is connected to a second signal transmission pad; the first signal output terminal is connected to a first device connection fixing part, and the second signal output terminal is connected to a second device connection fixing part; wherein... When the first chip-side surface of the high-speed interface chip is disposed away from the device mounting area, the transmission path connection circuit connects the first signal input terminal and the first signal output terminal, and connects the second signal input terminal and the second signal output terminal. When the first chip-side surface of the high-speed interface chip is positioned facing the device mounting area, the transmission path connection circuit connects the first signal input terminal and the second signal output terminal, and also connects the second signal input terminal and the first signal output terminal.

2. The semiconductor device as claimed in claim 1, characterized in that, The transmission path connection circuit includes: A first signal input switch circuit has a first controlled terminal and a second controlled terminal respectively connected to a first connection control signal and a second connection control signal. The first signal input terminal of the first signal input switch circuit is connected to the first signal input terminal, and the second signal input terminal of the first signal input switch circuit is connected to the second signal input terminal. The signal output terminal of the first signal input switch circuit is connected to both the first signal output terminal and the second signal input terminal. The second signal input switch circuit has its first controlled terminal and second controlled terminal respectively connected to a second connection control signal and a first connection control signal. The first signal input terminal of the second signal input switch circuit is connected to the first signal input terminal, and the second signal input terminal of the second signal input switch circuit is connected to the second signal input terminal. The signal output terminal of the second signal input switch circuit is connected to both the first signal output terminal and the second signal output terminal. When the first chip-side surface of the high-speed interface chip is disposed away from the device mounting area, the first signal input switch circuit and the second signal input switch circuit realize the transmission of the first transmission signal through the first signal input terminal and the first signal output terminal, and realize the transmission of the second transmission signal through the second signal input terminal and the second signal output terminal; When the first chip-side surface of the high-speed interface chip is disposed facing the device mounting area, the first signal input switch circuit and the second signal input switch circuit realize the transmission of the first transmission signal through the first signal input terminal and the second signal output terminal, and realize the transmission of the second transmission signal through the second signal input terminal and the first signal output terminal.

3. The semiconductor device as described in claim 2, characterized in that, The first signal input switch circuit includes a first pull-up controlled switch, a second pull-up controlled switch, a first transmission gate, a second transmission gate, a first pull-down controlled switch, a second pull-down controlled switch, and a first inverter. The first pull-up controlled switch, the first transmission gate, and the first pull-down controlled switch are connected in series. The controlled terminals of the first pull-up controlled switch and the first pull-down controlled switch are respectively connected to a first connection control signal and a second connection control signal. The input terminal of the first transmission gate is connected to the first signal input terminal of the first signal input switch circuit, and the output terminal of the first transmission gate is connected to the signal output terminal of the first signal input switch circuit via the first inverter. The second pull-up controlled switch, the second transmission gate, and the second pull-down controlled switch are connected in series. The controlled terminals of the second pull-up controlled switch and the second pull-down controlled switch are respectively connected to the second connection control signal and the first connection control signal. The input terminal of the second transmission gate is connected to the second signal input terminal of the first signal input switch circuit. The output terminal of the second transmission gate is connected to the signal output terminal of the first signal input switch circuit via the first inverter.

4. The semiconductor device as claimed in claim 2, characterized in that, The second signal input switch circuit includes a third pull-up controlled switch, a fourth pull-up controlled switch, a third transmission gate, a fourth transmission gate, a third pull-down controlled switch, a fourth pull-down controlled switch, and a second inverter. The third pull-up controlled switch, the third transmission gate, and the third pull-down controlled switch are connected in series. The controlled terminals of the third pull-up controlled switch and the third pull-down controlled switch are respectively connected to a second connection control signal and a first connection control signal. The input terminal of the third transmission gate is connected to the first signal input terminal of the second signal input switch circuit, and the output terminal of the third transmission gate is connected to the signal output terminal of the second signal input switch circuit via the second inverter. The fourth pull-up controlled switch, the fourth transmission gate, and the fourth pull-down controlled switch are connected in series. The controlled terminals of the fourth pull-up controlled switch and the fourth pull-down controlled switch are respectively connected to the first connection control signal and the second connection control signal. The input terminal of the fourth transmission gate is connected to the second signal input terminal of the second signal input switch circuit. The output terminal of the fourth transmission gate is connected to the signal output terminal of the second signal input switch circuit via the second inverter.

5. The semiconductor device according to any one of claims 2 to 4, characterized in that, The semiconductor device further includes: An input buffer circuit is provided, wherein two input terminals of the input buffer circuit are respectively connected to the first signal input terminal and the second signal input terminal, one output terminal of the input buffer circuit is connected to the first signal input terminal of the first signal input switch circuit and the first signal input terminal of the second signal input switch circuit, and the other output terminal of the input buffer circuit is connected to the second signal input terminal of the first signal input switch circuit and the second signal input terminal of the second signal input switch circuit.

6. The semiconductor device according to any one of claims 2 to 4, characterized in that, The semiconductor device further includes: An output buffer circuit is provided, wherein the two input terminals of the output buffer circuit are respectively connected to the signal output terminals of the first signal input switch circuit and the second signal input switch circuit, and the two output terminals of the output buffer circuit are respectively connected to the first signal output terminal and the second signal output terminal.

7. The semiconductor device according to any one of claims 2 to 4, characterized in that, The semiconductor device further includes a controller disposed in the device mounting area. The control terminal of the controller is connected to the controlled terminal of the transmission path connection circuit. The controller is used to acquire the packaging mode information of the semiconductor device. When it is determined that the first chip side surface of the high-speed interface chip is set away from the device mounting area according to the packaging mode information, the controller controls the first signal input switch circuit to connect the first signal input terminal and the first signal output terminal. In addition, the control circuit for the second signal input switch connects the second signal input terminal and the second signal output terminal; When the packaging mode information determines that the first chip-side surface of the high-speed interface chip is oriented toward the device mounting area, the first signal input switch circuit is controlled to connect the first signal input terminal and the second signal output terminal; and the second signal input switch circuit is controlled to connect the second signal input terminal and the first signal output terminal.

8. The semiconductor device according to any one of claims 1 to 4, characterized in that, When the first chip-side surface of the high-speed interface chip is disposed away from the device mounting area, the first signal transmission pad is bonded to the first signal input terminal via a lead, and the second signal transmission pad is bonded to the second signal input terminal via a lead. When the first chip-side surface of the high-speed interface chip is disposed facing the device mounting area, the first signal transmission pad is connected to the first signal input terminal through circuit wiring disposed on the packaging substrate, and the second signal transmission pad is connected to the second signal input terminal through circuit wiring disposed on the packaging substrate.

9. A high-speed interface circuit, characterized in that, Includes the semiconductor device as described in any one of claims 1 to 8.

10. A storage system, characterized in that, Includes the semiconductor device as described in any one of claims 1 to 8; and / or the high-speed interface circuit as described in claim 9.

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