An adaptive calibration method and system for SLC NAND threshold voltage

Abstract

The application relates to the technical field of semiconductor storage, and discloses an SLC NAND threshold voltage self-adaptive calibration method and system. The method comprises the following steps: obtaining initial voltage data of a target flash memory, calculating a distribution offset of the target flash memory, comparing the distribution offset with a preset offset threshold, determining a density fast and slow change region of the distribution voltage of the target flash memory according to a comparison result, obtaining a voltage interval span value according to the density fast and slow change region to perform non-equidistant division, generating a non-equidistant division width set, obtaining a boundary candidate value sequence of the non-equidistant division width set, reconstructing a distribution curve, extracting a valley voltage, adjusting a boundary to generate a dynamic voltage boundary, judging a storage state according to the dynamic voltage boundary, obtaining reading data, and completing calibration reading. The method realizes self-adaptive calibration reading by offset detection and gradient analysis, in combination with a preset offset threshold and non-equidistant division, to generate a dynamic voltage boundary.

Description

Technical Field

[0001] This invention relates to the field of semiconductor storage technology, and in particular to an adaptive calibration method and system for SLC NAND threshold voltage. Background Technology

[0002] Currently, SLC NAND flash memory, as a crucial component of solid-state storage, is widely integrated into SSDs, embedded storage devices, and various application-specific integrated circuits. It is extensively used in high-speed caches, enterprise-level storage, and embedded devices with high data reliability requirements. Its read accuracy directly impacts the stability and reliability of the entire storage system. SLC NAND flash memory uses threshold voltages of storage cells to represent different storage states. The read process requires comparing the threshold voltages of the storage cells with a set threshold voltage to determine the corresponding storage state. Therefore, the setting of the threshold voltage directly affects the accuracy of data reads.

[0003] In existing technologies, a fixed read threshold or a method of equally spaced threshold voltage ranges is typically used to establish read determination boundaries for identifying storage states. While some solutions may offset the read threshold based on empirical parameters to accommodate device aging or environmental changes, the determination boundaries still employ a fixed division method. After prolonged erasure or storage of SLC NAND flash memory, factors such as program / erase cycles, charge leakage, and process variations can cause the threshold voltage distribution of storage cells to shift and widen. The fixed or offset determination boundaries are difficult to maintain consistency with the actual threshold voltage distribution, easily leading to incorrect storage state determination, increasing the data read error rate, and raising the overhead of subsequent error correction processes.

[0004] Existing technologies use a fixed quantization method, which results in the read judgment boundary being unable to adapt to changes in threshold voltage distribution, leading to reduced read accuracy and storage reliability. Summary of the Invention

[0005] This invention provides an adaptive calibration method and system for SLC NAND threshold voltage to solve the problem that the existing technology uses a fixed quantization division method for the read judgment boundary, which cannot adapt to changes in threshold voltage distribution, resulting in decreased read accuracy and reduced storage reliability.

[0006] In a first aspect, to address the aforementioned technical problems, the present invention provides an adaptive calibration method for SLC NAND threshold voltage, comprising: Acquire the initial voltage data of the target flash memory and calculate the distribution offset of the target flash memory. Compare the distribution offset with a preset offset threshold and determine the regions where the density of the distributed voltage of the target flash memory changes rapidly and regions where the density changes slowly based on the comparison result. Local density data corresponding to the rapidly changing density region and the slowly changing density region are extracted from the voltage distribution density function, and the first voltage span and the second voltage span of the corresponding voltage interval are calculated. The first voltage span and the second voltage span are divided into voltage interval widths to generate a first non-equidistant division width set. Calculate the minimum width value of the first non-equidistant partition width set and compare it with a preset noise tolerance. Based on the comparison result, obtain the second non-equidistant partition width set. Obtain the boundary candidate value sequence of the second non-equidistant partition width set, construct a threshold voltage distribution curve based on the boundary candidate value sequence and extract the valley voltage between adjacent storage states, adjust the corresponding boundary candidate value based on the valley voltage, and generate the dynamic voltage boundary of the target flash memory; The storage state of the target flash memory is determined based on the dynamic voltage boundary to obtain discrete read data, thereby completing the threshold voltage adaptive calibration read of the target flash memory.

[0007] In a second aspect, the present invention provides an SLC NAND threshold voltage adaptive calibration system, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method described above.

[0008] Compared with the prior art, the present invention has the following beneficial effects: (1) This invention analyzes the voltage distribution density function of the target flash memory and calculates the distribution offset, then compares the distribution offset with a preset offset threshold to identify the change state of the threshold voltage distribution of the target flash memory. This method compares the degree of offset of the current threshold voltage distribution relative to the initial state with a preset offset threshold, so that the change of the current voltage distribution of the target flash memory can be quantitatively characterized, and generates a corresponding aging state identifier based on the comparison result, thereby providing a state judgment basis for the subsequent determination of regions with rapid density changes and regions with slow density changes, as well as the adjustment of dynamic voltage boundaries; (2) This invention extracts local density data corresponding to regions with rapid and slow density changes from the voltage distribution density function, and calculates the first and second voltage spans of the corresponding voltage intervals, thereby achieving non-equidistant division based on the characteristics of threshold voltage distribution changes. This technique establishes a correlation between the local variation characteristics of the threshold voltage distribution and the width of the voltage interval, enabling different density change regions to use matching division widths, effectively avoiding the problem in the prior art where the fixed equidistant division method leads to a mismatch between the division boundary and the actual characteristics of threshold voltage distribution changes; (3) This invention achieves anomaly detection and correction of voltage interval division width by calculating the minimum width value in the first set of non-equidistant division widths and comparing it with a preset noise tolerance. This method establishes a correlation between the non-equidistant division width and the noise tolerance, and uses the average value of the division widths of adjacent intervals to correct the abnormal division intervals, avoiding the problem of reading and judgment offset caused by noise fluctuations due to excessively small division widths, thereby improving the stability and anti-noise capability of the non-equidistant division results. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of an adaptive calibration method for SLC NAND threshold voltage provided in the first embodiment of the present invention. Detailed Implementation

[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0011] Reference Figure 1 The first embodiment of the present invention provides an adaptive calibration method for SLC NAND threshold voltage, comprising the following steps: S1, acquire the initial voltage data of the target flash memory, calculate the distribution offset of the target flash memory, compare the distribution offset with a preset offset threshold, and determine the region of rapid density change and region of slow density change of the distribution voltage of the target flash memory based on the comparison result. S2, extract the local density data corresponding to the rapidly changing density region and the slowly changing density region from the voltage distribution density function, and calculate the first voltage span and the second voltage span of the corresponding voltage interval. Divide the first voltage span and the second voltage span into the width of the voltage interval to generate a first non-equidistant division width set. S3, calculate the minimum width value of the first non-equidistant partition width set, compare it with the preset noise tolerance, and obtain the second non-equidistant partition width set based on the comparison result; S4, obtain the boundary candidate value sequence of the second non-equidistant partition width set, construct a threshold voltage distribution curve based on the boundary candidate value sequence and extract the valley voltage between adjacent storage states, adjust the corresponding boundary candidate value based on the valley voltage, and generate the dynamic voltage boundary of the target flash memory; S5, determine the storage state of the target flash memory based on the dynamic voltage boundary, obtain discrete read data, and complete the threshold voltage adaptive calibration read of the target flash memory.

[0012] In step S1, the initial voltage data of the target flash memory is acquired, and the distribution offset of the target flash memory is calculated. The distribution offset is compared with a preset offset threshold, and the regions of rapid density change and slow density change of the target flash memory distribution voltage are determined based on the comparison result. This includes: Acquire the initial voltage data of the target flash memory, preprocess the initial voltage data, and obtain the voltage distribution density function of the target flash memory; The distribution offset of the target flash memory is calculated based on the voltage distribution density function, and the distribution offset is compared with a preset offset threshold to obtain an aging status indicator. The probability density gradient is calculated based on the aging state identifier, and the probability density gradient is compared with a preset gradient threshold to determine the regions where the density of the target flash memory distribution voltage changes rapidly and the regions where the density changes slowly.

[0013] In one implementation, acquiring the initial voltage data of the target flash memory and preprocessing the initial voltage data to obtain the voltage distribution density function of the target flash memory includes: The target flash memory array is scanned line by line according to a preset read reference voltage sequence, and the response data of each memory cell under different read reference voltages is collected. The threshold voltage sampling result corresponding to each memory cell is determined based on the change of the response data to obtain the initial voltage data. Based on the preset kernel function bandwidth parameters, the weights of each voltage sampling point in the initial voltage data are calculated to obtain the corresponding probability density estimation results; The probability density estimation results are accumulated and a continuous voltage probability distribution curve is constructed to obtain the voltage distribution density function of the target flash memory.

[0014] In one implementation, this embodiment uses a voltage sensing circuit to scan the target flash memory array line by line to obtain response data corresponding to the memory cells, and determines initial voltage data based on the response data. Specifically, this embodiment first acquires the word line arrangement information of the target flash memory array and establishes a corresponding scan sequence based on the physical arrangement order of each word line in the target flash memory array. Then, each word line in the target flash memory array is sequentially selected according to the scan sequence, and multiple different read reference voltages are applied to the selected word lines. Under each read reference voltage, the conduction state or conduction current response of the corresponding memory cell is detected by a sensing amplifier, and the response results corresponding to different read reference voltages are recorded. As the read reference voltage gradually changes, when the read reference voltage crosses the threshold voltage of the memory cell, the conduction state or conduction current response of the memory cell changes. Therefore, based on the response changes corresponding to multiple read reference voltages, the threshold voltage sampling result corresponding to each memory cell is determined. The above read reference voltage scanning process is repeated for each memory cell in the target flash memory array to obtain initial voltage data containing the threshold voltage sampling results of multiple memory cells.

[0015] In one implementation, this embodiment calculates the weights of each voltage sampling point in the initial voltage data based on a preset kernel function bandwidth parameter to obtain the corresponding probability density estimation result. Specifically, this embodiment first obtains the voltage sampling points corresponding to all initial voltage data and determines the preset kernel function bandwidth parameter. Then, using each voltage sampling point as the kernel function center, the kernel function weights are calculated based on the distance between each voltage sampling point and the target voltage position. The weight contributions corresponding to all voltage sampling points are then accumulated to obtain the probability density estimation result corresponding to each voltage position.

[0016] Furthermore, the formula for calculating the probability density estimation result can be expressed as: ; in, Indicates voltage position The corresponding probability density estimation results; This indicates the number of sampling points in the initial voltage data; This represents the kernel function bandwidth parameter; Represents the kernel function; Indicates the first One voltage sampling point; Indicates the target voltage position and the first Voltage distance between voltage sampling points.

[0017] It should be noted that the kernel function bandwidth parameter is used to adjust the influence range of voltage sampling points during probability density estimation. Its determination is based on the number of samples of the initial voltage data of the target flash memory and the degree of dispersion of the voltage distribution. Specifically, firstly, the initial voltage data set corresponding to the target flash memory is obtained, and the standard deviation and number of samples for all voltage sampling points are calculated. Subsequently, a bandwidth calculation relationship is established based on the standard deviation and the number of samples to obtain the corresponding kernel function bandwidth parameter.

[0018] In one implementation, this embodiment accumulates the probability density estimation results and constructs a continuous voltage probability distribution curve to obtain the voltage distribution density function of the target flash memory. Specifically, this embodiment arranges the probability density estimation results corresponding to each voltage position continuously in ascending order of voltage values, and constructs a continuous voltage probability distribution curve based on the probability density estimation results corresponding to each voltage position, ultimately obtaining the voltage distribution density function corresponding to the target flash memory.

[0019] Furthermore, in this embodiment, the probability density estimation results corresponding to adjacent voltage positions are used as continuous connection nodes to continuously fit the probability density estimation results across the entire voltage range, forming a continuously changing probability density curve between adjacent voltage positions. Then, a voltage distribution density function corresponding to the target flash memory is generated based on the continuous voltage probability distribution curve. This voltage distribution density function continuously describes the probability distribution state of the threshold voltages of all memory cells in the target flash memory, providing a unified data foundation for subsequent calculation of the threshold voltage distribution offset.

[0020] It should be noted that the voltage distribution density function describes the probability density variation corresponding to each threshold voltage in the target flash memory. A larger function value indicates a greater number of memory cells clustered near the corresponding voltage position; a smaller function value indicates a smaller number of memory cells near the corresponding voltage position. Therefore, the voltage distribution density function can continuously reflect the overall distribution characteristics of the target flash memory's threshold voltages, avoiding the distortion of distribution characteristics caused by fixed bin widths in traditional histogram statistical methods. This provides reliable data support for subsequent threshold voltage distribution offset calculations, aging state determination, and dynamic voltage boundary generation.

[0021] For example, this embodiment uses a certain SLC NAND flash memory as the target flash memory for explanation. First, the voltage sensing circuit scans line by line according to the word line order of the target flash memory array, completing the scan of 1024 word lines. Multiple different read reference voltages are applied to each word line, and the conduction state or conduction current response of the corresponding memory cell under each read reference voltage is collected, resulting in multiple sets of response data corresponding to 131072 memory cells. Subsequently, in this embodiment, the response data corresponding to each memory cell are compared in ascending order of read reference voltage. When a change in read reference voltage causes a change in the conduction state or conduction current response of the memory cell, the read reference voltage with the changed response is used as the threshold voltage sampling result of the corresponding memory cell, thereby obtaining 131072 threshold voltage sampling points, and an initial voltage data set is constructed according to the memory cell address order. Subsequently, in this embodiment, based on the preset Gaussian kernel function bandwidth parameters, the kernel function weights are calculated for each voltage position within the entire threshold voltage range, using 131,072 threshold voltage sampling points as the kernel function centers. The weight values ​​generated by all sampling points at the same voltage position are then summed to obtain the corresponding probability density estimation results. For example, at a voltage value of 0.95V, the corresponding probability density estimation result is 0.186; at a voltage value of 1.08V, the corresponding probability density estimation result is 0.271. Then, in this embodiment, all probability density estimation results are continuously arranged in ascending order of voltage value, and a continuous threshold voltage probability distribution curve is constructed, ultimately obtaining the voltage distribution density function corresponding to the target flash memory.

[0022] In one implementation, the step of calculating the distribution offset of the target flash memory based on the voltage distribution density function, and comparing the distribution offset with a preset offset threshold to obtain an aging state identifier, includes: The voltage distribution density function is subjected to extreme value search to determine the peak position of the threshold voltage distribution corresponding to the target flash memory; Obtain the reference peak position corresponding to the initial state of the target flash memory, and calculate the difference between the peak position of the threshold voltage distribution and the reference peak position to obtain the distribution offset. The distribution offset is compared with the offset threshold, and the aging status identifier is obtained based on the comparison result.

[0023] In one implementation, this embodiment performs an extreme value search on the voltage distribution density function to determine the peak position of the threshold voltage distribution corresponding to the target flash memory. Specifically, this embodiment obtains the target flash memory voltage distribution density function generated in step S1. This voltage distribution density function characterizes the distribution of memory cells corresponding to each threshold voltage position in the target flash memory. Subsequently, based on the threshold voltage range corresponding to the erase and programmable states in the SLC NAND flash memory, the voltage distribution density function is divided into voltage intervals. The threshold voltage range corresponding to the programmable state is used as the programmable state peak search interval, and the density value corresponding to each voltage position within the programmable state peak search interval is obtained. The density values ​​corresponding to each voltage position within the programmable state peak search interval are compared, and the voltage position with the largest density value is taken as the peak position of the threshold voltage distribution in the current state of the target flash memory.

[0024] It should be noted that by limiting the search range of the programmed state peak, the problem of switching peak objects in different storage states caused by directly searching for the global maximum density value within the entire threshold voltage distribution range can be avoided. This ensures that the currently determined peak position always corresponds to the programmed state storage state of the SLC NAND flash memory, thereby guaranteeing that the peak position of the threshold voltage distribution and the subsequently obtained programmed state reference peak position belong to the same storage state, providing a unified peak position reference for the accurate calculation of the distribution offset.

[0025] In one implementation, to obtain the distribution offset, this embodiment acquires the initial voltage data corresponding to the unused state of the target flash memory, and establishes a reference voltage distribution density function in the initial state based on the initial voltage data. Subsequently, using the same peak search method as the current state, the reference voltage distribution density function is analyzed to obtain the voltage position with the largest threshold voltage distribution density in the initial state, and this position is used as the reference peak position corresponding to the target flash memory.

[0026] Furthermore, before the target flash memory is put into use, the target flash memory array is initialized using testing equipment, and the initial threshold voltage data corresponding to each memory cell is collected. Since the target flash memory has not undergone an erase / write cycle at this time, the charge distribution state in the memory cell is in a stable state. Therefore, the reference voltage distribution density function established based on the data collected at this stage can serve as the distribution benchmark for the initial state of the target flash memory. Subsequently, when the target flash memory is in actual operation, the current threshold voltage distribution peak position is compared with the benchmark peak position to obtain the distribution offset of the current voltage distribution relative to the initial state.

[0027] In one implementation, this embodiment compares the currently calculated distribution offset with a preset offset threshold. When the distribution offset is less than or equal to the preset offset threshold, it indicates that the current threshold voltage distribution change is within the allowable range, and a normal status indicator is output; when the distribution offset is greater than the preset offset threshold, it indicates that the current threshold voltage distribution change exceeds the preset allowable range, and an aging status indicator is output.

[0028] Furthermore, the preset offset threshold is determined in advance based on the historical threshold voltage distribution offset data of the same model SLC NAND under normal operating conditions, and stored in the controller to determine whether the current distribution offset exceeds the allowable range.

[0029] For example, this embodiment uses a certain SLC NAND flash memory as the target object for description. According to step S1, the voltage distribution density function of the target flash memory in its current state is obtained, and a peak search is performed on the voltage distribution density function based on a predetermined programming state threshold voltage range, resulting in a threshold voltage distribution peak position of 2.35V corresponding to the current programming state. Subsequently, initial voltage data collected by the target flash memory in its unused state is obtained, and the reference voltage distribution density function established based on the initial voltage data is analyzed using the same programming state peak search method as the current state, resulting in a reference peak position of 2.10V corresponding to the programming state in the initial state. By calculating the difference between the current programming state threshold voltage distribution peak position of 2.35V and the programming state reference peak position of 2.10V, the distribution offset of the target flash memory in its current state is obtained as 0.25V. Furthermore, a preset offset threshold of 0.18V is obtained, and the distribution offset of 0.25V is compared with the offset threshold of 0.18V. Since the distribution offset is greater than the offset threshold, an aging status indicator is output, indicating that the threshold voltage distribution corresponding to the current programming state of the target flash memory has shifted beyond the preset allowable range relative to the initial state. Further subsequent threshold voltage distribution analysis and adaptive calibration processing are required to improve the accuracy of read determination.

[0030] In one implementation, the step of calculating the probability density gradient based on the aging state identifier, comparing the probability density gradient with a preset gradient threshold, and determining the regions of rapid density change and slow density change of the target flash memory distributed voltage includes: The voltage distribution density function corresponding to the target flash memory is obtained based on the aging state identifier; The probability density gradient corresponding to each voltage position is obtained by performing difference calculation based on the density values ​​corresponding to adjacent voltage positions in the voltage distribution density function. The probability density gradient is compared with a preset gradient threshold, and the regions of rapid density change and slow density change of the target flash memory distributed voltage are determined based on the comparison results.

[0031] In one implementation, to determine the probability density gradient, this embodiment discretizes the voltage distribution density function in ascending order of voltage values, dividing the continuous voltage range into multiple adjacent voltage positions and obtaining the probability density value corresponding to each voltage position. Subsequently, the difference between the probability density values ​​corresponding to two adjacent voltage positions is calculated sequentially, and the ratio of this difference to the voltage interval between the corresponding two voltage positions is calculated to obtain the probability density gradient of the corresponding voltage position. By traversing adjacent voltage positions in the voltage distribution density function, the probability density gradient corresponding to each voltage position is obtained, thereby characterizing the degree of local variation of the probability density with voltage change.

[0032] Furthermore, for a voltage position located at the junction of two adjacent differential intervals, this embodiment obtains the probability density gradients corresponding to the two differential intervals before and after the voltage position, calculates the average of the two probability density gradients, and uses the average as the probability density gradient corresponding to the voltage position, so that each voltage position in the voltage distribution density function has a corresponding probability density gradient value. For a boundary voltage position located at the start or end of the analyzed voltage range, the probability density gradient corresponding to the adjacent differential interval is used as the probability density gradient corresponding to the boundary voltage position.

[0033] It should be noted that the probability density gradient is used to characterize the degree of change in voltage distribution density along the voltage direction. When the probability density difference between adjacent voltage positions is large, the corresponding absolute value of the probability density gradient is large, indicating that the voltage distribution density near that position changes rapidly; when the probability density difference between adjacent voltage positions is small, the corresponding absolute value of the probability density gradient is small, indicating that the voltage distribution density near that position changes slowly. By obtaining the probability density gradients corresponding to different voltage positions, the rate of change of the target flash memory threshold voltage distribution at different voltage positions can be quantitatively characterized, and a data basis can be provided for subsequently comparing the probability density gradient with a preset gradient threshold to determine regions of rapid density change and regions of slow density change.

[0034] In one implementation, the target flash memory's distributed voltage is identified as having rapidly changing density regions and slowly changing density regions. This embodiment compares the probability density gradient with a preset gradient threshold, and divides the target flash memory threshold voltage distribution region according to the degree of density change in different regions.

[0035] Furthermore, when the probability density gradient within a certain voltage region is greater than the gradient threshold, it indicates that the distribution of memory cells in that region changes rapidly, and that region is defined as a region with rapidly changing voltage distribution density; when the probability density gradient within a certain voltage region is less than or equal to the gradient threshold, it indicates that the distribution of memory cells in that region changes slowly, and that region is defined as a region with slowly changing voltage distribution density.

[0036] It should be noted that the gradient threshold is predetermined based on the historical operating data of the target flash memory and the variation pattern of the threshold voltage distribution. Specifically, by collecting threshold voltage distribution data of the target flash memory under different erase / write cycles, the density variation range of different voltage regions under normal operating conditions is analyzed, and a gradient threshold is set based on the variation range to distinguish between regions with rapid density changes and regions with slow density changes.

[0037] For example, this embodiment uses a certain SLC NAND flash memory as the target flash memory for explanation. First, a voltage distribution density function is obtained based on the current aging state identifier of the target flash memory. The voltage distribution density function includes multiple voltage positions arranged in ascending order of voltage value and their corresponding probability density values. Then, according to the arrangement order of adjacent voltage positions, the probability density values ​​corresponding to two adjacent voltage positions are obtained sequentially, and the difference between adjacent probability density values ​​is calculated to obtain the probability density gradient corresponding to each voltage position. For example, the probability density values ​​corresponding to voltage positions of 0.95V, 0.96V, and 0.97V are 0.186, 0.214, and 0.258, respectively. The corresponding probability density gradient is obtained based on the difference in density values ​​between adjacent positions. Then, the probability density gradient corresponding to each voltage position is compared with a preset gradient threshold. When the absolute value of the probability density gradient in a certain continuous voltage region is greater than the gradient threshold, the region is determined as a region of rapid density change; when the absolute value of the probability density gradient is less than or equal to the gradient threshold, the corresponding region is determined as a region of slow density change. This completes the division of the target flash memory threshold voltage distribution area, providing a basis for subsequent non-equidistant division based on the voltage distribution characteristics of different areas.

[0038] In step S2, the step of extracting local density data corresponding to the rapidly changing density region and the slowly changing density region from the voltage distribution density function, calculating the first voltage span and the second voltage span of the corresponding voltage interval, and dividing the first voltage span and the second voltage span into voltage interval widths to generate a first non-equidistant division width set includes: Extract local density data corresponding to regions with rapid density changes, and calculate the first-order trend value based on the local density data; Calculate the local extreme points in the region of rapid density change based on the first-order trend value, and calculate the first voltage span between adjacent local extreme points; Based on the probability density gradient corresponding to the region of slowly changing density, the continuous voltage positions of the region of slowly changing density are extracted, and the start and end positions of the continuous voltage positions are respectively used as the left boundary position and the right boundary position. The local density values ​​corresponding to the left and right boundary positions are obtained from the voltage distribution density function, and the density attenuation rate is calculated based on the left and right boundary positions and the corresponding local density values. The second voltage span of the region where the density changes slowly is calculated based on the density decay rate and a preset compensation coefficient. The voltage range is divided into widths based on the first voltage span and the second voltage span to generate a first non-equidistant width set.

[0039] In one implementation, this embodiment extracts local density data corresponding to regions of rapid density change and calculates a first-order trend value based on the local density data. Specifically, this embodiment obtains the voltage range corresponding to the rapidly changing voltage distribution density region determined in step S1, and extracts the density data corresponding to that voltage range from the voltage distribution density function obtained in step S1 to obtain the local density data corresponding to the rapidly changing density region.

[0040] Furthermore, the formula for calculating the first-order trend value can be expressed as: ; in, Indicates the first The first-order trend value of the probability density within a voltage range; This represents the change in probability density between adjacent voltage locations; This indicates the voltage interval between adjacent voltage sampling points.

[0041] It should be noted that in this embodiment, the voltage positions in the local voltage distribution density function are traversed in ascending order of voltage, and the density value changes corresponding to adjacent voltage positions are compared to obtain a first-order trend value reflecting the degree of voltage distribution density change in areas of rapid density change. This first-order trend value describes the rate at which the voltage distribution density changes with voltage. A larger value indicates a more significant density change and stronger distribution variation characteristics within the corresponding area; a smaller value indicates a more gradual density change within the corresponding area.

[0042] In one implementation, this embodiment calculates local extrema within the rapidly changing density region based on the first-order trend value, and calculates the first voltage span between adjacent local extrema. Specifically, this embodiment analyzes the voltage distribution density changes within the rapidly changing density region based on the first-order trend value, identifies locations where the density change changes from an increasing trend to a decreasing trend as candidate local extrema, and filters these candidate locations based on the density values ​​corresponding to those locations to obtain the corresponding local extrema within the rapidly changing density region.

[0043] Furthermore, in this embodiment, the voltage positions corresponding to adjacent local extreme points are obtained, and the voltage interval between adjacent local extreme points is calculated. The voltage interval is used as the first voltage span corresponding to the region of rapid density change.

[0044] It should be noted that the first voltage span is used to reflect the actual distribution range between different voltage cluster locations within a region of rapid density change. Since the number of memory cells is concentrated within a region of rapid density change, the threshold voltage distribution changes more significantly. Therefore, determining the division range of this region by the voltage span between local extreme points allows subsequent boundary settings to better reflect the actual voltage distribution.

[0045] In one implementation, this embodiment extracts continuous voltage positions within the slowly changing density region based on the probability density gradient corresponding to that region, and designates the start and end positions of these continuous voltage positions as the left and right boundary positions, respectively. Specifically, this embodiment obtains the probability density gradient corresponding to each voltage position within the slowly changing density region in ascending order of voltage value, compares the probability density gradient with a preset gradient threshold, and continuously associates adjacent voltage positions that satisfy the criteria for determining a slowly changing density region to obtain a set of continuous voltage positions.

[0046] Furthermore, in this embodiment, the set of continuous voltage positions is arranged in ascending order of voltage value, and the minimum voltage position and the maximum voltage position in the set of continuous voltage positions are obtained. The minimum voltage position is taken as the left boundary position of the region with slowly changing density, and the maximum voltage position is taken as the right boundary position of the region with slowly changing density.

[0047] It should be noted that the gradient threshold is obtained by performing differential calculations on the historical voltage distribution density functions under multiple normal operating conditions to obtain the corresponding historical probability density gradients, and statistically analyzing the range of values ​​of the historical probability density gradients. The statistical value that characterizes the degree of change in voltage distribution density under normal conditions is used as the gradient threshold.

[0048] In one implementation, regarding the determination of the density decay rate, this embodiment uses the left boundary position and the right boundary position as the starting voltage position and the ending voltage position of the slowly changing density region, respectively. The probability density values ​​corresponding to the starting voltage position and the ending voltage position are read from the voltage distribution density function to obtain the local density values ​​at the left and right boundaries, respectively. Subsequently, the density difference between the local density values ​​at the left and right boundaries is calculated, and the voltage span between the left and right boundary positions is obtained. The density decay rate corresponding to the slowly changing density region is then calculated based on the density difference and the voltage span.

[0049] It should be noted that the local density values ​​at the left and right boundaries are both derived from the voltage distribution density function of the target flash memory. The density decay rate is used to describe the degree of change of the probability density values ​​at both ends of the slowly changing density region within the corresponding voltage span. Its calculation results are consistent with the voltage distribution density function, providing a basis for calculating the second voltage span based on the degree of density change in the slowly changing density region.

[0050] In one implementation, this embodiment calculates the second voltage span of the slowly changing density region based on the density decay rate and a preset compensation coefficient. Specifically, this embodiment obtains the density decay rate corresponding to the slowly changing density region, where the density decay rate characterizes the probability density change degree corresponding to a unit voltage change. Then, a preset compensation coefficient is obtained, and the compensation coefficient is divided by the density decay rate to obtain the second voltage span corresponding to the slowly changing density region; that is, the second voltage span is equal to the compensation coefficient divided by the density decay rate.

[0051] Furthermore, the compensation coefficient is predetermined based on the historical operating data of the target flash memory and the expansion of the threshold voltage distribution under different erase / write cycles. It is used to correct the impact of voltage distribution changes in slowly changing density regions on the partition width under different aging degrees. As the aging degree of the target flash memory increases, the threshold voltage distribution expands to both sides, and the compensation coefficient allows the second voltage span to be adjusted according to the actual distribution changes.

[0052] It should be noted that the compensation coefficient is used to convert the density attenuation level into a corresponding voltage range. The compensation coefficient is dimensionless, and the second voltage span obtained by dividing the compensation coefficient by the density attenuation rate has a voltage unit V.

[0053] In one implementation, this embodiment performs a voltage range width division operation based on the first voltage span and the second voltage span to generate a first non-equidistant division width set. Specifically, this embodiment divides the overall threshold voltage range of the target flash memory into partitions based on the first voltage span corresponding to the rapidly changing density region and the second voltage span corresponding to the slowly changing density region. Specifically, for regions with rapidly changing voltage distribution density, a finer division width is set based on the smaller first voltage span; for regions with slowly changing voltage distribution density, a wider division width is set based on the larger second voltage span.

[0054] Furthermore, in this embodiment, the partition widths corresponding to different regions are combined according to the order of the target flash memory threshold voltage distribution regions to obtain a first non-equidistant partition width set containing multiple different width parameters.

[0055] It should be noted that the first non-equidistant division width set is generated based on the actual threshold voltage distribution characteristics of the target flash memory. Compared with the fixed equidistant division method used in the prior art, this embodiment can make the read judgment boundary more refined in the region of rapid density change and more relaxed in the region of slow density change, thereby improving the matching degree between the threshold voltage division and the actual storage state distribution.

[0056] For example, this embodiment uses a certain SLC NAND flash memory as the target object for description. According to step S1, the target flash memory threshold voltage distribution is determined to have a rapidly changing density region and a slowly changing density region, where the rapidly changing density region corresponds to a voltage range of 1.8V to 2.4V, and the slowly changing density region corresponds to a voltage range of 2.4V to 2.9V. First, the voltage distribution density function corresponding to the rapidly changing density region is obtained, and local extreme points are extracted according to the probability density gradient, resulting in a first voltage span of 0.12V between adjacent local extreme points. Subsequently, the left and right boundary positions corresponding to the slowly changing density region and the local density values ​​corresponding to the left and right boundary positions are obtained from the voltage distribution density function. The density decay rate is calculated as 0.20 / V based on the voltage difference between the left and right boundary positions and the difference between the corresponding local density values, and a preset compensation coefficient of 0.07 is obtained. The compensation coefficient is divided by the density decay rate to obtain a second voltage span of 0.35V corresponding to the slowly changing density region. Furthermore, based on the first voltage span and the second voltage span, the width of different voltage regions is divided to obtain a first non-equidistant division width set, so that regions with rapid density changes adopt a smaller division width and regions with slow density changes adopt a larger division width, thereby enabling the generated non-equidistant division method to adapt to the changing characteristics of the actual threshold voltage distribution of the target flash memory.

[0057] In step S3, calculating the minimum width value of the first non-equidistant partition width set and comparing it with a preset noise tolerance, and obtaining the second non-equidistant partition width set based on the comparison result, includes: Obtain each division width value in the first non-equidistant division width set, calculate the minimum width value of each division width value, and compare it with a preset noise tolerance; When the minimum width value is less than the noise tolerance, the corresponding voltage range is determined to be an abnormal division range; otherwise, the first non-equidistant division width set is used as the second non-equidistant division width set. Obtain the partition width of adjacent intervals of the abnormal partition interval, and calculate the average partition width of the adjacent intervals; The average of the segmentation widths is used as the corrected segmentation width for the abnormal segmentation intervals, and the segmentation widths corresponding to the abnormal segmentation intervals in the first set of non-equidistant segmentation widths are replaced to obtain the second set of non-equidistant segmentation widths.

[0058] In one implementation, this embodiment obtains each partition width value in the first non-equidistant partition width set, calculates the minimum width value of each partition width value, and compares it with a preset noise tolerance. Specifically, this embodiment obtains the first non-equidistant partition width set generated in step S2, which includes multiple partition width values ​​corresponding to different threshold voltage regions of the target flash memory. Subsequently, all partition width values ​​in the first non-equidistant partition width set are traversed, and the minimum width value is selected from the multiple partition width values.

[0059] Furthermore, this embodiment obtains a preset noise margin, which characterizes the minimum voltage partitioning interval that can be tolerated during the target flash memory read process. The noise margin is predetermined based on the target flash memory read noise level, the storage cell voltage fluctuation range, and historical read error data. Subsequently, the minimum width value is compared with the noise margin to determine whether the current non-equidistant partitioning result has a problem of decreased read reliability due to an excessively small partitioning width.

[0060] It should be noted that when the partition width is less than the noise tolerance, it means that the voltage interval between adjacent read judgment areas is too small. When the storage cell is affected by factors such as charge fluctuations and read noise, it is easy to cross the adjacent judgment boundary, resulting in read errors. Therefore, further width adjustment is required.

[0061] In one implementation, regarding the determination of the second non-equidistant division width set, when the minimum width value is less than the noise tolerance, this embodiment determines the voltage interval corresponding to the minimum width value based on the voltage position corresponding to each width value in the first non-equidistant division width set, and marks the voltage interval as an abnormal division interval.

[0062] Furthermore, when the minimum width value is greater than or equal to the noise tolerance, it means that each partition width in the current first non-equidistant partition width set meets the noise tolerance requirement, and the reading judgment will not be unstable due to the boundary interval being too small. Therefore, the first non-equidistant partition width set is directly used as the second non-equidistant partition width set.

[0063] In one implementation, this embodiment obtains the partition width of adjacent partitions of the abnormal partition interval and calculates the average partition width of the adjacent partitions. Specifically, this embodiment determines the preceding and following partitions adjacent to the abnormal partition interval based on the voltage position corresponding to the abnormal partition interval, and obtains the partition width values ​​corresponding to the preceding and following partitions respectively; then, the partition width values ​​corresponding to the preceding and following partitions are summed and divided by the number of adjacent partitions (2) to obtain the average partition width of the adjacent partitions.

[0064] Furthermore, the average partition width is used to determine the corrected partition width of the abnormal partition interval. When the original partition width of the abnormal partition interval is less than the preset noise tolerance, it indicates that the voltage interval of the abnormal partition interval is too small, making it susceptible to fluctuations in the memory cell threshold voltage and read noise, leading to misjudgment of the status. Therefore, this embodiment uses the average partition width of the adjacent voltage intervals on both sides of the abnormal partition interval as a correction reference for the abnormal partition interval, adjusting the partition width of the abnormal partition interval towards the normal partition width of its adjacent areas, thereby avoiding the problem of unstable read boundaries caused by excessively small partition widths in local areas.

[0065] In one implementation, this embodiment uses the average division width as the corrected division width for the abnormal division interval, replacing the division width corresponding to the abnormal division interval in the first set of non-equidistant division widths, to obtain a second set of non-equidistant division widths. Specifically, this embodiment obtains the position of the abnormal division interval in the first set of non-equidistant division widths and replaces the original division width corresponding to that position with the average division width, ensuring that the division width of the abnormal division interval changes continuously with the division widths of its adjacent intervals. Subsequently, according to the original arrangement order of the division widths in the first set of non-equidistant division widths, the replaced division widths are rearranged to obtain the second set of non-equidistant division widths.

[0066] It should be noted that the second set of non-equidistant partition widths only corrects abnormal partition widths that are smaller than the noise tolerance. Partition widths that are not judged as abnormal retain their original partition results. In this way, while preserving the overall non-equidistant partition characteristics of the first set of non-equidistant partition widths, the problem of reading judgment being easily affected by noise fluctuations due to excessively small local partition widths is avoided.

[0067] For example, this embodiment uses a certain SLC NAND flash memory as the target object for description. According to step S2, a first non-equidistant partition width set is generated, which contains partition width values ​​corresponding to multiple voltage regions. The minimum partition width in the set is calculated to be 0.015V. Then, the noise tolerance corresponding to the current read noise level of the target flash memory is obtained as 0.02V. Since the minimum partition width is less than the noise tolerance, the corresponding voltage interval is determined as an abnormal partition interval. Further, the partition widths of the adjacent intervals before and after the abnormal partition interval are obtained, which are 0.028V and 0.030V, respectively, and the average partition width of the two is calculated to be 0.029V. Then, the average partition width of 0.029V is used as the corrected partition width of the abnormal partition interval, and the original partition width of 0.015V in the first non-equidistant partition width set is replaced with 0.029V to obtain a second non-equidistant partition width set. Through the above processing, the voltage interval of the abnormal division range is adjusted from 0.015V to 0.029V to meet the noise tolerance requirements. At the same time, the non-equidistant characteristics of the division width of different voltage regions are maintained, thereby reducing the possibility of misjudgment of status caused by reading noise due to excessively fine local division.

[0068] In step S4, obtaining the boundary candidate value sequence of the second non-equidistant width division set, constructing a threshold voltage distribution curve based on the boundary candidate value sequence and extracting the valley voltage between adjacent storage states, adjusting the corresponding boundary candidate values ​​based on the valley voltage, and generating the dynamic voltage boundary of the target flash memory includes: Obtain the voltage division width from the second non-equidistant division width set, and accumulate the voltage division width in combination with the preset reading start voltage to obtain the boundary candidate value sequence; A read voltage is applied to the target flash memory according to the boundary candidate value sequence, and the corresponding memory cell response data is collected; A threshold voltage distribution curve is constructed based on the memory cell response data, and the valley voltage between adjacent memory states is extracted based on the threshold voltage distribution curve. The dynamic voltage boundary of the target flash memory is generated by adjusting the corresponding boundary candidate value according to the valley voltage.

[0069] In one implementation, for the boundary candidate value sequence, this embodiment obtains a second non-equidistant partition width set obtained in step S3. The second non-equidistant partition width set includes multiple voltage partition width values ​​adjusted according to the current threshold voltage distribution characteristics of the target flash memory. Subsequently, the read start voltage corresponding to the read range of the target flash memory is obtained, and the read start voltage is used as the starting point for boundary calculation. Then, each partition width value is accumulated and calculated sequentially in order of threshold voltage from low to high.

[0070] Furthermore, in each cumulative calculation process, the previous boundary position is added to the current voltage division width to obtain the corresponding boundary candidate position. After traversing all the division width values ​​in the second non-equidistant division width set, a boundary candidate value sequence composed of multiple candidate boundary positions is formed.

[0071] In one implementation, this embodiment applies a read voltage to the target flash memory based on the boundary candidate value sequence and collects the corresponding memory cell response data. Specifically, this embodiment sequentially loads each candidate voltage value in the boundary candidate value sequence to the read voltage terminal of the corresponding word line of the target flash memory and performs a read operation on the memory cell. Since the threshold voltages of different memory cells differ, the memory cells will produce corresponding conduction state changes when different read voltages are applied.

[0072] Furthermore, in this embodiment, the response signals generated by the memory cells under different read voltage conditions are acquired by the flash memory sensing amplifier circuit. The response signals include information on the change in the number of memory cells turned on or the corresponding current response information, and a correspondence between the read voltage and the memory cell response is established based on the response results under different read voltages.

[0073] It should be noted that by actually reading and verifying the candidate boundary voltage, the response characteristics of the current target flash memory under actual working conditions can be obtained, avoiding the problem of inconsistent boundary positions with actual storage state distribution caused by relying solely on theoretical width calculation.

[0074] In one implementation, to determine the valley voltage, the specific operation is as follows: based on the memory cell response data collected under different read voltages, the number distribution of memory cells corresponding to each read voltage position is statistically analyzed to obtain threshold voltage distribution data under the current target flash memory state. Subsequently, a continuous threshold voltage distribution curve is constructed based on the threshold voltage distribution data.

[0075] Furthermore, in this embodiment, the threshold voltage distribution curve is analyzed to obtain the lowest density position between the distribution peaks corresponding to adjacent storage states, and the voltage value corresponding to the lowest density position is taken as the valley voltage between adjacent storage states.

[0076] In one implementation, the determination of the dynamic voltage boundary specifically involves the following steps: Based on the threshold voltage distribution curve obtained in step S4, this embodiment determines the two memory state distributions corresponding to the erase and program states in the target flash memory. Then, it searches for the valley position with the lowest probability density between the two memory state distributions and determines the voltage value corresponding to the valley position as the valley voltage between the two memory states. Subsequently, the valley voltage is compared with the boundary candidate values ​​generated based on the second non-equidistant partition width set to determine the boundary candidate value corresponding to the valley voltage. The valley voltage is then used as a correction value for this boundary candidate value to obtain the dynamic voltage boundary corresponding to the target flash memory.

[0077] Furthermore, this embodiment determines a dynamic voltage boundary only for the two storage states of SLC NAND flash memory: erase and program. Specifically, a boundary candidate value corresponding to the valley voltage is determined from multiple boundary candidate values, and the valley voltage is used to replace the boundary candidate value to obtain a unique dynamic voltage boundary. The dynamic voltage boundary is used to perform binary storage state determination for the erase and program states. It should be noted that the multiple boundary candidate values ​​are used to apply different read voltages to the target flash memory and collect storage cell response data to obtain sampling information for reconstructing the threshold voltage distribution curve, and do not correspond to multiple final storage state determination boundaries. Since SLC NAND flash memory only has two stable storage states, erase and program, this embodiment determines a unique dynamic voltage boundary based on the valley voltage between the two storage state distributions, so that the final read determination boundary can be adjusted according to the offset and widening of the actual threshold voltage distribution of the target flash memory, thereby improving the matching degree between the read determination boundary and the actual threshold voltage distribution and reducing state misjudgment caused by a fixed read boundary.

[0078] This embodiment uses a specific SLC NAND flash memory as the target object for illustration. Based on the second non-equidistant partition width set obtained in step S3, which contains multiple corrected voltage partition width values, the target flash memory read start voltage is set to 1.0V. These partition width values ​​are then sequentially accumulated to obtain a sequence of boundary candidate values: 1.18V, 1.35V, 1.62V, and 1.90V. Subsequently, the candidate read voltages corresponding to the boundary candidate values ​​are sequentially applied to the word lines of the target flash memory, and the response data of the corresponding memory cells under each candidate read voltage is collected. Based on the response data, the threshold voltage distribution curve of the target flash memory is reconstructed. By analyzing the threshold voltage distribution curve, two memory state distributions corresponding to the erase and program states of the target flash memory are determined, and the valley voltage between the two memory state distributions is extracted as 1.38V. Subsequently, the valley voltage of 1.38V is compared with the boundary candidate value sequence to determine that the boundary candidate value adjacent to the valley voltage is 1.35V. Based on the valley voltage, the corresponding boundary candidate value of 1.35V is adjusted to 1.38V, ultimately generating a dynamic voltage boundary of 1.38V. Through this process, multiple candidate read voltages are used to scan and reconstruct the threshold voltage distribution of the target flash memory. Finally, a unique dynamic voltage boundary is determined based on the actual valley position between the erase and program states of the SLC NAND flash memory. This allows the read boundary to adaptively calibrate following changes in the threshold voltage distribution, improving the data read accuracy of the SLC NAND flash memory.

[0079] In step S5, determining the storage state of the target flash memory based on the dynamic voltage boundary to obtain discrete read data and complete the threshold voltage adaptive calibration read of the target flash memory includes: The dynamic voltage boundary is used as the read reference voltage of the target flash memory to read data from the target flash memory and obtain the memory cell response data. The storage state is determined based on the storage unit response data and the dynamic voltage boundary to obtain the corresponding read state, and logic level data is generated based on the read state. Based on the logic level data, the stored data of the target flash memory is recovered to obtain discrete read data, and the threshold voltage adaptive calibration read of the target flash memory is completed.

[0080] In one implementation, this embodiment uses the dynamic voltage boundary as the read reference voltage for the target flash memory to read data from the target flash memory and obtain the memory cell response data. Specifically, this embodiment obtains the unique dynamic voltage boundary generated in step S4 and loads the dynamic voltage boundary into the read circuit of the memory array corresponding to the target flash memory, using the dynamic voltage boundary as the read reference voltage to perform read operations on the memory cells.

[0081] Furthermore, when the read reference voltage is applied, the memory cell generates a corresponding conduction state based on the relationship between its own threshold voltage and the read reference voltage. The inductive amplifier circuit acquires the corresponding response signal of the memory cell to obtain memory cell response data. The memory cell response data characterizes the actual response result of the memory cell under the read reference voltage.

[0082] It should be noted that, unlike the existing technology which uses a fixed read voltage for state determination, this embodiment uses a dynamic voltage boundary calibrated with a threshold voltage distribution as a read reference. This allows the read process to adapt to the threshold voltage offset and distribution changes caused by factors such as erase / write cycles and charge leakage in the target flash memory, thereby improving the matching degree between the read reference voltage and the actual storage state distribution.

[0083] In one implementation, the generation of the logic level data specifically involves obtaining the threshold voltage determination result corresponding to each memory cell based on the memory cell response data, and then performing interval matching between the determination result and the dynamic voltage boundary. Specifically, two state intervals are divided using a unique dynamic voltage boundary, and the response result corresponding to each memory cell is mapped to the corresponding voltage determination interval.

[0084] Further, the corresponding storage state is determined based on the voltage determination range of the storage cell, and the storage state is converted into corresponding logic level data according to the pre-set state mapping relationship within the target flash memory. The state mapping relationship describes the correspondence between the threshold voltage determination result and the logic level. This state mapping relationship is pre-determined based on the storage structure of the SLC NAND flash memory. When the threshold voltage of the storage cell is lower than the corresponding dynamic voltage boundary, it is mapped to a first logic state; when the threshold voltage of the storage cell is higher than the corresponding dynamic voltage boundary, it is mapped to a second logic state.

[0085] It should be noted that the state mapping relationship includes the correspondence between different threshold voltage determination intervals of the storage cell and logic level data. Since SLC NAND flash memory uses a single-bit storage method, each storage cell corresponds to only two stable storage states. Therefore, in this embodiment, the state of the storage cell is determined according to the dynamic voltage boundary division result, and the corresponding storage state is converted into logic "0" or logic "1" according to the state mapping relationship to obtain logic level data.

[0086] In one implementation, this embodiment recovers the stored data of the target flash memory based on the logic level data to obtain discrete read data, thereby completing the threshold voltage adaptive calibration read of the target flash memory. Specifically, this embodiment obtains the logic level data corresponding to the storage unit, and arranges and combines the logic level data according to the data encoding rules of the target flash memory to restore the original storage state of the corresponding storage unit.

[0087] Furthermore, the logic level data corresponding to multiple storage cells are reorganized according to the target flash memory page structure to obtain discrete read data corresponding to the current read result of the target flash memory. Subsequently, the threshold voltage adaptive calibration read process of the target flash memory is completed so that the obtained discrete read data can reflect the current true storage state of the target flash memory.

[0088] In summary, this invention discloses an adaptive calibration method for SLC NAND threshold voltage. By constructing a target flash memory threshold voltage distribution density function, combined with distribution offset calculation, aging state identification, probability density gradient analysis, and non-equidistant partition width generation, it achieves adaptive perception of threshold voltage distribution characteristics. Furthermore, by generating dynamic voltage boundaries through noise tolerance constraints and valley voltage calibration, it realizes dynamic adjustment of the read judgment boundary. This effectively solves the problem in existing technologies where fixed quantization partitioning methods cannot adapt to changes in threshold voltage distribution, leading to reduced read accuracy and decreased storage reliability, thus improving the read accuracy and storage reliability of SLC NAND flash memory.

[0089] A second embodiment of the present invention provides an SLC NAND threshold voltage adaptive calibration system, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method described above.

[0090] It should be noted that the SLC NAND threshold voltage adaptive calibration system provided in this embodiment of the invention is used to execute all the process steps of the SLC NAND threshold voltage adaptive calibration method in the above embodiment. The working principle and beneficial effects of the two are one-to-one, so they will not be described again.

[0091] It should be noted that the system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0092] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. An adaptive calibration method for SLC NAND threshold voltage, characterized in that, include: The initial voltage data of the target flash memory is acquired, and the initial voltage data is preprocessed to obtain the voltage distribution density function of the target flash memory. The distribution offset of the target flash memory is calculated based on the voltage distribution density function, and the distribution offset is compared with a preset offset threshold to obtain an aging state identifier. The probability density gradient is calculated based on the aging state identifier, and the probability density gradient is compared with a preset gradient threshold to determine the regions where the density of the distributed voltage of the target flash memory changes rapidly and regions where the density changes slowly. Local density data corresponding to the rapidly changing density region and the slowly changing density region are extracted from the voltage distribution density function, and the first voltage span and the second voltage span of the corresponding voltage interval are calculated. The first voltage span and the second voltage span are divided into voltage interval widths to generate a first non-equidistant division width set. Calculate the minimum width value of the first non-equidistant partition width set and compare it with a preset noise tolerance. Based on the comparison result, obtain the second non-equidistant partition width set. Obtain the boundary candidate value sequence of the second non-equidistant partition width set, construct a threshold voltage distribution curve based on the boundary candidate value sequence and extract the valley voltage between adjacent storage states, adjust the corresponding boundary candidate value based on the valley voltage, and generate the dynamic voltage boundary of the target flash memory; The storage state of the target flash memory is determined based on the dynamic voltage boundary to obtain discrete read data, thereby completing the threshold voltage adaptive calibration read of the target flash memory.

2. The SLC NAND threshold voltage adaptive calibration method according to claim 1, characterized in that, The process of acquiring the initial voltage data of the target flash memory and preprocessing the initial voltage data to obtain the voltage distribution density function of the target flash memory includes: The target flash memory array is scanned line by line according to a preset read reference voltage sequence, and the response data of each memory cell under different read reference voltages is collected. The threshold voltage sampling result corresponding to each memory cell is determined based on the change of the response data to obtain the initial voltage data. Based on the preset kernel function bandwidth parameters, the weights of each voltage sampling point in the initial voltage data are calculated to obtain the corresponding probability density estimation results; The probability density estimation results are accumulated and a continuous voltage probability distribution curve is constructed to obtain the voltage distribution density function of the target flash memory.

3. The SLC NAND threshold voltage adaptive calibration method according to claim 1, characterized in that, The step of calculating the distribution offset of the target flash memory based on the voltage distribution density function, comparing the distribution offset with a preset offset threshold, and obtaining an aging status indicator includes: The voltage distribution density function is subjected to extreme value search to determine the peak position of the threshold voltage distribution corresponding to the target flash memory; Obtain the reference peak position corresponding to the initial state of the target flash memory, and calculate the difference between the peak position of the threshold voltage distribution and the reference peak position to obtain the distribution offset. The distribution offset is compared with a preset offset threshold, and the aging status identifier is obtained based on the comparison result.

4. The SLC NAND threshold voltage adaptive calibration method according to claim 1, characterized in that, The step of calculating the probability density gradient based on the aging state identifier, comparing the probability density gradient with a preset gradient threshold, and determining the regions of rapid density change and slow density change of the target flash memory distributed voltage includes: The analysis range of the voltage distribution density function is determined based on the aging state identifier to obtain the density data to be analyzed. The probability density gradient corresponding to each voltage position is obtained by performing differential calculation based on the density values ​​corresponding to adjacent voltage positions in the density data to be analyzed. The probability density gradient is compared with a preset gradient threshold, and the regions of rapid density change and slow density change of the target flash memory distributed voltage are determined based on the comparison results.

5. The SLC NAND threshold voltage adaptive calibration method according to claim 1, characterized in that, The process involves extracting local density data corresponding to the rapidly changing density region and the slowly changing density region from the voltage distribution density function, calculating the first voltage span and the second voltage span of the corresponding voltage interval, dividing the voltage interval width by the first voltage span and the second voltage span, and generating a first non-equidistant division width set, including: Extract local density data corresponding to regions with rapid density changes, and calculate the first-order trend value based on the local density data; Calculate the local extreme points in the region of rapid density change based on the first-order trend value, and calculate the first voltage span between adjacent local extreme points; Based on the probability density gradient corresponding to the region of slowly changing density, the continuous voltage positions of the region of slowly changing density are extracted, and the start and end positions of the continuous voltage positions are respectively used as the left boundary position and the right boundary position. The local density values ​​corresponding to the left and right boundary positions are obtained from the voltage distribution density function, and the density attenuation rate is calculated based on the left and right boundary positions and the corresponding local density values. The second voltage span of the region where the density changes slowly is calculated based on the density decay rate and a preset compensation coefficient. The voltage range is divided into widths based on the first voltage span and the second voltage span to generate a first non-equidistant width set.

6. The SLC NAND threshold voltage adaptive calibration method according to claim 1, characterized in that, The step of calculating the minimum width value of the first non-equidistant partition width set and comparing it with a preset noise tolerance, and obtaining the second non-equidistant partition width set based on the comparison result, includes: Obtain each division width value in the first non-equidistant division width set, calculate the minimum width value of each division width value, and compare it with a preset noise tolerance; When the minimum width value is less than the noise tolerance, the corresponding voltage range is determined to be an abnormal division range; otherwise, the first non-equidistant division width set is used as the second non-equidistant division width set. Obtain the partition width of adjacent intervals of the abnormal partition interval, and calculate the average partition width of the adjacent intervals; The average of the segmentation widths is used as the corrected segmentation widths for the abnormal segmentation intervals, and the segmentation widths corresponding to the abnormal segmentation intervals in the first set of non-equidistant segmentation widths are replaced to obtain the second set of non-equidistant segmentation widths.

7. The SLC NAND threshold voltage adaptive calibration method according to claim 1, characterized in that, The step of obtaining the boundary candidate value sequence of the second non-equidistant partition width set, constructing a threshold voltage distribution curve based on the boundary candidate value sequence and extracting the valley voltage between adjacent storage states, adjusting the corresponding boundary candidate values ​​based on the valley voltage, and generating the dynamic voltage boundary of the target flash memory includes: Obtain the voltage division width from the second non-equidistant division width set, and accumulate the voltage division width in combination with the preset reading start voltage to obtain the boundary candidate value sequence; A read voltage is applied to the target flash memory according to the boundary candidate value sequence, and the corresponding memory cell response data is collected; The threshold voltage distribution curve is reconstructed based on the memory cell response data, and the valley voltage between adjacent memory states is extracted based on the threshold voltage distribution curve. The dynamic voltage boundary of the target flash memory is generated by adjusting the corresponding candidate boundary value according to the valley voltage.

8. The SLC NAND threshold voltage adaptive calibration method according to claim 1, characterized in that, The step of determining the storage state of the target flash memory based on the dynamic voltage boundary to obtain discrete read data and complete the threshold voltage adaptive calibration read of the target flash memory includes: The dynamic voltage boundary is used as the read reference voltage of the target flash memory to read data from the target flash memory and obtain the memory cell response data. The storage state is determined based on the storage unit response data and the dynamic voltage boundary to obtain the corresponding read state, and logic level data is generated based on the read state. The stored data of the target flash memory is recovered based on the logic level data to obtain discrete read data, and the threshold voltage adaptive calibration read of the target flash memory is completed.

9. An SLC NAND threshold voltage adaptive calibration system, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the method according to any one of claims 1 to 8.

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