Distributed multi-channel real-time synchronous DAS sensing system and method

Abstract

The application discloses a kind of distributed multi-channel real-time synchronous DAS sensing system and method.System includes light source, optical pulse modulation module, N-way optical splitter, N EDFA, N sensing channels, N PD, N ADC, clock source and FPGA.Clock source provides same reference clock to FPGA and ADC.FPGA generates optical pulse trigger signal t1 and acquisition trigger signal t2, and is configured in it: optical fiber length initialization unit measures optical fiber length by OTDR;Delay calculation unit calculates delay amount accordingly;Delay control unit controls t2 delay to make each ADC synchronous sampling, and adopts coarse delay and fine delay combination to realize nanosecond to picosecond level control.Channel inter-compensation unit realizes sub-sampling level delay difference correction by cross-correlation estimation and parabolic fitting.The application realizes accurate synchronization and adaptive control of multi-channel DAS system.

Description

Technical Field

[0001] This invention relates to the field of distributed optical fiber sensing technology, and in particular to a distributed multi-channel real-time synchronous DAS sensing system and method. Background Technology

[0002] Distributed Acoustic Sensing (DAS) technology utilizes the Rayleigh backscattering effect in optical fibers to transform the entire optical cable into a continuous array of vibration sensors, which has been widely used in fields such as oil and gas exploration, pipeline monitoring, geological disaster early warning, and perimeter security.

[0003] As the performance of single-channel DAS continues to improve, target industry applications are gradually evolving from linear monitoring to mesh-structured monitoring. In mesh monitoring scenarios, multiple DAS channels need to operate simultaneously, placing extremely high demands on the synchronization between channels. However, existing DAS hosts are all single-channel or multi-channel time-division multiplexing architectures, and time synchronization between hosts can only be achieved via Ethernet. Synchronization accuracy is limited by network latency jitter, typically at the millisecond level. When different channels detect the same event at the same location, the inability to accurately align the time between channels directly leads to the system's inability to accurately identify the event type and location.

[0004] In the prior art, Chinese invention patent application CN120970797A discloses a high spatial resolution distributed fiber optic acoustic wave sensing system based on FPGA real-time demodulation, which uses a narrow linewidth laser source, a swept frequency signal modulation module, and an FPGA integrated module to achieve real-time demodulation. However, this system is a single-channel architecture and does not address multi-channel synchronization issues; it also does not have an OTDR (Optical Time Domain Reflectometry) function, making it unable to automatically measure fiber length; and it does not disclose a timing control scheme between the optical pulse trigger signal and the acquisition trigger signal.

[0005] Chinese invention patent application CN122027015A discloses an optical module integrating OTDR and delay adaptive compensation functions. It measures the fiber optic link status using an OTDR and compensates for fiber optic transmission delay fluctuations using an FPGA digital delay line. However, this solution is applied to the field of fiber optic communication, and its delay compensation targets environmental fluctuations (fine-tuning) in service data transmission delay, rather than the timing relationship between the emission of the detection optical pulse and the arrival of the backscattered signal in a DAS system (establishing an absolute timing correlation). Furthermore, it is a single-channel architecture and does not address the issue of multi-channel synchronous acquisition.

[0006] Existing multi-channel data acquisition systems (such as FPGA-based multi-channel synchronous acquisition schemes) typically use a unified clock source and synchronous trigger signal to achieve multi-channel synchronization. However, these schemes do not consider the propagation delay of backscattered signals in fiber optic sensing systems. In a DAS system, after an optical pulse is injected into the fiber, the backscattered signal takes time T = 2n_g·z / c to return from the far end of the fiber (where z is the fiber length, n_g is the group refractive index, and c is the speed of light in vacuum). If the ADC starts continuous sampling immediately after the optical pulse is emitted, a large sampling window will be wasted waiting for the backscattered signal to arrive, limiting the system's data efficiency and real-time performance. If a fixed delay sampling is used, it cannot adapt to the differences in fiber length between different channels, requiring manual reconfiguration after replacing the optical cable.

[0007] In summary, existing DAS multi-channel systems have the following shortcomings: First, they can only achieve Ethernet-level time synchronization between multiple channels, which is insufficient in synchronization accuracy and cannot meet the needs of cross-channel event identification and location in mesh monitoring; second, they lack acquisition trigger timing control based on fiber length adaptation, resulting in low ADC sampling efficiency; third, they lack accurate measurement and correction methods for fixed delay differences between channels; and fourth, they lack automatic reconfiguration capabilities when fiber length changes. Summary of the Invention

[0008] To address the problems of insufficient synchronization accuracy, inability to adapt acquisition triggering timing to fiber length, and lack of correction for inter-channel delay differences in existing multi-channel DAS systems, this invention provides a distributed multi-channel real-time synchronized DAS sensing system and method.

[0009] The technical solution adopted by this invention to solve its technical problem is:

[0010] A distributed multi-channel real-time synchronous DAS sensing system includes a light source, an optical pulse modulation module, N optical splitters, N erbium-doped fiber amplifiers (EDFAs), N parallel sensing channels, N photodetectors (PDs), N analog-to-digital converters (ADCs), a clock source, and an FPGA.

[0011] The light source emits continuous light, which is modulated into a detection light pulse by the light pulse modulation module. The N-channel splitter divides the light pulse into N channels. Each channel is amplified by the EDFA and enters the corresponding sensing channel. The backscattered light signal returned from each channel is converted into an electrical signal by the PD and then into a digital signal by the ADC.

[0012] The clock source provides the same reference clock to the FPGA and each ADC;

[0013] The FPGA generates a time modulation trigger signal t1 and a data acquisition trigger signal t2. t1 controls the optical pulse modulation module to generate a probe optical pulse, and t2 synchronously triggers N ADCs to start sampling.

[0014] The FPGA is configured with a fiber length initialization unit, a delay calculation unit, and a delay control unit to realize adaptive timing control based on OTDR fiber length measurement.

[0015] The beneficial effects of this invention are:

[0016] (1) This invention uses an optical fiber length initialization unit configured within the FPGA to automatically measure the optical fiber length of each channel via the OTDR function after the system is powered on. The delay calculation unit calculates the delay between t1 and t2 based on the optical fiber length. The delay control unit controls the delay time of t2 relative to t1 according to the delay amount, so that each ADC starts sampling synchronously when the backscattered signal of the corresponding channel arrives. Compared with the continuous sampling or fixed delay sampling mode used in existing DAS systems, this invention realizes event-triggered sampling of "sampling as soon as the backscattered signal arrives", avoiding invalid sampling by the ADC while waiting for the signal to arrive, significantly improving the system's data efficiency and real-time performance; and it can adapt to the differences in optical fiber length of different channels without manual configuration.

[0017] (2) The present invention uses a single light source to split the light through an N-way beam splitter to achieve multi-channel emission. The detection light pulses of all channels are strictly from the same source, which ensures the phase consistency of the multi-channel signals from a physical perspective. Each channel uses an independent EDFA amplification to ensure the sensing distance of each channel.

[0018] (3) This invention employs a combination of coarse and fine delay to achieve digital control of the t2 delay: the coarse delay uses a counter method with the internal clock cycle of the FPGA as the resolution; the fine delay uses IDELAYE2 or IDELAYE3 delay lines to provide sub-clock cycle delay steps. The combination of the two achieves continuous delay control from nanosecond to picosecond levels, and the system synchronization error can be controlled within the nanosecond level. Practical testing has verified that the phase difference of the waveforms in each channel is on the order of 100ns under a 1000Hz vibration signal, proving that this invention can indeed achieve nanosecond-level synchronization accuracy.

[0019] (4) The multi-channel compensation unit of the present invention measures the fixed delay difference between channels by injecting calibration signal cross-correlation estimation method, and performs parabolic fitting near the cross-correlation peak to achieve sub-sampling level accuracy delay estimation, performs phase correction in the frequency domain, and further eliminates the residual delay difference between channels.

[0020] (5) The fiber breakage alarm and automatic reconfiguration function of the present invention triggers an alarm when the sensing fiber breaks or changes in length. Users can choose to keep the existing configuration or restart the OTDR fiber length initialization for automatic reconfiguration, which improves the convenience of system operation and maintenance. Attached Figure Description

[0021] Figure 1This is a schematic diagram of the overall architecture of the distributed multi-channel real-time synchronous DAS sensing system of the present invention;

[0022] Figure 2 This is a block diagram of the internal functional units of the FPGA in this invention;

[0023] Figure 3 This is a flowchart of the OTDR fiber length initialization and delay control process of the present invention.

[0024] Figure 4 This is a timing diagram illustrating the combined coarse and fine delay control of the present invention.

[0025] Figure 5 This is a flowchart of the signal processing for inter-channel compensation according to the present invention;

[0026] Figure 6 This is a flowchart of the distributed multi-channel real-time synchronous DAS sensing method of the present invention.

[0027] Reference numerals: 1. Light source; 2. Optical pulse modulation module; 3. Beam splitter; 4. Erbium-doped fiber amplifier (EDFA); 5. Parallel sensing channel; 6. Photodetector (PD); 7. Analog-to-digital converter (ADC); 8. Clock source; 9. FPGA; 91. Fiber length initialization unit; 92. Delay calculation unit; 93. Delay control unit; 94. Multi-channel compensation unit. Detailed Implementation

[0028] Example 1

[0029] like Figure 1 As shown, the distributed multi-channel real-time synchronous DAS sensing system of this embodiment includes a light source 1, an optical pulse modulation module 2, N optical splitters 3, N erbium-doped fiber amplifiers (EDFAs) 4, N parallel sensing channels 5, N photodetectors (PDs) 6, N analog-to-digital converters (ADCs) 7, a clock source 8, and an FPGA 9.

[0030] Light source 1 uses a narrow-linewidth laser to emit a continuous light signal. Optical pulse modulation module 2 receives the continuous light emitted by light source 1 and modulates it into probe light pulses under the control of a time modulation trigger signal t1 generated by FPGA 9. Optical pulse modulation module 2 can be an acousto-optic modulator (AOM) or an electro-optic modulator (EOM). Taking AOM as an example, its response time is approximately 10–50 ns.

[0031] The input of the N-channel beam splitter 3 is connected to the output of the optical pulse modulation module 2, which divides the modulated optical pulse into N optical signals. The N-channel beam splitter 3 uses a 1:N PLC (planar waveguide) beam splitter, which has a uniform splitting ratio and the power difference between each optical signal is less than 0.5dB.

[0032] N EDFA 4 units are connected to the N outputs of the N-channel optical splitter 3, respectively, to amplify each optical signal. Since the power of each optical signal is reduced to 1 / N of the input after splitting, the EDFA 4 amplifies each optical signal to the power level required for sensing (typically 10~20dBm), ensuring the sensing distance of each channel. Gain consistency among the EDFA 4 units is ensured by automatic gain control (AGC), with gain differences less than 0.5dB.

[0033] N parallel sensing channels 5 are each connected to the output of an EDFA 4, used to transmit the amplified optical signal to the fiber under test and receive the returned backscattered optical signal. Each sensing channel 5 includes a circulator and a sensing fiber. The circulator injects the optical signal output from the EDFA 4 into the sensing fiber, and simultaneously guides the Rayleigh backscattered optical signal returned from the sensing fiber to the corresponding photodetector 6. The length of the sensing fiber in each channel may vary (typically 1km to 50km), therefore the time for the backscattered signal to reach the PD also varies.

[0034] N PDs 6 are connected to N parallel sensing channels 5, respectively, and are used to convert the backscattered light signals returned from each channel into electrical signals. PDs 6 can be PIN-type or APD-type photodetectors. Taking the PIN-type as an example, the response time is approximately 0.05–0.5 ns.

[0035] N ADCs 7 are connected to the outputs of N PDs 6, respectively, to convert the electrical signals of each channel into digital signals. The sampling rate of the ADCs 7 is set according to the system's spatial resolution requirements, typically ranging from 100MHz to 1GHz. For a sampling rate of 100MHz, the corresponding spatial resolution is approximately 1m.

[0036] Clock source 8 is connected to FPGA 9 and each ADC 7, providing the same reference clock to both FPGA 9 and ADC 7. Clock source 8 uses a 100MHz oven-controlled crystal oscillator (OCXO) with a frequency stability better than 10ppb. FPGA 9 and all ADC 7 share the same reference clock, ensuring the synchronization of multi-channel sampling at the physical level.

[0037] like Figure 2 As shown, FPGA 9 is connected to optical pulse modulation module 2, each ADC 7, and clock source 8. FPGA 9 generates time modulation trigger signal t1 and acquisition trigger signal t2. t1 is used to control optical pulse modulation module 2 to generate probe optical pulses, and t2 is used to synchronously trigger N ADCs 7 to start sampling.

[0038] The FPGA 9 is equipped with the following functional units:

[0039] 1. The fiber optic length initialization unit 91 is used to measure the fiber optic length of each sensor channel via the OTDR function after the system is powered on. The specific process is as follows:

[0040] (1) After the system is powered on, the fiber length initialization unit 91 controls the optical pulse modulation module 2 to generate OTDR test pulses (typical pulse width 10ns~1μs, corresponding to spatial resolution 1m~100m).

[0041] (2) Each channel PD 6 receives the OTDR reflected signal, and the ADC 7 collects it and sends it to FPGA 9;

[0042] (3) The fiber length initialization unit 91 analyzes the OTDR signal and calculates the length L_n (n=1,2,...,N) of the sensing fiber of each channel by detecting the position of the reflection peak.

[0043] (4) Recommend the optimal combination of system configuration parameters to users based on the test results, including parameters such as the t2 delay of each channel, the starting position of the ADC sampling window, and the sampling length;

[0044] (5) Users can select configuration parameter combinations according to the actual situation so that users can complete the system automatic configuration with one click.

[0045] When the sensing fiber is broken or its length changes, the system triggers a fiber breakage alarm. The alarm is implemented through real-time monitoring of the fiber status of each channel by the OTDR: when the OTDR detects an abnormal reflection peak (fiber breakage point) in a channel or a fiber length change exceeding a preset threshold (e.g., 1m), an alarm signal is triggered. Users can choose to keep the existing configuration parameters unchanged (suitable for brief jitter or false alarm scenarios), or trigger the OTDR fiber length initialization unit 91 to restart the automated reconfiguration process (suitable for fiber breakage or replacement scenarios).

[0046] 2. The delay calculation unit 92 is used to calculate the delay between t1 and t2 based on the fiber length measured by the fiber length initialization unit 91.

[0047] The total delay from the FPGA issuing the t1 trigger signal to the ADC acquiring the kth valid sampling point consists of the following six parts:

[0048] (1) Pulse emission trigger delay T_trigger: The delay from the FPGA sending the trigger electrical signal to the actual output optical pulse of the laser. It includes the FPGA trigger signal propagation delay (approximately 1-5 ns / 15 cm for PCB traces), the laser driver circuit response time (1-5 ns for direct modulation lasers; 10-50 ns for acousto-optic modulators), and the laser build-up time. T_trigger = T_FPGA_out + T_driver + T_laser_rise.

[0049] (2) Optical path delay T_optical_path: The internal optical path propagation delay from the laser output end to the fiber injection end. This includes internal fiber jumper delay and the passage delay of optical components (circulators, beam splitters, optical isolators). T_optical_path = Σ( · / c) + ΣT_device_j, where Let be the refractive index of the internal fiber of the i-th segment. Its length.

[0050] (3) Propagation delay T_propagation in optical fiber: The round-trip propagation time of an optical pulse in the fiber under test is the main component of the time delay. T_propagation(z) = 2·n_g·z / c, where z is the distance from a point on the fiber to the injection end, n_g is the group refractive index, and c is the speed of light in vacuum. For G.652 standard single-mode fiber at a wavelength of 1550nm, the group refractive index is about 1.468, corresponding to a light speed in the fiber of about 204,000 km / s, and a one-way propagation delay of about 4.89μs / km. For a 10km fiber, the backscattered signal takes about 97.8μs to return from the far end.

[0051] (4) Receiver delay T_receiver: The delay from receiving the optical signal from the photodetector to converting it into an electrical signal for output. It includes the APD / PIN response time (APD approximately 0.1 to 2 ns, PIN approximately 0.05 to 0.5 ns), the internal optical path delay of the receiver, and the TIA response time.

[0052] (5) Circuit processing delay T_electronic: The analog signal processing link delay from the detector electrical signal output to the ADC input. It includes amplifier group delay, filter group delay (the Nth-order Bessel low-pass filter group delay is approximately N / (2πf_c)) and transmission line delay.

[0053] (6) ADC sampling start delay T_ADC: The time from when the ADC receives the sampling trigger signal to when the first valid sampling actually begins. For high-speed ADCs (100MHz~1GHz sampling rate), it is about 2 to 5 sampling clock cycles.

[0054] The total delay model is: T_total(k) = T_trigger + T_optical_path + T_propagation(z_k) + T_receiver + T_electronic + T_ADC.

[0055] The delay between t1 and t2, T_delay = T_trigger + T_optical_path + T_receiver + T_electronic + T_ADC, is the sum of all fixed delays independent of fiber distance. This delay is the minimum time that t2 needs to be delayed relative to t1, ensuring that the ADC only starts sampling after the backscattered signal reaches the PD, avoiding invalid sampling during signal propagation.

[0056] The propagation delay T_propagation(z) in the optical fiber determines the starting position and duration of the ADC sampling window: for a channel n with an optical fiber length of L_n, the time required for the backscattered signal to return from the near end to the far end of the optical fiber is T_propagation = 2·n_g·L_n / c, and the duration of the ADC sampling window is 2·T_propagation (from the nearest end signal to the farthest end signal).

[0057] 3. The delay control unit 93 is used to control the delay time of t2 relative to t1 according to the delay amount calculated by the delay calculation unit 92, so that each ADC can start sampling synchronously when the backscatter signal of the corresponding channel arrives.

[0058] The delay control unit 93 uses a combination of coarse and fine delays to control the delay time t2. Its timing control principle is as follows: Figure 4 As shown, Figure 3 The overall process from OTDR fiber length initialization to the delay control unit completing the configuration is shown.

[0059] The coarse delay is achieved using a counter method, with the FPGA's internal clock cycle as the resolution. Clock source 8 is a 100MHz clock source. FPGA 9 multiplies the 100MHz clock source to 500MHz via an internal phase-locked loop (PLL) before outputting it to the global clock buffer (BUFG) network. The PLL multiplication formula is f_out = f_in × N / (P × M), where the prescaler P is 1, the feedback divider N is 5, and the post-divider M is 1, so f_out = 100MHz × 5 / (1 × 1) = 500MHz. This corresponds to a clock cycle of 2ns, meaning the coarse delay resolution is 2ns.

[0060] t1 and t2 are generated by two independent counters within the FPGA 9, both connected to the global clock (BUFG) network to ensure consistent timing references. The coarse delay is implemented as follows: after the t1 trigger signal is issued, the counter starts counting, and when it reaches the preset value N_coarse, it outputs the t2 trigger pulse. The counter bit width is set according to the maximum delay requirement; for example, a 32-bit counter can cover a delay range of approximately 8.6 seconds at a 2ns resolution.

[0061] Fine delay utilizes the IDELAYE2 or IDELAYE3 delay line of the FPGA, providing a delay step less than a clock cycle. Taking the IDELAYE2 of the Xilinx 7 series FPGA as an example, it is located between the I / O Pad and the internal logic, with a tap delay accuracy of approximately 78ps (at a reference clock of 200MHz) or 39ps (at 300MHz), a delay range of 0~31 taps, and a total delay range of 0~2.4ns (78ps×31). The fine delay is implemented as follows: after the coarse delay counter outputs the t2 trigger pulse, the IDELAYE2 delay line performs a sub-clock cycle fine delay on the pulse, ultimately outputting a precise t2 signal.

[0062] The combination of the two can achieve continuous delay control from nanosecond to picosecond level: total delay T_delay = N_coarse × T_clk + N_tap × T_tap, where T_clk is the clock period (2ns @500MHz) and T_tap is the IDELAYE2's Tap delay (78ps @200MHz reference clock).

[0063] Each channel uses a 100MHz clock source, and the synchronization error is limited to the jitter Δt of the clock pulse signal. It remains stable at the picosecond level over a long period of time, and the error at the actual system application level is at the nanosecond level.

[0064] IV. The multi-channel compensation unit 94 is used to measure and correct the fixed delay difference between channels, and further eliminate the residual delay difference caused by factors such as differences in component parameters and PCB trace lengths between channels.

[0065] like Figure 5 As shown, the multi-channel compensation unit 94 uses the cross-correlation estimation method of injected calibration signal to measure the fixed delay difference Δ_n between channel n and reference channel 0.

[0066] The received signal model is: y_n(t) = x(t - Δ_n) + m_n(t), where x(t) is the calibration signal and m_n(t) is the noise of channel n.

[0067] Measurement steps:

[0068] (1) Inject calibration signal: In system calibration mode, inject the same calibration signal (such as sine wave signal or linear frequency modulation signal) into each channel.

[0069] (2) Cross-correlation estimation: Calculate the cross-correlation function between channel n and reference channel 0:

[0070] R_{n,0}(τ) = IFFT{FFT(y_n) · conj(FFT(y_0))}

[0071] The fixed delay difference is estimated as: Δ_n = argmax |R_{n,0}(τ)|.

[0072] (3) Parabolic Fitting: To achieve subsampling accuracy, parabolic fitting is performed near the peak of the cross-correlation. Three points R(p-1), R(p), and R(p+1) near the peak are selected, with the following offsets:

[0073] δ = 0.5 × (R(p-1) - R(p+1)) / (R(p-1) - 2·R(p) + R(p+1))

[0074] The precise delay difference estimate is: Δ_n = p + δ, where p is the integer peak position.

[0075] (4) Frequency domain phase correction: Phase correction is performed in the frequency domain.

[0076] Y_n^comp(f) = Y_n(f) · exp(j2πf·Δ_n)

[0077] Where Y_n(f) is the frequency domain signal of channel n, and Y_n^comp(f) is the compensated frequency domain signal.

[0078] Through the above compensation, the fixed delay difference between channels is corrected to sub-sampling level accuracy (i.e., less than the ADC sampling period), achieving precise synchronization of multi-channel signals.

[0079] During system operation, FPGA 9 processes multiple signals in real time and performs event feature extraction and cross-channel data fusion. Specifically, the digital signals acquired by ADC 7 of each channel are sent to FPGA 9. FPGA 9 performs time-domain or frequency-domain analysis on the signals of each channel to extract the characteristic information of the vibration event (such as frequency, amplitude, and duration), and performs cross-channel data fusion based on the synchronization timestamp of each channel to achieve event type identification and accurate positioning.

[0080] like Figure 6 As shown, the distributed multi-channel real-time synchronous DAS sensing method of the present invention includes the following steps:

[0081] Step S1: After the system is powered on, the fiber length of each sensing channel is measured using the OTDR function. Specifically, the fiber length initialization unit 91 controls the optical pulse modulation module 2 to generate OTDR test pulses. Each channel PD 6 receives the OTDR reflected signal, which is then acquired by the ADC 7 and sent to the FPGA 9. The fiber length L_n of each channel is calculated by detecting the position of the reflection peak.

[0082] Step S2: Calculate the propagation delay in the optical fiber T_propagation(z) = 2·n_g·z / c based on the measured optical fiber length, and calculate the total delay in combination with the system fixed delay to determine the delay between t1 and t2 T_delay = T_trigger + T_optical_path + T_receiver + T_electronic + T_ADC.

[0083] Step S3: FPGA 9 generates a time modulation trigger signal t1, which controls the optical pulse modulation module 2 to modulate the continuous light emitted by the light source 1 into a probe light pulse.

[0084] Step S4: The modulated optical pulse is divided into N optical signals by the N-way beam splitter 3, and then amplified by N EDFAs 4 before entering N parallel sensing channels 5.

[0085] Step S5: FPGA 9 generates a sampling trigger signal t2 according to the delay amount, synchronously triggering N ADCs 7 to start sampling, acquiring the electrical signal after photoelectric conversion of the backscattered light signal returned from each channel by PD 6. The delay of t2 relative to t1 is controlled by a combination of coarse delay and fine delay: the coarse delay uses a counter method with the internal clock cycle of the FPGA as the resolution; the fine delay uses the FPGA's IDELAYE2 or IDELAYE3 delay line.

[0086] Step S6: Perform time-domain and frequency-domain analysis on the digital signals acquired from each channel, extract event feature information, and perform cross-channel data fusion based on the synchronization timestamps of each channel. Before data fusion, measure and correct the fixed delay difference between channels: inject a calibration signal, calculate the cross-correlation function between channel n and reference channel 0, estimate the fixed delay difference, perform parabolic fitting near the cross-correlation peak to achieve subsampling level accuracy, and perform phase correction in the frequency domain.

[0087] Verification by measured data

[0088] To verify the multi-channel synchronization performance of this system, the following test plan was adopted:

[0089] The testing equipment includes: 1 multi-channel synchronous DAS device, 1 4-channel waveform generator, 4 PZT piezoelectric ceramics (15-meter standard fiber optic coil length), and 4 standard 10-kilometer fiber optic coils (with a splice length difference of less than 1 meter).

[0090] The test method is as follows: The waveform generator is set to synchronous output mode, and each channel is connected to a PZT via an RF cable. Sine drive signals at frequencies of 100Hz and 1000Hz are applied to the PZT respectively, and the time domain waveform at the 100010-meter position (i.e., the end of the 10-kilometer fiber optic coil + 15-meter PZT fiber optic coil) is recovered using the software built into the multi-channel synchronous DAS device.

[0091] 100Hz Test Results: The waveform generator synchronously applied a 100Hz signal to four PZTs. The phase difference between the four channels of the time-domain waveforms restored by the multi-channel synchronous DAS was no greater than 1ms. It should be noted that this phase difference includes the time error introduced by the application software CPU calculation part. The actual multi-channel synchronization error of the DAS hardware demodulation is much better than 1ms.

[0092] 1000Hz Test Results: The waveform generator synchronously applied a 1000Hz signal to four PZTs, and the phase difference between the time-domain waveforms of the four channels was approximately 100ns. However, this value includes the time error introduced by the CPU calculation; the actual hardware synchronization error is far better than 100ns.

[0093] The above measured data shows that the synchronization error between channels of the present invention can be controlled at the nanosecond level, which can meet the needs of accurate positioning and identification of cross-channel events in mesh monitoring scenarios.

[0094] Those skilled in the art should understand that the specific device selections in the above embodiments (such as narrow-linewidth lasers, acousto-optic modulators, OCXOs, and IDELAYE2) are merely illustrative and do not constitute a limitation on the scope of protection of this invention. For example, a swept-frequency laser source can be selected as the light source according to system cost and performance requirements; a Mach-Zehnder modulator can be used in the optical pulse modulation module to reduce the driving voltage; a GPS-disciplined crystal oscillator can be used as the clock source to further improve long-term frequency stability; and the fine delay can be achieved by using dynamic phase adjustment technology instead of IDELAYE2. These equivalent substitutions and improvements based on the concept of this invention all fall within the scope of protection of this invention.

Claims

1. A distributed multi-channel real-time synchronous DAS sensing system, characterized in that: include: light source; An optical pulse modulation module is used to modulate the continuous light emitted by the light source into a detection optical pulse; An N-channel optical splitter, whose input is connected to the output of the optical pulse modulation module, is used to divide the modulated optical pulse into N optical signals. N erbium-doped fiber amplifiers (EDFAs) are connected to the N outputs of the N optical splitters to amplify each optical signal. N parallel sensing channels, each sensing channel is connected to the output of an EDFA, which is used to transmit the amplified optical signal to the fiber under test and receive the backscattered optical signal returned. N photodetectors (PDs) are connected to the N parallel sensing channels to convert the backscattered light signals returned from each channel into electrical signals. N analog-to-digital converters (ADCs) are connected to the output terminals of the N photodetectors, respectively, to convert the electrical signals of each channel into digital signals; A clock source, connected to the FPGA and each of the ADCs respectively, is used to provide the same reference clock to the FPGA and each of the ADCs; And the FPGA, which is connected to the optical pulse modulation module, each of the ADCs and the clock source respectively; The FPGA generates a time modulation trigger signal t1 and a data acquisition trigger signal t2. t1 is used to control the optical pulse modulation module to generate a probe optical pulse, and t2 is used to synchronously trigger the N ADCs to start sampling. The FPGA is configured with: The fiber length initialization unit is used to measure the fiber length of each sensing channel via the OTDR function after the system is powered on. The delay calculation unit is used to calculate the delay between t1 and t2 based on the measured fiber length. The delay control unit is used to control the delay time of t2 relative to t1 according to the calculated delay amount, so that each ADC starts sampling synchronously when the backscatter signal of the corresponding channel arrives.

2. The distributed multi-channel real-time synchronous DAS sensing system according to claim 1, characterized in that: The fiber length initialization unit starts the OTDR function after the system is powered on to complete the fiber length test, and recommends the optimal combination of system configuration parameters to the user based on the test results, so that the user can complete the automated configuration of the system with one click. When the sensing fiber is broken or its length changes, the system triggers a fiber breakage alarm and automatically reconfigures the fiber length initialization unit based on the user's choice to either keep the existing configuration parameters or restart the fiber length initialization unit.

3. The distributed multi-channel real-time synchronous DAS sensing system according to claim 1, characterized in that: The delay between t1 and t2, T_delay, is calculated as: T_trigger + T_optical_path + T_receiver + T_electronic + T_ADC, where T_trigger is the delay from the FPGA sending the trigger electrical signal to the actual output optical pulse from the optical pulse modulation module; T_optical_path is the internal optical path transmission delay from the light source output to the fiber injection end; T_receiver is the response delay of the photodetector converting the optical signal into an electrical signal; T_electronic is the analog signal processing link delay from the photodetector's electrical signal output to the ADC input; and T_ADC is the delay from the ADC receiving the sampling trigger signal to the actual start of the first effective sampling.

4. The distributed multi-channel real-time synchronous DAS sensing system according to claim 1, characterized in that: The clock source is a 100MHz clock source, and the FPGA multiplies the clock source frequency through an internal phase-locked loop (PLL) and outputs it to the global clock buffer (BUFG) network. t1 and t2 are generated by two independent counters inside the FPGA, and both counters are connected to the global clock network.

5. The distributed multi-channel real-time synchronous DAS sensing system according to claim 1, characterized in that: The delay control unit uses a combination of coarse and fine delay to control the delay time of t2; The coarse delay is achieved using a counter method, with the internal clock cycle of the FPGA as the resolution. The fine delay uses the IDELAYE2 or IDELAYE3 delay line of the FPGA to provide a delay step smaller than the clock cycle.

6. The distributed multi-channel real-time synchronous DAS sensing system according to claim 1, characterized in that: The system also includes a multi-channel compensation unit for measuring and correcting the fixed delay difference between channels; The multi-channel compensation unit uses a cross-correlation estimation method based on injected calibration signals to measure the fixed delay difference Δ_n between channel n and reference channel 0, and performs parabolic fitting near the cross-correlation peak to achieve sub-sampling level precision delay estimation. The compensation is performed in the frequency domain for phase correction: Y_n^comp(f) = Y_n(f) · exp(j2πf·Δ_n), where Y_n(f) is the frequency domain signal of channel n, Y_n^comp(f) is the compensated frequency domain signal, and f is the frequency.

7. A distributed multi-channel real-time synchronous DAS sensing method, characterized in that, Includes the following steps: Step 1: After the system is powered on, measure the fiber optic length of each sensor channel using the OTDR function; Step 2: Calculate the propagation delay in the optical fiber based on the measured fiber length, and combine it with the system fixed delay to calculate the total delay, and determine the delay between the time modulation trigger signal t1 and the acquisition trigger signal t2; Step 3: The FPGA generates a time modulation trigger signal t1, which controls the optical pulse modulation module to modulate the continuous light emitted by the light source into a probe light pulse; Step 4: The modulated optical pulse is divided into N optical signals by an N-way beam splitter, and then amplified by N EDFAs before entering N parallel sensing channels. Step 5: The FPGA generates a sampling trigger signal t2 according to the aforementioned delay amount, synchronously triggering N ADCs to start sampling, and collecting the electrical signal after photoelectric conversion of the backscattered light signal returned from each channel; Step 6: Perform time-domain and frequency-domain analysis on the digital signals acquired from each channel, extract event feature information, and perform cross-channel data fusion based on the synchronization timestamps of each channel.

8. The distributed multi-channel real-time synchronous DAS sensing method according to claim 7, characterized in that: In step two, the propagation delay in the optical fiber is T_propagation(z) = 2·n_g·z / c, where z is the distance from a point on the optical fiber to the injection end, n_g is the group refractive index, and c is the speed of light in vacuum. The delay between t1 and t2, T_delay, is calculated as: T_trigger + T_optical_path + T_receiver + T_electronic + T_ADC, where T_trigger is the pulse emission trigger delay, T_optical_path is the internal optical path delay, T_propagation in the optical fiber is used to determine the starting position of the ADC sampling window, the sum of T_delay and T_propagation is the total delay, T_receiver is the response delay of the photodetector converting the optical signal into an electrical signal, T_electronic is the analog signal processing link delay from the electrical signal output of the photodetector to the input of the ADC, and T_ADC is the delay from when the ADC receives the sampling trigger signal to when the first effective sampling actually begins.

9. The distributed multi-channel real-time synchronous DAS sensing method according to claim 7, characterized in that: In step five, the FPGA generates t1 and t2 respectively through two independent internal counters. Both counters are connected to the same global clock network. The delay of t2 relative to t1 is controlled by a combination of coarse delay and fine delay: the coarse delay uses a counter method with the internal clock cycle of the FPGA as the resolution; the fine delay uses the FPGA's IDELAYE2 or IDELAYE3 delay line.

10. The distributed multi-channel real-time synchronous DAS sensing method according to claim 7, characterized in that: Step six also includes the step of measuring the fixed delay difference between each channel: injecting a calibration signal, calculating the cross-correlation function R_{n,0}(τ) = IFFT{FFT(y_n) · conj(FFT(y_0))} between channel n and reference channel 0, and estimating the fixed delay difference Δ_n = argmax |R_{n,0}(τ)|; Delay estimation with subsampling accuracy is achieved by parabolic fitting near the cross-correlation peak; phase correction is performed in the frequency domain: Y_n^comp(f) = Y_n(f) · exp(j2πf·Δ_n); Where y_n is the time-domain signal of channel n, y_0 is the time-domain signal of the reference channel, τ is the time delay variable, FFT represents Fourier transform, IFFT represents inverse Fourier transform, and conj represents taking the conjugate.

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