Bus voltage abnormality monitoring circuit and method, controller and air conditioning apparatus

Abstract

The application relates to a bus voltage abnormality monitoring circuit and method, a controller and air conditioning equipment, and conforms to the electronic core industry in the strategic emerging industry. The industry classification positioning bus voltage abnormality monitoring circuit comprises a first bus capacitor, a second bus capacitor, a bus voltage dividing circuit, an overvoltage protection circuit, a bus voltage dividing sampling circuit and an abnormality monitoring chip. The first end of the second bus capacitor is electrically connected with the abnormality monitoring chip to supply power for the abnormality monitoring chip. A sampling pin of the abnormality monitoring chip is connected with a voltage sampling node of the bus voltage dividing circuit, and a flag bit pin is connected with the overvoltage protection circuit. When the bus voltage is less than or equal to a set voltage threshold, the overvoltage protection circuit controls the two bus capacitors to be connected in parallel, and the flag bit pin is connected with a first level signal; when the bus voltage is greater than the set voltage threshold, the two bus capacitors are controlled to be disconnected, and the flag bit pin is connected with a second level signal. The application can not only protect related devices in time, but also trace abnormal reasons.

Description

Technical Field

[0001] This application relates to the field of power conversion and control technology, and in particular to a bus voltage anomaly monitoring circuit and method, controller and air conditioning equipment. Background Technology

[0002] The normal output of the switching power supply in the air conditioner controller and the reliable drive of the motor by the IPM (Intelligent Power Module) both rely on a normal DC bus voltage. The switching transistors in the switching power supply circuit and the switching transistors inside the IPM module have defined limiting operating voltage ranges and must operate reliably within their withstand voltage limits. However, during actual operation, the DC bus voltage may experience a rapid and abnormal increase due to various reasons. If the bus voltage exceeds the withstand voltage limit of the downstream power devices, it will cause damage to the switching transistors or IPM modules and other related components, leading to controller failure. Summary of the Invention

[0003] In view of this, in order to solve the technical problem that a rapid abnormal rise in DC bus voltage in the prior art may lead to damage to related devices, this application provides a bus voltage abnormality monitoring circuit and method, controller and air conditioning equipment.

[0004] According to a first aspect of the embodiments of this application, a bus voltage anomaly monitoring circuit is provided, the bus voltage anomaly monitoring circuit including a first bus capacitor, a second bus capacitor, a bus voltage divider circuit, an overvoltage protection circuit, a bus voltage divider sampling circuit, and an anomaly monitoring chip; The bus voltage divider circuit is connected in parallel with the first bus capacitor. The second end of the first bus capacitor and the second end of the second bus capacitor are both grounded. The first end of the second bus capacitor is electrically connected to the anomaly monitoring chip to supply power to the anomaly monitoring chip. The sampling pin of the anomaly monitoring chip is electrically connected to the voltage sampling node of the bus voltage divider circuit for voltage sampling; the flag pin of the anomaly monitoring chip is electrically connected to the overvoltage protection circuit for switching the flag level signal based on the state of the overvoltage protection circuit; the monitoring chip is used to record the voltage information collected by the sampling pin and the flag level signal collected by the flag pin. Specifically, when the DC bus voltage is less than or equal to a set voltage threshold, the overvoltage protection circuit controls the first terminal of the first bus capacitor and the first terminal of the second bus capacitor to connect, so that the first bus capacitor and the second bus capacitor are connected in parallel, and the flag pin of the anomaly monitoring chip is connected to a first level signal; when the DC bus voltage is greater than the set voltage threshold, the overvoltage protection circuit controls the first terminal of the first bus capacitor and the first terminal of the second bus capacitor to disconnect, so that the first bus capacitor and the second bus capacitor are disconnected, and the flag pin of the anomaly monitoring chip is connected to a second level signal.

[0005] In one alternative implementation, The overvoltage protection circuit includes a switching unit, an isolation unit, and a relay. The control terminal of the switching unit is electrically connected to the first node of the bus voltage divider circuit. The first terminal of the switching unit is electrically connected to the isolation unit. The isolation unit is electrically connected to the relay. The second terminal of the switching unit is grounded. At least one voltage dividing resistor is provided between the first node and the ground terminal of the bus voltage divider circuit. At least one voltage dividing resistor is provided between the voltage sampling node of the bus voltage divider circuit and the first node. The first node is closer to the ground terminal of the bus voltage divider circuit than the voltage sampling node. The relay includes a first contact, a second contact, and a third contact. The first end of the first bus capacitor is electrically connected to the first contact, and the first end of the second bus capacitor is electrically connected to the second contact. When the DC bus voltage is less than or equal to a set voltage threshold, the switching unit is in a cut-off state, so that the isolation unit controls the first contact of the relay to connect with the second contact, and the flag pin is connected to a first level signal; when the DC bus voltage is greater than the set voltage threshold, the switching unit is in a conducting state, so that the isolation unit controls the first contact of the relay to connect with the third contact, and the flag pin is connected to a second level signal.

[0006] In one alternative implementation, The isolation unit includes an optocoupler unit, which includes a light emitter and a light receiver. The input terminal of the light emitter is electrically connected to the second node of the bus voltage divider circuit. At least one voltage divider resistor is provided between the second node of the bus voltage divider circuit and the voltage sampling node. The second node is located away from the ground terminal of the bus voltage divider circuit relative to the voltage sampling node. The output terminal of the light emitter is electrically connected to the first terminal of the switching unit, the input terminal of the light receiver is electrically connected to the negative terminal of the relay, the positive terminal of the relay is connected to the power supply, and the output terminal of the light receiver is electrically connected to the flag pin. In the switch unit, when it is in the cut-off state, the light emitter does not emit light, thereby disconnecting the light receiver to control the connection between the first contact and the second contact, and to connect the flag pin to a first level signal; when the switch unit is in the on state, the light emitter emits light, thereby turning on the light receiver to control the connection between the first contact and the third contact, and to connect the flag pin to a second level signal.

[0007] In one alternative implementation, The bus voltage anomaly monitoring circuit includes a power conversion circuit. The input terminal of the power conversion circuit is electrically connected to the first terminal of the second bus capacitor, and the first output terminal of the power conversion circuit is electrically connected to the positive terminal of the relay, serving as the power supply for the relay.

[0008] In one alternative implementation, The overvoltage protection circuit includes a voltage regulator unit, the input terminal of which is grounded, and the output terminal of which is electrically connected to the input terminal of the light emitter.

[0009] In one alternative implementation, The input terminal of the light emitter is electrically connected to the second node through a first current-limiting resistor; and / or, the output terminal of the light emitter is electrically connected to the first terminal of the switching unit through a second current-limiting resistor.

[0010] In one alternative implementation, The second end of the light receiver is electrically connected to the flag pin through a filter circuit, and the second end of the light receiver is grounded through a pull-down resistor.

[0011] In one alternative implementation, The bus voltage anomaly monitoring circuit includes a power conversion circuit. The input terminal of the power conversion circuit is electrically connected to the first terminal of the second bus capacitor, and the second output terminal of the power conversion circuit is electrically connected to the anomaly monitoring chip to supply power to the anomaly monitoring chip.

[0012] According to a second aspect of the embodiments of this application, a controller is provided, the controller including a bus voltage anomaly monitoring circuit as described in any of the first aspects.

[0013] According to a third aspect of the embodiments of this application, an air conditioning device is provided, the air conditioning device including a controller as described in the second aspect.

[0014] According to a fourth aspect of the embodiments of this application, a bus voltage anomaly monitoring method is provided, the bus voltage anomaly monitoring method being applied to a bus voltage anomaly monitoring circuit as described in any of the first aspects, the bus voltage anomaly monitoring method comprising: When a change in the flag bit level signal of the flag bit pin is detected, the current flag bit level signal is recorded, and the target information corresponding to the voltage information collected by the sampling pin is also recorded; wherein, the target information is the duration and voltage information corresponding to the amplitude of the sampled voltage in the current sampling phase during the set change phase. The cause of the anomaly is determined based on the target information corresponding to the change in the flag bit level signal.

[0015] In one alternative implementation, The determination of the cause of the anomaly based on the target information corresponding to the change in the flag bit level signal includes: The cause of the anomaly is determined based on the rate of rise of the sampled voltage in the target information.

[0016] In one alternative implementation, The step of determining the cause of the anomaly based on the rate of rise of the sampled voltage in the target information includes: If the rise time of the sampled voltage in the target information is on the order of microseconds, then the cause of the anomaly is determined to be a power grid surge. If the rise time of the sampled voltage in the target information is in the millisecond range, then the cause of the anomaly is determined to be the back electromotive force of the motor.

[0017] In one alternative implementation, The set change phase refers to the period during which the amplitude of the sampled voltage changes from 10% to 90% of the maximum amplitude.

[0018] The technical solution provided by the embodiments of this application can include the following beneficial effects: In this application, the bus voltage abnormality monitoring circuit can include a first bus capacitor, a second bus capacitor, a bus voltage divider circuit, an overvoltage protection circuit, a bus voltage divider sampling circuit, and an abnormality monitoring chip. The bus voltage divider circuit is connected in parallel with the first bus capacitor, and the second terminals of both bus capacitors are grounded. The first terminal of the second bus capacitor is electrically connected to the abnormality monitoring chip to supply power to it. The sampling pin of the abnormality monitoring chip is connected to the voltage sampling node of the bus voltage divider circuit to collect voltage information, and the flag pin is connected to the overvoltage protection circuit to obtain the flag level signal and record the above two information. When the DC bus voltage is less than or equal to a set threshold, the overvoltage protection circuit controls the two bus capacitors to be connected in parallel, and the flag pin is connected to a first level signal; when the voltage is greater than the set threshold, the overvoltage protection circuit controls the two bus capacitors to be disconnected, and the flag pin is connected to a second level signal. This application directly controls the switching of the two bus capacitors based on the bus voltage amplitude through an overvoltage protection circuit. The entire judgment and switching process is completed by pure hardware logic, without relying on software sampling and judgment by the anomaly monitoring chip, achieving a response speed of microseconds. Even in the face of transient overvoltage events such as grid surges, it can quickly disconnect the bus circuit before the relevant power devices are subjected to overvoltage impact, effectively preventing related devices from being damaged due to exceeding the limit voltage. Moreover, the anomaly monitoring chip of this application continuously collects voltage information through sampling pins and obtains the state switching information of the overvoltage protection circuit in real time through flag pins, while simultaneously recording both data. Once overvoltage protection is triggered, the voltage information and flag changes at the trigger moment can be retained, making each protection event traceable and facilitating fault tracing. In addition, the hardware-level overvoltage protection circuit is responsible for rapid disconnection to ensure safety, while the monitoring chip is responsible for continuous monitoring and data recording to ensure information traceability. The two work together, each performing its own function, leveraging the advantage of fast hardware response speed while compensating for the lack of data recording in pure hardware protection. This provides a data foundation for subsequent analysis of the root cause of overvoltage and helps to accurately locate the cause of the fault. In other words, this application achieves an effective combination of rapid hardware protection for bus voltage anomalies and fault process data recording. It can not only provide timely protection for relevant devices when bus voltage is abnormal, but also trace the cause of the anomaly based on the recorded data, thereby improving operation and maintenance efficiency and product reliability.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0023] Figure 1 This is a schematic diagram of a bus voltage anomaly monitoring circuit according to an exemplary embodiment.

[0024] Figure 2 This is a schematic diagram illustrating a bus voltage anomaly monitoring method according to an exemplary embodiment. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] The following disclosure provides numerous different embodiments or examples for implementing various aspects of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of the invention. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0027] For ease of description, spatial relative terms may be used in the text to describe the relative position or movement of one element or feature relative to another element or feature, as shown in the figure. These relative terms include, for example, "inside," "outside," "middle," "outer," "below," "below," "above," "front," "back," etc. Such spatial relative terms are intended to include different orientations of the device in use or operation, other than those depicted in the figure. For example, if the device in the figure undergoes a positional flip, orientation change, or change of motion, these directional indications will change accordingly. For instance, an element described as "below other elements or features" or "below other elements or features" will subsequently be oriented "above other elements or features" or "above other elements or features." Therefore, the example term "below" can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or in other directions), and the spatial relative descriptors used in the text will be interpreted accordingly.

[0028] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0029] The embodiments of this application will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be understood that the preferred embodiments are only for illustrating this application and are not intended to limit the scope of protection of this application.

[0030] To address the technical problem that a rapid and abnormal increase in DC bus voltage in the prior art may lead to damage to related devices, this application provides a bus voltage abnormality monitoring circuit and method, a controller, and an air conditioning device.

[0031] In this application, the bus voltage anomaly monitoring circuit may include a first bus capacitor, a second bus capacitor, a bus voltage divider circuit, an overvoltage protection circuit, a bus voltage divider sampling circuit, and an anomaly monitoring chip. The bus voltage divider circuit is connected in parallel with the first bus capacitor, and the second terminals of both bus capacitors are grounded. The first terminal of the second bus capacitor is electrically connected to the anomaly monitoring chip to supply power to it. The sampling pin of the anomaly monitoring chip is connected to the voltage sampling node of the bus voltage divider circuit to collect voltage information, and the flag pin is connected to the overvoltage protection circuit to obtain the flag level signal and record the above two information. When the DC bus voltage is less than or equal to a set threshold, the overvoltage protection circuit controls the two bus capacitors to be connected in parallel, and the flag pin is connected to a first level signal; when the voltage is greater than the set threshold, the overvoltage protection circuit controls the two bus capacitors to be disconnected, and the flag pin is connected to a second level signal. This application directly controls the on / off state of the two bus capacitors based on the bus voltage amplitude through the overvoltage protection circuit. The entire judgment and switching process is completed by pure hardware logic, without relying on the software sampling and judgment of the anomaly monitoring chip, and the response speed can reach the microsecond level. Even in the face of transient overvoltage events such as power grid surges, the bus circuit can be quickly disconnected before the relevant power devices are subjected to overvoltage impact, effectively preventing the devices from being damaged due to exceeding the limit voltage. Furthermore, the anomaly monitoring chip in this application continuously collects voltage information through sampling pins and obtains the state switching information of the overvoltage protection circuit in real time through flag pins, simultaneously recording both data. Once overvoltage protection is triggered, the voltage information and flag changes at the trigger moment can be retained, making each protection event traceable and facilitating fault tracing. In addition, the hardware-level overvoltage protection circuit is responsible for rapid disconnection to ensure safety, while the monitoring chip is responsible for continuous monitoring and data recording to ensure information traceability. The two work together, each fulfilling its function, leveraging the advantages of fast hardware response while compensating for the lack of data recording in pure hardware protection. This provides a data foundation for subsequent analysis of the root cause of overvoltage and helps to accurately locate the fault. In other words, this application achieves an effective combination of rapid hardware protection for bus voltage anomalies and fault process data recording. It can not only provide timely protection for relevant devices when bus voltage is abnormal, but also trace the cause of the anomaly based on the recorded data, thereby improving operation and maintenance efficiency and product reliability.

[0032] In one exemplary embodiment, reference Figure 1 and Figure 2 As shown, a bus voltage anomaly monitoring circuit and a bus voltage anomaly monitoring method are provided, as well as a controller for the aforementioned bus voltage anomaly monitoring circuit and an air conditioning unit equipped with the aforementioned controller. In this embodiment, the bus voltage anomaly monitoring circuit includes a first bus capacitor CL1, a second bus capacitor CL2, and a bus voltage divider circuit (see reference). Figure 1 The circuit containing R0-R6), overvoltage protection circuit (reference) Figure 1The circuit consisting of Q1, T1, U1, and K1, etc.), and the bus voltage divider sampling circuit (refer to...) Figure 1 (The circuit is connected to the analog-to-digital sampling pin VDC_A_V) and the abnormal monitoring chip U2.

[0033] The first bus capacitor CL1 and the second bus capacitor CL2 are used for filtering and storing energy on the DC bus voltage. The first bus capacitor CL1 is connected to the front-end DC bus VDC_A (i.e., the rectifier output terminal), and the second bus capacitor CL2 is connected to the rear-end load bus VDC_B (i.e., the bus supplying the IPM (Intelligent Power Module) and the switching power supply). The two are connected or isolated through an overvoltage protection circuit.

[0034] The bus voltage divider circuit is connected in parallel with the first bus capacitor CL1. The bus voltage divider circuit is equipped with multiple voltage divider resistors to divide the voltage of the preceding DC bus VDC_A to provide a lower voltage signal proportional to the bus voltage for subsequent sampling and judgment.

[0035] The bus voltage divider sampling circuit is connected to the voltage sampling node in the bus voltage divider circuit. The voltage of the sampling node is proportional to the bus voltage and is used to provide the abnormal monitoring chip U2 with analog-to-digital conversion sampling.

[0036] The overvoltage protection circuit detects whether the bus voltage exceeds a set safety threshold and controls the on / off state between the first bus capacitor CL1 and the second bus capacitor CL2 based on the detection result. Simultaneously, it provides a status flag signal to the anomaly monitoring chip U2. It should be noted that the overvoltage protection circuit can monitor whether the bus voltage exceeds the set voltage threshold by directly monitoring the bus voltage or by using a voltage divider proportional to the bus voltage; neither method is limited.

[0037] The anomaly monitoring chip U2 has an analog-to-digital sampling pin VDC_A_V and a flag pin VDC_HIGH, which are used to collect the sampled value of the bus voltage and the status signal of the overvoltage protection circuit. It also has a data storage function and can record the above information.

[0038] In this embodiment, the second terminal of the first bus capacitor CL1 and the second terminal of the second bus capacitor CL2 are both grounded, and their first terminals are connected to the front-stage DC bus VDC_A and the rear-stage load bus VDC_B, respectively. A bus voltage divider circuit is connected in parallel with the first bus capacitor CL1, and its voltage sampling node is connected to the sampling pin of the anomaly monitoring chip U2. An overvoltage protection circuit is connected to the first terminal of the first bus capacitor CL1, the first terminal of the second bus capacitor CL2, and the flag pin VDC_HIGH of the anomaly monitoring chip U2. The first terminal of the second bus capacitor CL2 also provides operating power to the anomaly monitoring chip U2, ensuring that the chip can obtain a brief power supply to complete data saving in abnormal situations.

[0039] When the DC bus voltage is within the normal range (below the set voltage threshold), the overvoltage protection circuit controls the first terminal of the first bus capacitor CL1 to be connected to the first terminal of the second bus capacitor CL2. At this time, the first bus capacitor CL1 and the second bus capacitor CL2 are connected in parallel, jointly providing a stable bus voltage for downstream loads (such as IPM modules and switching power supplies). Simultaneously, the overvoltage protection circuit outputs a first-level signal (e.g., low level) to the flag pin VDC_HIGH of the anomaly monitoring chip U2, indicating that the current bus voltage is normal. The anomaly monitoring chip U2 continuously acquires the voltage signal provided by the bus voltage divider sampling circuit through the analog-to-digital sampling pin VDC_A_V, and cyclically monitors the level state of the flag pin VDC_HIGH.

[0040] When the DC bus voltage rises above a set voltage threshold (e.g., due to grid surges or motor back electromotive force), the overvoltage protection circuit immediately activates, disconnecting the first terminal of the first bus capacitor CL1 from the first terminal of the second bus capacitor CL2. This means the first bus capacitor CL1 and the second bus capacitor CL2 are no longer connected in parallel, isolating the high voltage from the downstream load and preventing damage to downstream components from high-voltage surges. Simultaneously, the overvoltage protection circuit switches the level signal of the flag pin to a second level signal (e.g., high level), reporting the overvoltage event to the anomaly monitoring chip U2. Once the anomaly monitoring chip U2 detects the change in the flag level, it records the sampled voltage data for the current moment and a period before and after it, along with the flag state change information, into its internal memory.

[0041] It should be noted that when the first bus capacitor CL1 is disconnected from the second bus capacitor CL2, the residual charge stored in the second bus capacitor CL2 can still briefly power the anomaly monitoring chip U2 after the overvoltage protection trips, ensuring that the chip has sufficient time to complete the data saving operation. The saved data can be reported to external devices via a communication interface (such as UART) to provide a basis for subsequent fault analysis. Of course, the anomaly monitoring chip U2 can also analyze the saved data to determine the cause of the fault.

[0042] In this embodiment, the overvoltage protection circuit controls the connection between the first bus capacitor CL1 and the second bus capacitor CL2 based on whether the bus voltage is overvoltage. When the voltage is normal, they are connected in parallel to power the subsequent stage; when there is an overvoltage, they are immediately disconnected for isolation. The entire judgment and switching process is completed independently by the overvoltage protection circuit, without relying on the software sampling, filtering, and interrupt response of the abnormality monitoring chip U2, and the response speed can reach the microsecond level. Even in the face of microsecond-level transient overvoltage events such as power grid surges, it can quickly isolate the high voltage of the front stage from the load of the subsequent stage before the power devices are subjected to the overvoltage impact, effectively preventing the IPM module and the switching transistors in the switching power supply from being damaged due to exceeding the limit voltage.

[0043] The anomaly monitoring chip U2 continuously collects bus voltage information through its sampling pins and simultaneously acquires the overvoltage protection circuit's state switching signal in real time through its flag pin. When the flag level switches from the first level signal to the second level signal, the anomaly monitoring chip U2 immediately records the sampled voltage data for the current moment and a period before and after it, along with the flag state change information, into its internal memory. Complete voltage change data is available for each overvoltage protection event, allowing maintenance personnel to analyze the cause of the fault based on the saved data, preventing repeated damage to components and significantly improving maintenance efficiency and product reliability.

[0044] In this embodiment, the first terminal of the second bus capacitor CL2 simultaneously provides operating power to the anomaly monitoring chip U2. When the overvoltage protection is activated and the two capacitors are disconnected, the residual charge stored in the second bus capacitor CL2 can still briefly maintain the power supply to the anomaly monitoring chip U2, ensuring that the chip has enough time to complete the storage operation of sampling data and flag bit information. This avoids data saving failure due to instantaneous power loss and ensures the reliability of the fault tracing function.

[0045] In other words, this embodiment achieves microsecond-level hardware rapid protection while automatically recording and saving complete fault process data through the coordinated operation of the overvoltage protection circuit and the abnormal monitoring chip U2. This organically combines rapid response with fault tracing, ensuring the safe operation of power devices and providing reliable data support for subsequent fault analysis and location, thus comprehensively improving the reliability and maintainability of the system.

[0046] In one exemplary embodiment, reference Figure 1 and Figure 2As shown, a bus voltage anomaly monitoring circuit and method are provided, along with a controller for the aforementioned bus voltage anomaly monitoring circuit and an air conditioning unit equipped with the aforementioned controller. In this embodiment, the overvoltage protection circuit includes a switching unit Q1, an isolation unit, and a relay K1. The control terminal of the switching unit Q1 is electrically connected to the first node of the bus voltage divider circuit, the first terminal of the switching unit Q1 is electrically connected to the isolation unit, the isolation unit is electrically connected to the relay K1, and the second terminal of the switching unit Q1 is grounded. At least one voltage-dividing resistor is provided between the first node and the ground terminal of the bus voltage divider circuit, and at least one voltage-dividing resistor is provided between the voltage sampling node of the bus voltage divider circuit and the first node. The first node is closer to the ground terminal of the bus voltage divider circuit than the voltage sampling node, meaning the voltage at the first node is lower than the voltage at the voltage sampling node. The first node (closer to ground) is responsible for highly sensitive "on / off judgment"; the voltage sampling node (slightly above) is responsible for pure "voltage measurement." The two are physically isolated, ensuring that the stability of the hardware protection and the purity of the software sampling do not interfere with each other.

[0047] The relay K1 includes a first contact A, a second contact B, and a third contact C. A first terminal of the first bus capacitor CL1 is electrically connected to the first contact A, and a first terminal of the second bus capacitor CL2 is electrically connected to the second contact B. That is, this embodiment controls the connection state of the first bus capacitor CL1 and the second bus capacitor CL2 by controlling the connection state between the first contact A, the second contact B, and the third contact C in the relay K1.

[0048] When the first DC bus voltage is within the normal range (below the set voltage threshold), the voltage at the first node in the bus voltage divider circuit is lower than the conduction threshold voltage of the switching unit Q1, and the switching unit Q1 is in the cut-off state. Because the switching unit Q1 is cut off, the isolation unit does not operate, the coil of relay K1 is not energized, and relay K1 maintains the connection between the first contact A and the second contact B. At this time, the first bus capacitor CL1 and the second bus capacitor CL2 are connected in parallel, jointly providing a stable bus voltage for the downstream load (such as the IPM module and the switching power supply). Simultaneously, the flag pin of the anomaly monitoring chip U2 is connected to a first-level signal (e.g., low level), indicating that the current bus voltage is normal. The anomaly monitoring chip U2 continuously acquires the voltage signal of the voltage sampling node through the sampling pin and cyclically detects the level state of the flag pin.

[0049] When the voltage of the first DC bus rises above the set voltage threshold due to grid surges or motor back electromotive force, the voltage at the first node in the bus voltage divider circuit rises accordingly and exceeds the conduction threshold voltage of the switching unit Q1, causing the switching unit Q1 to quickly enter the conduction state. After the switching unit Q1 is turned on, the input circuit of the isolation unit is completed, the isolation unit operates, and the coil of the relay K1 is energized. The contacts of the relay K1 switch from being connected between the first contact A and the second contact B to being connected between the first contact A and the third contact C. At this time, the first bus capacitor CL1 and the second bus capacitor CL2 are disconnected, isolating the high voltage of the front stage from the load of the back stage, preventing high voltage surges from damaging the power devices of the back stage. At the same time, the flag pin of the anomaly monitoring chip U2 is connected to a second level signal (e.g., high level) to indicate that an overvoltage event has occurred. After the anomaly monitoring chip U2 detects a change in the flag level, it immediately records the sampled voltage data of the current moment and a period before and after it, along with the flag state change information, into its internal memory. The memory can be, for example, an erasable programmable read-only memory (EEPROM) or flash memory, and there is no limitation on the latter.

[0050] Because the second bus capacitor CL2 stores residual charge, it can still briefly power the fault monitoring chip U2 after the overvoltage protection trips, ensuring that the chip has enough time to complete data saving. The saved data can be reported to external devices via the communication interface for maintenance personnel to perform fault analysis.

[0051] The isolation unit includes an optocoupler unit U1, which comprises a light emitter (e.g., a light-emitting diode) and a light receiver (e.g., a phototransistor). There is no electrical connection between the two; information is transmitted solely through optical signals. When current flows through the light emitter at the input terminal, the emitter converts the electrical signal into an optical signal and emits it. Upon receiving the optical signal, the light receiver converts it back into an electrical signal, and the output terminal is then turned on.

[0052] In this embodiment, the input terminal of the emitter is electrically connected to the second node of the bus voltage divider circuit, and at least one voltage dividing resistor is provided between the second node of the bus voltage divider circuit and the voltage sampling node. The second node is further away from the ground terminal of the bus voltage divider circuit than the voltage sampling node, meaning the voltage at the second node is higher than the voltage at the voltage sampling node. The output terminal of the emitter is electrically connected to the first terminal of the switching unit Q1, the input terminal of the light receiver is electrically connected to the negative terminal of the relay K1, the positive terminal of the relay K1 is connected to a power supply, and the output terminal of the light receiver is electrically connected to the flag pin.

[0053] When the first DC bus voltage is within the normal range (below the set safety threshold), the voltage at the first node in the bus voltage divider circuit is lower than the conduction threshold voltage of switch unit Q1, and switch unit Q1 is in the cut-off state. Because switch unit Q1 is cut off, the circuit of the emitter cannot be completed, the emitter does not emit light, and the receiver is in the off state. After the receiver is disconnected, the coil of relay K1 is not energized, and relay K1 maintains the connection between the first contact A and the second contact B, meaning that the first bus capacitor CL1 and the second bus capacitor CL2 are connected in parallel, jointly providing a stable bus voltage for the downstream load. Simultaneously, the flag pin of the anomaly monitoring chip U2 is connected to a low level (first level signal) through pull-down resistor R9, indicating that the current bus voltage is normal. The anomaly monitoring chip U2 continuously acquires the voltage signal of the voltage sampling node through the sampling pin and cyclically detects the level state of the flag pin.

[0054] When the voltage of the first DC bus rises to a level greater than or equal to a set threshold due to grid surges or motor back electromotive force, the voltage at the first node in the bus voltage divider circuit rises accordingly and exceeds the conduction threshold voltage of switch unit Q1, causing switch unit Q1 to quickly enter the conduction state. After switch unit Q1 is turned on, the circuit of the emitter is completed: the current path is the second node of the bus voltage divider circuit, the emitter, the first terminal of switch unit Q1, the second terminal of switch unit Q1, and ground. The emitter emits light, and the receiver turns on after receiving the light signal.

[0055] After the receiver is turned on, the coil of relay K1 is energized (the power supply path is: power supply, relay K1 coil, receiver input terminal, receiver output terminal, and ground). The connection between the first contact A and the second contact B of relay K1 is switched to the connection between the first contact A and the third contact C. At this time, the first bus capacitor CL1 and the second bus capacitor CL2 are disconnected, isolating the high voltage of the front stage from the load of the rear stage, preventing high voltage surges from damaging the power devices of the rear stage. Simultaneously, the turn-on of the receiver pulls the flag pin of the abnormal monitoring chip U2 to a high level (second level signal), indicating that an overvoltage event has occurred.

[0056] In addition, in this embodiment, the bus voltage anomaly monitoring circuit includes a power conversion circuit. The input terminal of the power conversion circuit is electrically connected to the first terminal of the second bus capacitor CL2, and the first output terminal of the power conversion circuit is electrically connected to the positive terminal of the relay K1, serving as the power supply for the relay K1. The power conversion circuit converts the high-voltage DC power provided by the second bus capacitor CL2 into the driving voltage required by the relay K1.

[0057] The second output terminal of the power conversion circuit is electrically connected to the anomaly monitoring chip U2, and is used to power the anomaly monitoring chip U2. The power conversion circuit can also convert the high-voltage DC power provided by the second bus capacitor CL2 into the low-voltage logic voltage required by the anomaly monitoring chip U2.

[0058] When the DC bus voltage is within the normal range (below the set voltage threshold), the power conversion circuit draws power from the second bus capacitor CL2. Its first output provides standby voltage to the positive terminal of relay K1, and its second output continuously powers the fault monitoring chip U2, ensuring normal chip operation. When the DC bus voltage rises to a level greater than or equal to the set voltage threshold, the input of the power conversion circuit is connected to the first terminal of the second bus capacitor CL2. Its first output provides drive current to the relay K1 coil during switching, ensuring reliable contact operation. Its second output continues to power the fault monitoring chip U2 after an overvoltage occurs. Because the second bus capacitor CL2 stores residual charge, after relay K1 disconnects the connection between the preceding and following stages, the second bus capacitor CL2 can still provide power to both keep relay K1 in the engaged state and to enable the fault monitoring chip U2 to save data. This allows relay K1 to remain disconnected after an overvoltage occurs, while the chip has sufficient time to complete data storage, preventing protection failure or data loss due to power interruption. The saved data can be reported to external devices via the communication interface for subsequent fault analysis.

[0059] In addition, in this embodiment, the input terminal of the emitter can be electrically connected to the second node through a first current-limiting resistor R7 to limit the current flowing into the emitter. Furthermore, the output terminal of the emitter is electrically connected to the first terminal of the switching unit Q1 through a second current-limiting resistor R8, similarly limiting the current in that branch. The first current-limiting resistor R7 and the second current-limiting resistor R8 can be set simultaneously, or only one can be set according to actual needs; there is no limitation in this regard. By reasonably selecting the resistance values ​​of the first current-limiting resistor R7 and / or the second current-limiting resistor R8, this embodiment can precisely adjust the operating current of the emitter to the optimal luminous current range recommended in its datasheet, ensuring that the emitter emits a sufficiently strong light signal, enabling the light receiver to reliably conduct, and avoiding the risk of insufficient light receiver conduction, delayed operation or failure of relay K1 due to insufficient luminous intensity.

[0060] First, the control terminal of the switching unit Q1 is directly connected to the first node of the bus voltage divider circuit. Its conduction and cutoff are entirely determined by the physical level of the bus voltage after voltage division. The entire judgment and switching process is completed independently by hardware, without relying on the software sampling and judgment of the abnormality monitoring chip U2, and the response speed can reach the microsecond level. Even in the face of microsecond-level transient overvoltage events such as power grid surges, it can quickly disconnect the connection between the upstream and downstream stages before the power devices are subjected to overvoltage impact, effectively preventing the IPM module and the switching transistors in the switching power supply from being damaged due to exceeding the limit voltage.

[0061] Secondly, there is no electrical connection between the emitter and receiver in the optocoupler unit U1; information is transmitted only through optical signals. High-voltage surges, common-mode noise, and ground potential fluctuations on the bus side are all blocked and cannot be conducted to the anomaly monitoring chip U2. This avoids damage or malfunction of the chip due to high-voltage interference, improving the system's safety and anti-interference capabilities. Simultaneously, the placement of the second node, which is far from the grounding terminal relative to the voltage sampling node, provides sufficient positive operating voltage and drive current for the emitter, ensuring reliable illumination during overvoltage and guaranteeing the reliability of the protection link.

[0062] Secondly, the anomaly monitoring chip U2 monitors the operation status of the switching unit Q1 and the optocoupler unit U1 in real time through the flag bit pin. Once the flag bit level switches from the first level signal to the second level signal, data recording is triggered, storing the sampled voltage data of the current moment and a period before and after it, along with the flag bit change information, in the internal memory. Complete voltage change data is available for each overvoltage protection event, allowing maintenance personnel to accurately locate the cause of the fault and prevent repeated damage to the device. This solves the technical problem in the background technology where the lack of fault data recording led to unclear fault causes and repeated device damage.

[0063] In addition, in this embodiment, the first node is close to the ground terminal and is responsible for highly sensitive on / off judgment; the voltage sampling node is located above the first node and is responsible for pure voltage measurement. The two are physically isolated, so that the control of the switching unit Q1 is not affected by the load change of the sampling circuit, and the sampling signal is not disturbed by the current fluctuation when the switching unit Q1 is turned on, thus ensuring the stability of hardware protection and the accuracy of software sampling.

[0064] Furthermore, the first output of the power conversion circuit provides the driving voltage for the coil of relay K1, and the second output provides the operating voltage for the abnormal monitoring chip U2. After an overvoltage occurs, the residual charge stored in the second bus capacitor CL2 maintains both the engaged state of relay K1 and the operation of the chip through the power conversion circuit, ensuring that the isolation between the front and rear stages is maintained continuously. At the same time, the chip has sufficient power to complete the storage of sampling data and flag information, avoiding protection failure or data loss due to power interruption, and eliminating the need for additional backup batteries or large-capacity energy storage components.

[0065] In other words, this embodiment achieves rapid protection against bus voltage anomalies at the microsecond level through hardware-level coordinated linkage of the switching unit Q1, optocoupler unit U1, relay K1, and power conversion circuit. At the same time, it automatically records and saves complete fault process data through the anomaly monitoring chip U2, and completely electrically isolates the high-voltage side from the low-voltage side. Meanwhile, the power conversion circuit draws power from the second bus capacitor CL2 to power the relay K1 and the chip, thus comprehensively improving the system's response speed, safety, reliability, and maintainability.

[0066] In one exemplary embodiment, reference Figure 1 and Figure 2 As shown, a bus voltage anomaly monitoring circuit and a bus voltage anomaly monitoring method are provided, along with a controller for the aforementioned bus voltage anomaly monitoring circuit, and an air conditioning unit equipped with the aforementioned controller. In this embodiment, the overvoltage protection circuit includes a voltage regulator unit T1, the input terminal of which is grounded, and the output terminal of which is electrically connected to the input terminal of the LED. The voltage regulator unit T1 can be, for example, a Zener diode, used to stabilize the input voltage at a fixed voltage value before outputting it to the input terminal of the LED, providing a stable operating voltage for the LED.

[0067] In this embodiment, when overvoltage on the bus causes voltage fluctuations at the second node, this unit clamps and stabilizes the input voltage of the emitter at a fixed safe value. This ensures that the emitter receives a constant and sufficient operating voltage regardless of whether it faces minor or severe overvoltage, emitting a consistent light signal and ensuring reliable conduction of the receiver. This guarantees the consistency and reliability of each overvoltage protection action. Simultaneously, the voltage regulator T1 also provides clamping protection—when extreme high voltage occurs on the bus and the voltage at the second node far exceeds the emitter's tolerance limit, the voltage regulator T1 limits the output voltage to a regulated value, preventing the emitter from being damaged by excessive voltage and effectively extending the service life of the optocoupler unit U1.

[0068] Furthermore, by employing a Zener diode to achieve voltage regulation, only a single component is needed to complete voltage stabilization and clamping protection. This eliminates the need for complex voltage regulator chips and external circuitry, resulting in an extremely simple and low-cost circuit structure. Moreover, the voltage regulation response time is in the nanosecond range, without affecting the microsecond-level response speed of the overvoltage protection link. In summary, the voltage regulator unit T1, at the cost of an extremely simple circuit, simultaneously achieves multiple benefits, including providing a stable operating voltage for the LED, protecting the LED from high-voltage surges, ensuring consistent protection actions, and maintaining a fast system response.

[0069] In one exemplary embodiment, reference Figure 1As shown, a bus voltage anomaly monitoring circuit and method are provided, along with a controller for the aforementioned bus voltage anomaly monitoring circuit, and an air conditioning unit equipped with the aforementioned controller. In this embodiment, the second end of the light receiver is electrically connected to the flag pin through a filter circuit, and the second end of the light receiver is grounded through a pull-down resistor R9. The filter circuit is located between the second end of the light receiver and the flag pin of the anomaly monitoring chip U2. It can filter out high-frequency noise and line coupling noise during signal transmission, ensuring that the flag pin obtains a clean and stable DC level signal. The pull-down resistor R9 can ensure that the flag pin is at a definite low level when the light receiver is off, preventing floating false alarms; and can cooperate with voltage division to output a definite high level when the light receiver is on, so as to achieve accurate acquisition of the flag level signal.

[0070] The filtering circuit includes a filtering resistor R10 and a first filtering capacitor C1. The second end of the photodetector is electrically connected to the first end of the filtering resistor R10. The second end of the filtering resistor R10 is electrically connected to the flag pin. The second end of the filtering resistor R10 is grounded through the first filtering capacitor C1.

[0071] In this embodiment, the filter resistor R10 and the subsequently grounded filter capacitor together form a first-order RC low-pass filter network. Its cutoff frequency is determined by the product of the resistance and capacitance values. High-frequency interference signals above this cutoff frequency will be effectively attenuated, while DC level signals below this cutoff frequency can pass normally. When the receiver is momentarily turned on, the filter resistor R10 limits the current flowing into the flag pin of the anomaly monitoring chip U2, preventing damage to the chip pins due to a large instantaneous current. For high-frequency noise and spike interference, the filter capacitor presents a low-impedance path, allowing high-frequency noise to bypass directly to ground through the capacitor without entering the flag pin of the anomaly monitoring chip U2.

[0072] In addition, when the light receiver switches between on and off, the filter capacitor, through its charging and discharging action, smooths the voltage change of the flag pin, preventing the abnormal monitoring chip U2 from misjudging due to excessively steep signal edges or glitches. The pull-down resistor R9 provides a discharge circuit for the filter capacitor, accelerating level switching and enhancing anti-interference capabilities.

[0073] In this embodiment, the flag pin is used to distinguish between two states: normal bus voltage (first level signal) and overvoltage (second level signal). The circuit may contain the following interference sources: reverse induced electromotive force and electromagnetic noise generated when the relay K1 coil operates; high-frequency switching noise generated when the switching power supply operates; and spatial electromagnetic interference coupled from PCB traces. If these interferences are directly superimposed on the flag signal, they may cause a momentary jump in the flag pin level, leading the anomaly monitoring chip U2 to misjudge or miss an overvoltage event. This embodiment, by setting up an RC filter circuit, effectively filters out the aforementioned high-frequency interference, retaining only the DC level signal output from the receiver to be transmitted to the flag pin. This ensures that the anomaly monitoring chip U2 correctly identifies the bus voltage state, significantly improving the anti-interference capability and reliability of overvoltage detection.

[0074] In one exemplary embodiment, reference Figure 1 and Figure 2 As shown, a bus voltage anomaly monitoring method is provided, which can be applied to the bus voltage anomaly monitoring circuit of the above embodiment. In this embodiment, the bus voltage anomaly monitoring method may include: S110. When a change in the flag level signal of the flag pin is detected, the current flag level signal is recorded, and the target information corresponding to the voltage information collected by the sampling pin is also recorded; wherein, the target information is the duration and voltage information corresponding to the amplitude of the sampled voltage collected in the current phase of the set change. S120. Determine the cause of the anomaly based on the target information corresponding to the change in the flag bit level signal.

[0075] In step S110, the set change stage refers to the time period during which the amplitude of the sampled voltage changes from 10% to 90% of its maximum value. For example, if the maximum amplitude of the sampled voltage collected by the anomaly monitoring chip U2 is A when the flag bit level signal changes, then the time period during which the amplitude of the sampled voltage changes from 10%A to 90%A is determined as the set change stage. Then, the sampled voltage information of the set change stage and the required duration are determined as the target information.

[0076] In step S120, after determining the target information, the cause of the anomaly can be determined based on the target information corresponding to the change in the flag bit level signal. Considering that different causes of anomalies may result in different rates of rise of the sampling voltage of the target information, the cause of the anomaly can be determined based on the rate of rise of the sampling voltage in the target information.

[0077] It should be noted that in this embodiment, the voltage rise caused by the power grid surge is extremely rapid (on the order of microseconds), typically a unidirectional pulse. The voltage rise caused by the motor's back electromotive force (Back-EMF) is relatively slower (depending on the motor speed and inductance), but it is continuous. The cause of relay K1's operation can be analyzed based on whether the voltage rise time is steep (μs) or gradual (ms).

[0078] For example, if the rise time of the sampled voltage in the target information is on the order of microseconds, then the cause of the anomaly is determined to be a power grid surge. If the rise time of the sampled voltage in the target information is on the order of milliseconds, then the cause of the anomaly is determined to be a motor back electromotive force.

[0079] It should be noted that, in addition to the methods mentioned above, other methods can also be used to determine the cause of the anomaly, and there are no restrictions on these methods.

[0080] In addition, in this embodiment, the anomaly monitoring chip U2 can directly determine the anomaly cause corresponding to the change of the flag bit based on the information it collects. Alternatively, it can package the collected information; for example, if a flag bit changes, the changed flag bit and the corresponding target information can be written into the internal memory of the anomaly monitoring chip U2, and a UART data packet can be constructed: frame header, timestamp, data, checksum, etc. Then, when the UART transmit buffer is idle, the data packet is sent to the receiving target through the UART interface, thus completing this reporting, updating the old information to the current new information, and recording a log for subsequent local debugging.

[0081] In one exemplary embodiment, reference Figure 1 and Figure 2 As shown, a bus voltage anomaly monitoring circuit and a bus voltage anomaly monitoring method are provided, along with a controller for the aforementioned bus voltage anomaly monitoring circuit, and an air conditioning unit equipped with the aforementioned controller. In this embodiment, AC is the AC input of mains power, Full-Wave Rectification is a full-wave rectifier circuit, and VDC_A and VDC_B are DC voltages, corresponding to the DC voltages of the preceding DC bus VDC_A and the subsequent load bus VDC_B, respectively.

[0082] The first bus capacitor CL1 and the second bus capacitor CL2 together constitute the overall bus capacitor, which is connected through relay K1. When the first contact A and the third contact C of relay K1 are connected, the two capacitors are independent and do not affect each other. When the first contact A and the second contact B of relay K1 are connected, the first bus capacitor CL1 and the second bus capacitor CL2 are connected in parallel, jointly providing bus voltage for the DC link bus for IPM and the switching power supply.

[0083] After the circuit operates normally, the abnormal monitoring chip U2 (which can be the main chip of the air conditioning equipment controller) is configured with a UART interface, VDC_HIGH is configured as an input port, reads the current flag bit level signal, and VDC_A_V is configured as an ADC port to perform continuous monitoring, obtain sampled values ​​in a loop, and reads the latest flag bit register or variable used to store VDC_HIGH.

[0084] The bus voltage divider circuit can have multiple voltage divider resistors, denoted as R0, R1, R2, R3, R4, R5, and R6. The voltage across the sixth resistor, R6, determines the on / off (or cut-off) state of the switching unit Q1 (e.g., a transistor). The voltages across the fourth resistor, R4, and the fifth resistor, R5, serve as the sampling points for the ADC (Analog-to-Digital Converter) to perform bus voltage division sampling. The voltages across the fourth resistor, R5, and the sixth resistor, R6, also act as the voltage sources for the optocoupler unit U1, the voltage regulator unit T1, and the switching unit Q1. The voltage regulator unit T1 provides a stable operating voltage for the optocoupler U1 and the switching unit Q1. Additionally, the circuit includes a first current-limiting resistor R7, a second current-limiting resistor R8, and a second filter capacitor C2.

[0085] The base voltage of transistor Q1 is: ; The sampling point voltage of the ADC is: ; The supply voltage of the Zener diode T1 is: .

[0086] When the voltage of the current stage DC bus VDC_AVDC_A is at its normal value, the voltage of the sixth resistor R6 is lower than the turn-on voltage of the switching unit Q1. At this time, the optocoupler unit U1 is not conducting, the first contact A of the relay is connected to the second contact B of the relay, the first terminals of the first bus capacitor CL1 and the second bus capacitor CL2 are electrically connected, and the first bus capacitor CL1 and the second bus capacitor CL2 are connected in parallel. The voltage values ​​of the front-stage DC bus VDC_AVDC_A and the rear-stage load bus VDC_B are the same. The voltages of the switching power supply section and the DC bus section are normal, and the circuit is working normally at this time.

[0087] When the voltage of the preceding DC bus VDC_AVDC_A is too high, it will cause the voltage of the sixth resistor R6 to be too high. When this voltage exceeds the turn-on voltage of the switching unit Q1, the switching unit Q1 will turn on, the optocoupler unit U1 will turn on synchronously, the first contact A of the relay will connect to the third contact C of the relay, and the first terminal of the first bus capacitor CL1 will be disconnected from the first terminal of the second bus capacitor CL2. The subsequent load bus VDC_B will be separated from the preceding DC bus VDC_AVDC_A to prevent the high voltage of the preceding DC bus VDC_AVDC_A from continuously affecting the related circuits of the subsequent load bus VDC_B. Because the second bus capacitor CL2 stores a short-term charge, the related circuits of the subsequent load bus VDC_B will operate briefly for a period of time to ensure the brief execution of the abnormality monitoring chip U2.

[0088] Power Conversion is a power conversion circuit that provides power to the anomaly monitoring chip U2 and relay K1. R9 is a pull-down resistor, R10 is a filter resistor, and C1 is the first filter capacitor. Together, they form a filter circuit to filter out noise on the line and prevent erroneous signals. When the optocoupler unit U1 is off (cut off), the voltage of the pull-down resistor R9 is low, and the level signal of the flag pin VDC_HIGH is low, indicating that the bus voltage is normal. When the optocoupler unit U1 is on, the voltage of the pull-down resistor R9 is high, and the level signal of the flag pin VDC_HIGH is high, indicating that the bus voltage is too high, and relay K1 has switched. VDC_A_V is the sampling port of the ADC. The sampled value can be inversely calculated to obtain VDC_A. When the flag changes, the sampled value of VDC_A during time period t and the change of the flag are stored in the memory of the anomaly monitoring chip U2. The changes in the flag bit and VDC_A / t can be reported through the communication interface UART, which helps to analyze whether the high bus voltage is caused by a power grid surge or an IPM short circuit motor back electromotive force (Back-EMF).

[0089] The time interval t can be defined as the period during which the amplitude of the sampled voltage changes from 10% to 90% of its maximum amplitude. For example, t can be in the millisecond range, such as 2ms, and the ADC sampling frequency is 50kHz. The rise time (tr) of the sampled voltage is calculated as the time required for it to rise from 10% to 90% of its maximum amplitude.

[0090] It should be noted that voltage rise caused by power grid surges is extremely rapid (on the order of microseconds), typically a unidirectional pulse. Voltage rise caused by motor back electromotive force (Back-EMF) is relatively slower (depending on motor speed and inductance), but it is continuous. The cause of relay operation can be analyzed based on whether the voltage rise time is steep (μs) or gradual (ms). For example, if tr < 5μs, the cause of the anomaly is determined to be a surge. If tr > 1ms, the cause is determined to be motor back electromotive force (Back-EMF).

[0091] In this embodiment, to achieve DC bus voltage anomaly protection and fault tracing, the logic is as follows: Step 1: Initialization: Configure the UART interface, configure VDC_HIGH as the input port, read the current flag status, configure VDC_A_V as the ADC port, and obtain the sampled value.

[0092] The second step is to conduct continuous monitoring and obtain sampled values ​​in a loop.

[0093] The third step is to read the latest flag register or variable.

[0094] Step 4: Has the flag bit changed? Is the new value not equal to the old value? It should be noted that a change in the flag bit means that the level of the VDC_HIGH input port has changed, and the relay has switched. In this case, the new value will definitely not be equal to the old value. If the new value is equal to the old value, the flag bit has not changed, and the relay has not switched.

[0095] Step 5: If the flag does not change, return to step 2.

[0096] Step 6: If the flag bit changes, write the changed flag bit and the sampled value of VDC_A during time period t into the internal memory of the main chip U2.

[0097] Step 7: Construct the UART data packet: Add a timestamp, data, and checksum to the frame header. It should be noted that to ensure accurate data transmission, the data transmission format and specifications must be followed. Adding the timestamp is to reconstruct the relay's action time; adding the checksum is to ensure accurate data transmission.

[0098] Step 8: Determine if the UART transmit buffer is free. Step 9: If the buffer is busy, wait for it to become available, then return to step 8.

[0099] Step 10: If the system is idle, send data packets via the UART interface. For example, this can be sent to a display terminal connected to the UART bus. This allows technicians to analyze the voltage changes during relay operation.

[0100] Step 11: This marks the completion of the submission.

[0101] Step 12: Update the old value to the current new value.

[0102] Step 13: Log the log, which can be used for local debugging; then return to step 2.

[0103] This embodiment solves the problem of breakdown caused by limited device withstand voltage, preventing the busbar from rapidly reaching abnormally high voltage and ensuring the normal operation of the air conditioning equipment controller. Through a logic switch integrated with the hardware circuit, when the busbar voltage exceeds a preset safety threshold, the system can quickly disconnect the busbar circuit, preventing the MOS switches and IPM modules from operating beyond their voltage limits, thus effectively preventing device breakdown and damage. After the abnormal voltage disappears, the busbar circuit is reconnected, and the controller resumes operation. Furthermore, this embodiment can record the number of abnormal busbar disconnections, retaining the data for actual analysis, solving the problem of repeated device damage due to unknown fault causes, and achieving the effect of improving operation and maintenance efficiency and product reliability.

[0104] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0105] Although terms such as first, second, third, etc., may be used in this document to describe multiple elements, components, regions, layers, and / or segments, these elements, components, regions, layers, and / or segments should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or segment from another. Unless the context clearly indicates otherwise, terms such as "first," "second," and other numerical terms used herein do not imply order or sequence. Therefore, the first element, component, region, layer, or segment discussed below may be referred to as the second element, component, region, layer, or segment without departing from the teachings of the exemplary embodiments.

[0106] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A bus voltage anomaly monitoring circuit, characterized in that, The bus voltage anomaly monitoring circuit includes a first bus capacitor, a second bus capacitor, a bus voltage divider circuit, an overvoltage protection circuit, a bus voltage divider sampling circuit, and an anomaly monitoring chip. The bus voltage divider circuit is connected in parallel with the first bus capacitor. The second end of the first bus capacitor and the second end of the second bus capacitor are both grounded. The first end of the second bus capacitor is electrically connected to the anomaly monitoring chip to supply power to the anomaly monitoring chip. The sampling pin of the anomaly monitoring chip is electrically connected to the voltage sampling node of the bus voltage divider circuit for voltage sampling; the flag pin of the anomaly monitoring chip is electrically connected to the overvoltage protection circuit for switching the flag level signal based on the state of the overvoltage protection circuit; the monitoring chip is used to record the voltage information collected by the sampling pin and the flag level signal collected by the flag pin. Specifically, when the DC bus voltage is less than or equal to a set voltage threshold, the overvoltage protection circuit controls the first terminal of the first bus capacitor and the first terminal of the second bus capacitor to connect, so that the first bus capacitor and the second bus capacitor are connected in parallel, and the flag pin of the anomaly monitoring chip is connected to a first level signal; when the DC bus voltage is greater than the set voltage threshold, the overvoltage protection circuit controls the first terminal of the first bus capacitor and the first terminal of the second bus capacitor to disconnect, so that the first bus capacitor and the second bus capacitor are disconnected, and the flag pin of the anomaly monitoring chip is connected to a second level signal.

2. The bus voltage anomaly monitoring circuit according to claim 1, characterized in that, The overvoltage protection circuit includes a switching unit, an isolation unit, and a relay. The control terminal of the switching unit is electrically connected to the first node of the bus voltage divider circuit. The first terminal of the switching unit is electrically connected to the isolation unit. The isolation unit is electrically connected to the relay. The second terminal of the switching unit is grounded. At least one voltage dividing resistor is provided between the first node and the ground terminal of the bus voltage divider circuit. At least one voltage dividing resistor is provided between the voltage sampling node of the bus voltage divider circuit and the first node. The first node is closer to the ground terminal of the bus voltage divider circuit than the voltage sampling node. The relay includes a first contact, a second contact, and a third contact. The first end of the first bus capacitor is electrically connected to the first contact, and the first end of the second bus capacitor is electrically connected to the second contact. When the DC bus voltage is less than or equal to a set voltage threshold, the switching unit is in a cut-off state, so that the isolation unit controls the first contact of the relay to connect with the second contact, and the flag pin is connected to a first level signal; when the DC bus voltage is greater than the set voltage threshold, the switching unit is in a conducting state, so that the isolation unit controls the first contact of the relay to connect with the third contact, and the flag pin is connected to a second level signal.

3. The bus voltage anomaly monitoring circuit according to claim 2, characterized in that, The isolation unit includes an optocoupler unit, which includes a light emitter and a light receiver. The input terminal of the light emitter is electrically connected to the second node of the bus voltage divider circuit. At least one voltage divider resistor is provided between the second node of the bus voltage divider circuit and the voltage sampling node. The second node is located away from the ground terminal of the bus voltage divider circuit relative to the voltage sampling node. The output terminal of the light emitter is electrically connected to the first terminal of the switching unit, the input terminal of the light receiver is electrically connected to the negative terminal of the relay, the positive terminal of the relay is connected to the power supply, and the output terminal of the light receiver is electrically connected to the flag pin. In the switch unit, when it is in the cut-off state, the light emitter does not emit light, thereby disconnecting the light receiver to control the connection between the first contact and the second contact, and to connect the flag pin to a first level signal; when the switch unit is in the on state, the light emitter emits light, thereby turning on the light receiver to control the connection between the first contact and the third contact, and to connect the flag pin to a second level signal.

4. The bus voltage anomaly monitoring circuit according to claim 3, characterized in that, The bus voltage anomaly monitoring circuit includes a power conversion circuit. The input terminal of the power conversion circuit is electrically connected to the first terminal of the second bus capacitor, and the first output terminal of the power conversion circuit is electrically connected to the positive terminal of the relay, serving as the power supply for the relay.

5. The bus voltage anomaly monitoring circuit according to claim 3, characterized in that, The overvoltage protection circuit includes a voltage regulator unit, the input terminal of which is grounded, and the output terminal of which is electrically connected to the input terminal of the light emitter.

6. The bus voltage anomaly monitoring circuit according to claim 3, characterized in that, The input terminal of the light emitter is electrically connected to the second node through a first current-limiting resistor; and / or, the output terminal of the light emitter is electrically connected to the first terminal of the switching unit through a second current-limiting resistor.

7. The bus voltage anomaly monitoring circuit according to claim 3, characterized in that, The second end of the light receiver is electrically connected to the flag pin through a filter circuit, and the second end of the light receiver is grounded through a pull-down resistor.

8. The bus voltage anomaly monitoring circuit according to any one of claims 1-7, characterized in that, The bus voltage anomaly monitoring circuit includes a power conversion circuit. The input terminal of the power conversion circuit is electrically connected to the first terminal of the second bus capacitor, and the second output terminal of the power conversion circuit is electrically connected to the anomaly monitoring chip to supply power to the anomaly monitoring chip.

9. A controller, characterized in that, The controller includes the bus voltage anomaly monitoring circuit as described in any one of claims 1-8.

10. An air conditioning device, characterized in that, The air conditioning equipment includes the controller as described in claim 9.

11. A method for monitoring abnormal bus voltage, characterized in that, The bus voltage anomaly monitoring method is applied to the bus voltage anomaly monitoring circuit as described in any one of claims 1-8, and the bus voltage anomaly monitoring method includes: When a change in the flag bit level signal of the flag bit pin is detected, the current flag bit level signal is recorded, and the target information corresponding to the voltage information collected by the sampling pin is also recorded; wherein, the target information is the duration and voltage information corresponding to the amplitude of the sampled voltage in the current sampling phase during the set change phase. The cause of the anomaly is determined based on the target information corresponding to the change in the flag bit level signal.

12. The bus voltage anomaly monitoring method according to claim 11, characterized in that, The determination of the cause of the anomaly based on the target information corresponding to the change in the flag bit level signal includes: The cause of the anomaly is determined based on the rate of rise of the sampled voltage in the target information.

13. The bus voltage anomaly monitoring method according to claim 12, characterized in that, The step of determining the cause of the anomaly based on the rate of rise of the sampled voltage in the target information includes: If the rise time of the sampled voltage in the target information is on the order of microseconds, then the cause of the anomaly is determined to be a power grid surge. If the rise time of the sampled voltage in the target information is in the millisecond range, then the cause of the anomaly is determined to be the back electromotive force of the motor.

14. The bus voltage anomaly monitoring method according to any one of claims 11-13, characterized in that, The set change phase refers to the period during which the amplitude of the sampled voltage changes from 10% to 90% of the maximum amplitude.

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