A semiconductor transient thermal test result analysis method and system

Abstract

The application discloses a semiconductor transient thermal test result analysis method and system, and belongs to the technical field of semiconductor device aging test and reliability analysis. The method comprises the following steps: calculating a thermal impedance value according to a transient thermal response data set, and generating a thermal impedance response curve; determining a regularization processing parameter, and performing adaptive preprocessing on the thermal impedance response curve based on the regularization processing parameter to obtain an optimized thermal impedance response curve; extracting thermal time constant distribution information based on the optimized thermal impedance response curve, and generating a structure function curve according to the thermal time constant distribution information; obtaining an enhanced structure function curve; determining the interlayer boundary positions of each functional layer in a semiconductor packaging structure; calculating the thermal resistance parameters and the heat capacity parameters of each functional layer based on the interlayer boundary positions, and determining an abnormal thermal structure position according to the comparison result of the calculated thermal parameters and preset reference thermal parameters, and outputting semiconductor transient thermal test result analysis information.

Description

Technical Field

[0001] This application relates to the field of semiconductor device aging testing and reliability analysis technology, and more specifically, to a method and system for analyzing semiconductor transient thermal test results. Background Technology

[0002] Semiconductor devices generate a significant amount of heat during operation. If this heat cannot be dissipated in time, the junction temperature will continuously rise, leading to parameter drift, shortened lifespan, and even thermal failure. For high-power devices such as discrete power devices, insulated-gate bipolar transistor modules, metal-oxide-semiconductor field-effect transistor modules, and multi-chip integrated packaging modules, their packaging structures typically consist of multiple functional layers stacked together, including a chip, solder layer, substrate layer, insulating layer, thermally conductive dielectric layer, and heat sink substrate. Process defects such as voids, delamination, or poor wetting in any functional layer can cause sudden changes in localized thermal resistance, affecting device reliability. Therefore, accurately obtaining the thermal resistance and thermal capacitance parameter distributions of each functional layer within the packaging structure and identifying the locations of abnormal thermal structures are crucial for packaging process quality assessment and reliability improvement.

[0003] Currently, the industry typically uses a combination of transient thermal testing and structure function analysis to characterize the thermal properties of semiconductor packaging structures: by applying a step heating power excitation to the device under test, the change of junction temperature over time is measured to obtain the thermal impedance response curve; then, based on a network identification algorithm, it is converted into an equivalent thermal network model of Foster type and Coul type, and the structure function curve is obtained by cumulative calculation along the heat conduction path; since the inflection point on the structure function curve usually corresponds to the boundary position of different material layers, the interlayer boundary and thermal resistance and thermal capacity parameters of each functional layer can be obtained from this, thereby determining whether there is an abnormal thermal structure inside the package.

[0004] However, existing methods still have the following shortcomings in practical applications: First, data acquisition often adopts a fixed sampling strategy, failing to dynamically adjust based on the curvature change characteristics of the device at different thermal response stages, and also failing to adequately compensate for the additional self-heating error generated by the temperature measurement current itself, resulting in insufficient sampling in key areas and limited accuracy in thermal impedance calculation; Second, noise inevitably gets mixed into the thermal response data, and existing methods often use fixed parameter smoothing or filtering, failing to perform adaptive regularization based on noise characteristics, making it difficult to achieve a balance between noise suppression and feature preservation; Third, when the thermal resistance-thermal capacity characteristics of adjacent functional layers in the package structure are very close, their peak and valley characteristics on the structure function curve are prone to overlap, making it difficult for existing methods to effectively separate them, which easily leads to... Fourth, the determination of interlayer boundaries mostly relies on manual experience and lacks a quantitative boundary identification and confidence assessment mechanism. The obtained thermal parameters are also generally not subject to uncertainty assessment, making it difficult to quantify the reliability of the results. Fifth, existing methods usually stop at outputting structure function curves or functional layer thermal parameters, without systematically comparing them with the benchmark parameters under standard packaging process conditions. It is difficult to automatically and accurately locate the abnormal thermal structure position caused by process defects, and still requires secondary manual interpretation. Sixth, different types of semiconductor device packaging structures and thermal characteristics vary greatly. Existing methods generally lack adaptation mechanisms for different packaging types and lack the ability to identify the thermal coupling influence area between chips in multi-chip integrated packaging modules.

[0005] In summary, existing methods for analyzing semiconductor transient thermal test results have limitations in terms of data acquisition accuracy, noise suppression effect, ability to separate overlapping thermal features, automation and quantification of interlayer boundary identification, ability to locate abnormal thermal structures, and adaptability to different packaging structures. These limitations make it difficult to meet the increasing demands for accuracy and automation in packaging process quality assessment and reliability testing. Summary of the Invention

[0006] In order to overcome a series of defects in the existing technology, the purpose of this application is to provide a method for analyzing semiconductor transient thermal test results, which includes the following steps: The transient thermal response data of the semiconductor device under test under step heating conditions is collected based on a preset sampling strategy, and the thermal impedance value is calculated based on the transient thermal response data to generate a thermal impedance response curve. Noise characteristics of the thermal impedance response curve are analyzed to determine the regularization parameters. Based on the regularization parameters, the thermal impedance response curve is adaptively preprocessed to obtain the optimized thermal impedance response curve. The thermal time constant distribution information is extracted based on the optimized thermal impedance response curve, and a structure function curve is generated based on the thermal time constant distribution information; The structure function curve is subjected to thermal feature enhancement processing, and the overlapping regions of thermal features are separated based on preset thermal property constraints to obtain the enhanced structure function curve; Structural features are extracted from the enhanced structure function curves, and matching analysis is performed based on the structural features and preset material thermal property data to determine the interlayer boundary positions of each functional layer in the semiconductor packaging structure. Based on the interlayer boundary location, the thermal resistance and thermal capacity parameters corresponding to each functional layer are calculated. Based on the comparison results of the calculated thermal parameters with the preset reference thermal parameters, the location of abnormal thermal structures is determined, and semiconductor transient thermal test result analysis information is output.

[0007] In some embodiments, the method for calculating the thermal impedance value based on the transient thermal response dataset is as follows: Based on the step heating power and the real-time collected junction temperature change, the ratio of the junction temperature change to the step heating power at each sampling time is calculated to obtain the initial thermal impedance time domain sequence. Based on the pre-calibrated temperature-sensitive parameter calibration curve and the self-heating correction coefficient of the temperature measuring current, the additional self-heating effect of the temperature measuring current on the junction temperature change is determined, and the initial thermal impedance time domain sequence is compensated and corrected based on the additional self-heating effect to obtain the corrected thermal impedance time domain sequence. The corrected thermal impedance time-domain sequence is continuously fitted using a piecewise rational function fitting method to construct a continuous thermal impedance function. By introducing the residual sum of squares constraint, the fitting error between the continuous thermal impedance function and the corrected thermal impedance time-domain sequence meets the preset requirements. Based on a continuous thermal impedance function that meets the preset fitting error requirements, the thermal impedance value corresponding to the semiconductor device under test is obtained.

[0008] In some embodiments, the method for generating thermal impedance response curves is as follows: Based on a preset logarithmic time axis, the thermal impedance time domain sequence is transformed into a logarithmic time domain thermal impedance sequence. Based on the sampling node distribution in the logarithmic time domain thermal impedance sequence, interpolation calculations are performed on the missing time nodes between adjacent sampling nodes, and the corresponding thermal impedance values ​​are determined based on the cubic spline interpolation method to obtain the interpolated thermal impedance sequence. The interpolated thermal impedance sequence is constrained and corrected based on the preset monotonicity constraint conditions to obtain a continuous thermal impedance curve that satisfies the thermal response change law. The boundary extension parameters are determined based on the estimated thermal time constant distribution range of the semiconductor device under test, and the start and end points of the continuous thermal impedance curve are extended based on the boundary extension parameters to generate a complete thermal impedance response curve.

[0009] In some embodiments, the method for determining the regularization parameters is as follows: Based on the signal-to-noise ratio parameter in the noise feature analysis results, a Tikhonov regularization objective function containing a data fidelity term and a regularization penalty term is constructed. The Tikhonov regularization objective function is solved based on a pre-defined set of candidate regularization parameters, and the residual norm and solution norm corresponding to each candidate regularization parameter are obtained. The L-curve is constructed based on the residual norm and solution norm corresponding to each candidate regularization parameter, and the initial regularization parameter is determined based on the candidate regularization parameter corresponding to the maximum curvature of the L-curve. The initial regularization parameters are modified based on the generalized cross-validation criterion, and the optimized regularization parameters are determined based on the cross-validation error. The optimized regularization parameters are adaptively adjusted based on the signal-to-noise ratio parameters to obtain the regularization processing parameters.

[0010] In some embodiments, the method for extracting thermal time constant distribution information based on the optimized thermal impedance response curve is as follows: Based on the optimized thermal impedance response curve, a convolution model between thermal impedance response data and continuous time constant distribution is established in the logarithmic time domain. The convolution relationship model is solved by regularized deconvolution based on the network recognition algorithm. Non-negativity constraints and smoothing constraints are introduced in the solution process to obtain the continuous time constant distribution density function. The regularized deconvolution solution process is iteratively controlled based on the preset convergence condition, and the continuous time constant distribution density function after convergence is determined. Extreme value detection and cluster analysis were performed on the continuous time constant distribution density function to determine the representative thermal time constant and the contribution of partial thermal resistance. The continuous time constant distribution density function is discretized based on the representative thermal time constant and the contribution of partial thermal resistance to generate thermal time constant distribution information.

[0011] In some embodiments, the method for generating structure function curves based on thermal time constant distribution information is as follows: Based on the representative thermal time constants and their corresponding partial thermal resistance contributions from the thermal time constant distribution information, a Foster-type equivalent thermal network model is constructed. The network topology transformation of the Foster-type equivalent thermal network model is performed based on the continuous fraction expansion method to obtain the Caul-type equivalent thermal network model. Based on the thermal resistance and heat capacity parameters of each network node in the Coulomb equivalent thermal network model, cumulative calculations are performed along the heat conduction path to obtain the cumulative thermal resistance sequence and the cumulative heat capacity sequence, respectively. The coordinate relationship of the structure function is established based on the cumulative thermal resistance sequence and the cumulative thermal capacity sequence, and the logarithmic transformation of the cumulative thermal capacity sequence is performed to generate the initial structure function curve. The initial structure function curve is checked for monotonicity, and then constrained and corrected according to the increasing relationship between the cumulative thermal resistance sequence and the cumulative thermal capacity sequence to obtain a structure function curve that satisfies the physical laws of heat conduction.

[0012] In some embodiments, the method for separating overlapping regions of thermal features based on preset thermal property constraints is as follows: The overlapping region of thermal features is determined based on the positional relationship between the peak and valley feature points in the thermal feature enhancement parameters. The components of the thermal feature overlap region are fitted based on the Gaussian mixture model, and the parameters of each component are solved by the expectation-maximization algorithm. The component parameters are screened and constrained based on the preset thermal property constraints and the thermal resistance-to-capacity ratio range of the candidate materials. Based on the corrected component parameters, the position and shape parameters of each independent thermal feature component are determined, and the separation results of the thermal feature overlapping region are obtained.

[0013] In some embodiments, the method for extracting structural features from the enhanced structure function curve is as follows: Based on the separation results of overlapping regions of thermal features, the independent peak and valley characteristics in the enhanced structure function curve are determined; Extract the peak position parameters, peak amplitude parameters, and peak width parameters corresponding to the independent peak features; Extract the valley location parameters, valley depth parameters, and valley width parameters corresponding to independent valley features; Based on the above characteristic parameters, a structural feature sequence is generated by sorting and associating them along the cumulative thermal resistance axis.

[0014] In some embodiments, the method for matching analysis based on structural features and preset material thermal property data is as follows: Establish a database of material thermal properties containing thermophysical parameters of candidate materials; The cumulative thermal resistance change and cumulative heat capacity change of the corresponding material layer are determined based on the peak characteristic parameters in the structural characteristic sequence. The equivalent thermal resistance-heat capacity characteristic ratio is calculated based on the cumulative change in thermal resistance and the cumulative change in heat capacity. The material layer matching result is determined based on the distance relationship between the equivalent thermal resistance-heat capacity characteristic ratio and the corresponding characteristic parameters of the candidate materials; Based on the preset matching threshold and the material arrangement order in the packaging structure, the material layer matching results are screened and consistency is verified to obtain the material matching analysis results.

[0015] The purpose of this application is also to provide a semiconductor transient thermal test result analysis system for implementing the above-mentioned semiconductor transient thermal test result analysis method, including: The data acquisition module is used to acquire transient thermal response data of the semiconductor device under test under step heating conditions, calculate the thermal impedance value, and generate thermal impedance response curves. The curve optimization module is used to perform noise analysis on the thermal impedance response curve, determine the regularization parameters, and perform adaptive optimization based on the regularization parameters to obtain the optimized thermal impedance response curve. The thermal feature analysis module is used to extract thermal time constant distribution information based on the optimized thermal impedance response curve, generate a structure function curve, and perform thermal feature enhancement and overlapping region separation processing on the structure function curve to obtain an enhanced structure function curve. The structure recognition module is used to extract features from the enhanced structure function curve and match them with preset material thermal property data to determine the interlayer boundary position of the semiconductor packaging structure. The results analysis module is used to calculate the thermal resistance and thermal capacity parameters of each functional layer based on the interlayer boundary position, determine the location of abnormal thermal structures based on the thermal parameter analysis results, and output semiconductor transient thermal test result analysis information.

[0016] Compared with the prior art, this application has the following beneficial effects: This application achieves accurate identification of functional layer boundaries, thermal parameter distribution, and abnormal thermal structure locations within the package by performing adaptive noise reduction, thermal feature decoupling, and structured analysis on semiconductor transient thermal response data, thereby improving the accuracy and reliability of semiconductor device thermal characteristic testing and analysis. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the transient thermal response dataset acquisition process in an embodiment of the present invention; Figure 2 This is a schematic diagram of the thermal impedance response curve generation and adaptive preprocessing process in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure function curve generation and thermal feature enhancement process in an embodiment of the present invention; Figure 4 This is a schematic diagram of the process for identifying the interlayer boundary location and calculating the thermal parameters of the functional layer in an embodiment of the present invention; Figure 5 This is a schematic diagram of the process for determining and analyzing the location of abnormal thermal structures in an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of the embodiments of this invention will be described in more detail below with reference to the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The described embodiments are some embodiments of this invention, but not all embodiments.

[0019] Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0020] The embodiments and directional terms described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0021] In a broad embodiment of the present invention, a method for analyzing semiconductor transient thermal test results includes the following steps: The transient thermal response data of the semiconductor device under test under step heating conditions is collected based on a preset sampling strategy, and the thermal impedance value is calculated based on the transient thermal response data to generate a thermal impedance response curve. Noise characteristics of the thermal impedance response curve are analyzed to determine the regularization parameters. Based on the regularization parameters, the thermal impedance response curve is adaptively preprocessed to obtain the optimized thermal impedance response curve. The thermal time constant distribution information is extracted based on the optimized thermal impedance response curve, and a structure function curve is generated based on the thermal time constant distribution information; The structure function curve is subjected to thermal feature enhancement processing, and the overlapping regions of thermal features are separated based on preset thermal property constraints to obtain the enhanced structure function curve; Structural features are extracted from the enhanced structure function curves, and matching analysis is performed based on the structural features and preset material thermal property data to determine the interlayer boundary positions of each functional layer in the semiconductor packaging structure. Based on the interlayer boundary location, the thermal resistance and thermal capacity parameters corresponding to each functional layer are calculated. Based on the comparison results of the calculated thermal parameters with the preset reference thermal parameters, the location of abnormal thermal structures is determined, and semiconductor transient thermal test result analysis information is output.

[0022] Furthermore, the method for obtaining the transient thermal response dataset is as follows: Obtain the package type, junction temperature change rate, and thermal capacity estimation parameters of the semiconductor device under test; Based on the package type, junction temperature change rate and heat capacity estimation parameters, the thermal response stages in the step heating process are divided, and the sampling time window and sampling density corresponding to each stage are determined. The semiconductor device under test is subjected to step heating test according to the sampling time window and sampling density to obtain the initial transient thermal response data. Curve characteristic analysis was performed on the initial transient thermal response data to determine the curvature change characteristics of the transient thermal response curve; Based on the curvature change characteristics, the sampling time window and sampling density are adaptively adjusted, and supplementary sampling is performed according to the adjusted sampling strategy to obtain optimized transient thermal response data. The optimized transient thermal response data are integrated to obtain a transient thermal response dataset for thermal impedance analysis.

[0023] Furthermore, the method for establishing the step heating conditions is as follows: Before applying a step heating power excitation, a temperature measuring current less than the heating current is used to perform thermal equilibrium detection on the semiconductor device under test, and the junction voltage change rate during the detection process is compared with the preset thermal stability threshold to determine whether the semiconductor device under test has reached thermal equilibrium. When the semiconductor device under test reaches thermal equilibrium, a step heating power excitation is applied to the PN junction of the semiconductor device under test through a constant current source. The current stability of the constant current source is not less than 99.5%, and the rise time of the power jump does not exceed 1μs. During the process of switching from heating mode to temperature measurement mode, the temperature response data of the switching stage is corrected based on the pre-acquired switching delay compensation curve; The heating duration is determined based on the upper limit of the estimated thermal time constant corresponding to the semiconductor device under test, and a transient thermal response dataset that meets the requirements of thermal impedance analysis is collected.

[0024] Furthermore, the method for calculating the thermal impedance value based on the transient thermal response dataset is as follows: Based on the step heating power and the real-time collected junction temperature change, the ratio of the junction temperature change to the step heating power at each sampling time is calculated to obtain the initial thermal impedance time domain sequence. Based on the pre-calibrated temperature-sensitive parameter calibration curve and the self-heating correction coefficient of the temperature measuring current, the additional self-heating effect of the temperature measuring current on the junction temperature change is determined, and the initial thermal impedance time domain sequence is compensated and corrected based on the additional self-heating effect to obtain the corrected thermal impedance time domain sequence. The corrected thermal impedance time-domain sequence is continuously fitted using a piecewise rational function fitting method to construct a continuous thermal impedance function. By introducing the residual sum of squares constraint, the fitting error between the continuous thermal impedance function and the corrected thermal impedance time-domain sequence meets the preset requirements. Based on a continuous thermal impedance function that meets the preset fitting error requirements, the thermal impedance value corresponding to the semiconductor device under test is obtained.

[0025] Furthermore, the method for generating the thermal impedance response curve is as follows: Based on a preset logarithmic time axis, the thermal impedance time domain sequence is transformed into a logarithmic time domain thermal impedance sequence. Based on the sampling node distribution in the logarithmic time domain thermal impedance sequence, interpolation calculations are performed on the missing time nodes between adjacent sampling nodes, and the corresponding thermal impedance values ​​are determined based on the cubic spline interpolation method to obtain the interpolated thermal impedance sequence. The interpolated thermal impedance sequence is constrained and corrected based on the preset monotonicity constraint conditions to obtain a continuous thermal impedance curve that satisfies the thermal response change law. The boundary extension parameters are determined based on the estimated thermal time constant distribution range of the semiconductor device under test, and the start and end points of the continuous thermal impedance curve are extended based on the boundary extension parameters to generate a complete thermal impedance response curve.

[0026] Furthermore, the method for noise characteristic analysis of the thermal impedance response curve is as follows: Based on the thermal impedance response curve, a difference operation is performed in the logarithmic time domain to extract the local slope sequence corresponding to the thermal impedance change trend. A short-time Fourier transform is performed on the local slope sequence to extract the corresponding time-frequency distribution features, and the noise type is determined based on the energy proportion of the high-frequency components in the time-frequency distribution features. Based on the noise type, noise parameters are extracted from the thermal impedance response curve to obtain the corresponding noise power spectral density and signal-to-noise ratio parameters. The local variance of the thermal impedance response curve is calculated based on a preset sliding window, and the location information of outliers is determined based on the characteristics of local variance changes. Based on the noise type, noise power spectral density, signal-to-noise ratio parameter, and anomaly location information, noise characteristic analysis results are generated for the thermal impedance response curve.

[0027] Furthermore, the method for determining the regularization parameters is as follows: Based on the signal-to-noise ratio parameter in the noise feature analysis results, a Tikhonov regularization objective function containing a data fidelity term and a regularization penalty term is constructed. The Tikhonov regularization objective function is solved based on a pre-defined set of candidate regularization parameters, and the residual norm and solution norm corresponding to each candidate regularization parameter are obtained. The L-curve is constructed based on the residual norm and solution norm corresponding to each candidate regularization parameter, and the initial regularization parameter is determined based on the candidate regularization parameter corresponding to the maximum curvature of the L-curve. The initial regularization parameters are modified based on the generalized cross-validation criterion, and the optimized regularization parameters are determined based on the cross-validation error. The optimized regularization parameters are adaptively adjusted based on the signal-to-noise ratio parameters to obtain the regularization processing parameters.

[0028] Furthermore, the method for adaptive preprocessing of the thermal impedance response curve based on regularization parameters is as follows: Multi-scale decomposition of thermal impedance response curves based on discrete wavelet transform yields wavelet subband coefficients corresponding to different frequency scales. Based on the signal-to-noise ratio parameter in the noise feature analysis results, the initial threshold parameter corresponding to each wavelet subband coefficient is determined, and the initial threshold parameter is adaptively adjusted based on the regularization processing parameter to obtain the adaptive threshold parameter. The wavelet subband coefficients are subjected to threshold shrinkage processing based on adaptive threshold parameters to obtain the corrected wavelet subband coefficients. Perform inverse wavelet transform on the corrected wavelet subband coefficients to obtain the denoised thermal impedance response curve; The filtering parameters of the denoised thermal impedance response curve are adjusted based on the regularization processing parameters, and the length of the filtering window is determined according to the local curvature change characteristics of the thermal impedance response curve. Adaptive filtering is then performed on the denoised thermal impedance response curve to obtain an optimized thermal impedance response curve.

[0029] Furthermore, the method for extracting thermal time constant distribution information based on the optimized thermal impedance response curve is as follows: Based on the optimized thermal impedance response curve, a convolution model between thermal impedance response data and continuous time constant distribution is established in the logarithmic time domain. The convolution relationship model is solved by regularized deconvolution based on the network recognition algorithm. Non-negativity constraints and smoothing constraints are introduced in the solution process to obtain the continuous time constant distribution density function. The regularized deconvolution solution process is iteratively controlled based on the preset convergence condition, and the continuous time constant distribution density function after convergence is determined. Extreme value detection and cluster analysis were performed on the continuous time constant distribution density function to determine the representative thermal time constant and the contribution of partial thermal resistance. The continuous time constant distribution density function is discretized based on the representative thermal time constant and the contribution of partial thermal resistance to generate thermal time constant distribution information.

[0030] Furthermore, the method for generating structure function curves based on the thermal time constant distribution information is as follows: Based on the representative thermal time constants and their corresponding partial thermal resistance contributions from the thermal time constant distribution information, a Foster-type equivalent thermal network model is constructed. The network topology transformation of the Foster-type equivalent thermal network model is performed based on the continuous fraction expansion method to obtain the Caul-type equivalent thermal network model. Based on the thermal resistance and heat capacity parameters of each network node in the Coulomb equivalent thermal network model, cumulative calculations are performed along the heat conduction path to obtain the cumulative thermal resistance sequence and the cumulative heat capacity sequence, respectively. The coordinate relationship of the structure function is established based on the cumulative thermal resistance sequence and the cumulative thermal capacity sequence, and the logarithmic transformation of the cumulative thermal capacity sequence is performed to generate the initial structure function curve. The initial structure function curve is checked for monotonicity, and then constrained and corrected according to the increasing relationship between the cumulative thermal resistance sequence and the cumulative thermal capacity sequence to obtain a structure function curve that satisfies the physical laws of heat conduction.

[0031] Furthermore, the method for enhancing the thermal characteristics of the structure function curve is as follows: The differential structure function curve is obtained by performing a first-order differential operation along the direction of cumulative thermal resistance based on the structure function curve. Local extrema detection is performed on the curve of the differential structure function to determine the corresponding local maxima and local minima, and the peak feature parameters and valley feature parameters corresponding to each extrema are extracted. Based on the salience parameters and half-width at half-maximum parameters corresponding to the peak and valley characteristic parameters, local extreme value features are screened to determine effective thermal characteristic parameters; The location and amplitude parameters corresponding to the effective thermal characteristic parameters are normalized to obtain the thermal characteristic enhancement parameter set.

[0032] Furthermore, the preset thermal property constraints include a multi-dimensional thermal property constraint database based on the semiconductor packaging structure. The multi-dimensional thermal property constraint database contains the range of thermal conductivity, volumetric heat capacity parameters, and typical thickness range of material layers corresponding to common packaging materials. The multi-dimensional thermal property constraint database is established according to the packaging type of the semiconductor device under test, and stores the thermal property parameter constraint ranges of typical packaging functional layer materials such as chip silicon material, eutectic solder layer, copper substrate layer, ceramic insulating layer, thermally conductive silicone grease layer, and heat sink substrate.

[0033] Furthermore, the method for separating overlapping regions of thermal features based on preset thermal property constraints is as follows: The overlapping region of thermal features is determined based on the positional relationship between the peak and valley feature points in the thermal feature enhancement parameters. The components of the thermal feature overlap region are fitted based on the Gaussian mixture model, and the parameters of each component are solved by the expectation-maximization algorithm. The component parameters are screened and constrained based on the preset thermal property constraints and the thermal resistance-to-capacity ratio range of the candidate materials. Based on the corrected component parameters, the position and shape parameters of each independent thermal feature component are determined, and the separation results of the thermal feature overlapping region are obtained.

[0034] Furthermore, the method for extracting structural features from the enhanced structure function curve is as follows: Based on the separation results of overlapping regions of thermal features, the independent peak and valley characteristics in the enhanced structure function curve are determined; Extract the peak position parameters, peak amplitude parameters, and peak width parameters corresponding to the independent peak features; Extract the valley location parameters, valley depth parameters, and valley width parameters corresponding to independent valley features; Based on the above characteristic parameters, a structural feature sequence is generated by sorting and associating them along the cumulative thermal resistance axis.

[0035] Furthermore, the method for matching and analyzing structural features with preset material thermal property data is as follows: Establish a database of material thermal properties containing thermophysical parameters of candidate materials; The cumulative thermal resistance change and cumulative heat capacity change of the corresponding material layer are determined based on the peak characteristic parameters in the structural characteristic sequence. The equivalent thermal resistance-heat capacity characteristic ratio is calculated based on the cumulative change in thermal resistance and the cumulative change in heat capacity. The material layer matching result is determined based on the distance relationship between the equivalent thermal resistance-heat capacity characteristic ratio and the corresponding characteristic parameters of the candidate materials; Based on the preset matching threshold and the material arrangement order in the packaging structure, the material layer matching results are screened and consistency is verified to obtain the material matching analysis results.

[0036] Furthermore, the method for determining the interlayer boundary positions of each functional layer in a semiconductor package structure is as follows: Based on the material matching analysis results, the valley value characteristic positions corresponding to adjacent material layers are determined, and the valley value characteristic positions are used as the initial interlayer boundary positions. The initial interlayer boundary position is corrected by weighted centroid correction based on valley feature parameters, resulting in the corrected interlayer boundary position. The confidence level is calculated based on the material matching parameters, valley characteristic parameters, and noise characteristic parameters corresponding to the corrected interlayer boundary locations. When the confidence level does not meet the preset requirements, the interlayer boundary position is corrected according to the packaging structure constraint parameters; The interlayer boundaries between functional layers are determined based on the corrected interlayer boundary locations.

[0037] Furthermore, the method for calculating the thermal resistance and thermal capacity parameters of each functional layer based on the interlayer boundary location is as follows: The structure function curves are divided into intervals based on the location of the interlayer boundary to determine the thermal resistance contribution interval and thermal capacity contribution interval for each functional layer. Based on the cumulative change in thermal resistance and the cumulative change in thermal capacity between adjacent layer boundary positions, calculate the thermal resistance parameters and thermal capacity parameters corresponding to each functional layer respectively. Based on the confidence information of the interlayer boundary location, the uncertainty of the thermal resistance parameter and the thermal capacity parameter are evaluated and the error propagation is calculated to obtain the joint uncertainty parameter; The thermal resistance parameter, thermal capacity parameter, and joint uncertainty parameter are standardized to generate a set of thermal parameters corresponding to each functional layer.

[0038] Furthermore, the method for determining the location of abnormal thermal structures based on the comparison results between the calculated thermal parameters and the preset reference thermal parameters is as follows: Establish a reference thermal parameter range for the functional layer based on sample thermal parameter data under standard packaging process conditions; The thermal parameter deviation is determined based on the difference between the thermal resistance and thermal capacity parameters corresponding to each functional layer and the reference thermal parameter range. Candidate regions for abnormal thermal structures are determined based on the comparison results between the thermal parameter deviation and the preset deviation threshold. Anomaly feature verification is performed based on the structural feature parameters and material matching parameters corresponding to the candidate regions of the anomalous thermal structure. The location of the abnormal thermal structure was determined based on the verification results.

[0039] Furthermore, the steps for outputting semiconductor transient thermal test result analysis information include: Obtain the interlayer boundary location, thermal resistance parameter, thermal capacity parameter, uncertainty parameter, and abnormal thermal structure location determination results for each functional layer; Based on the heat conduction path corresponding to the packaging structure, the parameter information is correlated to generate structured thermal test analysis data. Based on the results of the abnormal thermal structure location determination, abnormal feature information is determined, and the structured thermal test analysis data is marked as abnormal. Based on the structured thermal test analysis data, structure function curves, enhanced structure function curves, and interlayer boundary location information are generated; Record the regularization parameters, noise feature analysis results, and intermediate calculation parameters during the testing process to generate semiconductor transient thermal test result analysis information.

[0040] Furthermore, the semiconductor device under test includes at least one of discrete power devices, insulated gate bipolar transistor modules, metal-oxide-semiconductor field-effect transistor modules, and multi-chip integrated packaging modules; The corresponding preset configuration template is called according to the package type identification information of the semiconductor device under test. The preset configuration template includes a preset sampling strategy, an initial range of regularization processing parameters, and material database configuration parameters corresponding to thermal property constraints. The test and analysis process is configured with parameters based on the preset configuration template to adapt to the differences in thermal characteristics of different packaging structures. When the semiconductor device under test is a multi-chip integrated package module, thermal analysis is performed on the thermal impedance response curves of each chip, and the thermal coupling influence area is determined based on the heat transfer relationship between chips.

[0041] The purpose of this application is also to provide a semiconductor transient thermal test result analysis system for implementing the above-mentioned semiconductor transient thermal test result analysis method, including: The data acquisition module is used to acquire transient thermal response data of the semiconductor device under test under step heating conditions, calculate the thermal impedance value, and generate thermal impedance response curves. The curve optimization module is used to perform noise analysis on the thermal impedance response curve, determine the regularization parameters, and perform adaptive optimization based on the regularization parameters to obtain the optimized thermal impedance response curve. The thermal feature analysis module is used to extract thermal time constant distribution information based on the optimized thermal impedance response curve, generate a structure function curve, and perform thermal feature enhancement and overlapping region separation processing on the structure function curve to obtain an enhanced structure function curve. The structure recognition module is used to extract features from the enhanced structure function curve and match them with preset material thermal property data to determine the interlayer boundary position of the semiconductor packaging structure. The results analysis module is used to calculate the thermal resistance and thermal capacity parameters of each functional layer based on the interlayer boundary position, determine the location of abnormal thermal structures based on the thermal parameter analysis results, and output semiconductor transient thermal test result analysis information.

[0042] The preferred embodiments of the present invention are described below with reference to the accompanying drawings, and the present invention will be further described in detail.

[0043] This embodiment uses a certain type of insulated gate bipolar transistor (IGBT) module as the semiconductor device under test to illustrate the semiconductor transient thermal test result analysis method of the present invention. This IGBT module, from the chip to the heat dissipation substrate, comprises six typical functional layers: a chip silicon material layer, a eutectic solder layer, a copper substrate layer, a ceramic insulating layer, a thermally conductive silicone grease layer, and a heat sink substrate layer. The thermal conductivity, volumetric heat capacity, and thickness of each functional layer material differ significantly, exhibiting obvious layered thermal conduction characteristics, making it suitable as a typical application scenario for verifying the effectiveness of the method of the present invention.

[0044] like Figure 1 As shown, before conducting transient thermal testing, the package type identifier, estimated junction temperature change rate, and estimated thermal capacity parameters of the IGBT module under test are first obtained. In this embodiment, the nominal junction-to-case thermal resistance of the module is about 0.85 K / W, and the upper limit of the estimated total thermal time constant is about 2 seconds.

[0045] Based on the above parameters, the step heating process is divided into a fast response stage (corresponding to the chip and solder layer, with a timescale of approximately 1 microsecond to 10 milliseconds), an intermediate transition stage (corresponding to the copper substrate and ceramic insulating layer, with a timescale of approximately 10 milliseconds to 500 milliseconds), and a gradual change response stage (corresponding to the thermal grease layer and heat sink substrate, with a timescale of approximately 500 milliseconds to 100 seconds). Sampling time windows and sampling densities are set for each stage: the fast response stage uses logarithmically evenly spaced dense sampling, with no less than 50 sampling points per 10 octaves; the sampling density decreases sequentially in the intermediate and gradual change stages, with approximately 30 and 15 sampling points per 10 octaves, respectively.

[0046] After applying step heating to the device under test and acquiring initial transient thermal response data according to the above sampling strategy, curvature change characteristic analysis was performed on the initial data. Regions with relatively drastic curvature changes were identified around 8 milliseconds and 420 milliseconds, indicating that these regions correspond to inflection points in interlayer heat conduction characteristics. Based on this, the sampling density of the above two time intervals was locally increased and supplemented with additional sampling. Finally, a transient thermal response dataset covering 1 microsecond to 100 seconds and containing approximately 1800 valid data points was obtained, providing a data foundation for subsequent thermal impedance calculations.

[0047] During the establishment of the step heating conditions, a thermal equilibrium detection is first performed on the device under test using a temperature measuring current of 1 mA, which is much smaller than the heating current (10A in this embodiment). When the junction voltage change rate is found to be lower than the preset thermal stability threshold, the device is determined to have reached thermal equilibrium. Subsequently, a step heating power excitation (20W in this embodiment) is applied through a constant current source with a current stability of not less than 99.5% and a power jump rise time of no more than 1 microsecond. During the approximately 2-microsecond switching process from the heating state to the temperature measuring state, the temperature response data of this stage is corrected based on a pre-calibrated switching delay compensation curve to avoid the measurement deviation introduced by the switching process from affecting the accuracy of subsequent analysis.

[0048] See Figure 2 Based on the transient thermal response dataset obtained in step one, and according to the step heating power of 20 watts and the real-time junction temperature change, the thermal impedance time-domain sequence corresponding to each sampling moment is calculated. To eliminate the additional self-heating effect generated by the temperature measuring current itself, this embodiment compensates and corrects the initial thermal impedance time-domain sequence according to the pre-calibrated temperature-sensitive parameter calibration curve and the temperature measuring current self-heating correction coefficient. The correction magnitude is approximately 0.003 K / W. After correction, the thermal impedance sequence converges to 0.85 K / W at the end of heating (approximately 100 seconds), which is basically consistent with the nominal junction-shell thermal resistance of the module, indicating that the compensation and correction effect is good.

[0049] Subsequently, a piecewise rational function fitting method was used to continuously fit the corrected thermal impedance time-domain sequence, and a residual sum of squares constraint was introduced to control the fitting error. In this embodiment, the fitting residual sum of squares was controlled within a preset threshold to obtain a continuous thermal impedance function. The continuous thermal impedance function was then transformed along a logarithmic time axis, and cubic spline interpolation was used to interpolate the missing time nodes between adjacent sampling nodes. Simultaneously, a monotonicity constraint correction was applied to avoid introducing non-physical thermal impedance drop phenomena during the interpolation process. Finally, the boundary extension parameters were determined based on the estimated thermal time constant distribution range (1 microsecond to 2 seconds), and the start and end points of the curve were extended to obtain a complete thermal impedance response curve.

[0050] In the noise characteristic analysis stage, the thermal impedance response curve is differentially processed in the logarithmic time domain to obtain a local slope sequence. A short-time Fourier transform is then performed on this sequence. In this embodiment, the high-frequency component energy accounts for approximately 12%, indicating that the noise type is primarily broadband Gaussian noise. The noise power spectral density and signal-to-noise ratio (SNR) parameters are then extracted (approximately 28 dB in this embodiment). Using a preset sliding window, local variance calculation is performed on the curve, identifying a region of abnormally high local variance around 50 milliseconds, which is marked as a candidate location for anomalies.

[0051] Based on the aforementioned signal-to-noise ratio (SNR) parameters, a Tikhonov regularization objective function containing a data fidelity term and a regularization penalty term is constructed. The residual norm and solution norm corresponding to each candidate parameter are solved on a preset set of candidate regularization parameters. An L-curve is plotted, and the parameter corresponding to its maximum curvature is taken as the initial regularization parameter. This parameter is then corrected using a generalized cross-validation criterion. Finally, adaptive adjustment is performed using the SNR parameters to obtain the regularization parameters used in this embodiment. Based on these parameters, the thermal impedance response curve is subjected to discrete wavelet multi-scale decomposition. The initial threshold for each wavelet subband is determined according to the SNR and adaptively adjusted to complete threshold shrinkage and inverse wavelet transform denoising. The filter window length is determined based on the local curvature change characteristics of the curve for adaptive filtering, ultimately resulting in an optimized thermal impedance response curve with an improved SNR of approximately 40 dB.

[0052] See Figure 3Based on the optimized thermal impedance response curve, a convolution relationship between thermal response data and continuous time constant distribution is established in the logarithmic time domain. A network recognition algorithm is then used for regularized deconvolution solving, incorporating non-negativity and smoothing constraints. After iteration until a preset convergence condition is met, the continuous time constant distribution density function is obtained. Extremum detection and cluster analysis are performed on this density function. This embodiment identifies four representative thermal time constants, approximately 1.2 ms, 15 ms, 120 ms, and 850 ms, corresponding to thermal resistance contributions of approximately 0.15 K / W, 0.35 K / W, 0.10 K / W, and 0.20 K / W, respectively. Based on this, the discretization of the thermal time constant distribution information is completed.

[0053] Based on the aforementioned representative thermal time constants and contributions of partial thermal resistance, a Foster-type equivalent thermal network model is constructed, and then transformed into a Caulfield-type equivalent thermal network model with clear physical meaning using the continued fraction expansion method. The thermal resistance and heat capacity parameters of each node in the Caulfield-type network are cumulatively calculated along the heat conduction path, yielding a cumulative thermal resistance sequence (accumulating from 0 to approximately 0.85 K / W) and a corresponding cumulative heat capacity sequence. A logarithmic transformation is then performed on the cumulative heat capacity sequence to establish the structure function coordinate relationship, forming an initial structure function curve. After monotonicity verification and constraint correction, a structure function curve satisfying the physical laws of heat conduction is obtained.

[0054] In the thermal feature enhancement process, the structure function curve is differentiated along the direction of cumulative thermal resistance to obtain a differential structure function curve, and local extrema are detected. In this embodiment, five local extrema are detected on the curve. Three of these extrema meet the preset validity criteria in terms of prominence and half-width at half-maximum parameters and are therefore identified as valid thermal features. These three extrema correspond to structural transitions near the chip-solder interface, solder-copper substrate interface, and copper substrate-ceramic insulating layer interface, respectively. The other two extrema are discarded as noise residue because their prominence parameters are below a preset threshold. The position and amplitude parameters of the above valid thermal features are normalized to obtain a thermal feature enhancement parameter set.

[0055] Combining a multi-dimensional thermal property constraint database established based on the packaging structure (including the thermal conductivity range, volumetric heat capacity parameter range, and typical thickness range of typical functional layer materials such as chip silicon material, eutectic solder layer, copper substrate layer, ceramic insulating layer, thermally conductive silicone grease layer, and heat sink substrate), for regions where the concentrated positions of thermal feature enhancement parameters are adjacent and the peak and valley features partially overlap (feature overlap exists near the boundary between the copper substrate layer and the ceramic insulating layer in this embodiment), a Gaussian mixture model is used for component fitting, and the expectation-maximization algorithm is used to solve for the parameters of each component. Then, the component parameters are screened and constrained and corrected by combining the thermal property constraints and the thermal resistance-to-heat capacity ratio range of candidate materials. Finally, the originally overlapping single feature is separated into two independent thermal feature components, resulting in the enhanced structure function curve.

[0056] See Figure 4 Based on the separated independent peak and valley features in the enhanced structure function curve, the position, amplitude (or depth), and width parameters corresponding to each feature are extracted and sorted along the cumulative thermal resistance axis to generate a structural feature sequence. Combining this with a pre-established database of candidate material thermal properties, the equivalent thermal resistance-to-heat capacity characteristic ratio is calculated based on the cumulative thermal resistance and cumulative heat capacity changes corresponding to each peak feature in the structural feature sequence. The material layer matching result is then determined based on the distance relationship between this characteristic ratio and the corresponding feature parameters of the candidate materials. In this embodiment, the matching results of the six functional layers correspond sequentially to the chip silicon material, eutectic solder layer, copper substrate layer, ceramic insulating layer, thermally conductive silicone grease layer, and heat sink substrate, consistent with the actual packaging structure of the module, thus verifying the effectiveness of the matching analysis method.

[0057] Further based on the material matching analysis results, the valley value feature positions corresponding to adjacent material layers are used as the initial interlayer boundary positions, and the initial boundary positions are corrected by weighted centroid based on the valley value feature parameters. The confidence level is calculated by combining the material matching parameters, valley value feature parameters, and noise feature parameters corresponding to the corrected boundary positions. In this embodiment, the confidence levels of the five interlayer boundaries all meet the preset requirements. Among them, the confidence level of the boundary at the junction of the copper substrate and the ceramic insulating layer is relatively low (because the thermal resistance and thermal capacity ratios of the materials at this location are close, and the feature differentiation is weak). After correction by the packaging structure constraint parameters, the confidence level is improved to meet the requirements, and the interlayer boundary positions between each functional layer are finally determined.

[0058] Based on the aforementioned interlayer boundary locations, the structure function curves are divided into intervals to determine the thermal resistance contribution interval and thermal capacity contribution interval for each functional layer. The cumulative change in thermal resistance and cumulative change in thermal capacity between adjacent boundaries are calculated to obtain the thermal resistance and thermal capacity parameters for each functional layer. The calculation results in this embodiment show that the thermal resistance of the chip silicon material layer is approximately 0.06 K / W, the thermal resistance of the eutectic solder layer is approximately 0.18 K / W, the thermal resistance of the copper substrate layer is approximately 0.09 K / W, the thermal resistance of the ceramic insulating layer is approximately 0.27 K / W, the thermal resistance of the thermal grease layer is approximately 0.15 K / W, and the thermal resistance of the heat sink substrate layer is approximately 0.10 K / W. Combining the confidence information of the interlayer boundary locations, uncertainty assessment and error propagation calculations are performed on the aforementioned thermal resistance and thermal capacity parameters to obtain the joint uncertainty parameters corresponding to each functional layer (in this embodiment, the joint uncertainty of the solder layer and thermal grease layer is slightly higher than that of the other functional layers due to relatively poor material consistency). All parameters are then standardized to form a set of thermal parameters corresponding to each functional layer.

[0059] To determine whether the IGBT module under test has packaging process abnormalities (such as solder layer voids, interface delamination, etc.), this embodiment pre-establishes a reference thermal parameter range for each functional layer based on thermal parameter data from multiple samples under the same batch of standard packaging process conditions. The reference thermal resistance range for the eutectic solder layer is approximately 0.12 K / W to 0.16 K / W. The measured thermal resistance of the solder layer of the device under test in this embodiment, 0.18 K / W, is compared with this reference range. If the resulting thermal parameter deviation exceeds a preset deviation threshold, the solder layer region is marked as a candidate region for abnormal thermal structures.

[0060] For this candidate region, further verification of abnormal features was conducted by combining the corresponding structural feature parameters (the peak feature half-width at half-maximum is significantly wider than that of normal samples) and material matching parameters (the equivalent thermal resistance-heat capacity feature ratio deviates from the center of the typical range of candidate materials). The verification results show that the phenomenon of high thermal resistance and feature broadening in the solder layer region is consistent with the typical thermal characteristics of process defects such as local voids or poor wetting inside the solder layer. Based on this, it was confirmed that this functional layer region is an abnormal thermal structure location. The thermal parameters of the other five functional layers are all within the corresponding benchmark range and are judged to be normal.

[0061] Finally, the interlayer boundary positions, thermal resistance parameters, thermal capacity parameters, uncertainty parameters, and abnormal thermal structure location determination results for each functional layer are obtained. Based on the heat conduction path corresponding to the packaging structure, the above parameter information is correlated to generate structured thermal test analysis data. Anomalies are identified in this structured data based on the solder layer anomaly determination results. Based on this structured data, the structure function curve, enhanced structure function curve, and interlayer boundary position information corresponding to this embodiment are generated. Simultaneously, the regularization parameters used during the test, noise characteristic analysis results, and key intermediate calculation parameters are recorded. Finally, complete semiconductor transient thermal test result analysis information is output, providing a basis for subsequent packaging process quality assessment and reliability improvement.

[0062] It should be noted that the above embodiments use an insulated-gate bipolar transistor module as an example for illustration. The method described in this invention is also applicable to other types of semiconductor devices under test, such as discrete power devices, metal-oxide-semiconductor field-effect transistor modules, and multi-chip integrated package modules. In practical applications, a corresponding preset configuration template can be called according to the package type identification information of the device under test. This template includes a preset sampling strategy that matches the device package structure, an initial range of regularization parameters, and material database configuration parameters corresponding to thermal property constraints, thereby achieving adaptive configuration for the differences in thermal characteristics of different package structures.

[0063] When the semiconductor device under test is a multi-chip integrated package module, the above process can be performed independently for the transient thermal response data corresponding to each chip. Figures 1 to 5The analysis process shown yields the thermal impedance response curves and functional layer thermal parameters for each chip. Furthermore, based on the heat transfer relationship between chips, the thermal coupling influence area between chips is identified, providing a more comprehensive analytical basis for the overall thermal design optimization and layout improvement of multi-chip modules.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for analyzing semiconductor transient thermal test results, characterized in that, Includes the following steps: The transient thermal response data of the semiconductor device under test under step heating conditions is collected based on a preset sampling strategy, and the thermal impedance value is calculated based on the transient thermal response data to generate a thermal impedance response curve. Noise characteristics of the thermal impedance response curve are analyzed to determine the regularization parameters. Based on the regularization parameters, the thermal impedance response curve is adaptively preprocessed to obtain the optimized thermal impedance response curve. The thermal time constant distribution information is extracted based on the optimized thermal impedance response curve, and a structure function curve is generated based on the thermal time constant distribution information; The structure function curve is subjected to thermal feature enhancement processing, and the overlapping regions of thermal features are separated based on preset thermal property constraints to obtain the enhanced structure function curve; Structural features are extracted from the enhanced structure function curves, and matching analysis is performed based on the structural features and preset material thermal property data to determine the interlayer boundary positions of each functional layer in the semiconductor packaging structure. Based on the interlayer boundary location, the thermal resistance and thermal capacity parameters corresponding to each functional layer are calculated. Based on the comparison results of the calculated thermal parameters with the preset reference thermal parameters, the location of abnormal thermal structures is determined, and semiconductor transient thermal test result analysis information is output.

2. The semiconductor transient thermal test result analysis method according to claim 1, characterized in that, The method for calculating thermal impedance values ​​based on transient thermal response datasets is as follows: Based on the step heating power and the real-time collected junction temperature change, the ratio of the junction temperature change to the step heating power at each sampling time is calculated to obtain the initial thermal impedance time domain sequence. Based on the pre-calibrated temperature-sensitive parameter calibration curve and the self-heating correction coefficient of the temperature measuring current, the additional self-heating effect of the temperature measuring current on the junction temperature change is determined, and the initial thermal impedance time domain sequence is compensated and corrected based on the additional self-heating effect to obtain the corrected thermal impedance time domain sequence. The corrected thermal impedance time-domain sequence is continuously fitted using a piecewise rational function fitting method to construct a continuous thermal impedance function. By introducing the residual sum of squares constraint, the fitting error between the continuous thermal impedance function and the corrected thermal impedance time-domain sequence meets the preset requirements. Based on a continuous thermal impedance function that meets the preset fitting error requirements, the thermal impedance value corresponding to the semiconductor device under test is obtained.

3. The semiconductor transient thermal test result analysis method according to claim 1, characterized in that, The method for generating thermal impedance response curves is as follows: Based on a preset logarithmic time axis, the thermal impedance time domain sequence is transformed into a logarithmic time domain thermal impedance sequence. Based on the sampling node distribution in the logarithmic time domain thermal impedance sequence, interpolation calculations are performed on the missing time nodes between adjacent sampling nodes, and the corresponding thermal impedance values ​​are determined based on the cubic spline interpolation method to obtain the interpolated thermal impedance sequence. The interpolated thermal impedance sequence is constrained and corrected based on the preset monotonicity constraint conditions to obtain a continuous thermal impedance curve that satisfies the thermal response change law. The boundary extension parameters are determined based on the estimated thermal time constant distribution range of the semiconductor device under test, and the start and end points of the continuous thermal impedance curve are extended based on the boundary extension parameters to generate a complete thermal impedance response curve.

4. The semiconductor transient thermal test result analysis method according to claim 1, characterized in that, The method for determining the regularization parameters is as follows: Based on the signal-to-noise ratio parameter in the noise feature analysis results, a Tikhonov regularization objective function containing a data fidelity term and a regularization penalty term is constructed. The Tikhonov regularization objective function is solved based on a pre-defined set of candidate regularization parameters, and the residual norm and solution norm corresponding to each candidate regularization parameter are obtained. The L-curve is constructed based on the residual norm and solution norm corresponding to each candidate regularization parameter, and the initial regularization parameter is determined based on the candidate regularization parameter corresponding to the maximum curvature of the L-curve. The initial regularization parameters are modified based on the generalized cross-validation criterion, and the optimized regularization parameters are determined based on the cross-validation error. The optimized regularization parameters are adaptively adjusted based on the signal-to-noise ratio parameters to obtain the regularization processing parameters.

5. The method for analyzing semiconductor transient thermal test results according to claim 1, characterized in that, The method for extracting thermal time constant distribution information based on optimized thermal impedance response curves is as follows: Based on the optimized thermal impedance response curve, a convolution model between thermal impedance response data and continuous time constant distribution is established in the logarithmic time domain. The convolution relationship model is solved by regularized deconvolution based on the network recognition algorithm. Non-negativity constraints and smoothing constraints are introduced in the solution process to obtain the continuous time constant distribution density function. The regularized deconvolution solution process is iteratively controlled based on the preset convergence condition, and the continuous time constant distribution density function after convergence is determined. Extreme value detection and cluster analysis were performed on the continuous time constant distribution density function to determine the representative thermal time constant and the contribution of partial thermal resistance. The continuous time constant distribution density function is discretized based on the representative thermal time constant and the contribution of partial thermal resistance to generate thermal time constant distribution information.

6. The method for analyzing semiconductor transient thermal test results according to claim 1, characterized in that, The method for generating structure function curves based on thermal time constant distribution information is as follows: Based on the representative thermal time constants and their corresponding partial thermal resistance contributions from the thermal time constant distribution information, a Foster-type equivalent thermal network model is constructed. The network topology transformation of the Foster-type equivalent thermal network model is performed based on the continuous fraction expansion method to obtain the Caul-type equivalent thermal network model. Based on the thermal resistance and heat capacity parameters of each network node in the Coulomb equivalent thermal network model, cumulative calculations are performed along the heat conduction path to obtain the cumulative thermal resistance sequence and the cumulative heat capacity sequence, respectively. The coordinate relationship of the structure function is established based on the cumulative thermal resistance sequence and the cumulative thermal capacity sequence, and the logarithmic transformation of the cumulative thermal capacity sequence is performed to generate the initial structure function curve. The initial structure function curve is checked for monotonicity, and then constrained and corrected according to the increasing relationship between the cumulative thermal resistance sequence and the cumulative thermal capacity sequence to obtain a structure function curve that satisfies the physical laws of heat conduction.

7. The method for analyzing semiconductor transient thermal test results according to claim 1, characterized in that, The method for separating overlapping regions of thermal features based on preset thermal property constraints is as follows: The overlapping region of thermal features is determined based on the positional relationship between the peak and valley feature points in the thermal feature enhancement parameters. The components of the thermal feature overlap region are fitted based on the Gaussian mixture model, and the parameters of each component are solved by the expectation-maximization algorithm. The component parameters are screened and constrained based on the preset thermal property constraints and the thermal resistance-to-capacity ratio range of the candidate materials. Based on the corrected component parameters, the position and shape parameters of each independent thermal feature component are determined, and the separation results of the thermal feature overlapping region are obtained.

8. The method for analyzing semiconductor transient thermal test results according to claim 7, characterized in that, The method for extracting structural features from the enhanced structure function curve is as follows: Based on the separation results of overlapping regions of thermal features, the independent peak and valley characteristics in the enhanced structure function curve are determined; Extract the peak position parameters, peak amplitude parameters, and peak width parameters corresponding to the independent peak features; Extract the valley location parameters, valley depth parameters, and valley width parameters corresponding to independent valley features; Based on the above characteristic parameters, a structural feature sequence is generated by sorting and associating them along the cumulative thermal resistance axis.

9. The method for analyzing semiconductor transient thermal test results according to claim 8, characterized in that, The method for matching analysis based on structural features and preset material thermal property data is as follows: Establish a database of material thermal properties containing thermophysical parameters of candidate materials; The cumulative thermal resistance change and cumulative heat capacity change of the corresponding material layer are determined based on the peak characteristic parameters in the structural characteristic sequence. The equivalent thermal resistance-heat capacity characteristic ratio is calculated based on the cumulative change in thermal resistance and the cumulative change in heat capacity. The material layer matching result is determined based on the distance relationship between the equivalent thermal resistance-heat capacity characteristic ratio and the corresponding characteristic parameters of the candidate materials; Based on the preset matching threshold and the material arrangement order in the packaging structure, the material layer matching results are screened and consistency is verified to obtain the material matching analysis results.

10. A semiconductor transient thermal test result analysis system, used to implement the semiconductor transient thermal test result analysis method as described in any one of claims 1-9, characterized in that, include: The data acquisition module is used to acquire transient thermal response data of the semiconductor device under test under step heating conditions, calculate the thermal impedance value, and generate thermal impedance response curves. The curve optimization module is used to perform noise analysis on the thermal impedance response curve, determine the regularization parameters, and perform adaptive optimization based on the regularization parameters to obtain the optimized thermal impedance response curve. The thermal feature analysis module is used to extract thermal time constant distribution information based on the optimized thermal impedance response curve, generate a structure function curve, and perform thermal feature enhancement and overlapping region separation processing on the structure function curve to obtain an enhanced structure function curve. The structure recognition module is used to extract features from the enhanced structure function curve and match them with preset material thermal property data to determine the interlayer boundary position of the semiconductor packaging structure. The results analysis module is used to calculate the thermal resistance and thermal capacity parameters of each functional layer based on the interlayer boundary position, determine the location of abnormal thermal structures based on the thermal parameter analysis results, and output semiconductor transient thermal test result analysis information.

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