A first piece plate detection method and system

Abstract

The application belongs to the technical field of semiconductor device testing, and relates to a first piece board detection method and system, which comprises the following steps: acquiring a thermal image sequence of a memory chip surface under synchronous excitation of a pulse current, the pulse current flowing through all BGA pads to be tested; performing phase-locked processing on temperature data of each pixel point in the thermal image sequence, and extracting temperature fluctuation amplitude data and phase delay data of each pixel point; identifying a defective hotspot area on the chip surface according to the amplitude data and the phase delay data; inputting image coordinates of the defective hotspot area into a space mapping relationship established based on a BGA ball grid array solder ball pitch and an array size, to obtain corresponding physical positions of the defective hotspot area in a BGA ball grid array physical coordinate system; and determining corresponding BGA solder ball physical numbers according to the physical positions and the array size and outputting the BGA solder ball physical numbers. The application realizes efficient and accurate positioning of BGA welding defects by converting resistance differences of BGA pads into measurable thermal signals and combining phase-locked thermal imaging and space mapping.

Description

Technical Field

[0001] This application relates to the field of semiconductor device testing technology, and in particular to a method and system for first-piece board inspection. Background Technology

[0002] With the increasing integration density and faster signal speed of memory integrated circuits, chips are now commonly packaged using fine-pitch BGA (ball grid array).

[0003] Existing detection methods include automated optical inspection, flying probe testing (or in-circuit testing), and system-level functional verification. Automated optical inspection relies on visual recognition of solder joint morphology, but BGA solder joints are completely obscured beneath the chip body and cannot be directly observed. Flying probe testing or in-circuit testing measures the continuity of circuit networks through probe contact, but can only detect open or short circuits, lacking effective identification capabilities for defects such as minute impedance anomalies and hidden cold solder joints caused by poor soldering. System-level functional verification can detect intermittent read / write errors, but once a fault occurs, engineers must check each BGA solder joint individually, requiring X-ray inspection or even destructive cross-section analysis to confirm the fault point. This makes the fault location and cause confirmation process for soldering defects on the first-piece board extremely time-consuming, severely slowing down the first-piece verification progress and failing to meet the needs of rapid iteration and production transition for memory products. Therefore, how to improve the detection efficiency and accuracy of soldering defects of memory integrated circuits on the first-piece board of memory modules is a technical problem that needs to be solved.

[0004] In view of the above, this application is hereby submitted. Summary of the Invention

[0005] The purpose of this application is to provide a first-piece board inspection method and system, which aims to improve the detection efficiency and accuracy of soldering defects of memory integrated circuits on the first-piece board of memory modules.

[0006] To address the aforementioned technical problems, this application provides a first-piece inspection method, employing the following technical solution: Acquire a sequence of thermal images showing the evolution of the surface of a memory chip over time under synchronous pulsed current excitation, with the pulsed current flowing through all the BGA solder joints under test beneath the memory chip. Phase-locked processing is performed on the temperature data of each pixel in the thermal image sequence as it changes over time, and the temperature fluctuation amplitude data and phase delay data of each pixel are extracted. Based on the temperature fluctuation amplitude data and phase delay data of each pixel, the defect hotspot areas on the surface of the memory chip are identified. The coordinates of the defect hotspot region in the image coordinate system are input into a pre-established spatial mapping relationship to obtain the physical location of the coordinates in the physical coordinate system of the BGA ball grid array of the memory chip. The spatial mapping relationship is established based on the solder ball spacing and array size of the BGA ball grid array. Determine the physical number of the BGA solder ball corresponding to the physical location based on the physical location and array size, and output the physical number.

[0007] To address the aforementioned technical problems, this application also provides a first-piece inspection system, which employs the following technical solution: A first-piece inspection system, comprising: The acquisition module is used to acquire a thermal image sequence of the surface of the memory chip evolving over time under synchronous pulsed current excitation, with the pulsed current flowing through all the BGA solder joints under test below the memory chip. The processing module is used to perform phase-locked processing on the temperature data of each pixel in the thermal image sequence as it changes over time, and to extract the temperature fluctuation amplitude data and phase delay data of each pixel. The identification module is used to identify defect hotspot areas on the surface of the memory chip based on the temperature fluctuation amplitude data and phase delay data of each pixel. The mapping module is used to input the coordinates of the defect hotspot area in the image coordinate system into a pre-established spatial mapping relationship, and obtain the physical position of the coordinates in the physical coordinate system of the BGA ball grid array of the memory chip. The spatial mapping relationship is established based on the solder ball spacing and array size of the BGA ball grid array. The determination module is used to determine the physical number of the BGA solder ball corresponding to the physical location based on the physical location and array size, and output the physical number.

[0008] To address the aforementioned technical problems, this application also provides a computer device that employs the following technical solution: A computer device includes a memory and a processor, the memory storing computer-readable instructions, the processor executing the computer-readable instructions to implement the steps of the first piece board detection method as described above.

[0009] To address the aforementioned technical problems, this application also provides a computer-readable storage medium, employing the technical solution described below: A computer-readable storage medium storing computer-readable instructions, which, when executed by a processor, implement the steps of the first piece board detection method as described above.

[0010] Compared with the prior art, this application has the following main advantages: The first-piece board inspection method disclosed in this application acquires a sequence of thermal images showing the evolution of the memory chip surface over time under synchronous pulsed current excitation, with the pulsed current flowing through all the BGA solder joints under the memory chip. By converting the invisible electrical connection quality issues of the BGA solder joints into measurable thermal signals, it provides a data foundation for subsequent defect identification and solves the problem of BGA solder joints being obscured and unable to be directly inspected optically.

[0011] Phase-locked processing is performed on the temperature data of each pixel in the thermal image sequence over time to extract the temperature fluctuation amplitude data and phase delay data of each pixel. This phase-locked processing accurately separates the subtle temperature rise caused by defective weld joints from the background thermal noise, improving the signal-to-noise ratio and detection sensitivity of the thermal signal, and enabling the effective identification of minute impedance anomalies such as hidden weld defects and microcracks.

[0012] Based on the temperature fluctuation amplitude data and phase delay data of each pixel, defect hotspot areas on the surface of the memory chip are identified. Automatic identification of defect hotspot areas is achieved through joint determination of two parameters, eliminating the need for manual inspection of each solder joint and significantly reducing false alarm and false negative rates.

[0013] By inputting the coordinates of the defect hotspot region in the image coordinate system into a pre-established spatial mapping relationship, the physical location of the corresponding coordinates in the physical coordinate system of the BGA ball grid array of the memory chip is obtained. This spatial mapping relationship is established based on the solder ball spacing and array size of the BGA ball grid array. This spatial mapping relationship accurately converts the abstract image hotspot location into its position in the chip's physical space, providing a coordinate transformation basis for the precise localization of defective solder balls.

[0014] Based on the physical location and array size, the physical number of the BGA solder ball corresponding to the physical location is determined and output. By matching the physical location with the specific solder ball physical number, the detection result is directly converted into a rework instruction that can be operated by engineers. This eliminates the time-consuming process of traditional detection that requires X-ray or cross-section analysis to confirm the fault point, fundamentally improving the detection efficiency and positioning accuracy of soldering defects on the first piece board. Attached Figure Description

[0015] To more clearly illustrate the solutions in this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is an exemplary system architecture diagram to which this application can be applied; Figure 2This is a flowchart of one embodiment of the first-piece inspection method according to this application; Figure 3 This is a schematic diagram of a structure of one embodiment of the first piece inspection system according to this application; Figure 4 This is a schematic diagram of the structure of one embodiment of the computer device according to this application. Detailed Implementation

[0017] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0018] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0019] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0020] like Figure 1 As shown, the system architecture 100 may include a first terminal device 101, a second terminal device 102, a third terminal device 103, a network 104, and a server 105. The network 104 serves as a medium for providing communication links between the first terminal device 101, the second terminal device 102, the third terminal device 103, and the server 105. The network 104 may include various connection types, such as wired or wireless communication links, or fiber optic cables, etc.

[0021] Users can use the first terminal device 101, the second terminal device 102, and the third terminal device 103 to interact with the server 105 via the network 104 to receive or send messages, etc. Various communication client applications can be installed on the first terminal device 101, the second terminal device 102, and the third terminal device 103, such as web browser applications, shopping applications, search applications, instant messaging tools, email clients, social platform software, etc.

[0022] The first terminal device 101, the second terminal device 102, and the third terminal device 103 can be various electronic devices with displays and support web browsing, including but not limited to smartphones, tablets, e-book readers, MP3 (Moving Picture Experts Group Audio Layer III) players, MP4 (Moving Picture Experts Group Audio Layer IV) players, laptops, and desktop computers, etc.

[0023] Server 105 can be a server that provides various services, such as a backend server that supports the pages displayed on the first terminal device 101, the second terminal device 102, and the third terminal device 103.

[0024] It should be noted that the first piece inspection method provided in this application embodiment is generally executed by a terminal device, and correspondingly, the first piece inspection system is generally set in the terminal device.

[0025] It should be understood that Figure 1 The number of terminal devices, networks, and servers shown is merely illustrative. Depending on implementation needs, any number of terminal devices, networks, and servers can be included.

[0026] Continue to refer to Figure 2 A flowchart of an embodiment of the first piece inspection method according to this application is shown. The first piece inspection method includes the following steps: Step S201: Obtain a thermal image sequence of the surface of the memory chip evolving over time under synchronous pulse current excitation, with the pulse current flowing through all the BGA solder joints under test below the memory chip.

[0027] In this embodiment, the first-piece board detection method operates on electronic equipment (e.g., Figure 1 The terminal device shown can send or receive data via wired or wireless connection. It should be noted that the aforementioned wireless connection methods may include, but are not limited to, 3G / 4G / 5G connections, Wi-Fi connections, Bluetooth connections, WiMAX connections, Zigbee connections, UWB (ultra-wide band) connections, and other currently known or future wireless connection methods.

[0028] The coordinate range pulse current refers to a current signal output in a periodic manner, whose waveform can be a rectangular wave or a sine wave, and the frequency range is typically 0.1Hz to 10Hz. In this embodiment, the pulse current is generated by a controllable pulse current source and injected into the BGA solder joint under the memory chip through a switching network and a test fixture. A BGA (Ball Grid Array) solder joint is a spherical solder node that enables electrical connection between the memory chip and the printed circuit board (PCB). It is located below the chip package body and arranged in an array, enabling signal transmission and power supply between the internal circuitry of the chip and the PCB.

[0029] Synchronous excitation refers to all BGA solder joints under test receiving the excitation of the pulse current at the same time. That is, the pulse current flows through each solder joint at the same time, so that each solder joint generates Joule heating under the same excitation conditions.

[0030] A thermal image sequence refers to a collection of infrared radiation images, acquired sequentially over time by an infrared thermal imager, reflecting the temperature distribution on the surface of a memory chip. The infrared thermal imager acquires infrared radiation signals from the chip surface at a frame rate more than twice the pulse current frequency (satisfying the Nyquist sampling theorem), converting these signals into temperature data to form a thermal image sequence that evolves over time. This sequence records the temperature value of each pixel on the chip surface at different times, reflecting the complete thermal diffusion process from the underlying BGA solder joints through the chip packaging material to the upper surface.

[0031] In this embodiment, the memory module first board is clamped onto a dedicated test fixture, which is electrically connected to a controllable pulse current source and a switching network via gold fingers or pre-reserved test points. Then, the switching network is configured via host computer control software, selecting a group of BGA solder joints to be tested (e.g., all BGA solder joints in the VDD power domain), connecting this group of solder joints in parallel to the pulse current source through the switching network. Next, the pulse current source is activated, outputting a rectangular wave pulse current at a preset frequency (e.g., 0.5Hz), which flows through all selected BGA solder joints. Simultaneously, an infrared thermal imager is activated, continuously acquiring infrared thermal images of the memory chip surface at a frame rate more than twice the pulse frequency (e.g., 10Hz), and storing the acquired thermal image sequence in real time.

[0032] It should be noted that during pulse current excitation, the memory chip itself should be kept in a powered-off state, meaning the internal logic circuits of the chip should not be working, and only the test current should flow through the target BGA solder joints. This avoids interference from the chip's heat generation during operation, which could affect the thermal image acquisition. Specifically, the control pins of the memory chip (such as the chip select signal CE, write enable signal WE, etc.) should be set to an inactive level, so that the internal memory cells and control circuits of the chip are in a non-working state.

[0033] Step S202: Perform phase-locked processing on the temperature data of each pixel in the thermal image sequence as it changes over time, and extract the temperature fluctuation amplitude data and phase delay data of each pixel.

[0034] Coordinate-range phase-locked loop (PLL) processing is a signal processing method that uses the excitation frequency of a pulsed current as a reference frequency to perform correlation operations on the time-temperature curve of each pixel in a thermal image sequence. Its core principle is as follows: because the pulsed current periodically excites the BGA solder joints at a fixed frequency, the Joule heat generated by the solder joints also changes periodically at the same frequency. This thermal signal is conducted from the solder joints through the chip package to the surface, retaining a periodic component with the same excitation frequency in the temperature response of the chip surface. PLL processing utilizes this characteristic to correlate and integrate the temperature time series of each pixel with the sine and cosine signals of the reference frequency, respectively, to extract the amplitude and phase components of the temperature fluctuation of that pixel that are in sync with the excitation frequency.

[0035] Temperature fluctuation amplitude data refers to the magnitude of the periodic temperature fluctuation of each pixel over time, measured in degrees Celsius (°C). It reflects the intensity of the heat generation power of the underlying solder joint at the corresponding pixel location. The temperature fluctuation amplitude of a normal solder joint is uniformly distributed on the image. However, solder joints with welding defects (such as cold solder joints, microcracks, etc.) have increased contact resistance and Joule heating power, resulting in a correspondingly higher temperature fluctuation amplitude of the pixels on the chip surface above them, which is represented by a bright area on the amplitude image.

[0036] Phase delay data refers to the phase lag angle of temperature fluctuation at each pixel relative to the pulse current excitation signal, measured in degrees (°) or radians (rad). It reflects the time required for heat waves to travel from the underlying solder joint through the chip packaging material to the chip surface. Defects of different depths and solder joints with different thermal resistance characteristics will exhibit different phase delay characteristics.

[0037] In this embodiment, the thermal image sequence acquired in step S201 is used as input data. For each pixel, its temperature-time variation data sequence is phase-locked demodulated with the excitation frequency of the pulse current. Specifically, the temperature data sequence is correlated and integrated with a sine reference signal and a cosine reference signal with frequencies equal to the excitation frequency to obtain in-phase and quadrature components. The temperature fluctuation amplitude and phase delay of the pixel can be determined based on the in-phase and quadrature components. By performing the above operation on all pixels in the thermal image sequence, the temperature fluctuation amplitude data and phase delay data of each pixel can be obtained.

[0038] Phase-locked loop (PLL) processing can accurately separate the minute temperature changes (which may be only a few degrees Celsius) caused by defective solder joints from the interference caused by background thermal noise, ambient thermal radiation, and thermal diffusion of chip materials, significantly improving the signal-to-noise ratio and detection sensitivity of thermal signals.

[0039] Step S203: Based on the temperature fluctuation amplitude data and phase delay data of each pixel, identify the defect hotspot areas on the surface of the memory chip.

[0040] The defect hotspot region in the coordinate range refers to the area on the surface of the memory chip where the temperature fluctuation amplitude is abnormally high and accompanied by abnormal phase delay. This region corresponds to the location of the BGA solder joint below which there are soldering defects (such as cold solder joints, microcracks, etc.). Due to the increased contact resistance, defective solder joints generate higher Joule heat power under the same pulse current excitation. At the same time, the heat conduction path is changed due to the defect, so the time delay for heat to reach the chip surface is also different from that of normal solder joints.

[0041] Specifically, an amplitude image can be generated based on the temperature fluctuation amplitude data of each pixel. An amplitude image is a two-dimensional image with the pixel location as the horizontal and vertical axes and the temperature fluctuation amplitude of that pixel as the pixel grayscale value, reflecting the distribution of temperature fluctuation intensity at different locations on the chip surface. In the amplitude image, the area corresponding to normal solder joints is displayed as a uniform background grayscale, while the corresponding location above defective solder joints appears as a bright spot due to increased heat generation.

[0042] A phase image can be generated based on the phase delay data of each pixel. A phase image is a two-dimensional image with the pixel position as the horizontal and vertical axes and the phase delay value as the pixel's grayscale value, reflecting the time delay of heat wave arrival at different locations on the chip surface. In the phase image, the area above defective solder joints shows a characteristic phase delay due to changes in the heat conduction path.

[0043] When identifying defect hotspots, one can determine the region whose amplitude exceeds a set threshold in the amplitude image alone, or by combining the amplitude and phase images for a two-parameter joint determination—taking the intersection of amplitude and phase anomaly regions, i.e., the continuous region formed by pixels that simultaneously meet both amplitude and phase threshold conditions is identified as a defect hotspot. This two-parameter joint determination can significantly reduce the false alarm rate.

[0044] In this embodiment, an amplitude image is first generated based on the temperature fluctuation amplitude data of each pixel, and a phase image is generated based on the phase delay data of each pixel.

[0045] Subsequently, an amplitude threshold is set in the amplitude image. Specifically, the background region in the amplitude image (i.e., a uniform region with low temperature fluctuation amplitude, corresponding to normal solder joints) is determined, and the average value and standard deviation of the amplitude of each pixel in this region are calculated. The sum of the average value and the standard deviation by a preset multiple is set as the amplitude threshold. Pixels with temperature fluctuation amplitudes greater than this amplitude threshold are extracted from the amplitude image to form candidate hotspot regions.

[0046] A phase threshold is set in the phase image. Specifically, the background region in the phase image is determined, and the average value and standard deviation of the phase delay of each pixel in this region are calculated. The sum of the average value and the standard deviation by a preset multiple is set as the phase threshold. Pixels with a phase delay greater than this phase threshold are extracted from the phase image.

[0047] Finally, pixels that simultaneously belong to candidate hotspot regions and have a phase delay greater than a phase threshold are extracted. Continuous regions formed by adjacent pixels satisfying these conditions are identified as defect hotspot regions. When multiple continuous regions exist, each region is identified as an independent defect hotspot region, corresponding to one or a group of adjacent defective solder joints.

[0048] Step S204: Input the coordinates of the defect hotspot region in the image coordinate system into the pre-established spatial mapping relationship to obtain the physical position of the coordinates in the physical coordinate system of the BGA ball grid array of the memory chip. The spatial mapping relationship is established based on the solder ball spacing and array size of the BGA ball grid array.

[0049] The pixel position in the coordinate range image refers to the location of the defect hotspot area in the image acquired by the infrared thermal imager, expressed in pixels. This position can be the center pixel position of the area, or it can be the set of all pixel positions in the area.

[0050] The physical space of a BGA ball grid array refers to a two-dimensional space established based on the physical layout of the BGA solder ball array of a memory chip. Its origin can be set to a corner point of the array (such as the center of the first solder ball in the upper left corner). The horizontal and vertical axes correspond to the row and column directions of the solder ball array, respectively, and the position unit is the physical length unit (such as millimeters).

[0051] Spatial mapping refers to the mathematical transformation between pixel positions in an image and their physical positions in the physical space of a BGA ball grid array. It establishes a correspondence between the visual detection space and the physical solder ball space. This mapping is based on the solder ball pitch and array size of the BGA ball grid array. The solder ball pitch refers to the physical distance between the centers of two adjacent BGA solder balls, for example, 0.8 mm; the array size refers to the number of BGA solder balls in the row and column directions, for example, 10 × 10.

[0052] Specifically, the spatial mapping relationship consists of two parts: a scaling factor and an offset. The scaling factor refers to the correspondence between a unit pixel distance in the image and a unit physical distance in physical space; the offset refers to the relative positional deviation between the image origin and the physical space origin. Through this mapping relationship, any pixel position in the image can be converted into a specific physical position in physical space.

[0053] In this embodiment, the spatial mapping relationship needs to be established before implementing this step. Specifically, the solder ball pitch (e.g., 0.8 mm) and array size (e.g., 10 × 10) of the BGA ball grid array of the memory chip are obtained. Next, the infrared thermal imager is calibrated to determine the magnification and image resolution of the optical system, thereby establishing a proportionality coefficient between the unit pixel distance in the image and the unit physical distance in physical space (e.g., each pixel corresponds to 0.05 mm in physical space). Simultaneously, by identifying the characteristic corner points or marker points of the chip package in the image, the offset between the image origin and the physical space origin is determined (e.g., if the pixel position corresponding to the center of the solder ball at the upper left corner of the chip in the image is (120, 85), then the offset is 120 pixels in the horizontal direction and 85 pixels in the vertical direction). Based on the above proportionality coefficient and offset, the spatial mapping relationship is established and stored in the detection system database.

[0054] As an optional implementation, this spatial mapping relationship can be achieved through the following transformation: Let the x-coordinate of the pixel position in the image be X. I The vertical axis is Y I The x-coordinate of the physical location in physical space is X. P The vertical axis is Y P The scaling factor is k, and the offset of the image origin relative to the physical space origin is X. O Y O Then the physical location can be determined by X. P =k×(X I -X O ), Y P =k×(Y I -Y O )Sure.

[0055] When step S204 is executed, the pixel position of the defect hotspot region identified in step S203 (e.g., the position of the center pixel of the region) is input into the pre-established spatial mapping relationship and mapped to the physical position in the physical space of the BGA ball grid array according to the above transformation method.

[0056] Step S205: Determine the physical number of the BGA solder ball corresponding to the physical location based on the physical location and array size, and output the physical number.

[0057] The physical coordinate range identifier (PCO) is a unique identifier for each solder ball in a BGA ball grid array. It typically uses the JEDEC (Joint Electron Device Engineering Council) standard naming convention, such as using letters to represent rows (A, B, C…), numbers to represent columns (1, 2, 3…), or a combination of row and column numbers (e.g., A3, B7, C2). The PCO allows engineers to precisely locate the specific solder ball requiring rework.

[0058] The array size provides information about the number of solder balls in the row and column directions, as well as the arrangement order of the solder balls. Based on the array size, the physical number of each solder ball in the BGA ball grid array and its corresponding coordinate range in physical space can be determined.

[0059] The process of determining the physical number corresponding to the physical location is as follows: match the physical location obtained in step S204 with the coordinate range of each solder ball, determine which solder ball's coordinate range the physical location falls into, and thus obtain the physical number of the solder ball.

[0060] In this embodiment, the physical space number and coordinate range of each BGA solder ball are obtained according to the array size. Specifically, according to the JEDEC standard naming rules, each row in the array is assigned a letter number (e.g., row 1 is A, row 2 is B, ...), and each column is assigned a number number (e.g., column 1 is 1, column 2 is 2, ...), thereby assigning a unique physical number to each solder ball. For example, solder ball A3 represents the solder ball in row A and column 3.

[0061] Simultaneously, the physical location of each solder ball's center in physical space is determined based on the solder ball spacing. The rectangular area centered on each solder ball's center and bounded by half the solder ball spacing is the coordinate range of that solder ball.

[0062] Match the physical location obtained in step S204 with the coordinate range of each BGA solder ball to determine which solder ball's coordinate range the physical location falls into, and then determine the physical number of the solder ball as the physical number of the BGA solder ball corresponding to that physical location.

[0063] Finally, the physical number is output. Specifically, the output can be displayed on the user interface of the inspection system, along with a test report (e.g., a text report or spreadsheet file) containing the physical number of the defective solder joint and the degree of abnormality, for direct use in subsequent rework operations.

[0064] This application acquires a sequence of thermal images showing the evolution of the surface of a memory chip over time under synchronous pulsed current excitation, with the pulsed current flowing through all the BGA solder joints under test beneath the memory chip. By converting the invisible electrical connection quality issues of the BGA solder joints into measurable thermal signals, it provides a data foundation for subsequent defect identification and solves the problem of BGA solder joints being obscured and unable to be directly optically inspected.

[0065] Phase-locked processing is performed on the temperature data of each pixel in the thermal image sequence over time to extract the temperature fluctuation amplitude data and phase delay data of each pixel. This phase-locked processing accurately separates the subtle temperature rise caused by defective weld joints from the background thermal noise, improving the signal-to-noise ratio and detection sensitivity of the thermal signal, and enabling the effective identification of minute impedance anomalies such as hidden weld defects and microcracks.

[0066] Based on the temperature fluctuation amplitude data and phase delay data of each pixel, defect hotspot areas on the surface of the memory chip are identified. Automatic identification of defect hotspot areas is achieved through joint determination of two parameters, eliminating the need for manual inspection of each solder joint and significantly reducing false alarm and false negative rates.

[0067] By inputting the coordinates of the defect hotspot region in the image coordinate system into a pre-established spatial mapping relationship, the physical location of the corresponding coordinates in the physical coordinate system of the BGA ball grid array of the memory chip is obtained. This spatial mapping relationship is established based on the solder ball spacing and array size of the BGA ball grid array. This spatial mapping relationship accurately converts the abstract image hotspot location into its position in the chip's physical space, providing a coordinate transformation basis for the precise localization of defective solder balls.

[0068] Based on the physical location and array size, the physical number of the BGA solder ball corresponding to the physical location is determined and output. By matching the physical location with the specific solder ball physical number, the detection result is directly converted into a rework instruction that can be operated by engineers. This eliminates the time-consuming process of traditional detection that requires X-ray or cross-section analysis to confirm the fault point, fundamentally improving the detection efficiency and positioning accuracy of soldering defects on the first piece board.

[0069] In some optional implementations of this embodiment, the step of performing phase-locked processing on the temperature data of each pixel in the thermal image sequence that changes over time includes: Using the excitation frequency of the pulse current as a reference signal, correlation calculations are performed on the temperature data of each pixel to extract the temperature fluctuation amplitude data and phase delay data of each pixel at the excitation frequency.

[0070] The coordinate range excitation frequency refers to the repetition frequency of the pulse current output by the pulse current source, that is, the number of pulse cycles per unit time, measured in Hertz (Hz). In this embodiment, the excitation frequency is typically selected within the range of 0.1Hz to 10Hz, for example, 0.5Hz.

[0071] Reference signals refer to sine and cosine signals with the same frequency as the pulse current excitation frequency, and are used as reference signals in phase-locked loop processing.

[0072] Correlation operation refers to the process of integrating the temperature time series of each pixel with the reference signal in the time domain. Specifically, the products of the temperature time series with the sine and cosine reference signals are accumulated during the acquisition period to obtain the in-phase component and the quadrature component, respectively. The in-phase component and the quadrature component together constitute the phasor representation of the temperature fluctuation of that pixel at the excitation frequency.

[0073] In this embodiment, the thermal image sequence acquired in step S201 is used as input. For each pixel, its temperature change over time data sequence is correlated and integrated with a sinusoidal reference signal and a cosine reference signal with a frequency equal to the excitation frequency, respectively, to obtain in-phase and quadrature components. Both in-phase and quadrature components are numerical quantities; the former corresponds to the component in phase with the excitation signal in the temperature fluctuation, and the latter corresponds to the component orthogonal to the excitation signal. The temperature fluctuation amplitude and phase delay of the pixel can be determined through the in-phase and quadrature components. The above operation is performed on all pixels in the thermal image sequence to obtain the temperature fluctuation amplitude data and phase delay data for each pixel.

[0074] This application, through correlation calculations with reference to the excitation frequency, can accurately extract the subtle temperature changes generated by defective solder joints from strong background thermal noise, significantly improving the signal-to-noise ratio of the thermal signal, and enabling reliable detection of even slight temperature rises of a few degrees Celsius.

[0075] In some optional implementations of this embodiment, the step of identifying defect hotspot areas on the surface of the memory chip based on the temperature fluctuation amplitude data and phase delay data of each pixel includes: An amplitude image is generated based on the temperature fluctuation amplitude data of each pixel. Pixels with temperature fluctuation amplitudes greater than the amplitude threshold are extracted from the amplitude image to form candidate hotspot regions. A phase image is generated based on the phase delay data of each pixel, and pixels with a phase delay greater than the phase threshold are extracted from the phase image. A continuous region consisting of pixels that simultaneously belong to the candidate hotspot region and whose phase delay is greater than the phase threshold is identified as a defect hotspot region.

[0076] A coordinate range amplitude image is a two-dimensional grayscale image. Its horizontal and vertical axes correspond to the row and column directions of the chip surface in image space, respectively. The grayscale value of each pixel represents the amplitude of temperature fluctuation at that location. The amplitude image intuitively reflects the intensity distribution of temperature fluctuations at various points on the chip surface. Normal areas present a uniform background grayscale, while defective areas appear as bright spots.

[0077] The amplitude threshold is a critical value used to distinguish normal pixels from pixels suspected of defects. It can be set adaptively, based on the amplitude statistical characteristics of the background region in the amplitude image, or by using a fixed threshold. Pixels with temperature fluctuation amplitudes greater than the amplitude threshold indicate that the heat generation power at that location is significantly higher than normal, making them potential candidates for defects.

[0078] A phase image is a two-dimensional grayscale image where the horizontal and vertical axes correspond to the row and column directions of the chip surface in image space, respectively. The grayscale value of each pixel represents the phase delay at that location. The phase image reflects the time delay distribution of heat wave arrival at various points on the chip surface.

[0079] The phase threshold is a critical phase delay value used to distinguish normal pixels from suspected defective pixels. It can be set adaptively or with a fixed threshold. Pixels with a phase delay greater than the phase threshold indicate an abnormal change in the heat conduction path at that location, and are also considered potential defect candidates.

[0080] In this embodiment, the temperature fluctuation amplitude data of each pixel is first arranged by pixel to generate an amplitude image, and the phase delay data of each pixel is arranged by pixel to generate a phase image.

[0081] Subsequently, an amplitude threshold is set in the amplitude image. As an optional implementation, the average value and standard deviation of the amplitude of each pixel within the background region (i.e., a uniform region with low amplitude) in the amplitude image can be calculated, and the sum of the average value and the standard deviation of a preset multiple (e.g., 3 times) is set as the amplitude threshold. Pixels with amplitudes greater than this amplitude threshold are extracted from the amplitude image to form candidate hotspot regions.

[0082] A phase threshold is set in the phase image. As an optional implementation, the average value and standard deviation of the phase delay of each pixel within the background region of the phase image can be calculated, and the sum of the average value and the standard deviation of a preset multiple (e.g., 3 times) is set as the phase threshold. Pixels with a phase delay greater than this phase threshold are extracted from the phase image.

[0083] Finally, the intersection of the candidate hotspot region with the pixels whose phase delay is greater than the phase threshold is taken, and connectivity analysis is performed on the intersection to divide the adjacent pixels into continuous regions. Each continuous region is identified as a defect hotspot region.

[0084] This application employs both amplitude and phase conditions for joint determination, utilizing amplitude to identify abnormal heating areas and phase to distinguish defect types and suppress artifacts caused by changes in surface emissivity, significantly reducing the false alarm rate and improving detection reliability.

[0085] In some optional implementations of this embodiment, the step of identifying defect hotspot areas on the surface of the memory chip based on the temperature fluctuation amplitude data and phase delay data of each pixel includes: An amplitude image is generated based on the temperature fluctuation amplitude data of each pixel. In the amplitude image, the temperature fluctuation amplitude of each pixel is compared with the reference amplitude of the corresponding pixel in the reference amplitude image pixel by pixel to obtain the amplitude difference value of each pixel. Pixels with amplitude difference values ​​greater than the amplitude difference threshold are grouped into candidate hotspot regions; A phase image is generated based on the phase delay data of each pixel, and pixels with a phase delay greater than the phase threshold are extracted from the phase image. A continuous region consisting of pixels that simultaneously belong to the candidate hotspot region and whose phase delay is greater than the phase threshold is identified as a defect hotspot region.

[0086] The coordinate range reference amplitude image refers to the amplitude image obtained by acquiring and processing a known good first-piece board (i.e., a verified sample board with all BGA solder joints passing) under the same test conditions. The reference amplitude image represents the typical amplitude distribution of normal solder joints under standard process conditions, reflecting the inherent system thermal characteristics distribution of the chip package and substrate materials. This reference amplitude image is pre-stored in the testing system's database as a comparison benchmark for subsequent batch product testing.

[0087] Pixel-by-pixel differential refers to subtracting the amplitude values ​​at the same pixel position in the amplitude image of the current test board from those in the reference amplitude image. This differential operation eliminates systematic thermal distribution deviations such as uneven chip package thickness and differences in the thermal diffusion characteristics of substrate materials.

[0088] The amplitude difference value refers to the difference obtained from the above pixel-by-pixel difference operation. When the amplitude difference value is positive and large, it indicates that the heat generation power at the current pixel is significantly higher than the normal level, which is a suspected defect candidate.

[0089] The amplitude difference threshold is a critical value used to determine whether the amplitude difference value indicates the presence of a defect. This threshold can be set based on the noise statistics of the reference amplitude image, for example, by setting it to a preset multiple of the standard deviation of the background area of ​​the reference amplitude image; or it can be set to a fixed percentage tolerance.

[0090] In this embodiment, a pre-stored reference amplitude image is first read from the detection system database. This reference amplitude image is obtained by acquiring and processing a good first piece board that has been confirmed to have qualified solder joints through destructive cross-section analysis during the production line initialization or process verification stage, under the exact same conditions as the current test (the same pulse current parameters, the same infrared thermal imager settings, and the same ambient temperature).

[0091] Subsequently, the amplitude data of each pixel on the current test board are arranged pixel by pixel to generate a current amplitude image. The current amplitude image and the reference amplitude image are then compared pixel by pixel at the same pixel location to obtain the amplitude difference value for each pixel. An amplitude difference threshold is set. Specifically, the standard deviation of the background region (i.e., the uniform region with lower amplitude) in the reference amplitude image can be calculated, and a preset multiple (e.g., 3 times) of this standard deviation is set as the amplitude difference threshold. Pixels with amplitude difference values ​​greater than the amplitude difference threshold are extracted to form candidate hotspot regions.

[0092] Simultaneously, a phase image is generated based on the phase delay data of each pixel, and a phase threshold is set in the same way to extract pixels with a phase delay greater than the phase threshold.

[0093] The intersection of the candidate hotspot region with the pixels whose phase delay is greater than the phase threshold is taken, and the connectivity analysis is performed on the intersection. The adjacent pixels are divided into continuous regions, and each continuous region is identified as a defect hotspot region.

[0094] This application effectively eliminates the influence of systematic thermal distribution deviations such as uneven chip packaging thickness and differences in thermal diffusion of substrate materials on the detection results by using a reference amplitude image for pixel-by-pixel differential comparison. It adapts to the differences in baseline thermal characteristics of different product batches, thereby improving the adaptability and accuracy of the detection.

[0095] In some optional implementations of this embodiment, the step of identifying defect hotspot areas on the surface of the memory chip based on the temperature fluctuation amplitude data and phase delay data of each pixel includes: Generate an amplitude image based on the temperature fluctuation amplitude data of each pixel; In the amplitude image, the region formed by pixels whose temperature fluctuation amplitude is lower than the preset background judgment value is defined as the background region; Calculate the standard deviation of the temperature fluctuation amplitude in the background area, and set the preset multiple of the standard deviation as the amplitude threshold. Pixels with temperature fluctuation amplitudes greater than an amplitude threshold are extracted from the amplitude image to form candidate hotspot regions; A phase image is generated based on the phase delay data of each pixel, and pixels with a phase delay greater than the phase threshold are extracted from the phase image. A continuous region consisting of pixels that simultaneously belong to the candidate hotspot region and whose phase delay is greater than the phase threshold is identified as a defect hotspot region.

[0096] The background region of the coordinate range refers to the area in the amplitude image where the temperature fluctuation amplitude is at a low level and is uniformly distributed. This region corresponds to the solder joints below the chip surface that are normal and do not have obvious heating abnormalities. The background region represents the baseline level of the amplitude image, and its amplitude is mainly determined by the thermal capacity and thermal resistance of the chip packaging material, the ambient temperature, and the inherent noise of the infrared thermal imager.

[0097] The preset background judgment value is a pre-defined fixed amplitude threshold used to distinguish background pixels from non-background pixels. This value can be predetermined based on the known statistical characteristics of the amplitude image of the first good product board, such as taking the average or median multiple of the amplitude of all pixels in the amplitude image of the good product, or taking the amplitude corresponding to the right inflection point of the main peak in the amplitude histogram. In implementation, this value can be preset in the detection system parameter table according to different chip models and package sizes.

[0098] Standard deviation refers to the dispersion of the temperature fluctuation amplitude of all pixels in the background area relative to its average value, reflecting the noise level of the background area. A preset multiple of the standard deviation (e.g., 3 times) is set as the sum of the average amplitude of the background area. This threshold represents the upper limit of the normal solder joint amplitude fluctuation. Pixels exceeding this threshold are suspected defect candidates with amplitudes significantly higher than normal levels.

[0099] In this embodiment, the temperature fluctuation amplitude data of each pixel is first arranged by pixel to generate an amplitude image.

[0100] Subsequently, a preset background judgment value is read from the detection system parameter table. Each pixel in the amplitude image is traversed, and the region formed by pixels whose temperature fluctuation amplitude is lower than the background judgment value is determined as the background region. Within the background region, the average value and standard deviation of the amplitude of all pixels are calculated. The sum of the average value and the standard deviation of a preset multiple (e.g., 3 times) is set as the amplitude threshold. Pixels with amplitudes greater than this threshold are extracted from the amplitude image to form candidate hotspot regions.

[0101] Simultaneously, a phase image is generated based on the phase delay data of each pixel. The phase threshold is set in the same way: a background region is determined in the phase image (the pixel positions of the background region in the amplitude image can be used), the average value and standard deviation of the phase delay in this region are calculated, and the sum of the average value and the standard deviation of a preset multiple (e.g., 3 times) is set as the phase threshold. Pixels with a phase delay greater than the phase threshold are extracted.

[0102] The intersection of the candidate hotspot region with the pixels whose phase delay is greater than the phase threshold is taken, and the connectivity analysis is performed on the intersection. The adjacent pixels are divided into continuous regions, and each continuous region is identified as a defect hotspot region.

[0103] This application adaptively calculates the amplitude threshold based on the statistical characteristics of the background region of the current amplitude image itself, which can complete the defect judgment without relying on the external reference image. It adapts to test scenarios with changes in environmental noise and different ambient temperatures, avoids missed detections or false detections caused by fixed thresholds, and enables the detection system to have self-calibration capabilities.

[0104] In some optional implementations of this embodiment, the steps prior to inputting the coordinates of the defect hotspot region in the image coordinate system into the pre-established spatial mapping relationship include: Obtain the solder ball pitch and array size of the BGA ball grid array of the memory chip; Based on the solder ball spacing and array size, establish the proportional relationship between the unit pixel distance in the image coordinate system and the unit physical distance in the BGA ball grid array physical coordinate system, as well as the offset between the origin of the image coordinate system and the origin of the physical coordinate system. Based on the proportional relationship and the offset, the spatial mapping relationship is obtained.

[0105] The solder ball pitch, or coordinate range, refers to the physical distance between the centers of two adjacent solder balls in a BGA ball grid array. It is typically provided in the chip package datasheet and is measured in millimeters (mm), such as 0.8mm or 1.0mm. The solder ball pitch is a fundamental parameter for establishing the mapping relationship between image space and physical space.

[0106] Array size refers to the number of solder balls in the row and column directions of a BGA ball grid array. For example, 10×10 means that the array has 10 solder balls in the row direction and 10 solder balls in the column direction, for a total of 100 solder balls. Array size provides a logical framework for solder ball numbering.

[0107] The scaling factor refers to the correspondence between the unit pixel distance in the image and the unit physical distance in the physical space of the BGA ball grid array. It can be determined by the ratio of the solder ball pitch to the number of pixels with the corresponding solder ball pitch in the image, so that any pixel distance in the image can be converted into a physical distance.

[0108] Offset refers to the relative positional deviation between the image origin and the physical space origin, including offsets in the horizontal and vertical directions. Since the field of view center of an infrared thermal imager may not perfectly coincide with the geometric center of the chip package, and there may be slight angular and positional deviations in chip mounting, it is necessary to determine the offset to achieve a precise correspondence between image pixel positions and physical positions.

[0109] In this embodiment, the solder ball spacing and array size of the BGA ball grid array of the memory chip under test are first obtained from the product parameter database of the testing system or user input.

[0110] Subsequently, the infrared thermal imager was calibrated. During the calibration process, a standard calibration plate of known size was placed on the inspection station, and the infrared thermal imager was used to acquire images of the calibration plate. Based on the correspondence between the feature points of known physical spacing on the calibration plate and the corresponding pixels in the image, the ratio coefficient between the unit pixel distance in the image and the unit physical distance in physical space was calculated.

[0111] Simultaneously, by identifying corner markers or edge features of the chip package in the thermal image, the precise position of the chip in the image is determined. This position is then compared with the physical dimensions provided in the chip package specifications to calculate the offset between the image origin and the physical space origin. This offset may vary due to slight differences in position during each clamping, so rapid pre-alignment can be performed to correct the offset before actual inspection.

[0112] A spatial mapping relationship is established based on the aforementioned proportional coefficients and offsets, and stored as parameters in the detection system for subsequent steps to call.

[0113] This application establishes a spatial mapping relationship in advance, corresponding the abstract image pixel position to the specific physical spatial position, laying the foundation for the subsequent accurate conversion from image position to physical solder ball number, and ensuring positioning accuracy.

[0114] In some optional implementations of this embodiment, the step of inputting the coordinates of the defect hotspot region in the image coordinate system into a pre-established spatial mapping relationship to obtain the physical location of the coordinates in the physical coordinate system of the BGA ball grid array of the memory chip includes: Obtain the coordinates of the center pixel of the defect hotspot region in the image coordinate system; The coordinates of the center pixel are input into the spatial mapping relationship. Based on the ratio and offset between the image coordinate system and the BGA ball grid array physical coordinate system, the spatial mapping relationship maps the coordinates of the center pixel to the physical coordinates in the BGA ball grid array physical coordinate system. The physical coordinates are used to determine the physical location.

[0115] The center pixel of the coordinate range refers to the pixel at the geometric center of the defect hotspot region. For a continuous defect hotspot region consisting of multiple pixels, the position of its center pixel can be obtained by calculating the average position of all pixels in the region. The center pixel represents a representative position of the defect hotspot region; mapping the center pixel to physical space yields the approximate center position of the defective solder ball.

[0116] Physical location refers to the specific position of the center pixel of the defect hotspot area in the physical space of the BGA ball grid array. It is expressed in physical length units (such as millimeters) and accurately indicates the position of the defect in the chip's physical space.

[0117] In this embodiment, the identified defect hotspot region is used as input. The average value of the positions of all pixels in the region is calculated to obtain the position of the center pixel.

[0118] Subsequently, the parameters of the pre-established and stored spatial mapping relationship, including the scaling factor and offset, are read. The position of the center pixel is then substituted into the spatial mapping relationship for transformation to obtain the corresponding physical position.

[0119] The calculated physical location is determined as the physical location of the defect hotspot region in the physical space of the BGA ball grid array.

[0120] This application uses the center pixel of the defect hotspot area to represent the entire hotspot area for mapping, and only a single transformation is needed to complete the localization. It has low computational load and fast processing speed, and is suitable for rapid screening scenarios with high real-time requirements.

[0121] In some optional implementations of this embodiment, the step of determining the physical number of the BGA solder ball corresponding to the physical location based on the physical location and array size includes: Based on the array size, obtain the number and coordinate range of each BGA solder ball in the physical coordinate system of the BGA ball grid array; Match the physical location with the coordinate range of each BGA solder ball to determine the number of the BGA solder ball corresponding to the coordinate range in which the physical location falls, and use this number as the physical number of the BGA solder ball corresponding to the physical location.

[0122] The coordinate range number refers to the unique identifier of each solder ball in the BGA ball grid array, which is represented by a combination of letters and numbers according to the JEDEC standard naming rules. Specifically, the rows of the array are numbered sequentially with letters A, B, C, ..., and the columns are numbered sequentially with numbers 1, 2, 3, ...

[0123] The coordinate range refers to the area occupied by each BGA solder ball in physical space. Since solder balls have actual geometric dimensions in physical space, the coordinate range of each solder ball can be defined with its center position as the reference and half the distance between solder balls as the boundary.

[0124] Matching the physical location with the coordinate range of each BGA solder ball means comparing the obtained physical location with the coordinate range of each solder ball to determine which solder ball's coordinate range the physical location falls within.

[0125] In this embodiment, each solder ball is assigned a physical number according to the array size and the JEDEC standard naming rules.

[0126] Simultaneously, the position of the center of each solder ball in physical space is calculated based on the solder ball spacing, and a rectangular area centered on each solder ball and bounded by half the solder ball spacing is used as the coordinate range of that solder ball. Using half the solder ball spacing as the boundary ensures that the coordinate range of the solder balls continuously covers the entire array area and does not overlap.

[0127] The obtained physical locations are matched with the coordinate range of each solder ball: it is determined whether the horizontal axis value of the physical location falls within the horizontal axis range of a certain solder ball and whether the vertical axis value falls within the vertical axis range of that solder ball. When a solder ball that meets the conditions is found, the physical number of that solder ball is determined as the physical number of the BGA solder ball corresponding to that physical location.

[0128] When multiple defect hotspots exist simultaneously, the above matching process is performed on each defect hotspot to obtain its corresponding set of physical numbers.

[0129] This application converts abstract location information into physical solder ball numbers that engineers can directly manipulate by matching physical locations with the coordinate range of each solder ball. The generated defect list can be directly used to guide subsequent rework operations, saving the time-consuming process of manually comparing drawings after traditional inspection.

[0130] In some optional implementations of this embodiment, the step of inputting the coordinates of the defect hotspot region in the image coordinate system into a pre-established spatial mapping relationship to obtain the physical location of the coordinates in the physical coordinate system of the BGA ball grid array of the memory chip includes: Obtain the set of coordinates of all pixels in the defect hotspot region within the image coordinate system; Input the coordinates of each pixel in the coordinate set into the spatial mapping relationship to obtain the physical coordinate set corresponding to each pixel coordinate in the physical coordinate system of the BGA ball grid array. Calculate the center position of the physical coordinate set and determine the center position as the physical location.

[0131] The coordinate range coordinate set refers to the set of all pixel positions contained in the defect hotspot region in the image, which fully describes the shape, size and location information of the defect hotspot region.

[0132] The physical coordinate set refers to the set of physical locations obtained by transforming the position of each pixel in the coordinate set through spatial mapping relationships, reflecting the complete shape and range of the defect hotspot area in physical space.

[0133] The center position refers to the average position of all physical positions in the physical coordinate set. It represents the average position of the entire defect hotspot area in physical space and serves as a representative position for subsequent solder ball number matching.

[0134] In this embodiment, the identified defect hotspot region is used as input. The positions of all pixels in the image within the defect hotspot region are obtained, forming a coordinate set.

[0135] Read the parameters of the pre-established and stored spatial mapping relationship, input the position of each pixel in the coordinate set into the spatial mapping relationship for transformation, and obtain the physical position corresponding to each pixel, thus forming a physical coordinate set.

[0136] Calculate the average position of all physical locations in the physical coordinate set, and determine the average position as the physical location of the defect hotspot region in the physical space of the BGA ball grid array.

[0137] This application fully utilizes the entire shape information of the region by mapping all pixels in the defect hotspot area and then taking the center position. Compared with mapping using only a single center pixel, it can effectively suppress the influence of image noise and single pixel positioning error on the mapping result, and improve the robustness and accuracy of physical position determination.

[0138] Based on the above embodiments, preferably, before acquiring the thermal image sequence, a switching circuit can be configured to perform group selection testing of BGA solder joints.

[0139] A switching circuit is a programmable circuit composed of a switching network that can selectively connect a pulse current source to BGA solder joints in a specific functional domain or channel group according to the control commands of the detection system. Specifically, each switch in the switching network corresponds to a set of solder joints (such as all VDD solder joints in the same VDD power domain, or all DQ solder joints in the same DQ data signal channel group). By controlling the on and off states of the switches, the path selection of the test current is achieved.

[0140] When performing group selection testing, the host computer control software sends control commands to the switching circuit to select a power domain (e.g., all BGA solder joints in the VDD power domain) or a signal channel group (e.g., solder joints in all DQ data signal channels), so that all BGA solder joints in the group are synchronously subjected to pulse current, thereby achieving independent testing of different regions.

[0141] The advantage of group selection testing is that it avoids the mutual thermal interference and power overload problems caused by testing all solder joints on the board at the same time, and improves the targeting and flexibility of testing. At the same time, by separating the power domain and the signal channel, solder joints of different functional networks can be tested separately, which makes it easier to distinguish the defect type (such as cold solder joints of power supply joints and cold solder joints of signal joints), and improves the efficiency of fault analysis.

[0142] Based on the above embodiments, preferably, during pulse current excitation, the memory chip itself should be kept in a power-off state, and only the test current should flow through the target BGA solder joint.

[0143] Power-off state control refers to controlling the enable pins of the memory chip (such as chip select signal CE, write enable signal WE, output enable signal OE, etc.) to be at an invalid level, so that the internal memory cells, control circuits, input / output buffers and other logic circuits of the chip are all in a non-working state and do not generate their own operating heat.

[0144] When implementing this control, before the pulse current source is activated, the detection system sends a control signal to the memory chip through the control signal pins on the test fixture, setting the enable pins such as CE, WE, and OE to an invalid level to ensure that the internal logic of the chip is completely powered off. This power-off state is maintained during the pulse current excitation until the thermal image acquisition is completed, at which point the normal power supply to the chip is restored.

[0145] The advantages of chip power-off control are that it eliminates the interference of internal logic circuit heating on the thermal signal of solder joint defects during normal chip operation, significantly improving the signal-to-noise ratio of thermal images; at the same time, it avoids temperature baseline drift caused by chip heating, ensuring that the phase-locked loop algorithm can accurately extract the slight temperature rise caused by solder joint defects and prevent missed detection.

[0146] Based on the above embodiments, preferably, the series and parallel topology of the BGA solder joint network can be flexibly configured.

[0147] Configurable series-parallel topology refers to the ability to connect a selected group of BGA solder joints to a pulsed current source in either series or parallel configuration via the switching network. In parallel topology, the total current output from the pulsed current source is distributed to each parallel branch, ensuring that the voltage across each solder joint is the same, and each solder joint generates Joule heat independently, making it suitable for synchronous and rapid screening of the entire group. In series topology, the pulsed current flows sequentially through each solder joint, with the current magnitude being completely consistent, facilitating direct comparison of the relative heating power of each solder joint and eliminating the influence of current fluctuations on quantitative comparison.

[0148] During implementation, the detection system selects the series-parallel topology by controlling the switch states in the switch network based on the number of solder joints to be tested, their impedance characteristics, and the detection requirements. For example, when detecting the VDD power domain of a DDR5 memory module, since there are many solder joints (possibly dozens), a parallel connection is used to simultaneously connect all VDD solder joints to the pulse current source, enabling the entire group of solder joints to be detected in a single imaging test. If the detection signal DQ channel group (fewer in number and requiring precise comparison) is used, a series connection can be used to ensure that the current of each DQ solder joint is consistent.

[0149] Based on the above embodiments, preferably, the pulse current adopts a low-frequency rectangular wave or a sine wave.

[0150] The optimization of pulse current parameters involves three aspects: frequency, waveform, and amplitude. Regarding frequency, a low-frequency range of 0.1Hz to 10Hz is used. This frequency selection ensures sufficient heat diffusion, allowing enough time for heat to conduct from the underlying solder joints to the chip surface to form a detectable temperature field, while avoiding attenuation of high-frequency heat waves in the chip material. For the waveform, a rectangular or sine wave is used, with clear periodicity, facilitating frequency reference and phase extraction for phase-locked loop (PLL) algorithms. Regarding the amplitude, the current amplitude is controlled within an intensity range that causes a temperature rise of several degrees Celsius (e.g., 3°C to 8°C) at the BGA solder joints. This balanced design ensures detectability by infrared thermal imagers (temperature rise above the thermal noise substrate) while avoiding excessive thermal stress that could damage the solder joints or chip, enabling non-destructive testing.

[0151] During implementation, the detection system selects the optimal combination of pulse current parameters from a parameter table based on the package type, thickness, and thermal characteristics of the chip under test. For example, for a thicker DDR5 memory chip, a 0.5Hz rectangular wave can be used to generate a temperature rise of approximately 5°C; for thin-packaged chips with faster heat conduction, a 10Hz sine wave can be used to shorten the single-cycle time and improve the detection throughput.

[0152] Based on the above embodiments, preferably, the sampling frame rate of the infrared thermal imager should be more than twice the pulse frequency.

[0153] The sampling frame rate refers to the number of thermal image frames acquired per second by an infrared thermal imager, measured in frames per second (fps). According to the Nyquist sampling theorem, in order to accurately reconstruct the waveform of a periodic temperature signal, the sampling frequency must be at least twice the highest frequency of the signal. In this embodiment, if the pulse current frequency is f0, then the sampling frame rate f of the infrared thermal imager is... s f should be satisfied s >2×f0, preferably f s =20×f0 to 50×f0 oversampling scheme.

[0154] During implementation, the detection system automatically configures the sampling frame rate of the infrared thermal imager according to the set pulse frequency. For example, when the pulse frequency is 0.5Hz, the sampling frame rate is set to 10Hz (20 times the excitation frequency), continuously acquiring 10 complete pulse cycles (a total of 200 frames); when the pulse frequency is 1Hz, the sampling frame rate is set to 20Hz or higher to ensure the calculation accuracy of the phase-locked loop algorithm.

[0155] The advantages of high frame rate sampling are that it avoids temperature signal aliasing, ensuring accurate reconstruction of the time curve of temperature fluctuation; it provides sufficient data points for phase-locked loop (PLL) algorithms, improving the accuracy of phase calculation and amplitude extraction; at the same time, high frame rate acquisition can capture the rapid transient characteristics of temperature response and distinguish defects of different depths and types.

[0156] Based on the above embodiments, preferably, after continuously acquiring thermal image sequences of multiple complete pulse cycles, phase-locked processing is performed on the data of multiple cycles.

[0157] Multi-cycle accumulation refers to the process where an infrared thermal imager continuously acquires a sequence of thermal images across multiple (e.g., 10) complete pulse cycles, and then uses all the data from all cycles together for phase-locked processing. Compared to acquiring only a single cycle, multi-cycle accumulation can suppress random thermal noise according to the square root law, while coherently enhancing periodic defect thermal signals, significantly improving the signal-to-noise ratio.

[0158] During implementation, the detection system controls an infrared thermal imager to continuously acquire a sequence of thermal images for 10 complete pulse cycles (e.g., 2 seconds per cycle at a pulse frequency of 0.5 Hz, for a total of 20 seconds). After acquisition, a phase-locked loop algorithm is applied to the time-temperature data of each pixel in the thermal image sequence to calculate the amplitude and phase with the excitation frequency as a reference. For suspected intermittent defects, the acquisition period can be extended to 50 cycles to observe phase stability and distinguish between intermittent and stable defects.

[0159] Based on the above embodiments, preferably, the memory module first board is fixed by a special test fixture, which is connected to a controllable pulse current source and a switching network through gold fingers or reserved test points.

[0160] A dedicated test fixture is a tooling device used to hold the first board of memory modules during testing and to provide electrical connections and optical positioning. This fixture is equipped with flexible probes for reliable electrical contact with the gold fingers of the memory module (i.e., the metal contact array on the edge of the memory module, conforming to the DDR5 DIMM (Dual In-line Memory Module) interface standard). The fixture is designed so that the memory chip surface on the memory module is exposed upwards to the field of view of the infrared thermal imager.

[0161] For raw cards without gold fingers, the fixture connects via probes to pre-drilled VDD test points on the PCB. The dedicated fixture ensures a fixed distance and angle between the chip surface and the infrared thermal imager, guaranteeing clear thermal image focus and measurement repeatability, while also providing stable electrical contact impedance to reduce the impact of contact resistance on the test current.

[0162] The embodiments of this application can acquire and process relevant data based on artificial intelligence technology. Artificial intelligence (AI) refers to the theories, methods, technologies, and application systems that use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to obtain optimal results.

[0163] Foundational technologies for artificial intelligence generally include sensors, dedicated AI chips, cloud computing, distributed storage, big data processing, operating / interactive systems, and mechatronics. AI software technologies mainly encompass computer vision, robotics, biometrics, speech processing, natural language processing, and machine learning / deep learning.

[0164] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by instructing related hardware through computer-readable instructions. These computer-readable instructions can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. The aforementioned storage medium can be a non-volatile storage medium such as a magnetic disk, optical disk, or read-only memory (ROM), or random access memory (RAM).

[0165] It should be understood that although the steps in the flowcharts of the accompanying figures are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the accompanying figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0166] Further reference Figure 3 As a response to the above Figure 2The implementation of the method shown in this application provides an embodiment of a first-piece inspection system, which is similar to... Figure 2 Corresponding to the method embodiments shown, this device can be specifically applied to various electronic devices.

[0167] like Figure 3 As shown, the first-piece board inspection system 300 described in this embodiment includes: an acquisition module 301, a processing module 302, an identification module 303, a mapping module 304, and a determination module 305. Wherein: The acquisition module is used to acquire a thermal image sequence of the surface of the memory chip evolving over time under synchronous pulsed current excitation, with the pulsed current flowing through all the BGA solder joints under test below the memory chip. The processing module is used to perform phase-locked processing on the temperature data of each pixel in the thermal image sequence as it changes over time, and to extract the temperature fluctuation amplitude data and phase delay data of each pixel. The identification module is used to identify defect hotspot areas on the surface of the memory chip based on the temperature fluctuation amplitude data and phase delay data of each pixel. The mapping module is used to input the coordinates of the defect hotspot area in the image coordinate system into a pre-established spatial mapping relationship, and obtain the physical position of the coordinates in the physical coordinate system of the BGA ball grid array of the memory chip. The spatial mapping relationship is established based on the solder ball spacing and array size of the BGA ball grid array. The determination module is used to determine the physical number of the BGA solder ball corresponding to the physical location based on the physical location and array size, and output the physical number.

[0168] The first-piece board inspection system provided in this application acquires a sequence of thermal images showing the evolution of the memory chip surface over time under synchronous pulsed current excitation, with the pulsed current flowing through all the BGA solder joints under the memory chip. By converting the invisible electrical connection quality issues of the BGA solder joints into measurable thermal signals, it provides a data foundation for subsequent defect identification and solves the problem of BGA solder joints being obscured and unable to be directly inspected optically.

[0169] Phase-locked processing is performed on the temperature data of each pixel in the thermal image sequence over time to extract the temperature fluctuation amplitude data and phase delay data of each pixel. This phase-locked processing accurately separates the subtle temperature rise caused by defective weld joints from the background thermal noise, improving the signal-to-noise ratio and detection sensitivity of the thermal signal, and enabling the effective identification of minute impedance anomalies such as hidden weld defects and microcracks.

[0170] Based on the temperature fluctuation amplitude data and phase delay data of each pixel, defect hotspot areas on the surface of the memory chip are identified. Automatic identification of defect hotspot areas is achieved through joint determination of two parameters, eliminating the need for manual inspection of each solder joint and significantly reducing false alarm and false negative rates.

[0171] By inputting the coordinates of the defect hotspot region in the image coordinate system into a pre-established spatial mapping relationship, the physical location of the corresponding coordinates in the physical coordinate system of the BGA ball grid array of the memory chip is obtained. This spatial mapping relationship is established based on the solder ball spacing and array size of the BGA ball grid array. This spatial mapping relationship accurately converts the abstract image hotspot location into its position in the chip's physical space, providing a coordinate transformation basis for the precise localization of defective solder balls.

[0172] Based on the physical location and array size, the physical number of the BGA solder ball corresponding to the physical location is determined and output. By matching the physical location with the specific solder ball physical number, the detection result is directly converted into a rework instruction that can be operated by engineers. This eliminates the time-consuming process of traditional detection that requires X-ray or cross-section analysis to confirm the fault point, fundamentally improving the detection efficiency and positioning accuracy of soldering defects on the first piece board.

[0173] To address the aforementioned technical problems, embodiments of this application also provide a computer device. Please refer to [link / reference needed]. Figure 4 , Figure 4 This is a basic structural block diagram of the computer device in this embodiment.

[0174] The computer device 4 includes a memory 41, a processor 42, and a network interface 43 that are interconnected via a system bus. It should be noted that only the computer device 4 with components 41, 42, and 43 is shown in the figure; however, it should be understood that it is not required to implement all the shown components, and more or fewer components can be implemented alternatively. Those skilled in the art will understand that the computer device described here is a device capable of automatically performing numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes, but is not limited to, microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), embedded devices, etc.

[0175] The computer device can be a desktop computer, laptop, handheld computer, or cloud server, etc. The computer device can interact with the user via a keyboard, mouse, remote control, touchpad, or voice control.

[0176] The memory 41 includes at least one type of readable storage medium, including flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 41 may be an internal storage unit of the computer device 4, such as the hard disk or memory of the computer device 4. In other embodiments, the memory 41 may also be an external storage device of the computer device 4, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the computer device 4. Of course, the memory 41 may also include both the internal storage unit and its external storage device of the computer device 4. In this embodiment, the memory 41 is typically used to store the operating system and various application software installed on the computer device 4, such as computer-readable instructions for the first piece inspection method. In addition, the memory 41 can also be used to temporarily store various types of data that have been output or will be output.

[0177] In some embodiments, the processor 42 may be a central processing unit (CPU), a controller, a microcontroller, a microprocessor, or other data processing chip. The processor 42 is typically used to control the overall operation of the computer device 4. In this embodiment, the processor 42 is used to execute computer-readable instructions stored in the memory 41 or to process data, for example, to execute computer-readable instructions for the first piece inspection method.

[0178] The network interface 43 may include a wireless network interface or a wired network interface, which is typically used to establish communication connections between the computer device 4 and other electronic devices.

[0179] The computer device provided in this application acquires a sequence of thermal images showing the evolution of the surface of a memory chip over time under synchronous pulsed current excitation, with the pulsed current flowing through all the BGA solder joints under test beneath the memory chip. By converting the invisible electrical connection quality issues of the BGA solder joints into measurable thermal signals, it provides a data foundation for subsequent defect identification and solves the problem of BGA solder joints being obscured and unable to be directly optically inspected.

[0180] Phase-locked processing is performed on the temperature data of each pixel in the thermal image sequence over time to extract the temperature fluctuation amplitude data and phase delay data of each pixel. This phase-locked processing accurately separates the subtle temperature rise caused by defective weld joints from the background thermal noise, improving the signal-to-noise ratio and detection sensitivity of the thermal signal, and enabling the effective identification of minute impedance anomalies such as hidden weld defects and microcracks.

[0181] Based on the temperature fluctuation amplitude data and phase delay data of each pixel, defect hotspot areas on the surface of the memory chip are identified. Automatic identification of defect hotspot areas is achieved through joint determination of two parameters, eliminating the need for manual inspection of each solder joint and significantly reducing false alarm and false negative rates.

[0182] By inputting the coordinates of the defect hotspot region in the image coordinate system into a pre-established spatial mapping relationship, the physical location of the corresponding coordinates in the physical coordinate system of the BGA ball grid array of the memory chip is obtained. This spatial mapping relationship is established based on the solder ball spacing and array size of the BGA ball grid array. This spatial mapping relationship accurately converts the abstract image hotspot location into its position in the chip's physical space, providing a coordinate transformation basis for the precise localization of defective solder balls.

[0183] Based on the physical location and array size, the physical number of the BGA solder ball corresponding to the physical location is determined and output. By matching the physical location with the specific solder ball physical number, the detection result is directly converted into a rework instruction that can be operated by engineers. This eliminates the time-consuming process of traditional detection that requires X-ray or cross-section analysis to confirm the fault point, fundamentally improving the detection efficiency and positioning accuracy of soldering defects on the first piece board.

[0184] This application also provides another embodiment, namely, providing a computer-readable storage medium storing computer-readable instructions that can be executed by at least one processor to cause the at least one processor to perform the steps of the first piece inspection method as described above.

[0185] The computer-readable storage medium provided in this application acquires a sequence of thermal images showing the evolution of the surface of a memory chip over time under synchronous pulsed current excitation, with the pulsed current flowing through all the BGA solder joints under test beneath the memory chip. By converting the invisible electrical connection quality issues of the BGA solder joints into measurable thermal signals, it provides a data foundation for subsequent defect identification and solves the problem of BGA solder joints being obscured and unable to be directly optically inspected.

[0186] Phase-locked processing is performed on the temperature data of each pixel in the thermal image sequence over time to extract the temperature fluctuation amplitude data and phase delay data of each pixel. This phase-locked processing accurately separates the subtle temperature rise caused by defective weld joints from the background thermal noise, improving the signal-to-noise ratio and detection sensitivity of the thermal signal, and enabling the effective identification of minute impedance anomalies such as hidden weld defects and microcracks.

[0187] Based on the temperature fluctuation amplitude data and phase delay data of each pixel, defect hotspot areas on the surface of the memory chip are identified. Automatic identification of defect hotspot areas is achieved through joint determination of two parameters, eliminating the need for manual inspection of each solder joint and significantly reducing false alarm and false negative rates.

[0188] By inputting the coordinates of the defect hotspot region in the image coordinate system into a pre-established spatial mapping relationship, the physical location of the corresponding coordinates in the physical coordinate system of the BGA ball grid array of the memory chip is obtained. This spatial mapping relationship is established based on the solder ball spacing and array size of the BGA ball grid array. This spatial mapping relationship accurately converts the abstract image hotspot location into its position in the chip's physical space, providing a coordinate transformation basis for the precise localization of defective solder balls.

[0189] Based on the physical location and array size, the physical number of the BGA solder ball corresponding to the physical location is determined and output. By matching the physical location with the specific solder ball physical number, the detection result is directly converted into a rework instruction that can be operated by engineers. This eliminates the time-consuming process of traditional detection that requires X-ray or cross-section analysis to confirm the fault point, fundamentally improving the detection efficiency and positioning accuracy of soldering defects on the first piece board.

[0190] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0191] Obviously, the embodiments described above are only some embodiments of this application, not all embodiments. The accompanying drawings show preferred embodiments of this application, but do not limit the patent scope of this application. This application can be implemented in many different forms; rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing specific embodiments, or make equivalent substitutions for some of the technical features. Any equivalent structures made using the content of this application's specification and drawings, directly or indirectly applied to other related technical fields, are similarly within the scope of patent protection of this application.

Claims

1. A method for first-piece inspection, characterized in that, include: Acquire a sequence of thermal images showing the evolution of the surface of a memory chip over time under synchronous pulsed current excitation, wherein the pulsed current flows through all the BGA solder joints under test beneath the memory chip; Phase-locked processing is performed on the temperature data of each pixel in the thermal image sequence as it changes over time, and the temperature fluctuation amplitude data and phase delay data of each pixel are extracted. Based on the temperature fluctuation amplitude data and phase delay data of each pixel, the defect hotspot area on the surface of the memory chip is identified; The coordinates of the defect hotspot region in the image coordinate system are input into a pre-established spatial mapping relationship to obtain the physical position of the coordinates in the physical coordinate system of the BGA ball grid array of the memory chip. The spatial mapping relationship is established based on the solder ball spacing and array size of the BGA ball grid array. Based on the physical location and the array size, determine the physical number of the BGA solder ball corresponding to the physical location, and output the physical number.

2. The first-piece inspection method according to claim 1, characterized in that, The phase-locked processing of the temperature data of each pixel in the thermal image sequence over time includes: Using the excitation frequency of the pulse current as a reference signal, correlation calculations are performed on the temperature data of each pixel to extract the temperature fluctuation amplitude data and phase delay data of each pixel at the excitation frequency.

3. The first-piece inspection method according to claim 1, characterized in that, The step of identifying defect hotspot areas on the surface of the memory chip based on the temperature fluctuation amplitude data and phase delay data of each pixel includes: An amplitude image is generated based on the temperature fluctuation amplitude data of each pixel. Pixels with temperature fluctuation amplitudes greater than the amplitude threshold are extracted from the amplitude image to form candidate hotspot regions. A phase image is generated based on the phase delay data of each pixel, and pixels with a phase delay greater than a phase threshold are extracted from the phase image. A continuous region consisting of pixels that simultaneously belong to the candidate hotspot region and whose phase delay is greater than the phase threshold is identified as the defect hotspot region.

4. The first-piece inspection method according to claim 1, characterized in that, The step of identifying defect hotspot areas on the surface of the memory chip based on the temperature fluctuation amplitude data and phase delay data of each pixel includes: An amplitude image is generated based on the temperature fluctuation amplitude data of each pixel. In the amplitude image, the temperature fluctuation amplitude of each pixel is compared with the reference amplitude of the corresponding pixel in the reference amplitude image pixel by pixel to obtain the amplitude difference value of each pixel. Pixels with amplitude difference values ​​greater than the amplitude difference threshold are grouped into candidate hotspot regions; A phase image is generated based on the phase delay data of each pixel, and pixels with a phase delay greater than a phase threshold are extracted from the phase image. A continuous region consisting of pixels that simultaneously belong to the candidate hotspot region and whose phase delay is greater than the phase threshold is identified as the defect hotspot region.

5. The first-piece inspection method according to claim 1, characterized in that, The step of identifying defect hotspot areas on the surface of the memory chip based on the temperature fluctuation amplitude data and phase delay data of each pixel includes: An amplitude image is generated based on the temperature fluctuation amplitude data of each pixel. In the amplitude image, the region formed by pixels whose temperature fluctuation amplitude is lower than a preset background judgment value is defined as the background region; Calculate the standard deviation of the temperature fluctuation amplitude in the background region, and set a preset multiple of the standard deviation as the amplitude threshold. Pixels with temperature fluctuation amplitudes greater than the amplitude threshold are extracted from the amplitude image to form candidate hotspot regions; A phase image is generated based on the phase delay data of each pixel, and pixels with a phase delay greater than a phase threshold are extracted from the phase image. A continuous region consisting of pixels that simultaneously belong to the candidate hotspot region and whose phase delay is greater than the phase threshold is identified as the defect hotspot region.

6. The first-piece inspection method according to claim 1, characterized in that, Before inputting the coordinates of the defect hotspot region in the image coordinate system into a pre-established spatial mapping relationship, the process includes: Obtain the solder ball pitch and array size of the BGA ball grid array of the memory chip; Based on the solder ball spacing and the array size, establish the proportional relationship between the unit pixel distance in the image coordinate system and the unit physical distance in the BGA ball grid array physical coordinate system, as well as the offset between the origin of the image coordinate system and the origin of the physical coordinate system; The spatial mapping relationship is obtained based on the proportional relationship and the offset.

7. The first-piece inspection method according to claim 1, characterized in that, The step of inputting the coordinates of the defect hotspot region in the image coordinate system into a pre-established spatial mapping relationship to obtain the physical location of the coordinates in the physical coordinate system of the BGA ball grid array of the memory chip includes: Obtain the coordinates of the center pixel of the defect hotspot region in the image coordinate system; The coordinates of the center pixel are input into the spatial mapping relationship. The spatial mapping relationship maps the coordinates of the center pixel to the physical coordinates in the BGA ball grid array physical coordinate system according to the ratio and offset between the image coordinate system and the BGA ball grid array physical coordinate system. The physical coordinates are used to determine the physical location.

8. The first-piece inspection method according to claim 7, characterized in that, The step of determining the physical number of the BGA solder ball corresponding to the physical location based on the physical location and the array size includes: Based on the array size, obtain the number and coordinate range of each BGA solder ball in the physical coordinate system of the BGA ball grid array; The physical location is matched with the coordinate range of each BGA solder ball to determine the number of the BGA solder ball corresponding to the coordinate range in which the physical location falls, and this number is used as the physical number of the BGA solder ball corresponding to the physical location.

9. The first-piece inspection method according to claim 1, characterized in that, The step of inputting the coordinates of the defect hotspot region in the image coordinate system into a pre-established spatial mapping relationship to obtain the physical location of the coordinates in the physical coordinate system of the BGA ball grid array of the memory chip includes: Obtain the set of coordinates of all pixels in the defect hotspot region in the image coordinate system; Input the coordinates of each pixel in the coordinate set into the spatial mapping relationship to obtain the physical coordinate set corresponding to each pixel coordinate in the physical coordinate system of the BGA ball grid array. Calculate the center position of the physical coordinate set, and determine the center position as the physical location.

10. A first-piece inspection system, characterized in that, include: The acquisition module is used to acquire a thermal image sequence of the surface of the memory chip evolving over time under synchronous pulsed current excitation, wherein the pulsed current flows through all the BGA solder joints under test below the memory chip. The processing module is used to perform phase-locked processing on the temperature data of each pixel in the thermal image sequence that changes over time, and to extract the temperature fluctuation amplitude data and phase delay data of each pixel; The identification module is used to identify the defect hotspot areas on the surface of the memory chip based on the temperature fluctuation amplitude data and the phase delay data of each pixel. The mapping module is used to input the coordinates of the defect hotspot region in the image coordinate system into a pre-established spatial mapping relationship to obtain the physical position of the coordinates in the physical coordinate system of the BGA ball grid array of the memory chip, wherein the spatial mapping relationship is established based on the solder ball spacing and array size of the BGA ball grid array. The determination module is used to determine the physical number of the BGA solder ball corresponding to the physical location based on the physical location and the array size, and output the physical number.

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