A cable connection testing device, system, method and electronic device

Abstract

The application discloses a kind of cable connection test equipment, system, method and electronic equipment, it is related to the whole cabinet test technical field, connects three groups of connectors respectively and connects the uplink port of exchange type expansion unit, downlink port and slot type expansion unit, provides the access position of different test paths.Utilize node connection cable to select the access relationship of computing power node, and utilize cascade cable to connect exchange output side and slot input side, so that the same test equipment forms different test link.Therefore, it can solve the technical problems that the connection relationship between node and test equipment is fixed in the existing test scheme, and the test environment needs to be rebuilt when facing different measured nodes or link topologies, to improve the technical effects of test environment configuration efficiency, test resource reuse rate and test link configuration flexibility.

Description

Technical Field

[0001] This application relates to the field of whole cabinet testing technology, and in particular to a cable connection testing device, system, method and electronic device. Background Technology

[0002] Test setups typically involve building a fixed test link based on compute nodes, a backplane or interconnect cables, and GPU nodes. These components are connected according to a predetermined system topology, resulting in a relatively fixed connection between the test nodes and the node under test. However, when faced with different nodes under test or different link topologies, the test environment needs to be adjusted or rebuilt accordingly. This leads to low configuration efficiency and low resource reuse, further reducing configuration flexibility. Summary of the Invention

[0003] This application provides a cable connection testing device, system, method, and electronic device to at least solve the problems in the related art where the connection relationship between the test node and the node under test is fixed, and the test environment needs to be rebuilt when facing different nodes under test or different link topologies, resulting in low efficiency of test environment configuration, low reuse rate of test resources, and low flexibility of test link configuration.

[0004] This application provides a cable connection testing device, including a first connector group, a second connector group, a third connector group, a switching expansion unit, a slot-type expansion unit, and a cable assembly; The first connector group is connected to the uplink port of the switching expansion unit; the downlink port of the switching expansion unit is connected to the second connector group. The third connector group connects to the slot-type expansion unit; The cable assembly includes node connection cables, or includes node connection cables and cascade cables; the two ends of the node connection cables are respectively connected to multiple node connectors of at least one computing node and at least one set of connector groups to form a test link for transmitting signals through at least one expansion unit of switching expansion unit and slot expansion unit; the two ends of the cascade cables are respectively connected to a second connector group and a third connector group to form a cascaded test link from switching expansion unit to slot expansion unit.

[0005] This application also provides a cable connection testing system, including at least one computing node and cable connection testing equipment; The computing power node includes multiple node connectors. The two ends of the node connection cable in the cable connection test equipment are respectively connected to multiple node connectors of at least one computing power node and at least one group of each connector group to form a test link for transmitting signals through at least one expansion unit of the switching type expansion unit and the slot type expansion unit. In the case where the cable connection test equipment includes cascaded cables, the two ends of the cascaded cables are connected to the second connector group and the third connector group respectively to form a cascaded test link from the switching expansion unit to the slot expansion unit.

[0006] This application also provides a cable connection testing method, applied to a cable connection testing system, the method comprising: Obtain the test configuration information of the computing power nodes; According to the test configuration information, the two ends of the node connection cable are respectively connected to multiple node connectors of at least one computing power node and at least one group of each connector group to form a test link for transmitting signals through at least one expansion unit of the switching expansion unit and the slot expansion unit. When the test configuration information indicates the formation of a cascaded test link, the two ends of the cascaded cable are connected to the second connector group and the third connector group respectively to form a cascaded test link from the switching expansion unit to the slot expansion unit. The control computing nodes transmit test signals through the formed test link, and the test results of the test link are determined based on the transmission results of the test signals.

[0007] This application also provides an electronic device, including: Memory, used to store computer programs; A processor is used to execute computer programs to implement the steps of any of the above cable connection test methods.

[0008] This application achieves the following: First, the first connector group connects to the uplink port of the switching expansion unit; the downlink port of the switching expansion unit connects to the second connector group; and the third connector group connects to the slot-type expansion unit. This provides a hardware foundation for the computing node to select different expansion units for connection, ensuring that both types of expansion units have corresponding connection positions. Second, the node connection cable can selectively connect multiple node connectors of the computing node to at least one set of connectors, thereby forming a test link that transmits signals via the switching expansion unit or the slot-type expansion unit according to the test configuration, reducing the fixed nature of the connection relationship between the computing node and the test equipment. Finally, the cascade cable connects the downlink port of the switching expansion unit to the slot-type expansion unit by connecting the second and third connector groups, thereby forming a cascaded test link in which the two types of expansion units participate in signal transmission sequentially, expanding the configuration method of the test link. In summary, by combining three sets of connectors, two types of expansion units, and node connection cables and cascade cables, different test links can be formed according to the test configuration of the computing power nodes. This reduces the need to rebuild the test environment due to changes in the topology of the tested nodes or links, thereby improving the configuration efficiency of the test environment, the reuse rate of test resources, and the configuration flexibility of the test links.

[0009] Since both the uplink and downlink sides of the switching expansion unit and the slot-type expansion unit have independent connection positions for cable access, the computing node can select the appropriate signal transmission path according to the test requirements, and can further combine the two expansion methods to form a cascaded transmission path. Therefore, it can solve the technical problems in the existing test scheme where the connection relationship between the node and the test equipment is fixed and the test environment needs to be rebuilt when facing different tested nodes or link topologies, thus achieving the technical effects of improving the efficiency of test environment configuration, the reuse rate of test resources, and the flexibility of test link configuration. Attached Figure Description

[0010] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of the fixed interconnection relationship between general computing nodes and accelerated computing nodes in conventional related technologies within a server rack. Figure 2 This is a schematic diagram of the structure of a cable connection testing device provided in an embodiment of this application; Figure 3 This application provides a schematic diagram of a test scenario based on a cable connection test device. Figure 4 This application provides a schematic diagram of the structure of a connection cable connecting a general computing node as a master device to a test device. Figure 5 This application provides a schematic diagram of the structure of a connection cable connecting a test device when an accelerated computing node is used as a master device. Figure 6 This application provides a schematic diagram of the structure of a test device connected by a connection cable when an accelerated computing node is used as a slave device. Figure 7 This application provides a schematic diagram of the structure of a connection cable connecting a computing node as a master-slave device to a test device, as shown in the embodiments of this application. Figure 8 A schematic diagram illustrating a scenario where multiple node connectors of a general computing node are cross-connected to a test device, as provided in an embodiment of this application. Figure 9 A schematic diagram illustrating a scenario where a test device is connected by a cross-connection cable between a redundant first processor and a second processor, as provided in an embodiment of this application. Figure 10This is a schematic diagram illustrating a scenario where a redundant first processor and a second processor are both connected by cables to the same expansion unit under a test device, as provided in an embodiment of this application. Figure 11 A schematic diagram of a test scenario where a cable connection testing device is placed outside a computing node, as provided in an embodiment of this application; Figure 12 A schematic diagram of a test scenario where a cable connection test device is placed outside the computing node, as provided in an embodiment of this application; Figure 13 A schematic diagram of a test scenario in which a cable connection test device is placed inside a computing node, as provided in an embodiment of this application; Figure 14 A schematic diagram of a test scenario where a cable connection test device is placed outside a computing node, as provided in an embodiment of this application; Figure 15 A flowchart illustrating a cable connection testing method provided in this application embodiment; Figure 16 This is a schematic diagram of a cable connection testing device provided in an embodiment of this application. Detailed Implementation

[0012] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0013] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0014] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0015] Figure 1 This is a schematic diagram illustrating the fixed interconnection relationship between general-purpose computing nodes and accelerated computing nodes within a server rack, as described in conventional related technologies. Figure 1As shown, general-purpose computing node 1 is a Central Processing Unit (CPU) computing node, and accelerated computing node 2 is a Graphics Processing Unit (GPU) node. Signals between the two nodes need to be routed out through high-speed connector 3 and interconnected via a printed circuit board (PCB) or cables to achieve signal transmission throughout the rack. The design of the high-speed connector 3 between the computing nodes and the GPU nodes is extremely important; design errors may lead to the malfunction of the entire rack. Figure 1 In this design, the CPU computing nodes, providing CPU and memory functions, are located on the left side of the front window of the rack. The GPU nodes, providing GPU computing power, are located on the right side of the rear window. A backplane 4 is placed in the middle of the rack, using a PCB for signal interconnection. Alternatively, a cable tray can be placed there, using cables for signal interconnection. The high-speed connector 3 is located inside the rack, making testing and verification inconvenient. The backplane 4 or cables used for testing have simple functions and support limited configuration testing. They cannot independently perform signal function testing on either the computing node or the GPU node. Relying solely on the interconnection of these two types of nodes results in insufficient decoupling between the CPU and GPU nodes. When the link malfunctions or exhibits abnormal performance, the anomaly may originate from the computing node, the GPU node, or the intermediate interconnection. Without a test component capable of independently verifying the function of a single node, it is difficult to quickly narrow down the problem by changing node connections, and it is also difficult to distinguish whether the anomaly occurs on the CPU side or the GPU side. Consequently, the computing node and GPU node are not fully decoupled, making it difficult to quickly and accurately pinpoint the root cause of some complex problems—whether it lies on the CPU or the GPU side. The cable connection testing equipment provided in this application can solve the above technical problems.

[0016] Figure 2 This is a schematic diagram of the structure of a cable connection testing device provided in an embodiment of this application, as shown below. Figure 2 As shown, it includes a first connector group 5, a second connector group 6, a third connector group 7, a switching expansion unit 8, a slot-type expansion unit 9, and a cable assembly; The first connector group 5 is connected to the uplink port of the switching expansion unit 8; the downlink port of the switching expansion unit 8 is connected to the second connector group 6. The third connector group 7 is connected to the slot-type expansion unit 9; The cable assembly includes node connection cables, or includes node connection cables and cascade cables; the two ends of the node connection cables are respectively connected to multiple node connectors of at least one computing node and at least one set of connector groups to form a test link for transmitting signals through at least one expansion unit of the switching expansion unit 8 and the slot expansion unit 9; the two ends of the cascade cables are respectively connected to the second connector group 6 and the third connector group 7 to form a cascaded test link from the switching expansion unit 8 to the slot expansion unit 9.

[0017] Specifically, this cable connection testing equipment can replace or supplement backplanes and other interconnect structures during the AI ​​(Artificial Intelligence) rack verification phase, and is a testing device for functional, performance, and link integrity testing of computing nodes such as general-purpose computing nodes and accelerated computing nodes. A computing node is a node with computing processing capabilities that transmits signals externally through a node connector; it can be a general-purpose computing node, such as a CPU node, or an accelerated computing node, such as a GPU node.

[0018] The first connector group, the second connector group, and the third connector group are connector sets on the test equipment used for cable connection. A switching expansion unit is an expansion component that organizes signal transmission through the uplink and downlink ports of a switching device. In this embodiment, it uses a high-speed serial computer expansion bus (Peripheral Component Interconnect Express, PCIE) switch. The uplink port of the switching expansion unit is the port used to connect to the master device side, and the downlink port is the port used to connect to the backend device side. Uplink and downlink describe the topology location and do not indicate that the port only allows unidirectional signal transmission.

[0019] Slot-type expansion units are components that connect to expansion devices via slots. They can use PCIe x16 slots and can accommodate standard PCIe cards. PCIe x16, x8, and x4 represent the link width consisting of the corresponding number of channels. A channel is the basic transmission component in a PCIe link. The number of slots, the number of input connectors, and the link width corresponding to each connector can be set according to the design and testing requirements of the computing node.

[0020] Figure 2Connectors A1 and A2 are connected to the uplink port of the switching expansion unit 8, forming the first connector group 5; connectors B1 and B2 are connected to the downlink port of the switching expansion unit 8, forming the second connector group 6; connectors C1 and C2 are connected to the slot-type expansion unit 9, forming the third connector group 7, so that node signals can be accessed through the standard PCIe card without passing through the switching expansion unit 8.

[0021] The two uplink connectors and two downlink connectors described above represent a specific configuration. For example, when using a switching expansion unit with 144 channels, with two sets of x16 channels occupied on the uplink side, the remaining 112 channels can be configured with seven sets of x16 or fourteen sets of x8 channels for downlink connections. The specific number of connectors depends on the downlink configuration. This example illustrates the relationship between channel allocation and the number of connectors in the expansion unit; the test equipment does not need to be fixed. Figure 2 The number of connectors shown.

[0022] A cable assembly is a collection of cables used to establish external test connections for nodes. Node connection cables connect computing nodes to test equipment, while cascade cables connect the second and third connector groups of the test equipment. Both types of cables are designed to match the specifications of their respective connectors and can be configured with different lengths. In configurations where cascading is not required, node connection cables are used to connect node connectors to selected connector groups; in configurations requiring cascading, cascade cables are added in addition to the node connection cables, allowing the output side of the switching expansion unit to connect to the slot-type expansion unit. Node connectors are connectors located on computing nodes and used to bring out signals from within the node. Figure 2 It is not shown in the image.

[0023] A test link is the transmission path formed by connectors, cables, and expansion units that a test signal traverses when it originates from or arrives at a node connector. When a computing node is connected to the first connector group, the signal is transmitted via a switching expansion unit; when connected to the third connector group, the signal is transmitted via a slot-type expansion unit; if a slave computing node is added, and that slave node is connected to the second connector group, the signal reaches that slave device via the downlink side of the switching expansion unit. A cascaded test link further includes cable connections from the second to the third connector group, allowing switching expansion units and slot-type expansion units to participate in signal transmission sequentially.

[0024] In other words, in the test link, the computing nodes can act as either master or slave devices. When two computing nodes exist, both can act as master devices, both as slave devices, or one can act as master and the other as slave, etc. The specific cable connection relationship is not limited and can be set according to the actual situation. Furthermore, redundant devices can exist within a single computing node, connected to the first connector group and the second connector group respectively. This connection can be a one-to-one direct connection or a cross-connection. Considering that each redundant device connects to multiple node connectors, one node connector of each device can connect to a connector in the first connector group, and another node connector can connect to a connector in the third connector group. Similarly, redundant devices corresponding to the same device can be connected in this way to form a cross-connection relationship. Alternatively, all node connectors corresponding to each device can be cross-connected; this can be set according to the actual situation.

[0025] Figure 3 This application provides a schematic diagram of a test scenario based on a cable connection testing device, as shown in the embodiment of the present application. Figure 3 As shown, the node connector signal of the general computing node 1, originally located inside the cabinet, is led out to the test equipment via node connection cable 14 for functional verification. The test equipment can be used alone with the accelerated computing node 2, alone with the accelerated computing node, or placed between the two types of nodes or behind the accelerated computing node. By changing the cable access position, different topologies can be formed, and the corresponding functions and performance can be compared.

[0026] This application achieves the following: First, the first connector group connects to the uplink port of the switching expansion unit; the downlink port of the switching expansion unit connects to the second connector group; and the third connector group connects to the slot-type expansion unit. This provides a hardware foundation for the computing node to select different expansion units for connection, ensuring that both types of expansion units have corresponding connection positions. Second, the node connection cable can selectively connect multiple node connectors of the computing node to at least one set of connectors, thereby forming a test link that transmits signals via the switching expansion unit or the slot-type expansion unit according to the test configuration, reducing the fixed nature of the connection relationship between the computing node and the test equipment. Finally, the cascade cable connects the downlink port of the switching expansion unit to the slot-type expansion unit by connecting the second and third connector groups, thereby forming a cascaded test link in which the two types of expansion units participate in signal transmission sequentially, expanding the configuration method of the test link. In summary, by combining three sets of connectors, two types of expansion units, and node connection cables and cascade cables, different test links can be formed according to the test configuration of the computing power nodes. This reduces the need to rebuild the test environment due to changes in the topology of the tested nodes or links, thereby improving the configuration efficiency of the test environment, the reuse rate of test resources, and the configuration flexibility of the test links.

[0027] Since both the uplink and downlink sides of the switching expansion unit and the slot-type expansion unit have independent connection positions for cable access, the computing node can select the appropriate signal transmission path according to the test requirements, and can further combine the two expansion methods to form a cascaded transmission path. Therefore, it can solve the technical problems in the existing test scheme where the connection relationship between the node and the test equipment is fixed and the test environment needs to be rebuilt when facing different tested nodes or link topologies, thus achieving the technical effects of improving the efficiency of test environment configuration, the reuse rate of test resources, and the flexibility of test link configuration.

[0028] In some embodiments, in the case of a single computing node, and the computing node acting as the master device, both ends of the node connection cable are respectively connected to at least one node connector and a first connector group of the computing node, so that the computing node transmits test signals via a switching expansion unit; and / or, both ends of the node connection cable are respectively connected to at least one node connector and a third connector group of the computing node, so that the computing node transmits test signals via a slot-type expansion unit.

[0029] Specifically, the master device refers to the node that performs host-side functions in the corresponding test configuration, denoted by "host". This role is determined based on the function the node performs in the current link, not simply on whether the node is a general computing power node or an accelerated computing power node. Only nodes with the corresponding master device functions can use this master device configuration for verification.

[0030] Figure 4This application provides a schematic diagram of the structure of a connection cable connecting a general computing node as a master device to a test device, as shown in the embodiment of the application. Figure 4 As shown, the general-purpose computing node has two central processing units (CPUs), each providing two sets of PCIe x16 signals, which are led out through node connectors. The node signals can be connected to connectors A1 and A2 of the first connector group of the test equipment, and expanded by a switching expansion unit. Alternatively, they can be connected to connectors C1 and C2 of the third connector group of the test equipment, and connected to standard PCIe devices via slot-type expansion units. Both types of expansion units can also be connected simultaneously through different node connectors. The use of "and / or" indicates that the two access methods can be used separately or in combination.

[0031] Similarly, Figure 5 This application provides a schematic diagram of the structure of a connection cable connecting a test device when an accelerated computing node acts as a master device. Figure 5 As shown, this accelerated computing node has two accelerated processors, and their connection relationship is described as follows: Figure 4 The same applies, so I won't go into details here.

[0032] exist Figure 4 and Figure 5 In addition to PCIe signals, the node connectors also contain miscellaneous (MISC) function signals, such as Inter-Integrated Circuit (I2C), Universal Serial Bus (USB), Media Dependent Interface (MDI), General Purpose Input / Output (GPIO), and other MISC signals. These can also be functionally verified using testing equipment. In this embodiment, node functionality can be verified independently using either a general-purpose computing node or an accelerated computing node, satisfying testing scenarios such as general-purpose computing nodes with testing equipment and testing equipment with accelerated computing nodes.

[0033] This embodiment enables a single master device node to directly perform switch expansion or slot expansion tests with test equipment, reducing reliance on another type of complete computing power node. When the development progress of general-purpose computing power nodes and accelerated computing power nodes is inconsistent, nodes that already have testing capabilities can be used to conduct verification first, saving on supporting test materials and increasing the types of configurations that can be tested on a single node.

[0034] In some embodiments, in the case of a single computing node, and the computing node acting as a slave device, both ends of the node connection cable are connected to at least one node connector and a second connector group of the computing node, respectively, so that the computing node receives a test signal and returns a corresponding response signal via the downlink port of the switching expansion unit.

[0035] Specifically, a slave device refers to a device that receives signals from the master device and responds in the corresponding test link; it is denoted by "device". The response signal is the return signal corresponding to the processing performed by the node on the received test signal.

[0036] Figure 6 This application provides a schematic diagram of the structure of a test device connected by a connection cable when an accelerated computing node is used as a slave device. Figure 6 As shown, connectors B1 and B2 of the second connector group are directly connected to the node connectors of the accelerated computing node, such as node connectors E1 and E2, to verify the functionality of the corresponding ports when connected to the downlink side of the switching expansion unit. Depending on the test configuration, connectors B1 and B2 of the second connector group of the test equipment can also be connected to node connectors E1 and E3 of the accelerated computing node to change the node ports and internal processor paths involved in the test. General-purpose computing nodes with slave device functionality can also adopt this downlink access method according to their supported port functions.

[0037] The above connection description illustrates the access relationship of the node under test on the downlink side of the test equipment. Test signals should be provided by the side of the test environment that performs the corresponding master equipment function. The switching extension unit is used to forward signals and does not automatically possess the host function to independently initiate all tests simply because it is located in the test equipment. By observing the reception and response of the slave device, it can be determined whether the selected node connector and its related links have completed the expected transmission.

[0038] This embodiment provides a unified test access location on the device side via a second connector group, enabling the same test device to adapt to the slave device test role of a node and verify different paths by changing the node port combination. This improves the test device's adaptability to node roles and port combinations, providing conditions for individually verifying node-side functions and narrowing down the scope of anomalies.

[0039] In some embodiments, in the case of a single computing node comprising two devices, one device serving as a master device and the other as a slave device, the two ends of a node connection cable are respectively connected to at least one node connector and a second connector group of the computing node corresponding to the master device, so that the computing node receives test signals and returns corresponding response signals via the downlink port of the switching expansion unit; and / or, the two ends of the node connection cable are respectively connected to at least one node connector and a third connector group of the computing node corresponding to the slave device, so that the computing node transmits test signals via the slot-type expansion unit.

[0040] Figure 7 This application provides a schematic diagram of the structure of a test device connected by a connection cable when an accelerated computing node acts as a master-slave device. Figure 7 As shown, the connection relationship between the computing nodes corresponding to the slave devices and Figure 6 The timing is the same. When acting as the master device, the node connector E2 of the corresponding computing node is connected to the connector C2 of the third connector group to enable simultaneous testing of master and slave devices within a single computing node.

[0041] This embodiment provides a method for simultaneously testing master and slave devices on the same computing power node. This allows the node connector of the master device to receive the uplink input signal from the test device, and the node connector of the slave device to expand the PCIe device. This enriches the test scenarios and improves the reusability of node connectors in test scenarios involving multiple devices on the same computing power node.

[0042] In some embodiments, there is a preset port correspondence between multiple node connectors of a computing node and multiple connectors in a target connector group. Each node connector is connected to the corresponding connector in the target connector group through the corresponding node connection cable according to the preset port correspondence to form multiple directly connected test links; wherein, the target connector group is a first connector group and / or a third connector group.

[0043] It should be noted that the above embodiments are only test and verification scenarios for the computing node as a master device, a slave device, or a master-slave device, and its interaction with the first connector group, the second connector group, and the third connector group. Regarding the specific cable connection relationship, it can be a straight-through connection, a crossover connection, or a combination of both.

[0044] Combination Figure 4The general-purpose computing node's node connector D1 is connected to connector A1 of the first connector group of the test equipment; the general-purpose computing node's node connector D2 is connected to connector A2 of the first connector group of the test equipment; the general-purpose computing node's node connector D3 is connected to connector C1 of the third connector group of the test equipment; and the general-purpose computing node's node connector D4 is connected to connector C2 of the third connector group of the test equipment. The first two paths lead to the switching expansion unit, and the latter two paths lead to the slot-type expansion unit. This direct connection describes the direct pairing between the node port and the test equipment's access port, and does not mean that the signal does not pass through the expansion unit after entering the test equipment.

[0045] In actual configuration, the pairing relationship should be determined based on the connector specifications, the PCIe signal groups they carry, and the link width. The default port mapping does not require all nodes to use the same numbering. For different node designs, as long as the relationship between each node connector and its corresponding access connector is clear, the appropriate cables can be laid out according to that relationship.

[0046] This embodiment provides a clear port pairing system, enabling multiple links to have identifiable node sources and test equipment entry points, facilitating wiring verification and link-by-link comparison. When subsequently changing to cross-connect or cascade configurations, this direct pairing configuration can also serve as the comparison basis, thereby improving the clarity of multi-link test configurations and the consistency of repeated setups.

[0047] In some embodiments, the computing power node includes a first node connector and a second node connector; the first node connector is connected to a third connector group via a corresponding node connection cable, and the second node connector is connected to the first connector group to form a cross-test link for the computing power node to access the switching expansion unit and the slot expansion unit respectively.

[0048] Specifically, the first node connector is connected to the third connector group through the corresponding node connection cable, and the second node connector is connected to the first connector group through the corresponding cable, so that the computing power nodes are connected to the slot-type expansion unit and the switching expansion unit respectively, forming a cross-test link.

[0049] The first and second node connectors are used to distinguish the connection positions of the two currently selected nodes; their physical numbers (1 and 2) are not required to be respectively. A cross-test link is a test path formed by changing the pairing of node ports with test device ports relative to a pre-determined wiring relationship. The determination is based on a change in the connected objects, not on whether the cables intersect in space.

[0050] Figure 8 This application provides a schematic diagram illustrating a scenario where multiple node connectors of a general-purpose computing node are cross-connected via cables to a test device, as shown in the embodiments of this application. Figure 8 As shown, node connectors D1 and D2 of the general-purpose computing node are all reconnected to connectors C1 and C2 of the third connector group of the test equipment; node connectors D3 and D4 of the general-purpose computing node are all reconnected to connectors A1 and A2 of the first connector group of the test equipment. Figure 8 The general computing nodes in the system can be replaced with accelerated computing nodes, and no restrictions are imposed here.

[0051] This embodiment changes the expansion method of the node port by adjusting the external cable, allowing the same group of interfaces on the node to participate in switch expansion or slot expansion tests under different configurations. This eliminates the need to develop a separate fixed connection board for each pairing, facilitating comparison of functionality and performance under different port combinations and improving the coverage of test configurations.

[0052] In some embodiments, the computing node includes a first processor and a second processor that are redundant with each other; the multiple node connectors include a first processor connector corresponding to the first processor and a second processor connector corresponding to the second processor; the first processor connector is connected to a third connector group through a corresponding node connection cable, and the second processor connector is connected to the first connector group through a corresponding node connection cable, so that the first processor and the second processor are cross-connected to the switching expansion unit and the slot expansion unit.

[0053] Mutual redundancy is used to describe the redundant working relationship between the two processors in the design of the node under test. The specific redundancy function should be supported by the node and related equipment. The first processor connector and the second processor connector are node connectors that lead out signals from the corresponding processors, and are not a newly added interface type. A dual-processor node provides multiple sets of PCIe signals from different processors, from which interfaces corresponding to the two processors can be selected to form the aforementioned cross-path. Figure 9 A schematic diagram illustrating a scenario where a test device is connected via a cross-connection cable for a redundant first processor and a second processor, as provided in this application embodiment, is shown below. Figure 9 As shown, relative to Figure 4 The pairing relationship allows for the reconnection of the general-purpose computing node's connector D2 to the connector C1 of the third connector group on the test equipment, and the reconnection of the general-purpose computing node's connector D3 to the connector A2 of the third connector group on the test equipment. The former enters the slot-type expansion unit, and the latter enters the switching-type expansion unit. These two connectors involved in the adjustment serve as the first node connector and the second node connector, respectively, while the remaining node ports can continue to maintain their corresponding test connections.

[0054] It will come from the first processor, that is, in Figure 9The PCIe x16 signals from the central processing unit 1' are connected to the slots corresponding to connectors C1 and C2 in the third connector group of the test equipment via their corresponding node connectors; signals from the second processor, i.e., in... Figure 9 The PCIe x16 signals of the central processing unit 2' are connected to the uplink ports of the switching expansion units corresponding to connectors A1 and A2 in the first connector group of the test equipment via their corresponding node connectors. After changing the wiring, the signals under test of the two processors are extended through different methods, and the corresponding configuration can be verified by combining the actual transmission performance of each path.

[0055] This embodiment establishes the relationship between the processor source and the extension path through the node connector and the node connection cable, enabling separate testing of signals from different processors and reducing the uncertainty of determining the fault location based solely on the overall test results of the node.

[0056] In some embodiments, the computing node includes a redundant first processor and a second processor; multiple node connectors include a first processor connector corresponding to the first processor and a second processor connector corresponding to the second processor; the first processor connector is connected to the first connector of the first connector group via a corresponding node connection cable, and the second processor connector is connected to the second connector of the first connector group via a corresponding node connection cable; or, the first processor connector is connected to the first connector of the third connector group via a corresponding node connection cable, and the second processor connector is connected to the second connector of the third connector group via a corresponding node connection cable, so that both the first processor and the second processor are connected to the same switching expansion unit or the same slot-type expansion unit.

[0057] Specifically, the first connector and the second connector of the first connector group are connectors within the group that are used for the access of two signals, respectively. Figure 10 This application provides a schematic diagram of a scenario where a redundant first processor and a second processor are both connected by cables to the same expansion unit in a test device. Figure 10 As shown, the two sets of x16 uplink signals of the switching expansion unit come from two central processing units, thus verifying the dual-CPU host scenario. The dual-master capability connected to the same expansion unit should be adapted to the actual configuration of the switching expansion unit and the system; the physical connection of the two connectors does not replace the corresponding multi-master function.

[0058] In another access configuration, redundant first and second processors can be connected to the same slot-type expansion unit. That is, the two processors are connected to the same slot-type expansion unit via different connection points of the third connector group. This configuration illustrates the connection relationship where the signals from both processors face the slot expansion section, and each input and corresponding slot should have a path matching this configuration. Figure 10 The multiple PCIe slots in the middle can be used for corresponding slot expansion configurations, instead of directly connecting the signals of two independent master devices to a single ordinary uplink slot as the default implementation.

[0059] For dual-master device testing within the same expansion unit, a CPU failure can be simulated under appropriate test conditions. The response of the switching expansion unit and whether the backend PCIe devices can continue operating can be observed, and data loss can be checked. Continued operation and no data loss are the objectives to be verified in this configuration, not results directly guaranteed by the connecting cables themselves.

[0060] This embodiment enables two processors to jointly conduct tests on corresponding expansion units from different access locations, facilitating comparisons of backend device performance under dual-master device operation and single-processor failure conditions. Through actual testing, it can be determined whether the tested node and expansion configuration meet the required redundancy requirements, providing a basis for verifying the dual-processor configuration.

[0061] In some embodiments, at least one node connector of the computing node is connected to the first connector group via a node connection cable, and the two ends of the cascade cable are connected to the second connector group and the third connector group respectively, so as to form a cascaded test link in which the computing node passes through the first connector group, the switching expansion unit, the second connector group, the third connector group and the slot expansion unit in sequence.

[0062] Specifically, such as Figure 10 As shown, one specific path involves the central processing unit 1' within the general-purpose computing node, passing through node connector D1, node connection cables, and connector A1 of the first connector group of the test equipment to enter the switching expansion unit. It then passes through connector B1 of the second connector group of the test equipment, cascade cables, and connector C1 of the third connector group of the test equipment to reach the slot-type expansion unit, ultimately connecting to a standard PCIe card. Another path involves the central processing unit 2' via node connector A2, which can be constructed using the cascaded connection between connector B2 of the second connector group and connector C2 of the third connector group of the test equipment. Additionally, cross-connections of the cables corresponding to each connector can be made within the switching expansion unit. A standard PCIe card is an expansion card that can be installed in its corresponding slot and participate in the corresponding signal transmission.

[0063] This cascading method allows for separate verification of the front-end link from the node to the switching expansion unit and the link from the switching expansion unit to the back-end device. Link insertion loss is the transmission loss of a signal along its corresponding connection path, expressed in decibels. It addresses scenarios where link signal integrity loss (SI loss) exceeds specification requirements. As PCIe signal rates increase, link insertion loss also increases. Signal integrity describes whether a signal still meets transmission requirements after passing through an actual link. As the measured PCIe signal rate increases, losses caused by on-board traces, connectors, and cables become key factors requiring verification.

[0064] With all other design conditions being equal, the path from CPU 1' to node connector D1, node connection cable, and connector A1 of the first connector group of the test equipment into the switching expansion unit has lower insertion loss than the direct path from CPU 1' to the standard PCIe card via node connector D1, connector C1 of the third connector group of the test equipment, and the slot-type expansion unit. The switching expansion unit has corresponding link driving capabilities, allowing its front and rear sides to be used as separate links for loss design and testing, thus making it suitable for configurations where a tight insertion loss margin needs to be verified.

[0065] For example, loss verification is illustrated using PCIe 6th generation, 64GT / s test equipment, with comparisons made between the front and rear links based on a design budget of 32dB each. The aforementioned speed and loss values ​​are used as test conditions; the front and rear links should be evaluated separately. Two 32dB values ​​cannot be simply combined into a single, unprocessed passive link's allowable loss.

[0066] In other hardware variants used for signal driving capability verification, a retimer can be used to replace the corresponding switching expansion unit location, depending on the test requirements. This verifies the feasibility of the retiming scheme and enhances the link driving capability. The retimer is a device used to recover and retime high-speed signals. This variant follows the approach of constructing test paths using cables. Whether it has multi-port switching functionality should be determined based on the actual device; the retimer should not be treated as equivalent to the function of a switching expansion unit.

[0067] In addition, by using interconnect cables of different lengths, the performance and stability of PCIe devices under different link insertion losses were verified. The PCIe Gen 6 specification defines a link loss of no more than 32dB. By adjusting the cable length, the total link loss can be controlled within ranges of 31dB, 31.5dB, 32dB, 32.5dB, and 33dB, verifying the PCIe capabilities of the switching expansion unit. Combined with tests at different temperatures, the performance of PCIe devices under high-temperature and high-pressure scenarios was comprehensively verified, thereby guiding the link design within the entire server rack.

[0068] This embodiment provides a test path that connects the output of a switching expansion unit to a slot-type expansion unit via cascading cables, forming an intermediate active device. This path can be used to compare the functionality, performance, and loss adaptability of direct connections and connections via switching expansion units. This verifies the feasibility of introducing switching expansion units under specific layout and cabling conditions, providing data support for the overall rack interconnect design.

[0069] In some embodiments, the computing power node includes a general computing power node and an accelerated computing power node. A node connector on one side of the general computing power node is connected to a node connector on one side of the accelerated computing power node. At least one node connector on the other side of the accelerated computing power node is connected to a first connector group or a third connector group via a corresponding node connection cable to form a test link extending from the general computing power node through the accelerated computing power node to a switching expansion unit or a slot expansion unit.

[0070] Specifically, a general-purpose computing node is a node that primarily provides general-purpose processor computing functions; in this embodiment, it is a CPU computing node. An accelerated computing node is a node that provides accelerated processing functions; in this embodiment, it is a GPU node. One side and the other side are used to distinguish the connection positions facing the front-end node and the back-end test equipment, respectively, in the node connection relationship, without limiting the mechanical shape of the node to a specific relative orientation.

[0071] Figure 11 This is a schematic diagram illustrating a test scenario where a cable connection testing device is placed outside the computing node, as provided in an embodiment of this application. Figure 11 As shown, the test equipment is positioned behind the accelerated computing node. The general-purpose computing node is first interconnected with the accelerated computing node. One output of the accelerated computing node is connected to the third connector group of the test equipment, forming a path where the general-purpose computing node, the accelerated computing node, and the slot-type expansion unit are connected sequentially. The other output of the accelerated computing node is connected to the first connector group, and then cascaded with the third connector group via the downlink side of the switching expansion unit, forming a path where the general-purpose computing node, the accelerated computing node, the switching expansion unit, and the slot-type expansion unit are connected sequentially. By comparing the two configurations, the functional and performance differences after introducing switching expansion at the back end can be verified.

[0072] Figure 12 This is a schematic diagram illustrating a test scenario where the cable connection testing device provided in this application is located outside the computing node. Figure 12 As shown, in addition to the paths of general-purpose computing nodes, accelerated computing nodes, switching expansion units, and slot-type expansion units, another node connector of the general-purpose computing node can be directly connected to the slot-type expansion unit of the test device, forming a path from the general-purpose computing node to the slot-type expansion unit. Using PCIe x16 devices on both paths, the data exchange rate between the two devices under this system configuration can be verified, and the performance of the path extended via the accelerated computing node can be compared with that of the direct extension path via the general-purpose computing node.

[0073] This embodiment provides a test device that allows for the addition of test configurations to the system backend while preserving the original interconnection between compute nodes and accelerated compute nodes. Therefore, it can verify the interconnection function of nodes across the entire rack and compare different backend expansion methods, expanding the applicability of the same test device in rack-wide verification.

[0074] In some embodiments, the computing power node includes a general computing power node and an accelerated computing power node. The node connector of the general computing power node is connected to the first connector group through a corresponding node connection cable, and the node connector of the accelerated computing power node is connected to the second connector group through a corresponding node connection cable, so as to form a test link from the general computing power node through the first connector group, the switching expansion unit and the second connector group to the accelerated computing power node.

[0075] Specifically, Figure 13 This is a schematic diagram of a test scenario where a cable connection testing device is placed outside a computing node, as provided in an embodiment of this application. Figure 13As shown, the test equipment is located between the general-purpose computing nodes and the accelerated computing nodes, serving as the interconnect between the two types of nodes in the test environment. The general-purpose computing nodes connect from the uplink side of the switching expansion unit, while the accelerated computing nodes connect from the downlink side. Compared to connections formed solely by a backplane or cable tray, this test configuration incorporates a switching expansion unit in the middle, which can participate in expansion and verification. This allows for testing the link performance between the general-purpose and accelerated computing nodes after the introduction of the switching expansion unit, and effectively distinguishes between the two computing nodes. For problems with unclear causes, it can quickly narrow down the scope, pinpointing whether the problem lies with the general-purpose or accelerated computing node. In other words, when an anomaly with an unclear cause occurs in the overall link, the intermediate switching expansion unit provides a topologically distinguishable link segment between the general-purpose and accelerated computing node sides. By combining individual node testing with test results from each side's configuration, the scope of the anomaly can be narrowed down, helping to determine whether the problem is related to the general-purpose or accelerated computing node side, and comparing whether the introduction of the switching expansion unit meets the corresponding performance requirements.

[0076] Based on the actual interconnection capabilities and configurations of general computing nodes and accelerated computing nodes, test combinations can be selected such as one CPU corresponding to two GPUs, two CPUs corresponding to one GPU, and two CPUs corresponding to two GPUs. Figure 14 This is a schematic diagram illustrating a test scenario where a cable connection testing device is externally placed within a computing node, as provided in an embodiment of this application. Figure 14 As shown, it supports a configuration with two CPUs corresponding to a single GPU. Similarly, it can support a configuration with two CPUs corresponding to two GPUs.

[0077] This embodiment provides a way to replace simple interconnect components in the test environment with the same test equipment, forming a transmission path from general computing nodes to accelerated computing nodes, and providing more port combinations and extended configurations.

[0078] In some embodiments, such as Figure 2 As shown, the cable connection testing equipment also includes a signal verification processor 10 and a fourth connector group F; the first end of the signal verification processor 10 is connected to the first connector group 5, and the second end of the signal verification processor 10 is connected to the first end of the fourth connector group F; the second end of the fourth connector group F is connected to the computing node. The signal verification processor 10 is used to receive the signal to be verified output by the computing node via the fourth connector group F, and to process the signal to be verified in order to obtain the corresponding signal verification result.

[0079] Specifically, the signal verification processor is a processing component used to monitor and manage test equipment and verify related signal functions. It can be a Field Programmable Gate Array (FPGA), a Complex Programmable Logic Device (CPLD), or a Microcontroller Unit (MCU). The fourth connector group is a set of connectors used to extract or connect the required verification signals. Figure 2 The diagram shows connector F. The first and second ends of the signal verification processor represent the interface sides involved in the above connection; it is not required that each interface side has only one pin.

[0080] The signals to be verified are those output by the computing node whose connection status or function needs to be verified. Except for PCIe signals and signals verified by dedicated functional devices, the other corresponding signals are connected to FPGA, CPLD, or MCU. Some of these signals can be directly verified in the signal verification processor, while others are verified after being brought out through connector F. Figure 6 The accelerated computing node shown can transmit relevant management or other functional signals to the signal verification processor through connection with connector F. The signal verification result is a verification conclusion obtained based on the received signal state, corresponding response, or input-output comparison.

[0081] GPIO signals are general-purpose digital signals that can be configured as inputs or outputs according to the test function. For GPIOs actually used in the test equipment, control logic is written according to the corresponding function to enable the signal verification processor to perform predetermined actions or output corresponding states based on the input signals, and the link connectivity is tested. For GPIOs that do not need to perform actual functions in the test equipment, high-level, low-level, or periodic square waves can be transmitted, and the connection can be verified by observing the input and output at the receiving end and comparing them to confirm whether it meets expectations.

[0082] For example, the high and low states of GPIOs can be controlled at a specific frequency, such as a 1MHz square wave. Known state signals output from the node side or test equipment side are transmitted through the corresponding connection path, and the level changes or square wave periods at the receiving side are compared to verify the connectivity and functionality of the path.

[0083] This embodiment provides a signal verification processor and a fourth connector group to connect the relevant signals output by the node to the programmable verification path, thereby improving the testing function of the test equipment.

[0084] In some embodiments, such as Figure 2As shown, it also includes a first communication device 11, a second communication device 12 and a network port 13. The first connector of the first connector group 5 includes a first signal terminal, a second signal terminal, a third signal terminal and a fourth signal terminal. The first communication device 11 is connected to the first signal terminal to form a first signal verification link; The second communication device 12 is connected to the second signal terminal to form a second signal verification link; Network port 13 is connected to the third signal terminal to form a third signal link; The signal verification processor 10 is connected to the fourth signal terminal to form a fourth signal verification link; The first communication device 11, the second communication device 12, the network port 13, and the signal verification processor 10 are respectively used to receive the signal to be verified output by the computing power node through the corresponding signal verification link, and generate the corresponding signal response to determine the connection status of the corresponding signal verification link based on the signal response.

[0085] Specifically, for signals requiring simulated I2C functionality, the corresponding functional core or module can be called in the FPGA, CPLD, or MCU to implement I2C signal processing, and then the link and function can be verified through actual access and response. For management logic that needs to be brought out through connector F, the relevant logic can be programmed in the aforementioned processor first, and then the corresponding signals can be brought out, connected to the node under test, and the actual response can be checked to see if it meets expectations.

[0086] Furthermore, in this embodiment, the first communication device is used to verify the corresponding management bus function, and in this embodiment, it is an I2C device. The second communication device is used to verify the peripheral bus function, and in this embodiment, it is a USB interface device. The network port is an interface used to access network devices. The first connector of the first connector group includes a first signal terminal, a second signal terminal, a third signal terminal, and a fourth signal terminal, each carrying a relevant signal. Each signal terminal represents a terminal or set of terminals required to implement the corresponding function.

[0087] The first communication device connects to the first signal terminal, forming a first signal verification link. The second communication device connects to the second signal terminal, forming a second signal verification link. The network port communicates with the third signal terminal, forming a third signal verification link. The signal verification processor connects to the fourth signal terminal, forming a fourth signal verification link. Each functional device or its connected external device receives the corresponding signal to be verified and generates a corresponding response, determining the connection status of the corresponding path based on the actual response. The above branching structure corresponds to... Figure 2 The connector A1 of the first connector group of the test equipment is connected to the I2C device, USB interface, network port and signal verification processor respectively.

[0088] In the first signal verification link, the I2C device can be a power supply device or a temperature sensor of the test equipment. By accessing the power supply device and executing corresponding controls, the I2C signal function can be verified, and the power supply of the test equipment can be checked to ensure it operates according to the correct timing. By accessing the temperature sensor, the current ambient temperature can be obtained to determine whether it meets the device's operating requirements, and functions such as fan speed regulation can be implemented. This path combines actual monitoring and management actions with signal verification, enabling management functions to be implemented within the test equipment without relying entirely on management devices within another node under test.

[0089] In the second signal verification link, the USB signal is connected to the USB interface. USB functionality is verified using peripherals such as USB flash drives, keyboards, or mice. Support for USB 1.0, 2.0, or 3.0 devices is tested based on the capabilities of the interface under test. The USB signal can also be extended to accelerated computing nodes. For accelerated computing nodes that support log transmission via USB, the USB link and node functionality are verified by observing log transmission. Here, peripheral responses are implemented jointly by the actual USB peripheral and related interfaces; the passive interface connector itself is not used as a processor to execute all protocol processing.

[0090] In the third signal verification link, network-related signals can be MDI signals, or signals such as Reduced Gigabit Media Independent Interface (RGMII) or Serial Gigabit Media Independent Interface (SGMII). Based on the actual network interface design of the node, after connecting to the corresponding network interface circuit and network port, it is connected to the local area network via a network cable or interconnected with the network port of the GPU node to verify network communication and related topology. Different network signals are implemented using interfaces that match their functions; different electrical interfaces are not considered as unconditionally directly connectable to the same passive network port.

[0091] The I2C, USB, and network-related signals mentioned above are categorized under the functional signal verification section for high-speed PCIe interconnects. Other management and miscellaneous functional signals are indicated by MISC in the diagram. This classification is used to differentiate test functions and does not imply that the actual speed of each signal belongs to the same speed class.

[0092] This embodiment provides verification of management, peripheral, and network signals through a branched configuration of actual functional devices. This supplements the high-speed topology testing with verification capabilities for other connector signals, and allows some monitoring, management, and signal response functions to be handled by the test equipment, improving the independence of single-node testing and the reusability of test resources.

[0093] In some embodiments, there are multiple candidate cables in the connection relationship between node connection cables and cascaded cables, which can be used to form test links with different link insertion losses. The signal verification processor is used to determine the target cable that meets the preset signal transmission conditions from multiple candidate cables based on the signal verification results of each test link, so as to form the final topology.

[0094] Specifically, candidate cables are a variety of cables that can be used in the same corresponding connection location and match the connector specifications, mainly achieved through different length specifications. Target cables are those that meet the required test conditions and are selected for subsequent configuration. Preset signal transmission conditions are transmission requirements determined before testing based on the current node, interface, and application requirements. These conditions are used to determine whether the functionality, performance, and stability of the tested configuration meet expectations, rather than relying solely on cable length.

[0095] Specifically, adopt Figure 10 By modifying the cascaded path while maintaining consistent node, board, connector pairing, and other design conditions, different lengths of cables at the corresponding connection locations are used to construct test configurations with varying link insertion losses. This can be done by changing the node connection cable from the node to the test equipment, or by changing the cascaded cable from the downlink side of the switching expansion unit to the slot side. During testing, it is important to distinguish which link segment is being changed to ensure the results correspond to that segment's configuration.

[0096] In the PCIe 6th generation loss testing equipment, by adjusting the cable length, corresponding link conditions with total losses of approximately 31dB, 31.5dB, 32dB, 32.5dB, and 33dB can be constructed to observe the performance and stability changes of the equipment when the design budget is close to 32dB. Configurations exceeding the budget are used to explore device capabilities and design margins, and are not used to directly determine whether the configuration meets the proposed specification or should be selected as the final configuration.

[0097] Transmit test signals under each of the above configurations and observe whether the corresponding functions are completed, whether the relevant equipment can maintain expected operation, and whether the performance meets the current test requirements. Associate the verification results with the candidate cables used and the corresponding connection paths, and the signal verification processor determines the cables that meet the preset signal transmission conditions based on the results.

[0098] Furthermore, the above tests can be repeated under different temperature conditions to comprehensively observe the performance and stability of the equipment under high temperature and high pressure testing scenarios. The specific temperature, voltage, duration, and performance judgment values ​​used are determined based on the equipment under test and the testing requirements. By simultaneously comparing cable and environmental conditions, it can be determined whether the selected connection configuration has a suitable working margin for the corresponding application.

[0099] This embodiment correlates the link conditions formed by different cables with actual verification results, providing a basis for the final cable configuration through testing. By comparing the performance and stability under different loss conditions, it can be used to verify link signal integrity for cable and topology selection.

[0100] Furthermore, this application also provides a cable connection testing system, including at least one computing node and cable connection testing equipment; The computing power node includes multiple node connectors. The two ends of the node connection cable in the cable connection test equipment are respectively connected to multiple node connectors of at least one computing power node and at least one group of each connector group to form a test link for transmitting signals through at least one expansion unit of the switching type expansion unit and the slot type expansion unit. In the case where the cable connection test equipment includes cascaded cables, the two ends of the cascaded cables are connected to the second connector group and the third connector group respectively to form a cascaded test link from the switching expansion unit to the slot expansion unit.

[0101] Specifically, the two ends of the node connection cable are respectively connected to multiple node connectors of at least one computing node and at least one group of connectors, allowing the test signal to be transmitted through at least one of the switching expansion unit and the slot expansion unit. When the system adopts a cascaded configuration, the cascaded cable connects the second connector group and the third connector group, forming a subsequent path from the switching expansion unit to the slot expansion unit. When multiple cables are used, each cable is connected according to its corresponding port relationship.

[0102] For a description of the cable connection testing system provided in this application, please refer to the above method embodiments. This application will not repeat the description here, as it has the same beneficial effects as the above-described cable connection testing equipment.

[0103] The embodiments of this application provide a cable connection testing method, and the method is described in detail in conjunction with the execution flow of the cable connection testing method. Figure 15 A flowchart of a cable connection testing method provided in this application embodiment is shown below. Figure 15 As shown, this method, applied to a cable connection testing system, includes: S11: Obtain the test configuration information of the computing node.

[0104] Test configuration information is used to determine the nodes under test and the required connection methods. It should at least clearly identify the computing power nodes used in this test and the corresponding test links. This information can include the number of computing power nodes, the type of general-purpose or accelerated computing power nodes, the host or device role of each computing power node, the node connectors required, the expansion units to be connected, and whether cascading connections are used. The required information may differ for different tests; the same data fields are not required for every test.

[0105] Obtaining test configuration information clarifies the connection relationship between the test node and the node to be verified. For example, when verifying the direct expansion function of a compute node to a standard PCIe card, the configuration information corresponds to the general-purpose compute node, its master device role, the node connector used, and the slot-type expansion unit. In addition, when comparing the differences before and after the introduction of the switching expansion unit, the participation of the switching expansion unit in transmission and the required cascading relationship can be further clarified.

[0106] When determining the configuration, consider the number of node connectors, the signal distribution of each connector, and the link width (e.g., PCIe x16, x8, or x4) to select matching cables and test equipment ports. For dual-processor nodes, the signal source must be distinguished based on the correspondence between the processor under test and the node connector. For accelerated computing nodes, their role as host, device, or different roles via different ports should be determined based on the actual functions they support.

[0107] This step clarifies the test requirements by defining node roles and port connection relationships, providing a basis for subsequently establishing the actual test link. In this way, changes between different configurations can be reflected in specific port or cable changes, facilitating accurate test organization when reusing the same test equipment.

[0108] S12: According to the test configuration information, the two ends of the node connection cable are respectively connected to multiple node connectors of at least one computing power node and at least one group of each connector group to form a test link for transmitting signals through at least one expansion unit of the switching expansion unit and the slot expansion unit.

[0109] Based on the test configuration information obtained in step S11, both ends of the node connection cable are connected to multiple node connectors of at least one computing node and at least one group of connectors to form a test link for transmitting signals through at least one expansion unit of the switching expansion unit and the slot expansion unit. The connection here is a physical engagement between the cable and the corresponding connector, with multiple cables used to connect multiple groups of ports.

[0110] First, determine the access side of the test equipment based on the master and slave devices. When a node acts as a host and requires switching expansion, the node connection cable is connected to the first connector group; when a node acts as a host and requires direct slot expansion, it is connected to the third connector group; when a node acts as a device, it is connected to the second connector group to receive signals from the downlink side of the switching expansion unit. When the same node has multiple test paths, the access relationships of multiple node connectors can be configured separately.

[0111] Secondly, determine the specific ends of each node connection cable according to the required port correspondence. Connections can be made directly according to the pairing relationship between the node connector and the test equipment connector. Alternatively, the test equipment port connected to the node port participating in cross-testing can be changed. For configurations where two processors are connected to different expansion units, their corresponding node connectors should be connected to the first connector group and the third connector group, respectively. For configurations where two master devices are connected to the same switching expansion unit, the interfaces of different processors should be connected to different connectors in the first connector group.

[0112] Secondly, for multi-node configurations, connections should be made according to the position of the test equipment within the overall topology. Node connection cables should be designed according to the corresponding connector specifications, and the actual wiring should maintain the correspondence between signal distribution and the selected ports. This step establishes the actual test path through variable external cable connections, allowing the access relationship between nodes and expansion units to be adjusted according to the configuration.

[0113] S13: When the test configuration information indicates the formation of a cascaded test link, the two ends of the cascaded cable are connected to the second connector group and the third connector group respectively to form a cascaded test link from the switching expansion unit to the slot expansion unit.

[0114] When the test configuration information indicates the formation of a cascaded test link, connect both ends of the cascaded cable to the second connector group and the third connector group respectively to form a cascaded test link from the switching expansion unit to the slot-type expansion unit. The indication of forming a cascaded test link means that the configuration requires the signal to continue to be transmitted to the slot-type expansion unit through its downstream connector and slot input connector after passing through the switching expansion unit. This can be expressed through specific port connection relationships and does not require setting a flag field with a specific name.

[0115] S14: Control the computing nodes to transmit test signals through the formed test link, and determine the test results of the test link based on the transmission results of the test signals.

[0116] After the corresponding cable connections are established, the control computing nodes transmit test signals through the formed test links, and the test results of the test links are determined based on the transmission results of the test signals. Test signals are signals transmitted to verify the functionality or performance of the selected path. They can be transmission signals in the corresponding PCIe test configuration, or signals used for management, peripheral, network, or GPIO function tests when corresponding verification components are configured.

[0117] The transmission results are the reception, response, functional execution, or data interaction exhibited by the test signal after it actually passes through the specified link. The test results are the judgment made on this link based on these actual performances. The relationship between the two is that the actual transmission performance is observed first, and then the corresponding configuration is judged to meet expectations. The fact that the cable is plugged in cannot be used as the basis for determining whether the functional test has passed.

[0118] For a description of the cable connection testing method provided in this application, please refer to the above method embodiments. This application will not repeat the description here, but it has the same beneficial effects as the above cable connection testing equipment.

[0119] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0120] Embodiments of this application also provide a cable connection testing device. Figure 16 This is a schematic diagram of the structure of a cable connection testing device provided in an embodiment of this application, as shown below. Figure 16 As shown, the device includes: Module 21 is used to obtain the test configuration information of the computing power node; The first component module 22 is used to connect, according to the test configuration information, both ends of the node connection cable to multiple node connectors of at least one computing power node and at least one group of each connector group to form a test link for transmitting signals through at least one expansion unit of the switching expansion unit and the slot expansion unit. The second component module 23 is used to connect to the second connector group and the third connector group respectively through the two ends of the cascade cable when the test configuration information indicates the formation of a cascaded test link, so as to form a cascaded test link from the switching expansion unit to the slot expansion unit. The determination module 24 is used to control the computing power nodes to transmit test signals through the formed test link, and to determine the test results of the test link based on the transmission results of the test signals.

[0121] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above-described cable connection testing method embodiments.

[0122] Embodiments of this application also provide a computer-readable storage medium storing a computer program configured to execute the steps in any of the above-described cable connection testing method embodiments when running.

[0123] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0124] An embodiment of this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the cable connection testing method embodiments described above.

[0125] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described cable connection testing method embodiments.

[0126] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be performed at least in part by one or more hardware logic components, such as, but not limited to, CPUs, FPGAs, Application-Specific Integrated Circuits (ASICs), Application-Specific Standard Products (ASSPs), Systems on Chips (SoCs), CPLDs, MCUs, etc. The terms "system," "computing device," or "apparatus" used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or one or more combinations thereof. The aforementioned computer program (also known as a program, software, software application, application (App), script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0127] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0128] The foregoing has provided a detailed description of the cable connection testing equipment, system, method, and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A cable connection testing device, characterized in that, It includes a first connector group, a second connector group, a third connector group, a switching expansion unit, a slot-type expansion unit, and a cable assembly; The first connector group is connected to the uplink port of the switching expansion unit; the downlink port of the switching expansion unit is connected to the second connector group. The third connector group is connected to the slot-type expansion unit; The cable assembly includes node connection cables, or includes node connection cables and cascade cables; Both ends of the node connection cable are respectively connected to multiple node connectors of at least one computing node and at least one group of connectors to form a test link for transmitting signals through at least one expansion unit of the switching expansion unit and the slot expansion unit; both ends of the cascade cable are respectively connected to the second connector group and the third connector group to form a cascaded test link from the switching expansion unit to the slot expansion unit.

2. The cable connection testing equipment according to claim 1, characterized in that, In the case of a single computing node, where the computing node is the master device, both ends of the node connection cable are respectively connected to at least one node connector of the computing node and the first connector group, so that the computing node transmits test signals through the switching expansion unit. And / or, both ends of the node connection cable are respectively connected to at least one node connector of the computing power node and the third connector group, so that the computing power node transmits test signals through the slot-type expansion unit.

3. The cable connection testing equipment according to claim 1, characterized in that, In the case of a single computing node, where the computing node acts as a slave device, both ends of the node connection cable are connected to at least one node connector of the computing node and the second connector group, respectively, so that the computing node receives a test signal and returns a corresponding response signal through the downlink port of the switching expansion unit.

4. The cable connection testing equipment according to claim 2, characterized in that, There is a preset port correspondence between multiple node connectors in a computing node and multiple connectors in a target connector group. Each node connector is connected to the corresponding connector in the target connector group through a corresponding node connection cable according to the preset port correspondence to form multiple directly connected test links; wherein, the target connector group is the first connector group and / or the third connector group.

5. The cable connection testing equipment according to claim 2, characterized in that, The computing node has multiple node connectors, including a first node connector and a second node connector. The first node connector is connected to the third connector group via a corresponding node connection cable, and the second node connector is connected to the first connector group to form a cross-test link for the computing node to access the switching expansion unit and the slot expansion unit respectively.

6. The cable connection testing equipment according to claim 2, characterized in that, The computing node includes a first processor and a second processor that are redundant with each other; the plurality of node connectors include a first processor connector corresponding to the first processor and a second processor connector corresponding to the second processor. The first processor connector is connected to the third connector group via a corresponding node connection cable, and the second processor connector is connected to the first connector group via a corresponding node connection cable, so that the first processor and the second processor can be cross-connected to the switching expansion unit and the slot expansion unit.

7. The cable connection testing equipment according to claim 2, characterized in that, The computing node includes a first processor and a second processor that are redundant with each other; the plurality of node connectors include a first processor connector corresponding to the first processor and a second processor connector corresponding to the second processor. The first processor connector is connected to the first connector of the first connector group via a corresponding node connection cable, and the second processor connector is connected to the second connector of the first connector group via a corresponding node connection cable. Alternatively, the first processor connector is connected to the first connector of the third connector group via a corresponding node connection cable, and the second processor connector is connected to the second connector of the third connector group via a corresponding node connection cable, so that both the first processor and the second processor are connected to the same switching expansion unit or the same slot-type expansion unit.

8. The cable connection testing equipment according to any one of claims 2 to 7, characterized in that, At least one node connector of the computing node is connected to the first connector group via the node connection cable, and the two ends of the cascade cable are respectively connected to the second connector group and the third connector group to form a cascaded test link in which the computing node passes through the first connector group, the switching expansion unit, the second connector group, the third connector group and the slot expansion unit in sequence.

9. The cable connection testing equipment according to claim 1, characterized in that, The computing power node includes a general computing power node and an accelerated computing power node. One side node connector of the general computing power node is connected to one side node connector of the accelerated computing power node. At least one node connector of the other side node connector of the accelerated computing power node is connected to the first connector group or the third connector group through a corresponding node connection cable to form a test link extending from the general computing power node through the accelerated computing power node to the switching expansion unit or the slot expansion unit.

10. The cable connection testing equipment according to claim 1, characterized in that, The computing power nodes include general computing power nodes and accelerated computing power nodes. The node connector of the general computing power node is connected to the first connector group through a corresponding node connection cable. The node connector of the accelerated computing power node is connected to the second connector group through a corresponding node connection cable, so as to form a test link from the general computing power node through the first connector group, the switching expansion unit and the second connector group to the accelerated computing power node.

11. The cable connection testing equipment according to claim 1, characterized in that, The cable connection testing equipment also includes a signal verification processor and a fourth connector group; a first end of the signal verification processor is connected to the first connector group, and a second end of the signal verification processor is connected to the first end of the fourth connector group; the second end of the fourth connector group is connected to the computing node. The signal verification processor is used to receive the signal to be verified output by the computing node via the fourth connector group, and to process the signal to be verified in order to obtain the corresponding signal verification result.

12. The cable connection testing equipment according to claim 11, characterized in that, There are multiple candidate cables in the connection relationship between the node connection cable and the cascaded cable, which can be used to form test links with different link insertion losses. The signal verification processor is used to determine the target cable that meets the preset signal transmission conditions from multiple candidate cables based on the signal verification results of each test link, so as to form the final topology.

13. A cable connection testing system, characterized in that, It includes at least one computing node and the cable connection testing device as described in any one of claims 1 to 12; The computing node includes multiple node connectors. The two ends of the node connection cable in the cable connection test equipment are respectively connected to multiple node connectors of at least one computing node and at least one group of each connector group to form a test link for transmitting signals through at least one expansion unit of the switching expansion unit and the slot expansion unit. In the case where the cable connection test equipment includes cascaded cables, both ends of the cascaded cables are connected to the second connector group and the third connector group, respectively, to form a cascaded test link from the switching expansion unit to the slot-type expansion unit.

14. A cable connection testing method, characterized in that, The method, applied to the cable connection testing system of claim 13, comprises: Obtain the test configuration information of the computing power nodes; According to the test configuration information, the two ends of the node connection cable are respectively connected to multiple node connectors of at least one computing power node and at least one group of each connector group to form a test link for transmitting signals through at least one expansion unit of the switching expansion unit and the slot expansion unit. When the test configuration information indicates the formation of a cascaded test link, the two ends of the cascaded cable are connected to the second connector group and the third connector group respectively to form a cascaded test link from the switching expansion unit to the slot-type expansion unit. The computing nodes are controlled to transmit test signals through the formed test link, and the test results of the test link are determined based on the transmission results of the test signals.

15. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the cable connection testing method as described in claim 14 when executing the computer program.

Images