A hall element voltage compensation system

Abstract

The application relates to the field of Hall elements, in particular to a Hall element voltage compensation system which comprises a Hall element, a first operational amplifier, a second operational amplifier and a current monitoring module; the second port HP2 and the fourth port HP4 of the Hall element are electrically connected with the non-inverting input end and the inverting input end of the first operational amplifier respectively, the first output end and the second output end of the first operational amplifier are electrically connected with the non-inverting input end and the inverting input end of the second operational amplifier respectively, and the output end of the second operational amplifier outputs a Hall induction voltage Vo; the current detection module monitors the current of the Hall element, obtains the bias voltage change of the Hall element, proportionally samples the Hall current, and provides the first sampling current and the second sampling current to the first operational amplifier and the second operational amplifier respectively, so that the amplification multiple of the Hall induction voltage is adjusted, the fluctuation of the amplifier output voltage caused by voltage fluctuation is offset, and the measurement and application accuracy is improved.

Description

Technical Field

[0001] This invention relates to the field of Hall elements, and more specifically to a Hall element voltage compensation system. Background Technology

[0002] A Hall element is a semiconductor magnetoelectric sensor that operates based on the Hall effect. When current flows through a thin semiconductor sheet and a magnetic field is applied perpendicular to the current direction, the charge carriers are deflected by the Lorentz force, generating a voltage on both sides of the sheet that is proportional to the magnetic field strength. This voltage can be used to indirectly measure the magnitude and direction of the magnetic field. Hall elements are typically made of high-mobility semiconductors such as indium arsenide, indium antimonide, and gallium arsenide, because higher mobility results in a larger Hall voltage under the same magnetic field, thus increasing sensitivity. In practical products, the Hall element, amplifier, voltage regulator circuit, and output stage are integrated together to form a Hall sensor chip.

[0003] Monolithically integrated Hall effect devices are typically fabricated using conventional semiconductor processes such as bipolar, CMOS, or BiCMOS. They are generally constructed using N-type semiconductor materials, such as N-type epitaxial layers or N-wells, and typically feature symmetrical shapes such as squares or crosses. For electrical connections, a common method is to connect the diagonally opposite ends of the Hall effect device to the power supply and ground level respectively, creating a constant-voltage Hall bias. The other two ends of the Hall effect device output a Hall-induced voltage, which is amplified by a differential amplifier before being processed by subsequent circuitry. The drawback of this method is that changes in the power supply cause a linear change in the Hall effect device's induced voltage, resulting in a change in the amplifier's output voltage and introducing significant errors into actual measurements or applications. Summary of the Invention

[0004] The purpose of this invention is to provide a Hall element voltage compensation system, which aims to improve the problem that the induced voltage of the Hall element in conventional connection changes linearly, thus causing the amplifier output voltage to change accordingly, resulting in a large error in actual measurement or application.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A Hall element voltage compensation system includes a Hall element, a first operational amplifier, a second operational amplifier, and a current monitoring module; An external power supply is input to the first port HP1 of the Hall element. The current monitoring module is electrically connected to the third port HP3 of the Hall element and grounded. The second port HP2 and the fourth port HP4 of the Hall element are electrically connected to the non-inverting input and the inverting input of the first operational amplifier, respectively. The first output and the second output of the first operational amplifier are electrically connected to the non-inverting input and the inverting input of the second operational amplifier, respectively. The output of the second operational amplifier outputs the Hall induced voltage Vo. The current monitoring module outputs a first sampling current to the first operational amplifier to adjust the gain of the first operational amplifier, and the current monitoring module outputs a second sampling current to the second operational amplifier to adjust the gain of the second operational amplifier.

[0006] Furthermore, the first port HP1, the second port HP2, the third port HP3, and the fourth port HP4 of the Hall element are all equipped with switching devices and sampling devices.

[0007] Furthermore, the first operational amplifier includes MOSFETs MP1, MP2, MP3, and MP4; An external power supply is input to the source of MOSFET MP1, the source of MOSFET MP2, the source of MOSFET MP3, and the source of MOSFET MP4; the gate of MOSFET MP1 serves as the non-inverting input terminal, and the gate of MOSFET MP2 serves as the inverting input terminal. The gate and drain of MOS transistor MP3 are electrically connected to the drain of MOS transistor MP1 and serve as the first output terminal; the gate and drain of MOS transistor MP4 are electrically connected to the drain of MOS transistor MP2 and serve as the second output terminal; the first sampling current is connected to the gate and drain of MOS transistor MP3 and the gate and drain of MOS transistor MP4. The drain of MOS transistor MP1, the drain of MOS transistor MP2, the gate and drain of MOS transistor MP3, and the gate and drain of MOS transistor MP4 are all grounded through sampling current I2 or I3.

[0008] Furthermore, the circuit structure of the second operational amplifier is the same as that of the first operational amplifier.

[0009] Furthermore, the MOS transistors MP1, MP2, MP3, and MP4 are all PMOS transistors.

[0010] Furthermore, the first operational amplifier includes MOSFETs P220, P213, P239, P235, P194, P195, N107, N405, and N406. An external power supply is input to the source of MOSFET P220, the source of MOSFET P213, the source of MOSFET P239, and the source of MOSFET P235; the gate of MOSFET P194 serves as the non-inverting input terminal, and the gate of MOSFET P195 serves as the inverting input terminal; a monitoring bias signal biasMon is input to the gate of MOSFET N405 and the gate of MOSFET N406, and an external fixed bias voltage signal is input to the gate of MOSFET N107; The gate and drain of MOSFET P220 are electrically connected to the gate of MOSFET P213 and the drain of MOSFET N107. The drain of MOSFET P213 is electrically connected to the source of MOSFET P194 and the source of MOSFET P195. The drain of MOSFET P194 is electrically connected to the gate and drain of MOSFET P239 and the drain of MOSFET N405, and serves as the first output terminal. The drain of MOSFET P195 is electrically connected to the gate and drain of MOSFET P235 and the drain of MOSFET N406, and serves as the second output terminal. The sources of MOSFET N107, MOSFET N405, and MOSFET N406 are all grounded.

[0011] Furthermore, the Hall element is peripherally connected to MOSFETs N191, N190, N188, and N189. The external sample-and-hold clock signal SHck is input to the gate of MOSFET N191 and the gate of MOSFET N188, and the external sample-and-hold clock NOT signal SHckb is input to the gate of MOSFET N190 and the gate of MOSFET N189. The drains of MOSFETs N191 and N190 are connected to the first port HP1 and the second port HP2 of the Hall element, respectively; the sources of MOSFETs N188 and N189 are connected to the third port HP3 and the fourth port HP4 of the Hall element, respectively; the sources of MOSFETs N191 and N190 output Hall sensing voltage HALL02, and the drains of MOSFETs N188 and N189 output Hall sensing voltage HALL01; Furthermore, the Hall element is peripherally connected to MOSFETs N179, N178, N404, P197, P198, and transistor Q15. External Vdd is input to the emitter of transistor Q15, external Hall switch NOT signal hallswb is input to the gate of MOSFET P197 and the gate of MOSFET N179, and external Hall switch signal hallsw is input to the gate of MOSFET P198 and the gate of MOSFET N178. The collector of transistor Q15 is electrically connected to the source of MOSFET P197 and the source of MOSFET P198. The drains of MOSFET P197 and MOSFET P198 are respectively connected to the first port HP1 and the second port HP2 of the Hall element. The drains of MOSFETs N179 and N178 are connected to the third port HP3 and the fourth port HP4 of the Hall element, respectively; the sources of MOSFETs N179 and N178 are electrically connected to the drain and gate of MOSFET N404, and output a monitoring bias signal biasMon to the gate of the sampling current devices MOSFETs N405 and N406 of the amplifier. The source of the MOS transistor N404 and the base of the transistor Q15 are both grounded.

[0012] By adopting the above technical solution, the present invention has the following advantages compared with the prior art: The current detection module monitors the current of the Hall element to obtain the bias voltage change of the Hall element, performs proportional sampling of the Hall current, and provides the first sampling current and the second sampling current to the first operational amplifier and the second operational amplifier respectively, adjusting the amplification factor of the Hall induced voltage to offset the fluctuation of the amplifier output voltage caused by voltage fluctuation, thereby improving the accuracy of measurement and application. Attached Figure Description

[0013] Figure 1 This is a circuit diagram of the Hall element voltage compensation system described in this invention; Figure 2 This is a simplified circuit diagram of the first and second operational amplifiers of the Hall element voltage compensation system described in this invention. Figure 3 This is a circuit diagram of the current monitoring module of the Hall element voltage compensation system described in this invention; Figure 4 This is a circuit diagram of the Hall element peripheral circuit of the Hall element voltage compensation system described in this invention; Figure 5 This is a timing diagram for offset elimination in the Hall element voltage compensation system described in this invention; Figure 6 This is a simulation diagram of the Hall element current and voltage scan of the Hall element voltage compensation system described in this invention; Figure 7 Here are the specific circuit diagrams of the first and second operational amplifiers of the Hall element voltage compensation system described in this invention. Figure 8 This is a simulation diagram of the sampling current scan of the first and second operational amplifiers of the Hall element voltage compensation system described in this invention. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0015] Additionally, it should be noted that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" are all based on the orientation or positional relationship shown in the accompanying drawings. They are merely for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element of the present invention must have a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0016] When an element is referred to as being "fixed to," "set on," or "contained on" another element, it can be directly on or indirectly on that other element. When an element is referred to as being "connected to," it can be directly connected to or indirectly connected to that other element.

[0017] Unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. Example

[0018] Please refer to Figure 1 and Figure 2 As shown, this embodiment provides a Hall element voltage compensation system, including a Hall element, a first operational amplifier, a second operational amplifier, and a current monitoring module. An external power supply is input to the first port HP1 of the Hall element, and the current monitoring module is electrically connected to the third port HP3 of the Hall element and grounded. The second port HP2 and the fourth port HP4 of the Hall element are electrically connected to the non-inverting input and the inverting input of the first operational amplifier, respectively. The voltage difference between the outputs of the second port HP2 and the fourth port HP4 is the Hall induced voltage V of the Hall element. H The first and second output terminals of the first operational amplifier are electrically connected to the non-inverting and inverting input terminals of the second operational amplifier, respectively. The output terminal of the second operational amplifier outputs a Hall-effect voltage Vo. The current monitoring module outputs a first sampling current to the first operational amplifier to adjust its gain, and a second sampling current to the second operational amplifier to adjust its gain.

[0019] The current detection module monitors the current of the Hall element to obtain the bias voltage change of the Hall element. It performs proportional sampling of the Hall current and provides the first and second sampled currents to the first and second operational amplifiers, respectively, adjusting the amplification factor of the Hall-sensed voltage to offset the fluctuations in the amplifier output voltage caused by voltage fluctuations, thereby improving the accuracy of measurement and application. Specifically, the current monitoring module includes MOSFETs MNm, MNm1, and MNm2. MOSFETs MNm, MNm1, and MNm2 form a current mirror structure. The gate and drain of MOSFET MNm serve as the input terminals of the current monitoring module and are electrically connected to the Hall element. MOSFETs MNm1 and MNm2 replicate the current flowing through the Hall element according to the size ratio of MOSFET MNm.

[0020] The Hall element's first port HP1, second port HP2, third port HP3, and fourth port HP4 are all equipped with switching devices and sample-and-hold devices. Logic control is used to alternately supply power to the Hall element diagonally and alternately output Hall induced voltages to eliminate the output offset voltage of the Hall element.

[0021] Please refer to the appendix. Figure 4 and attached Figure 5Specifically, the Hall element is peripherally connected to MOSFETs N179, N178, N191, N190, N188, N189, N404, P197, P198, and transistor Q15. An external Vdd input is connected to the emitter of transistor Q15, and the base of transistor Q15 is grounded. The collector of transistor Q15 is electrically connected to the source of MOSFETs P197 and P198. The drains of MOSFETs P197 and P198 are connected to the first port HP1 and the second port HP2 of the Hall element, respectively. The gate of MOSFET P197 is controlled by the Hall switch inactive signal hallswb, and the gate of MOSFET P198 is controlled by the Hall switch signal hallsw. When the Hall switch inactive signal hallswb and the Hall switch signal hallsw are high, MOSFETs P197 and P198 are turned off. When the Hall switch inactive signal hallswb and the Hall switch signal hallsw are low, MOSFETs P197 and P198 are turned on. The drains of MOSFETs N179 and N178 are connected to the third port HP3 and the fourth port HP4 of the Hall element, respectively. The sources of MOSFETs N179 and N178 are electrically connected to the drain and gate of MOSFET N404. MOSFET N404 is configured as a diode and serves as a current monitoring circuit to monitor the current flowing through the Hall element and output a monitoring bias signal biasMon to the gates of the sampling current devices MOSFETs N405 and N406 of the amplifier. MOSFETs N404, N405, and N406 thus constitute a... Figure 3The circuit includes a current monitoring module for the Hall element voltage compensation system; the source of MOSFET N405 is grounded. The gate of MOSFET N179 is controlled by the Hall switch inverse signal hallswb, and the gate of MOSFET N178 is controlled by the Hall switch signal hallsw. When both hallswb and hallsw are high, MOSFETs N179 and N178 are turned on; when both are low, they are turned off. The drains of MOSFETs N191 and N190 are connected to the first port HP1 and the second port HP2 of the Hall element, respectively; the sources of MOSFETs N188 and N189 are connected to the third port HP3 and the fourth port HP4 of the Hall element, respectively. The sources of MOSFETs N191 and N190 output Hall-induced voltage HALL02, and the drains of MOSFETs N188 and N189 output Hall-induced voltage HALL01. The gates of MOSFETs N191 and N188 are controlled by the sample-and-hold clock signal SHck, while the gates of MOSFETs N190 and N189 are controlled by the sample-and-hold clock NOT signal SHckb. The sample-and-hold clock signal SHck is a non-overlapping control signal that is inverted from the Hall switch signal hallsw, and the sample-and-hold clock NOT signal SHckb is a non-overlapping control signal that is inverted from the Hall switch NOT signal hallswb. When both the sample-and-hold clock signal SHck and the sample-and-hold clock NOT signal SHckb are high, MOSFETs N191, N190, N188, and N189 are turned on; when both are low, MOSFETs N191, N190, N188, and N189 are turned off.

[0022] Among them, the appendix Figure 5 For the disorder elimination time series diagram, by Figure 5It can be seen that the Hall switch signal hallsw and the Hall switch inverse signal hallswb are complementary signals. When the Hall switch signal hallsw is high, the Hall switch inverse signal hallswb is low. At this time, MOSFET P197 is turned on, MOSFET P198 is turned off, MOSFET N179 is turned off, and MOSFET N178 is turned on. The current direction of the Hall element is from the first port HP1 to the third port HP3, forming a Hall induced voltage at the second port HP2 and the fourth port HP4 of the Hall element. Subsequently, the sample-and-hold clock signal SHck is kept low, and the sample-and-hold clock inverse signal SHckb gives a high-level pulse signal, causing MOSFET N191 to be turned off, MOSFET N190 to be turned on, MOSFET N188 to be turned off, and MOSFET N189 to be turned on, thus transmitting the Hall induced voltage at the second port HP2 and the fourth port HP4 of the Hall element. When hallsw is low, hallswb is high. At this time, MOSFET P197 is off, MOSFET P198 is on, MOSFET N179 is on, and MOSFET N178 is off. The current direction of the Hall element is from the second port HP2 to the fourth port HP4, forming Hall induced voltage at the first port HP1 and the third port HP3 of the Hall element. Subsequently, the sample-and-hold clock signal SHckb is kept low, and the sample-and-hold clock signal SHck gives a high-level pulse signal, which makes MOSFET N191 turn on, MOSFET N190 turn off, MOSFET N188 turn on, and MOSFET N189 turn off, outputting the Hall induced voltage at the first port HP1 and the third port HP3 of the Hall element. Thus, the logic controls the diagonal alternating power supply and alternating output of the Hall induced voltage of the Hall element to eliminate the output offset voltage of the Hall element.

[0023] For details, please refer to Figure 4 and Figure 6 , including Figure 6 The simulation diagram of the Hall element current-voltage sweep is attached. Figure 6 It can be seen that as the power supply voltage (Vdd) increases, the absolute value of the current (i(xi_hall.q15)) through the Hall element also increases synchronously.

[0024] Please refer to Figure 2 As shown, specifically, the first operational amplifier and the second operational amplifier adopt the same circuit structure. Taking the first operational amplifier as an example, the first operational amplifier includes MOS transistors MP1, MP2, MP3 and MP4.

[0025] An external power supply is input to the sources of MOSFETs MP1, MP2, MP3, and MP4. The gate of MOSFET MP1 serves as the non-inverting input, and the gate of MOSFET MP2 serves as the inverting input. The gate and drain of MOSFET MP3 are electrically connected to the drain of MOSFET MP1 and serve as the first output. The gate and drain of MOSFET MP4 are electrically connected to the drain of MOSFET MP2 and serve as the second output. A first sampling current is connected to the gate and drain of MOSFETs MP3 and MP4. The drains of MOSFETs MP1, MP2, MP3, and MP4 are all grounded through sampling current I2 or sampling current I3.

[0026] In this embodiment, MOSFETs MP1, MP2, MP3, and MP4 are all PMOS transistors. MOSFETs MP1 and MP2 form a differential pair, with a tail current I1, a fixed bias current generated by an external reference current source. MOSFETs MP3 and MP4 are connected in a diode configuration, with MP1 and MP2 outputting I1 / 2 to the gates of MP3 and MP4, respectively. Currents I2 and I3 are the bias currents of MOSFETs MP3 and MP4, provided by the first sampling current, and satisfy I2 = I3 = IS, where IS is the sampling current of the Hall element. In this embodiment, MOSFETs MP1 and MP3 satisfy the following conditions... (W / L) MP1 (W / L) MP3 =M: 1; where (W / L) MP1 The width-to-length ratio (W / L) of MOSFET MP1 MP3 This refers to the aspect ratio of the MOSFET MP3.

[0027] Therefore, the gain of the first operational amplifier is: ; Among them, g mMP1 For the transconductance of MOSFET MP1, g mMP3 For the transconductance of MOSFET MP3, u p C represents the channel carrier mobility of a PMOS transistor. ox This refers to the gate oxide capacitance per unit area of ​​the PMOS transistor.

[0028] Similarly, the gain of the second operational amplifier can be obtained as follows: ; Therefore, we can conclude that: ; Among them, I H R is the current of the Hall element. H Let I be the equivalent resistance of the Hall element, where I H =N*IS, which simplifies to: Vo=μ*(W / L)*G*[(M*N*I1*R H )*B]; Therefore, the expression for the Hall induced voltage Vo does not contain any parameters related to the power supply voltage. Thus, the Hall induced voltage V output by the Hall element... H The amplified Hall-induced voltage Vo is independent of the power supply voltage, thus achieving voltage compensation for the Hall element.

[0029] In this embodiment, the circuit structure of the second operational amplifier is the same as that of the first operational amplifier. That is, the second operational amplifier also includes MOS transistors MP1, MP2, MP3 and MP4, and the second sampling current is input to the gate and drain of MOS transistor MP3 and the gate and drain of MOS transistor MP4 of the second operational amplifier.

[0030] For details, please refer to Figure 7 and Figure 8 Taking the first operational amplifier as an example, the first operational amplifier specifically includes MOSFETs P220, P213, P239, P235, P194, P195, N107, N405, and N406.

[0031] An external power supply is input to the sources of MOSFETs P220, P213, P239, and P235. The gate of MOSFET P194 serves as the non-inverting input, and the gate of MOSFET P195 serves as the inverting input. The monitoring bias signal biasMon is input to the gates of MOSFETs N405 and N406. The reference bias signal biasREF is an external fixed bias voltage signal, which is input to the gate of MOSFET N107, generating the aforementioned fixed bias current I1 at the drain of MOSFET N107.

[0032] The gate and drain of MOSFET P220 are electrically connected to the gate of MOSFET P213 and the drain of MOSFET N107. The drain of MOSFET P213 is electrically connected to the source of MOSFET P194 and the source of MOSFET P195. The drain of MOSFET P194 is electrically connected to the gate and drain of MOSFET P239 and the drain of MOSFET N405, serving as the first output terminal. The drain of MOSFET P195 is electrically connected to the gate and drain of MOSFET P235 and the drain of MOSFET N406, serving as the second output terminal.

[0033] The sources of MOSFETs N107, N405, and N406 are all grounded. That is, MOSFET P194 is equivalent to MOSFET MP1, MOSFET P195 is equivalent to MOSFET MP2, MOSFET P239 is equivalent to MOSFET MP3, and MOSFET P235 is equivalent to MOSFET MP4.

[0034] Among them, the appendix Figure 8 This is a simulation diagram of the sampling current sweep of the first operational amplifier, provided by Appendix Figure 8 It can be seen that with Figure 6 As the power supply voltage increases, the current of the amplifier's tail current portion I1 remains unchanged (i(xi_hallamp.mn107)), while the current of the Hall element sampled by the amplifier increases synchronously (i(xi_hallamp.mn405)). This means that the amplifier's amplification factor decreases, which counteracts the trend of the Hall-induced voltage of the Hall element increasing due to the voltage rise.

[0035] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A Hall element voltage compensation system, characterized in that, Includes Hall effect sensors, a first operational amplifier, a second operational amplifier, and a current monitoring module; An external power supply is input to the first port HP1 of the Hall element. The current monitoring module is electrically connected to the third port HP3 of the Hall element and grounded. The second port HP2 and the fourth port HP4 of the Hall element are electrically connected to the non-inverting input and the inverting input of the first operational amplifier, respectively. The first output and the second output of the first operational amplifier are electrically connected to the non-inverting input and the inverting input of the second operational amplifier, respectively. The output of the second operational amplifier outputs the Hall induced voltage Vo. The current monitoring module outputs a first sampling current to the first operational amplifier to adjust the gain of the first operational amplifier, and the current monitoring module outputs a second sampling current to the second operational amplifier to adjust the gain of the second operational amplifier.

2. The Hall element voltage compensation system according to claim 1, characterized in that, The Hall element has a switching device and a sampling device at its first port HP1, second port HP2, third port HP3 and fourth port HP4.

3. The Hall element voltage compensation system according to claim 1, characterized in that, The first operational amplifier includes MOSFETs MP1, MP2, MP3, and MP4; An external power supply is input to the source of MOSFET MP1, the source of MOSFET MP2, the source of MOSFET MP3, and the source of MOSFET MP4; the gate of MOSFET MP1 serves as the non-inverting input terminal, and the gate of MOSFET MP2 serves as the inverting input terminal. The gate and drain of MOS transistor MP3 are electrically connected to the drain of MOS transistor MP1 and serve as the first output terminal; the gate and drain of MOS transistor MP4 are electrically connected to the drain of MOS transistor MP2 and serve as the second output terminal; the first sampling current is connected to the gate and drain of MOS transistor MP3 and the gate and drain of MOS transistor MP4. The drain of MOS transistor MP1, the drain of MOS transistor MP2, the gate and drain of MOS transistor MP3, and the gate and drain of MOS transistor MP4 are all grounded through sampling current I2 or sampling current I3. The sampling current I2 or sampling current I3 is the bias current of MOS transistor MP3 and MOS transistor MP4, which is provided by the first sampling current.

4. The Hall element voltage compensation system according to claim 1, characterized in that, The circuit structure of the second operational amplifier is the same as that of the first operational amplifier.

5. The Hall element voltage compensation system according to claim 3, characterized in that, The MOS transistors MP1, MP2, MP3, and MP4 are all PMOS transistors.

6. The Hall element voltage compensation system according to claim 1, characterized in that, The first operational amplifier includes MOSFETs P220, P213, P239, P235, P194, P195, N107, N405, and N406; An external power supply is input to the source of MOSFET P220, the source of MOSFET P213, the source of MOSFET P239, and the source of MOSFET P235; the gate of MOSFET P194 serves as the non-inverting input terminal, and the gate of MOSFET P195 serves as the inverting input terminal; a monitoring bias signal is input to the gate of MOSFET N405 and the gate of MOSFET N406, and a reference bias signal is input to the gate of MOSFET N107; The gate and drain of MOSFET P220 are electrically connected to the gate of MOSFET P213 and the drain of MOSFET N107. The drain of MOSFET P213 is electrically connected to the source of MOSFET P194 and the source of MOSFET P195. The drain of MOSFET P194 is electrically connected to the gate and drain of MOSFET P239 and the drain of MOSFET N405, and serves as the first output terminal. The drain of MOSFET P195 is electrically connected to the gate and drain of MOSFET P235 and the drain of MOSFET N406, and serves as the second output terminal. The sources of MOSFET N107, MOSFET N405, and MOSFET N406 are all grounded.

7. The Hall element voltage compensation system according to claim 1, characterized in that, The Hall element is peripherally connected to MOSFETs N191, N190, N188, and N189. An external sample-and-hold clock signal is input to the gate of MOSFET N191 and the gate of MOSFET N188, and an external sample-and-hold clock NOT signal is input to the gate of MOSFET N190 and the gate of MOSFET N189. The drains of MOSFETs N191 and N190 are connected to the first port HP1 and the second port HP2 of the Hall element, respectively; the sources of MOSFETs N188 and N189 are connected to the third port HP3 and the fourth port HP4 of the Hall element, respectively; the sources of MOSFETs N191 and N190 output Hall-induced voltage HALL02, and the drains of MOSFETs N188 and N189 output Hall-induced voltage HALL01.

8. The Hall element voltage compensation system according to claim 6, characterized in that, The Hall element is peripherally connected to MOSFETs N179, N178, N404, P197, P198 and Q15. An external Vdd input is given to the emitter of transistor Q15; an external Hall switch NOT signal input is given to the gates of MOSFET P197 and MOSFET N179; and an external Hall switch signal input is given to the gates of MOSFET P198 and MOSFET N178. The collector of transistor Q15 is electrically connected to the source of MOSFET P197 and the source of MOSFET P198. The drains of MOSFET P197 and MOSFET P198 are respectively connected to the first port HP1 and the second port HP2 of the Hall element. The drains of MOSFETs N179 and N178 are connected to the third port HP3 and the fourth port HP4 of the Hall element, respectively; the sources of MOSFETs N179 and N178 are electrically connected to the drain and gate of MOSFET N404, and output monitoring bias signals to the gates of the sampling current devices MOSFETs N405 and N406 of the amplifier. The source of the MOS transistor N404 and the base of the transistor Q15 are both grounded.

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