Integrated waveguide optoelectronic co-packaging structure and packaging method thereof

Abstract

The application discloses an integrated waveguide photoelectric co-encapsulation structure and photoelectric co-encapsulation method, and belongs to the technical field of semiconductor packaging. The structure comprises a glass substrate, a first optical waveguide and a conductive interconnection structure are arranged in the glass substrate, one end of the first optical waveguide extends to the inner wall of a blind groove, the other end extends to the side surface of the glass substrate for coupling an optical fiber; a photonic integrated circuit is embedded in the blind groove, a second optical waveguide of the photonic integrated circuit is coupled with the first optical waveguide, a cavity is formed at the gap of one side of the second optical waveguide; a first redistribution layer (RDL) structure, resistors, capacitors and inductors are integrated in the wiring layer of the first RDL structure; a second RDL structure; and an electronic integrated circuit. The application combines the transfer coupling in the glass optical waveguide with the RDL wiring layer integrated passive device, realizes efficient mode field conversion through the optical waveguide, reduces the coupling loss, replaces the external discrete components with the integrated resistance and capacitance, shortens the wiring and reduces the parasitic effect, and solves the problems of large packaging area occupied by discrete resistance and capacitance and serious high-frequency loss in the high-density CPO.

Description

Technical Field

[0001] This invention relates to the field of advanced semiconductor packaging technology, and in particular to an integrated waveguide optoelectronic co-packaging structure and method, which is especially suitable for high-performance optical interconnect scenarios such as high-speed optical modules and optoelectronic co-packaging switches. Background Technology

[0002] With the increasing demands for bandwidth density and energy efficiency from artificial intelligence, high-performance computing, and data centers, the bottlenecks of traditional pluggable optical modules in terms of signal integrity, power consumption, and integration density are becoming increasingly prominent. Co-packaged optics technology tightly integrates optical engines with electrical chips (such as switching chips, CPUs, and GPUs) within the same package to shorten the electrical signal transmission distance, and is considered a key path to overcome the "bandwidth wall."

[0003] Currently, mainstream optoelectronic co-packaging solutions can be mainly divided into the following categories: 2.5D / 3D packaging based on organic substrates: Typically, a silicon interposer or an organic interposer is used to place the electrical integrated circuit (EIC) and optical integrated circuit (PIC) side-by-side or vertically stacked. The optical engine is interconnected with the main chip via a high-speed SerDes interface.

[0004] Silicon-based optoelectronic integration: Utilizing a silicon-on-insulator (SOI) platform to fabricate optical waveguides and devices, achieving monolithic or heterogeneous optoelectronic integration. Silicon photonic engines are typically connected to electrical chips via microbumps or hybrid bonding techniques and are integrally mounted on an organic packaging substrate.

[0005] Plastic fan-out package: The optical chip is embedded in a molding compound and electrical interconnection is achieved through a redistribution layer.

[0006] The aforementioned mainstream optoelectronic co-packaging solutions have the following drawbacks in practical applications: First, there is a significant mismatch in the coefficient of thermal expansion between the organic substrate or molding compound and the silicon chip, generating enormous thermal stress during temperature cycling, leading to fatigue cracking of microbumps and affecting long-term reliability. Second, the high-frequency loss characteristics of molding compounds limit further increases in signal rate. As data rates evolve towards 224G / lane and above, electrical interconnect losses become a constraint on improving system bandwidth. Third, in traditional solutions, the fragile optical port area is easily damaged and contaminated during the optical chip packaging process, resulting in limitations in packaging structure and processes, high packaging costs, and low yields.

[0007] Furthermore, in high-speed CPO (112G / 224G PAM4) scenarios, EIC driver / TIA power filtering, micro-ring MRM modulator temperature control circuit, and high-speed matching termination all require integrated resistor and capacitor components. Traditionally, this relies on external discrete resistor and capacitor components or on-chip resistors and capacitors. Among these, discrete surface-mount capacitors occupy a large package area and suffer from severe high-frequency parasitic effects; while on-chip resistors and capacitors are limited by the area of ​​the PIC chip and process compatibility, resulting in limited integration.

[0008] Therefore, how to integrate passive devices at the packaging substrate level while ensuring efficient optical transmission has become a critical technical problem to be solved in the high-density CPO process.

[0009] The information disclosed in this background section was already known to the inventors prior to the implementation of this application or was acquired during the implementation of this disclosure. Therefore, it may contain information that does not constitute prior art known to the public. Summary of the Invention

[0010] This invention aims to at least partially solve one of the technical problems in the aforementioned technologies. Therefore, the objective of this invention is to propose an integrated optical waveguide optoelectronic co-packaging structure and method. This scheme fabricates an optical waveguide within a glass substrate to serve as an optical path relay and protect the optical port area. Simultaneously, passive devices such as thin-film resistors and MIM capacitors are integrated in the RDL wiring layer of the glass substrate, achieving integrated optical path transmission and passive integration. This solves the technical problems of large package area occupied by discrete resistors and capacitors and severe high-frequency parasitic effects in high-density CPO (Content Packaging Object) packaging.

[0011] To achieve the above objectives, the present invention provides, in a first aspect, an optoelectronic co-packaging structure integrating waveguides, comprising: A glass substrate has a first surface and a second surface opposite to each other. A blind groove is formed on the first surface of the glass substrate. A first optical waveguide and a conductive interconnect structure penetrating the first surface and the second surface are provided in the glass substrate. One end of the first optical waveguide extends to the inner wall of the blind groove and the other end extends to the side surface of the glass substrate for coupling with an external optical fiber. A photonic integrated circuit (PIC) is embedded in the blind trench, and there is a gap between the photonic integrated circuit and the sidewall of the blind trench. A second optical waveguide is provided in the photonic integrated circuit, and the end face of the second optical waveguide is located on the sidewall of the photonic integrated circuit to couple the first optical waveguide. A cavity is formed at the gap on the side with the second optical waveguide. A first wiring structure is disposed on the first surface of the glass substrate. The first wiring structure is electrically connected to the conductive interconnect structure and the photonic integrated circuit. The wiring layer of the first wiring structure integrates resistors, capacitors and inductors. The second wiring structure is disposed on the second surface of the glass substrate and is electrically connected to the conductive interconnect structure; An electronic integrated circuit (EIC) is mounted on the first wiring structure and is electrically connected to the first wiring structure.

[0012] According to an integrated waveguide optoelectronic co-packaging structure of the present invention, the structure uses a glass substrate as a carrier substrate, and a first optical waveguide is provided in the glass substrate as an optical path relay. After the PIC is buried in a blind slot, its second optical waveguide is connected and coupled to the end face of the first optical waveguide. The other end of the first optical waveguide extends to the side surface of the glass substrate and is coupled to an external optical fiber. By coupling through the glass waveguide intermediate end face, the mode field of the chip and the fiber can be matched by the mode field converter, and the mode field loss can be significantly reduced. Mature processes can achieve 1.0~2.5dB. The chip only needs to be coupled to the nearest waveguide end face, which relaxes the chip mounting tolerance (micrometer level). The back-end fiber is only aligned with the flat glass waveguide end face, which makes the fiber coupling more fault-tolerant and suitable for mass production. Array waveguides, beam splitting / combining waveguides, and folding optical paths can be made on a single glass substrate. A single substrate integrates multiple chips and passive beam splitting functions, realizing active and passive integration. The high-density array integration has a strong advantage. The first optical waveguide can be made of glass waveguide, which is the same glass as the substrate. The thermal expansion is perfectly matched. The whole optical path is made of the same substrate, with small high and low temperature loss drift, and better reliability for automotive and industrial applications. Meanwhile, resistors, capacitors and inductors are integrated in the wiring layer of the first wiring structure for EIC drive / TIA power filtering, micro-ring MRM modulator temperature control circuit and high-speed matching termination in high-speed CPO scenarios, replacing external discrete resistors and capacitors, shortening the traces and reducing SerDes loss. Furthermore, the dielectric constant and loss tangent of glass are significantly lower than those of molding compounds. The dielectric constant (Dk approximately 4.5-5.2 @ 10GHz) and loss factor (Df approximately 0.002-0.005) of glass are significantly superior to those of molding compounds (Dk approximately 3.0-3.5, Df approximately 0.008-0.02). Therefore, in high-speed electrical signal transmission, glass exhibits better signal integrity, lower crosstalk, and lower insertion loss. Simultaneously, the higher surface flatness of glass allows for the fabrication of finer RDL linewidths / spacings (<2μm), supporting higher-density PIC-EIC interconnects. Furthermore, the embedded blind slots in the PIC significantly shorten the interconnect distance with the EIC, eliminating long traces on the interposer, significantly reducing high-frequency signal loss and parasitic effects, and improving energy efficiency and bandwidth density. Finally, the coefficient of thermal expansion (CTE) of glass is approximately 3.2 ppm / K, which is more compatible with silicon (PIC / EIC) at 2.7 ppm / K, and far superior to molding compounds (>10 ppm / K). With a temperature of ppm / K, it can significantly reduce thermal cycling stress and improve packaging reliability; and the warpage under thermal cycling at 25-250℃ can be controlled to <50 μm (>300 μm for plastic-encapsulated fan-out), which greatly reduces the risk of stress failure of photonic integrated circuits, reduces stress birefringence of PIC waveguides, avoids optical performance degradation, and is especially suitable for high-power optical devices.

[0013] In addition, the optoelectronic co-packaging structure of the integrated waveguide proposed above according to the present invention may also have the following additional technical features: Optionally, the inductor is a planar spiral inductor, formed by planar spiral traces through the metal wiring layer of the first rewiring structure; or the inductor is a 3D inductor, formed by the conductive interconnect structure, the first metal wiring layer of the first rewiring structure, and the second metal wiring layer of the second rewiring structure.

[0014] Optionally, the resistor is a thin-film resistor, formed on the first surface by TiN deposition, photolithography and etching processes, and electrically connected to the metal wiring layer of the first redistribution structure.

[0015] Optionally, the capacitor is a MIM capacitor, comprising a lower electrode, an insulating layer, and an upper electrode stacked sequentially. The MIM capacitor is disposed between the layers of the first rewiring structure, and the lower electrode is the metal wiring layer of the first rewiring structure.

[0016] Optionally, the back side of the photonic integrated circuit is provided with a metal deposition layer, which is connected to the second rewiring structure through metal interconnect holes.

[0017] Optionally, the photonic integrated circuit is fixed to the bottom of the blind slot by an adhesive layer.

[0018] To achieve the above objectives, a second aspect of the present invention proposes an optoelectronic co-packaging method for integrated waveguides, comprising the following steps: S1. A glass substrate is provided, and a glass through hole or a blind hole opening into the first surface is formed in the glass substrate through a first surface and a second surface opposite to the glass substrate, and a blind groove is formed in the glass substrate on the first surface. S2. A first optical waveguide is formed in the glass substrate. One end of the first optical waveguide extends to the inner wall of the blind groove, and the other end extends to the side surface of the glass substrate for coupling with an external optical fiber. S3. Metallize the glass via or the blind via to form a conductive interconnect structure; and process a thin film resistor on the first surface. S4. A photonic integrated circuit is provided, wherein a second optical waveguide is provided within the photonic integrated circuit and the end face of the second optical waveguide is located on the sidewall of the photonic integrated circuit; the photonic integrated circuit is embedded in the blind trench and a gap is left between it and the sidewall of the blind trench; a film is pressed and patterned on the first surface to form a cavity at the gap on the side with the second optical waveguide, exposing the pads of the photonic integrated circuit, the conductive interconnect structure and the connection terminal of the thin film resistor; the cavity couples the second optical waveguide to the first optical waveguide; S5. A protective film is covered on the first surface of the glass substrate to seal the cavity, and a first rewiring structure is fabricated, such that the first rewiring structure is electrically connected to the conductive interconnect structure, the pads of the photonic integrated circuit, and the connection terminal of the thin film resistor; a capacitor and an inductor are integrated in the wiring layer of the first rewiring structure. S6. A second rewiring structure is formed on the second surface of the glass substrate, and the second rewiring structure is electrically connected to the conductive interconnect structure. S7. Provide an electronic integrated circuit, mount the electronic integrated circuit on the first wiring structure, so that the electronic integrated circuit is electrically connected to the first wiring structure; open the protective film.

[0019] According to a method for optoelectronic co-packaging of integrated waveguides based on the present invention, this method uses a glass substrate to replace the molding compound in the plastic fan-out scheme. Blind slots and glass vias / blind holes are formed on the glass substrate. A first optical waveguide is formed within the glass substrate as an optical path relay. A photonic integrated circuit with a second optical waveguide is embedded in the blind slot, allowing the second optical waveguide to be coupled face-to-face with the first optical waveguide. The other end of the first optical waveguide extends to the side surface of the glass substrate and couples with an external optical fiber. Through face-to-face coupling via the glass optical waveguide relay, mode field loss can be reduced to 1.0~2.5dB; chip mounting tolerance is relaxed to the micrometer level, suitable for mass production; active and passive integration can be achieved on a single glass substrate, offering strong advantages in high-density array integration; a cavity is formed at the gap on one side of the second optical waveguide by lamination patterning and sealed with a protective film, preventing subsequent RDL fabrication processes from contaminating the optical waveguide face and ensuring the cleanliness of the optical coupling area. Simultaneously, a thin-film resistor is formed on the first surface, and capacitors and inductors are integrated in the wiring layer of the first rewiring structure, realizing the integration of passive devices and optical path transmission. This is used for EIC drive / TIA power filtering, micro-ring MRM modulator temperature control circuit, and high-speed matching termination in high-speed CPO scenarios, replacing external discrete resistors and capacitors, shortening traces, and reducing SerDes loss. In addition, the low loss and low CTE characteristics of glass further improve high-frequency signal integrity and thermomechanical reliability.

[0020] In addition, the optoelectronic co-packaging method for integrated waveguides proposed above according to the present invention may also have the following additional technical features: Optionally, in step S3, the thin film resistor is formed on the first surface by TiN deposition, photolithography and etching processes.

[0021] Optionally, in step S5, the capacitor is a MIM capacitor, comprising a lower electrode plate, an insulating layer, and an upper electrode plate stacked sequentially, wherein the lower electrode plate is the metal wiring layer of the first rewiring structure.

[0022] Optionally, in step S5, the protective film is a high-modulus dry film.

[0023] Optionally, a metal deposition layer is formed on the back side of the photonic integrated circuit. Step S1 further includes: forming a TGV hole on the glass substrate that penetrates the bottom of the blind trench and the second surface; and step S3 further includes: metallizing the TGV hole to form a metal interconnect hole; the metal interconnect hole is connected to the metal deposition layer in step S4 and to the second rewiring structure in step S6.

[0024] Optionally, in step S7, the protective film is opened using a laser grooving process, and the cavity is cleaned.

[0025] Optionally, in step S5, when fabricating the first rewiring structure, the metal wiring layer of the first rewiring structure is arranged with planar spiral traces to form a planar spiral inductor; or, in step S5, when fabricating the first rewiring structure, the first metal wiring layer of the first rewiring structure is arranged with multiple first metal connection layers, and in step S6, when fabricating the second rewiring structure, the first metal wiring layer of the second rewiring structure is arranged with multiple second metal connection layers, and the multiple first metal connection layers and the multiple second metal connection layers are sequentially electrically connected through the conductive interconnection structure to jointly form a 3D inductor. Attached Figure Description

[0026] Figure 1 This is a cross-sectional schematic diagram of the optoelectronic co-packaging structure of Embodiment 1 of the present invention; Figure 2 This is a schematic flowchart of the optoelectronic co-packaging method according to Embodiment 1 of the present invention; Figures 3-14 This is a cross-sectional schematic diagram of the packaging structure for each step of the optoelectronic co-packaging method in Embodiment 1 of the present invention; Figure 15 This is a cross-sectional schematic diagram of the optoelectronic co-packaging structure of Embodiment 2 of the present invention; Label Explanation: Glass substrate 100, first surface 100a, second surface 100b, blind trench 110, conductive interconnect structure 120, first optical waveguide 130, cavity 140, metal interconnect hole 150; Photonic integrated circuit 200, second optical waveguide 210, metal deposition layer 220; Protective film 300; The first layer of wiring structure is 400, thin film resistor R, capacitor C, and inductor L; Second wiring structure 500, external connection terminal 510; Electronic integrated circuit 600. Detailed Implementation

[0027] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0028] This application is based on the inventor's considerations regarding the following aspects: In related optoelectronic co-packaging solutions, the molding compound fan-out solution uses molding compound embedded in the PIC chip. However, the CTE mismatch between the molding compound and the silicon chip leads to significant warpage and chip misalignment issues, directly affecting coupling accuracy and yield. Simultaneously, the high-frequency loss characteristics of the molding compound limit further increases in signal rate. Furthermore, in high-speed CPO (112G / 224G PAM4) scenarios, EIC driver / TIA power filtering, micro-ring MRM modulator temperature control circuit, and high-speed matching termination all require integrated resistor-capacitor components. Traditional discrete resistors and capacitors occupy a large package area and suffer from severe high-frequency parasitic effects.

[0029] On the other hand, existing PIC slotting solutions require pre-fabricating deep trenches on the PIC, with the dicing lines located within these trenches. This slotting solution suffers from the following drawbacks: inconsistent trench sidewall depths, easy edge chipping at trench corners, residual etching residue, and partial exposure of the end-face tapered mode field converter, directly impacting the optical quality and packaging yield of the coupling end face; high-speed RF traces and PAD wiring cannot be placed above the slotted area, compressing the active area; slotting requires reserving trench safety clearances, wasting dicing traces and effective chip area, reducing wafer layout utilization; deep trench lithography and dry deep etching processes are expensive and have large yield fluctuations; deep etching introduces lattice stress and dielectric layer microcracks on the waveguide sides, causing waveguide loss drift. Furthermore, the slotting space is small, and the assembly and adjustment of laser / discrete optical chips is difficult.

[0030] To address this, this application proposes an optoelectronic co-packaging scheme with integrated waveguides. A first optical waveguide is fabricated within a glass substrate to serve as an optical relay. Simultaneously, passive devices such as thin-film resistors, MIM capacitors, and inductors are integrated in the RDL wiring layer of the glass substrate, achieving the integration of optical path transmission and passive integration. This solves the technical problems of large package area occupied by discrete resistors and capacitors and severe high-frequency parasitic effects in high-density CPO packaging.

[0031] Specifically, according to one or more embodiments, an optoelectronic co-packaging structure of an integrated waveguide includes: a glass substrate having opposing first and second surfaces; a blind groove formed on the first surface of the glass substrate; a first optical waveguide and a conductive interconnect structure penetrating the first and second surfaces disposed within the glass substrate; one end of the first optical waveguide extending to the inner wall of the blind groove and the other end extending to the side surface of the glass substrate for coupling with an external optical fiber; a photonic integrated circuit embedded within the blind groove; a gap between the photonic integrated circuit and the side wall of the blind groove; and a second optical waveguide disposed within the photonic integrated circuit. The end face of the second optical waveguide is located on the sidewall of the photonic integrated circuit to couple the first optical waveguide; wherein a cavity is formed in the gap on the side having the second optical waveguide; a first rewiring structure is disposed on the first surface of the glass substrate, and the first rewiring structure is electrically connected to the conductive interconnect structure and the photonic integrated circuit respectively; a resistor, capacitor and inductor are integrated in the wiring layer of the first rewiring structure; a second rewiring structure is disposed on the second surface of the glass substrate and is electrically connected to the conductive interconnect structure; an electronic integrated circuit is mounted on the first rewiring structure and is electrically connected to the first rewiring structure.

[0032] In other words, the optoelectronic co-package structure of this integrated waveguide integrates the optical waveguide and passive devices on the same package structure, realizing the dual functions of optical path transmission and passive integration. The optical signal is coupled through the glass waveguide, and the PIC only needs to be coupled to the nearest waveguide end face, which relaxes the chip mounting tolerance. The back-end optical fiber is only aligned with the flat glass waveguide end face, which has greater fault tolerance for fiber coupling and is suitable for mass production. At the same time, the RC components are integrated in the RDL wiring layer to replace the external discrete RC components, shorten the wiring, reduce SerDes loss, and significantly improve the integration density and energy efficiency ratio.

[0033] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the invention to those skilled in the art.

[0034] Figure 1 An optoelectronic co-package structure for an integrated waveguide according to one or more embodiments is shown. Reference Figure 1 The optoelectronic co-packaging structure includes: a glass substrate 100, a photonic integrated circuit 200, a first rewiring structure 400, a second rewiring structure 500, and an electronic integrated circuit 600.

[0035] Specifically, the glass substrate 100 has opposing first surfaces 100a and second surfaces 100b, with a coefficient of thermal expansion of 2.5-3.5 ppm / K, which highly matches the coefficient of thermal expansion of silicon chips, significantly reducing thermal stress during temperature cycling. A blind trench 110 is formed on the first surface 100a of the glass substrate 100. A first optical waveguide 130 and a conductive interconnect structure 120 penetrating the first and second surfaces 100b are disposed within the glass substrate 100. One end of the first optical waveguide 130 extends to the inner wall of the blind trench 110, and the other end extends to the side surface of the glass substrate 100 for coupling with external optical fibers. The first optical waveguide 130 is fabricated inside the glass substrate 100 using a femtosecond laser direct-writing process to form a glass waveguide, and is an integral structure with the glass substrate 100. The conductive interconnect structure 120 has a diameter of 30-60 μm and a spacing of 60-200 μm, and is distributed in the peripheral area of ​​the blind trench 110.

[0036] The blind slot 110 is a blind hole structure with its opening facing the first surface 100a, and its depth matches the thickness of the photonic integrated circuit 200.

[0037] A photonic integrated circuit 200 is embedded within a blind trench 110, with a gap between the photonic integrated circuit 200 and the sidewall of the blind trench 110. A second optical waveguide 210 is provided within the photonic integrated circuit 200, with its end face located on the sidewall of the photonic integrated circuit 200 to couple with a first optical waveguide 130. A cavity 140 is formed at the gap on the side with the second optical waveguide 210. The photonic integrated circuit 200 is fixed to the bottom of the blind trench 110 by an adhesive layer, the gap is filled with an insulating dry film, and the cavity 140 allows for optical coupling between the second optical waveguide 210 and the first optical waveguide 130 via air. The adhesive layer firmly fixes the PIC to the bottom of the blind trench, and the insulating dry film fills the gap and covers the first surface 100a of the glass substrate 100, providing a flat process surface for RDL fabrication; however, the insulating dry film forming the gap of the cavity 140 is removed.

[0038] A first wiring structure 400 is disposed on the first surface 100a of the glass substrate 100, and includes at least one metal wiring layer with a line width / spacing of 5-20 μm. The dielectric layer is made of materials such as polyimide or ABF. The first wiring structure 400 is electrically connected to the pads of the conductive interconnect structure 120 and the photonic integrated circuit 200, respectively. Resistors, capacitors, and inductors are integrated in the wiring layer of the first wiring structure 400.

[0039] Specifically, the resistor in this embodiment can be a thin-film resistor, formed on the first surface 100a by TiN deposition, photolithography, and etching processes, and electrically connected to the metal wiring layer of the first rewiring structure 400. This thin-film resistor can be used as a decoupling resistor in EIC drive / TIA power supply filtering, a voltage divider resistor in the temperature control circuit of a micro-ring MRM modulator, or a terminating matching resistor in high-speed matching termination to eliminate reflection loss.

[0040] The capacitor can be a MIM capacitor, comprising a lower electrode, an insulating layer, and an upper electrode stacked sequentially. The MIM capacitor is disposed between the layers of the first wiring structure 400. The lower electrode is the metal wiring layer of the first wiring structure 400, meaning the lower electrode is copper, and the upper electrode is aluminum. The insulating layer acts as the insulating dielectric separating the two electrodes; the insulating layer can be a silicon nitride insulating layer or a polyimide insulating layer, etc. This MIM capacitor can be used as a decoupling capacitor in EIC drive / TIA power filtering, replacing external discrete capacitors, shortening traces, and reducing SerDes losses; or as a DC blocking capacitor in high-speed matching termination, reducing the number of traces on the packaged PCB.

[0041] The inductor can be a planar inductor disposed in the first wiring structure 400, that is, a planar inductor formed by planar spiral traces through the metal wiring layer of the first wiring structure 400. Alternatively, it can be a 3D inductor, which is jointly constructed by the conductive interconnect structure 120, the first metal wiring layer of the first wiring structure 400, and the second metal wiring layer of the second wiring structure 500. In other words, a 3D inductor can be formed by three-dimensional winding through TGV vias and the first and second metal wiring layers of the first and second wiring structures 400, resulting in a higher Q value.

[0042] The second wiring structure 500 is disposed on the second surface 100b of the glass substrate 100, and includes at least one metal wiring layer, which is electrically connected to the conductive interconnect structure 120. The second wiring structure 500 is provided with external connection terminals 510, which are solder balls or copper pillar bumps, and can be directly electrically connected to an external printed circuit board.

[0043] The electronic integrated circuit 600 is mounted on the first wiring structure 400 and electrically connected to the first wiring structure 400 through micro-bumps.

[0044] The optoelectronic co-packaging structure with integrated waveguide in this embodiment integrates functional units such as optical waveguide, conductive interconnect structure, and passive devices on a single packaging substrate. It replaces the existing multi-component stacking of silicon interposers, organic substrates, fiber arrays, and discrete resistors and capacitors, reducing the packaging height, improving the overall yield, and reducing the manufacturing cost.

[0045] Specifically, this optoelectronic co-packaging structure has the following advantages: (1) Advantages of glass waveguide relay end face coupling: The end face of the photonic integrated circuit is first connected to the integrated optical waveguide on the glass, and the optical waveguide serves as the optical path transition. Then, the other end face of the glass waveguide is connected to the optical fiber; the optical path is the chip end face. Air Glass waveguide end face Glass waveguide core layer Waveguide optical end face Optical fiber. Glass serves as both the packaging substrate and the transmission optical path. This allows for matching the chip and fiber mode field via a mode field converter, significantly reducing mode field loss; mature processes can achieve 1.0~2.5dB. The chip only needs to be coupled to the nearest waveguide end face, relaxing chip mounting tolerances (micrometer level). The back-end fiber is aligned only with the flat glass waveguide end face, resulting in greater fiber coupling tolerance and suitability for mass production. Arrayed waveguides, beam splitters / combiners, and folding optical paths can be fabricated on a single glass substrate. A single substrate integrates multiple chips and passive beam splitting functions, achieving active and passive integration, with significant advantages in high-density array integration. The first optical waveguide can be made of glass, homogeneous with the substrate, ensuring perfect thermal expansion matching. The homogeneous substrate throughout the optical path results in minimal high and low temperature loss drift, offering superior reliability for automotive and industrial applications.

[0046] (2) Advantages of passive component integration: Resistors, capacitors, and inductors are integrated in the wiring layer of the first wiring structure for the following three core applications in high-speed CPO scenarios: First, EIC driver / TIA power supply filtering. The PIC is equipped with a transimpedance amplifier (TIA) and a modulator driver chip. High-frequency power supply has power supply noise and switching parasitics. On-chip thin film resistors and MIM capacitors are used for decoupling and filtering, replacing external discrete resistors and capacitors, shortening the traces and reducing SerDes losses. Traditional discrete surface mount capacitors account for more than 30% of the package area. Second, micro-ring MRM modulator temperature control loop resistors and capacitors. The micro-ring modulator has its own on-chip heating resistor and temperature sensing diode. It is equipped with RC filter and voltage divider resistor to form a closed-loop temperature control circuit. The on-chip integrated RC network replaces the external surface mount components, solving the MRM temperature drift problem. Third, high-speed matching termination resistors and capacitors. 224G high-speed optoelectronic interconnect impedance matching. The PIC-EIC bonding interface integrates terminating matching thin film resistors and DC blocking capacitors to eliminate reflection losses and reduce the number of PCB traces.

[0047] (3) Excellent high-frequency and high-speed signal integrity: The dielectric constant and loss tangent of glass are much lower than those of molding compounds. The dielectric constant of glass (Dk approximately 4.5-5.2 @ 10 GHz) and loss factor (Df approximately 0.002-0.005) are significantly better than those of molding materials (Dk approximately 3.0-3.5, Df approximately 0.008-0.02). In high-speed electrical signal transmission, the signal integrity is better, the crosstalk is lower, and the insertion loss is smaller. At the same time, the surface flatness of glass is higher, which can produce finer RDL linewidth / spacing (<2 μm) and support higher density PIC-EIC interconnects.

[0048] (4) Excellent electrical performance and energy efficiency: The glass blind trench embedded in the PIC significantly shortens the interconnection distance with the EIC. Microbumps or hybrid bonding can be used to eliminate long traces on the interposer or substrate, significantly reduce high-frequency signal loss and parasitic effects, and improve energy efficiency and bandwidth density.

[0049] (5) Excellent thermomechanical reliability: The coefficient of thermal expansion (CTE) of glass is approximately 3.2 ppm / K, which is more compatible with silicon (PIC / EIC) at 2.7 ppm / K and far superior to molding compounds (>10 ppm / K). This significantly reduces thermal cycling stress and improves packaging reliability. Furthermore, the warpage under thermal cycling at 25-250℃ can be controlled to <50 μm (>300 μm for molded fan-out), greatly reducing the risk of stress failure in optical chips. This can also reduce stress birefringence in PIC waveguides and avoid optical performance degradation, making it particularly suitable for high-power optical devices.

[0050] (6) Manufacturing compatibility and scalability: Glass wafers are compatible with mature semiconductor wafer-level processes, making it easier to achieve through-hole glass (TGV) and 3D stacking. The via size and pitch are smaller, and the via density is higher (TGV minimum aperture can reach 5 μm, mass production is 20-50 μm; TMV is usually above 50 μm or even 450 μm), which is more conducive to high-density interconnects.

[0051] According to one or more embodiments, this embodiment also provides an optoelectronic co-packaging method for integrated waveguides. Figure 2 A process flow for an optoelectronic co-packaging method for integrated waveguides according to one or more embodiments is shown. (Reference) Figure 2 The optoelectronic co-packaging method includes the following steps: S1. A glass substrate is provided, and a glass through hole or a blind hole opening into the first surface is formed in the glass substrate through a first surface and a second surface opposite to the glass substrate, and a blind groove is formed in the glass substrate on the first surface. S2. A first optical waveguide is formed in the glass substrate. One end of the first optical waveguide extends to the inner wall of the blind groove, and the other end extends to the side surface of the glass substrate for coupling with an external optical fiber. S3. Metallize the glass via or the blind via to form a conductive interconnect structure; and process a thin film resistor on the first surface. S4. A photonic integrated circuit is provided, wherein a second optical waveguide is provided within the photonic integrated circuit and the end face of the second optical waveguide is located on the sidewall of the photonic integrated circuit; the photonic integrated circuit is embedded in the blind trench and a gap is left between it and the sidewall of the blind trench; a film is pressed and patterned on the first surface to form a cavity at the gap on the side with the second optical waveguide, exposing the pads of the photonic integrated circuit, the conductive interconnect structure and the connection terminal of the thin film resistor; the cavity couples the second optical waveguide to the first optical waveguide; S5. A protective film is covered on the first surface of the glass substrate to seal the cavity, and a first rewiring structure is fabricated, such that the first rewiring structure is electrically connected to the conductive interconnect structure, the pads of the photonic integrated circuit, and the connection terminal of the thin film resistor; a capacitor and an inductor are integrated in the wiring layer of the first rewiring structure. S6. A second rewiring structure is formed on the second surface of the glass substrate, and the second rewiring structure is electrically connected to the conductive interconnect structure. S7. Provide an electronic integrated circuit, mount the electronic integrated circuit on the first wiring structure, so that the electronic integrated circuit is electrically connected to the first wiring structure; open the protective film.

[0052] In other words, this method uses glass waveguides as intermediate end-face coupling, and the mode field of the chip and the fiber can be matched by a mode field converter, significantly reducing mode field loss. Mature processes can achieve 1.0~2.5dB. The chip only needs to be coupled to the nearest waveguide end-face, relaxing chip mounting tolerances (micrometer level). The back-end fiber is only aligned with the flat glass waveguide end-face, resulting in greater fiber coupling fault tolerance and suitability for mass production. Array waveguides, beam splitting / combining waveguides, and folding optical paths can be fabricated on a single glass substrate. A single substrate integrates multiple chips and passive beam splitting functions, achieving active and passive integration, with strong advantages in high-density array integration. Only a small area of ​​the chip end-face is connected to the waveguide, with most of the chip attached to the substrate, resulting in better stress isolation. The first optical waveguide can be made of glass, which is the same type of glass as the substrate, ensuring perfect thermal expansion matching. The homogeneous substrate throughout the optical path results in low high and low temperature loss drift, providing superior reliability for automotive and industrial applications. Meanwhile, the PIC does not require trenching to cut out light, eliminating the need for two core photonic processes: deep trench lithography and dry deep etching, thus avoiding waveguide cracking caused by trenching stress. Resistors, capacitors, and inductors are integrated in the wiring layer of the first wiring structure for EIC drive / TIA power filtering, micro-ring MRM modulator temperature control circuit, and high-speed matching termination in high-speed CPO scenarios, replacing external discrete resistors and capacitors, shortening traces, and reducing SerDes losses.

[0053] For details, please refer to Figures 3 to 14 as well as Figure 1 The diagram shows a cross-sectional view of each step in the above-described optoelectronic co-packaging method for integrated waveguides.

[0054] First, refer to Figure 3 Step S1: Provide a glass substrate 100, process a glass through hole through the first surface 100a and the second surface 100b of the glass substrate 100 or a blind hole opening on the first surface 100a, and process a blind groove 110 on the first surface 100a.

[0055] Specifically, the glass substrate 100 can be made of borosilicate glass with a thermal expansion coefficient of 2.5-3.5 ppm / K, which is highly compatible with the thermal expansion coefficient of silicon chips. This significantly reduces thermal stress during temperature cycling and improves packaging reliability. The blind trench 110 and glass vias / blind holes can be fabricated using a combination of laser-induced and wet etching processes: first, a femtosecond laser is used to scan and induce a predetermined area, causing localized modification of the glass to create a difference in etching selectivity; then, wet etching is performed in a hydrofluoric acid etching solution. The fabricated blind trench 110 is an upward-opening blind trench on the first surface 100a of the glass substrate, with a depth matching the thickness of the subsequently embedded photonic integrated circuit 200; glass vias or blind holes are distributed in the peripheral area of ​​the blind trench 110.

[0056] Since the blind slot 110 is used for embedding subsequent photonic integrated circuits, after step S1, the left side of the blind slot 110 can be finely processed, for example, by sidewall polishing.

[0057] Next, refer to Figure 4 Step S2: A first optical waveguide 130 is formed in the glass substrate 100. One end of the first optical waveguide 130 extends to the inner wall of the blind groove 110 (i.e., the right side wall of the blind groove 110), and the other end extends to the side surface of the glass substrate 100 for coupling with an external optical fiber.

[0058] Specifically, the first optical waveguide 130 is formed inside the glass substrate 100 using a femtosecond laser direct writing process: a femtosecond laser is focused into the glass to modify it and create a change in refractive index. This includes: pretreatment (ultrasonic cleaning and drying of the glass substrate 100); focusing and direct writing (using a high numerical aperture objective lens to focus a high-energy femtosecond laser pulse to approximately 50 μm to several hundred micrometers below the glass surface, and using a computer-controlled displacement stage to precisely move the laser focus along a preset path inside the glass, inducing a permanent change in the material's refractive index to form the waveguide); and section polishing (fine polishing of the sample to reduce end-face scattering loss). Performance testing: the waveguide structure is measured using a microscopic system or a spectrometer to test key performance indicators such as transmission loss. Of course, in other examples, the first optical waveguide 130 can also be fabricated using an ion exchange process: the refractive index of the glass is changed by ion "replacement" in a high-temperature salt bath, mainly including the following steps: substrate preparation and cleaning, using soda-lime glass, BK7, or other alkali metal ion-containing glass, and ultrasonically cleaning it; deposition of a mask layer, depositing a metal or dielectric film such as aluminum / titanium / silicon on the glass surface as a barrier layer; photolithography and windowing, uniform coating, exposure and development using a mask, etching away the mask in the window area to expose the glass to be exchanged; ion exchange: immersing the glass in a molten salt containing exchange ions (such as AgNO3 or KNO3) and heating it at high temperature, the high refractive index ions (Ag) in the molten salt (AgNO3, KNO3, etc.) in the molten salt... + or K + Na in the replacement glass + This process forms the "core layer." Depending on the required diffusion depth, it involves a single exchange (surface diffusion only) and a second exchange (high-temperature annealing to form a buried waveguide). Mask removal / annealing: residual mask is removed by etching, followed by final annealing at a specific temperature. End-face polishing: the glass end face is ground and polished for subsequent coupling with optical fibers. The completed first optical waveguide 130 has an input end face flush with the sidewall of the glass substrate 100, which can be used to connect to external optical fibers.

[0059] Next, refer to Figure 5 and Figure 6 Step S3 is performed: the glass via or blind via is metallized to form a conductive interconnect structure 120; and a thin film resistor R is formed on the first surface 100a.

[0060] Specifically, the metallization of glass vias or blind holes adopts an electroplating copper filling process: first, a Ti / Cu seed layer is deposited on the inner wall of the glass via or blind hole by magnetron sputtering; then, a DC electroplating process is used to fill the glass via or blind hole with metallic copper; finally, the excess metal layer on the surface of the glass substrate 100 is removed by chemical mechanical polishing, and the top of the formed conductive interconnect structure 120 is exposed on the first surface 100a of the glass substrate 100.

[0061] The thin-film resistor R can be formed on the first surface 100a through TiN deposition, photolithography, etching, and resist stripping processes. Specifically, a TiN thin film is first deposited on the first surface 100a of the glass substrate 100 by physical vapor deposition, then photoresist is coated, the resistor pattern is defined by photolithography, and finally the thin-film resistor R is formed by etching and resist stripping.

[0062] Next, refer to Figure 7 Step S4: Provide a photonic integrated circuit 200, in which a second optical waveguide 210 is provided and the end face of the second optical waveguide 210 is located on the side wall of the photonic integrated circuit 200; embed the photonic integrated circuit 200 in a blind trench 110 and leave a gap between it and the side wall of the blind trench 110; press a film on the first surface 100a and pattern it to form a cavity 140 at the gap on the side with the second optical waveguide 210, and expose the pads of the photonic integrated circuit 200, the conductive interconnect structure 120 and the connection terminal of the thin film resistor R; the cavity 140 couples the second optical waveguide 210 with the first optical waveguide 130.

[0063] Specifically, the back side of the photonic integrated circuit 200 can be attached to the bottom of the blind slot 110 via an adhesive layer (such as a DAF film). The sidewalls of the photonic integrated circuit 200 are flat sidewalls that have been ground and polished, and the waveguide end face has consistent flatness and perpendicularity. In other words, the provided photonic integrated circuit 200 eliminates two core photonic processes: deep trench lithography and dry deep etching. PIC trenching involves micron-level deep silicon etching, a process that is expensive and has high yield fluctuations. Direct side-outs rely solely on standard wafer dicing and end-face polishing, reducing the need for photoresist and special etching gases, significantly reducing front-end process costs. It avoids waveguide cracking caused by trenching stress, as deep etching of damaged waveguide sidewalls introduces lattice stress and microcracks in the dielectric layer, making high-refractive-index silicon waveguides prone to dark cracks and waveguide loss drift. The native diced side has no etching stress, improving the reliability of high-sensitivity optical waveguides such as modulators and resonant cavities, and significantly reducing high-temperature thermal cycling failures. Furthermore, wafer-level on-wafer testing (WAT) is unobstructed, as the unevenness of the trench after trenching hinders on-wafer optical detection by the probe station. The exposed side ports are exposed at the wafer edge, allowing for full-optical probe coupling testing at the wafer stage, pre-screening defective dies, and saving subsequent packaging costs.

[0064] Then, a dry film is pressed and patterned on the first surface 100a using a vacuum lamination process, forming a cavity 140 in the gap on the side with the second optical waveguide 210 (i.e., the dry film is not filled at this location, leaving space as a cavity), simultaneously exposing the pads of the photonic integrated circuit 200, the top of the conductive interconnect structure 120, and the connection terminal of the thin-film resistor R. The cavity 140 allows the second optical waveguide 210 and the first optical waveguide 130 to be optically coupled via air in subsequent operations.

[0065] Next, refer to Figures 8-10Step S5: Cover the first surface 100a of the glass substrate 100 with a protective film 300 to seal the cavity 140, and fabricate a first rewiring structure 400, so that the first rewiring structure 400 is electrically connected to the conductive interconnect structure 120, the pad of the photonic integrated circuit 200, and the connection terminal of the thin film resistor R respectively; the wiring layer of the first rewiring structure 400 integrates a capacitor C and an inductor L.

[0066] Specifically, firstly, a protective film 300 is applied to the first surface 100a of the glass substrate 100 to seal the cavity 140. The protective film 300 can be a high-modulus dry film material, and the cavity protection is formed by photolithography. The protective film 300 seals the cavity 140, preventing subsequent RDL fabrication processes from contaminating the optical waveguide end face. Then, laser drilling is performed on the protective film 300 to expose the pads of the photonic integrated circuit 200, the top of the conductive interconnect structure 120, and the connection terminal of the thin-film resistor R. Afterward, a first wiring structure 400 is fabricated. The first wiring structure 400 includes at least one metal wiring layer, which can be prepared by electroplating: sputtering a Ti / Cu seed layer followed by copper electroplating to form a conductive metal layer, achieving electrical connection with the conductive interconnect structure 120, the pads of the photonic integrated circuit 200, and the connection terminal of the thin-film resistor R, respectively.

[0067] While fabricating the first wiring structure 400, a capacitor C and an inductor L are integrated into the wiring layer. The capacitor C is a MIM capacitor, comprising a lower electrode C1, an insulating layer C2, and an upper electrode C3 stacked sequentially. The lower electrode C1 is the metal wiring layer of the first wiring structure 400. Specifically, refer to... Figure 9 After the first metal wiring layer of the first wiring structure 400 is fabricated, an insulating layer C2 and an upper electrode C3 are formed on the first metal wiring layer to form a MIM capacitor. The formation of the insulating layer C2 and the upper electrode C3 adopts existing processes, which will not be described in detail here.

[0068] The inductor L can be a planar spiral inductor or a 3D inductor. That is, when fabricating the first wiring structure 400, the metal wiring layer of the first wiring structure 400 is arranged with planar spiral traces to form a planar spiral inductor. Alternatively, in step S5, when fabricating the first wiring structure 400, the first metal wiring layer of the first wiring structure 400 is arranged with multiple first metal connection layers. In step S6, when fabricating the second wiring structure 500, the first metal wiring layer of the second wiring structure 500 is arranged with multiple second metal connection layers. The multiple first metal connection layers and the multiple second metal connection layers are sequentially electrically connected through the conductive interconnection structure 120 to jointly form a 3D inductor. In other words, a 3D inductor can be formed by the current extending horizontally along the first metal connection layer of the first rewiring structure 400, vertically transmitted through the conductive interconnect structure 120 to the second metal connection layer of the second rewiring structure 500, then extending horizontally along the second metal connection layer, and then vertically transmitted back to the first metal connection layer through another conductive interconnect structure 120. This process is repeated to form a three-dimensional winding path with alternating vertical (conductive interconnect structure 120) and horizontal (first metal connection layer, second metal connection layer) directions, thus constituting a 3D inductor. This 3D inductor utilizes the vertical segment of the conductive interconnect structure 120 and the horizontal segment of the RDL metal wiring layer to jointly form a complete inductor coil, achieving a higher inductance value within a limited package area.

[0069] Next, refer to Figure 11 and Figure 13 Step S6: A second rewiring structure 500 is fabricated on the second surface 100b of the glass substrate 100, and the second rewiring structure 500 is electrically connected to the conductive interconnect structure 120.

[0070] Specifically, firstly, a temporary glass support substrate is bonded to the surface of the first wiring structure 400 using a pyrolytic temporary bonding adhesive to avoid damaging the chip and wiring layer. Then, the second surface 100b of the glass substrate 100 is mechanically thinned by grinding. When step S1 forms a blind via opening on the first surface 100a, thinning is performed until the bottom end of the conductive interconnect structure 120 is fully exposed, thereby enabling electrical signal conduction from the front to the back of the glass substrate. Next, a second wiring structure 500 is fabricated on the second surface 100b using the same fabrication process as the first wiring structure 400. The second wiring structure 500 includes at least one metal wiring layer, electrically connected to the bottom end of the conductive interconnect structure 120. Subsequently, external connection terminals 510 are formed by soldering balls on the surface of the second wiring structure 500. These external connection terminals 510 can be solder balls arranged in an array, allowing direct electrical connection to an external printed circuit board. Finally, the support substrate is removed using laser debonding and bonding adhesive cleaning. Figure 13 As shown.

[0071] Finally, refer to Figure 14and Figure 1 Step S7: Provide an electronic integrated circuit 600, mount the electronic integrated circuit 600 onto the first wiring structure 400, so that the electronic integrated circuit 600 is electrically connected to the first wiring structure 400; open the protective film 300.

[0072] Specifically, the electronic integrated circuit 600 has microbumps on its bottom, and NiPdAu is plated at the corresponding pad positions of the first wiring structure 400. A flip-chip mounter is used to mount the electronic integrated circuit 600 onto the first wiring structure 400, and thermoforming bonding is used to form a strong metallurgical bond between the microbumps and the pads of the first wiring structure 400. After mounting, the protective film 300 is removed. A laser grooving process can be used to remove the protective film 300, and the cavity 140 is cleaned to expose the coupling end faces of the first optical waveguide 130 and the second optical waveguide 210.

[0073] Thus, the optoelectronic co-package structure of the integrated waveguide in this embodiment is fabricated. The optical signal path of this optoelectronic co-package structure is as follows: the optical signal input from the external optical fiber enters the first optical waveguide 130 through the sidewall of the glass substrate 100, is transmitted along the first optical waveguide 130 to the inner wall of the blind slot 110, and enters the second optical waveguide 210 through the air, completing the optical signal transmission. The electrical signal path is as follows: the electrical signal output from the photonic integrated circuit 200 is transmitted to the electronic integrated circuit 600 through the first rewiring structure 400, and the external power supply and control signals are transmitted to the photonic integrated circuit 200 and the electronic integrated circuit 600 through the second rewiring structure 500, the conductive interconnect structure 120, and the first rewiring structure 400.

[0074] Example 2 This embodiment is largely the same in structure and principle as Embodiment 1, and the similarities will not be described in detail here. The difference lies in: (Refer to...) Figure 15 According to one or more embodiments, the photonic integrated circuit 200 of the optoelectronic co-package structure has a metal deposition layer 220 on the back side, and the metal deposition layer 220 is connected to the second rewiring structure 500 through metal interconnect holes 150.

[0075] In other words, the photonic integrated circuit 200 is embedded in the blind trench 110, with a metal layer deposited on its back side. A TGV via is formed on the glass substrate 100, penetrating the bottom of the blind trench 110 and the second surface 100b. Metal interconnect vias 150 are formed within the TGV vias, with one end connected to the metal deposition layer 220 on the back side of the photonic integrated circuit 200 and the other end connected to the second rewiring structure 500. This increases the heat dissipation path of the photonic integrated circuit 200, allowing the heat generated by the photonic integrated circuit 200 to be directly conducted to the second rewiring structure 500 through the metal deposition layer 220 and the metal interconnect via 150. The shortened heat dissipation path reduces the chip junction temperature, further enhancing the excellent thermomechanical reliability of this optoelectronic co-package structure.

[0076] Specifically, in step S1 of embodiment 1, a TGV hole is formed on the glass substrate 100, penetrating the bottom of the blind trench 110 and the second surface 100b; in step S3, when the glass through-hole or blind hole is metallized, the TGV hole is also metallized to form a metal interconnect hole 150; in step S4, when the photonic integrated circuit 200 is buried in the blind trench 110, the metal deposition layer 220 on the back of the photonic integrated circuit 200 is connected to the metal interconnect hole 150; in step S6, when the second rewiring structure 500 is fabricated, the second rewiring structure 500 is connected to the metal interconnect hole 150, thereby achieving thermal connection between the metal deposition layer 220 and the second rewiring structure 500 through the metal interconnect hole 150.

[0077] The connection between the metal deposition layer 220 and the metal interconnect hole 150 can be either a conductive film layer bonding or a metal bonding connection.

[0078] Compared to existing CPO solutions, the optoelectronic co-packaging scheme of the integrated waveguide of this invention has the following performance advantages: Through coupling at the intermediate end face of the glass waveguide, the mode field of the chip and the fiber can be matched via a mode field converter, significantly reducing mode field loss; mature processes can achieve 1.0~2.5dB. The chip only needs to be coupled to the nearest waveguide end face, relaxing chip mounting tolerances (micrometer level); the back-end fiber is only aligned with the flat glass waveguide end face, resulting in greater fiber coupling tolerance and suitability for mass production. Array waveguides, beam splitters / combiners, and folding optical paths can be fabricated on a single glass substrate; a single substrate integrates multiple chips and passive beam splitting functions, achieving active and passive integration, with strong advantages in high-density array integration. Only a small area of ​​the chip's end face is connected to the waveguide, with most of the chip attached to the substrate, resulting in better stress isolation. The first optical waveguide can be made of glass, homogeneous with the substrate, ensuring perfect thermal expansion matching; the entire optical path uses a homogeneous substrate, resulting in low high and low temperature loss drift and superior reliability for automotive and industrial applications. Meanwhile, resistors, capacitors, and inductors are integrated into the wiring layer of the first wiring structure for EIC driver / TIA power filtering, micro-ring MRM modulator temperature control circuit, and high-speed matching termination in high-speed CPO scenarios, replacing external discrete resistors and capacitors, shortening traces, and reducing SerDes loss. The dielectric constant and loss tangent of glass are much lower than those of molding compound, resulting in better signal integrity, lower crosstalk, and lower insertion loss in high-speed electrical signal transmission; the glass surface has higher flatness, allowing for finer RDL linewidth / spacing (<2μm), supporting higher density PIC-EIC interconnects; the PIC buried blind slot significantly shortens the interconnect distance with EIC, eliminates long traces on the interposer, significantly reduces high-frequency signal loss and parasitic effects, and improves energy efficiency and bandwidth density; the glass's CTE of approximately 3.2 ppm / K is better matched to silicon's 2.7 ppm / K, and the warpage under 25-250℃ thermal cycling can be controlled to <50 μm, greatly reducing the risk of stress failure of optical chips.

[0079] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0080] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0081] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0082] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0083] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0084] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A photoelectric co-packaging structure for an integrated waveguide, characterized in that, include: A glass substrate has a first surface and a second surface opposite to each other. A blind groove is formed on the first surface of the glass substrate. A first optical waveguide and a conductive interconnect structure penetrating the first surface and the second surface are provided in the glass substrate. One end of the first optical waveguide extends to the inner wall of the blind groove and the other end extends to the side surface of the glass substrate for coupling with an external optical fiber. A photonic integrated circuit is embedded in the blind trench, and there is a gap between the photonic integrated circuit and the sidewall of the blind trench. A second optical waveguide is provided in the photonic integrated circuit, and the end face of the second optical waveguide is located on the sidewall of the photonic integrated circuit to couple the first optical waveguide. A cavity is formed at the gap on the side with the second optical waveguide. A first wiring structure is disposed on the first surface of the glass substrate. The first wiring structure is electrically connected to the conductive interconnect structure and the photonic integrated circuit. The wiring layer of the first wiring structure integrates resistors, capacitors and inductors. The second wiring structure is disposed on the second surface of the glass substrate and is electrically connected to the conductive interconnect structure; An electronic integrated circuit is mounted on the first wiring structure and is electrically connected to the first wiring structure.

2. The optoelectronic co-packaging structure as described in claim 1, characterized in that, The inductor is a planar spiral inductor, formed by planar spiral traces through the metal wiring layer of the first rewiring structure; or the inductor is a 3D inductor, formed by the conductive interconnect structure, the first metal wiring layer of the first rewiring structure, and the second metal wiring layer of the second rewiring structure.

3. The optoelectronic co-packaging structure as described in claim 1, characterized in that, The resistor is a thin-film resistor, formed on the first surface by TiN deposition, photolithography and etching processes, and electrically connected to the metal wiring layer of the first redistribution structure.

4. The optoelectronic co-packaging structure as described in claim 1, characterized in that, The capacitor is a MIM capacitor, comprising a lower electrode, an insulating layer, and an upper electrode stacked sequentially. The MIM capacitor is disposed between the layers of the first rewiring structure, and the lower electrode is the metal wiring layer of the first rewiring structure.

5. The optoelectronic co-packaging structure as described in claim 1, characterized in that, The back of the photonic integrated circuit has a metal deposition layer, which is connected to the second rewiring structure through metal interconnect holes.

6. The optoelectronic co-packaging structure as described in claim 1, characterized in that, The photonic integrated circuit is fixed to the bottom of the blind slot by an adhesive layer.

7. A method for optoelectronic co-packaging of integrated waveguides, characterized in that, Includes the following steps: S1. A glass substrate is provided, and a glass through hole or a blind hole opening into the first surface is formed in the glass substrate through a first surface and a second surface opposite to the glass substrate, and a blind groove is formed in the glass substrate on the first surface. S2. A first optical waveguide is formed in the glass substrate. One end of the first optical waveguide extends to the inner wall of the blind groove, and the other end extends to the side surface of the glass substrate for coupling with an external optical fiber. S3. Metallize the glass via or the blind via to form a conductive interconnect structure; and process a thin film resistor on the first surface. S4. A photonic integrated circuit is provided, wherein a second optical waveguide is provided within the photonic integrated circuit and the end face of the second optical waveguide is located on the sidewall of the photonic integrated circuit; the photonic integrated circuit is embedded in the blind trench and a gap is left between it and the sidewall of the blind trench; a film is pressed and patterned on the first surface to form a cavity at the gap on the side with the second optical waveguide, exposing the pads of the photonic integrated circuit, the conductive interconnect structure and the connection terminal of the thin film resistor; the cavity couples the second optical waveguide to the first optical waveguide; S5. A protective film is covered on the first surface of the glass substrate to seal the cavity, and a first rewiring structure is fabricated, such that the first rewiring structure is electrically connected to the conductive interconnect structure, the pads of the photonic integrated circuit, and the connection terminal of the thin film resistor; a capacitor and an inductor are integrated in the wiring layer of the first rewiring structure. S6. A second rewiring structure is formed on the second surface of the glass substrate, and the second rewiring structure is electrically connected to the conductive interconnect structure. S7. Provide an electronic integrated circuit, mount the electronic integrated circuit on the first wiring structure, so that the electronic integrated circuit is electrically connected to the first wiring structure; open the protective film.

8. The optoelectronic co-packaging method as described in claim 7, characterized in that, In step S3, the thin film resistor is formed on the first surface by TiN deposition, photolithography and etching processes.

9. The optoelectronic co-packaging method as described in claim 7, characterized in that, In step S5, the capacitor is a MIM capacitor, which includes a lower electrode plate, an insulating layer and an upper electrode plate stacked in sequence, wherein the lower electrode plate is the metal wiring layer of the first rewiring structure.

10. The optoelectronic co-packaging method as described in claim 7, characterized in that, In step S5, the protective film is a high-modulus dry film.

11. The optoelectronic co-packaging method as described in claim 7, characterized in that, A metal deposition layer is formed on the back side of the photonic integrated circuit. Step S1 further includes: forming a TGV hole on the glass substrate that penetrates the bottom of the blind trench and the second surface; and step S3 further includes: metallizing the TGV hole to form a metal interconnect hole; the metal interconnect hole is connected to the metal deposition layer in step S4 and to the second rewiring structure in step S6.

12. The optoelectronic co-packaging method as described in claim 7, characterized in that, In step S5, when fabricating the first super-wiring structure, the metal wiring layer of the first super-wiring structure is arranged with planar spiral traces to form a planar spiral inductor; or, in step S5, when fabricating the first super-wiring structure, the first metal wiring layer of the first super-wiring structure is arranged with multiple first metal connection layers; in step S6, when fabricating the second super-wiring structure, the first metal wiring layer of the second super-wiring structure is arranged with multiple second metal connection layers, and the multiple first metal connection layers and the multiple second metal connection layers are sequentially electrically connected through the conductive interconnection structure to jointly form a 3D inductor.

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