A safety margin driven adaptive step size generation circuit

Abstract

The application discloses a step continuous self-adaptive generation hardware circuit of safety margin driving, and belongs to the technical field of adaptive control hardware. The circuit comprises a safety margin calculation unit, a monotone mapping lookup table unit, a proportional scaling unit, a double-limit protection unit and a synchronous injection unit. The safety margin calculation unit takes the difference between a system state quantity S and a critical threshold I_th as a step control driving quantity; the monotone mapping lookup table unit maps into a scaling multiple; the proportional scaling unit generates an adaptive step; the double-limit protection unit comprises a divergence protection upper limit and a stagnation protection lower limit; and the synchronous injection unit writes the step into a downstream register without triggering coefficient recalculation. The application realizes step continuous self-adaptive generation with single-cycle fixed delay, and can be configured for scenes such as solution promotion, adaptive filtering and learning rate scheduling.

Description

Technical Field

[0001] This invention belongs to the field of adaptive control hardware technology, specifically relating to a hardware pipeline circuit that uses safety margin as a driving variable and continuously and adaptively generates execution step sizes through monotonic mapping. The circuit is independent of specific downstream applications and can be configured for high-density computing and control scenarios such as geodesic evolution solving, molecular dynamics simulation, adaptive filtering, motor control, photovoltaic maximum power point tracking, and artificial intelligence training learning rate scheduling. Background Technology

[0002] In numerical solutions, adaptive control, and machine learning training, the choice of step size (integration step size / iteration step size / learning rate) is a core mechanism that determines convergence accuracy, stability, and efficiency. An excessively large step size may cause the system to cross the stability boundary and enter a divergent or oscillating state, while an excessively small step size leads to low computational efficiency.

[0003] There are currently three main ways to implement step size control in hardware:

[0004] (a) Fixed step size register configuration. The step size is written as a constant into the step size register, and the step size remains unchanged throughout the evolution process. The advantage is that the control logic is simple and there is no additional delay; the disadvantage is that it cannot adapt to changes in system state—a large step size can be used to accelerate the progress in the stable region, while a small step size is required for fine evolution in the critical region, and a fixed step size cannot satisfy both at the same time; in order to ensure the stability of the worst case, the step size is forced to be set to the global minimum value, resulting in a large waste of computing resources.

[0005] (ii) Step size control based on truncation error (e.g., Dormand-Prince type adaptive integral). This method estimates the local truncation error by comparing the computational results of two different order methods within the same step. The step size is halved if the error exceeds the tolerance limit, and doubled otherwise. The disadvantages are: it requires double the computational resources (two orders in parallel); the truncation error estimation is only related to the numerical formula and is not aware of the system's physical / state information—the system may become disordered due to state degradation, even if the numerical error is small; step size jumps (halving / doubling) trigger the reinitialization of the coefficient cache within the downstream solver, introducing additional waiting delays.

[0006] (III) Discrete Multi-Step Size Scaling Scheme. Based on state-level triggering—the step size is multiplied by 0.5 after a critical state is triggered, and gradually restored by multiplying the step size by 1.2 after several consecutive steps without triggering. The disadvantages are: it only responds passively after the critical state has been triggered (post-event remediation rather than pre-event prevention); the step size has only a limited range, and it is impossible to smoothly reduce the step size during the continuous decrease of state variables; step size jumps cause the coefficient cache to be reloaded.

[0007] The above solution has the following drawbacks:

[0008] Defect 1: Fixed step size schemes cannot adapt to changes in system state. When the system state continuously decreases from the stable region to the unstable boundary, the step size must be continuously reduced before approaching the boundary to prevent overshooting while maintaining propulsion efficiency. Fixed step size cannot meet this dynamic requirement.

[0009] Defect 2: The truncation error scheme is unaware of the system state. The system may become disordered due to state degradation, even if the numerical truncation error is within the allowable range. State degradation is a change in the system state, not a numerical error, and cannot be detected by traditional error control methods.

[0010] Defect 3: The discrete gearing scheme only responds passively after the critical state is triggered, and the step size jump trigger coefficient cache is reloaded. The step size jump not only means that the system has briefly fallen into an disordered state (calculation error), but also requires an additional recovery period.

[0011] Defect 4: In the existing solution, the step size control logic is tightly coupled with the downstream solver / controller. When the step size changes, the downstream internal coefficient buffer needs to be renormalized, which increases the synchronization interaction between the control logic and the execution unit, resulting in complex timing and hindering pipeline parallelism.

[0012] In summary, existing step size control hardware has shortcomings in system state awareness, adaptive continuous adjustment, step size jump response delay, and decoupling from downstream components. There is a lack of a universal step size generation solution that does not rely on manual parameter tuning and can be configured across scenarios. Summary of the Invention

[0013] This invention aims to solve multiple technical bottlenecks in existing step size control hardware. The specific technical problems are as follows:

[0014] (i) Fixed step size cannot adapt to changes in system state, resulting in low efficiency in the stable region and high risk near the unstable boundary;

[0015] (ii) The truncation error scheme is not aware of the system state and cannot intervene in protection in advance when the state variable is close to the critical threshold;

[0016] (iii) The discrete gear scheme passively responds and the step size jump causes the coefficient cache to be reloaded;

[0017] (iv) The existing step size control is tightly coupled with the downstream solver, which is not conducive to pipeline parallelism.

[0018] Inventive concept

[0019] This invention includes the following technical solution: a safety margin between the current system state variable S and the critical threshold I_th. As the sole driving variable for step size control, it is implemented in a fixed-delay pipeline consisting of a monotonic mapping lookup table, a scaling factor, and dual limit protectors, according to... The monotonically increasing law continuously and adaptively generates the step size scaling factor—when the system is far from the critical threshold, it automatically uses a large step size to improve propagation efficiency; when the system is close to the critical threshold, it continuously and smoothly reduces the step size to prevent out-of-bounds errors, and the step size change does not trigger the reloading of the coefficient cache inside the downstream solver. This includes the following three aspects:

[0020] (a) The step-size continuous scaling mechanism of the monotonic mapping of safety margin. As input, a monotonic mapping lookup table and proportional scaling are used to generate the same result as... The monotonically increasing step size scaling factor ensures that the step size decreases smoothly and continuously as the state variable decreases, replacing the traditional discrete jump transition scheme. The continuous step size change eliminates the need to reload the coefficient cache within the downstream solver, thus eliminating additional waiting latency.

[0021] (ii) Dual-limit protection mechanism. An upper limit for divergence protection is set to prevent the mapped output from exceeding the safety limit, and a lower limit for stagnation protection is set to prevent the propulsion from stalling due to excessively small step size. The step size is constrained to the lower bound, and conservative progress is made with the minimum step size in the critical region.

[0022] (III) Single-cycle combinational logic computation and synchronous injection. All step size calculations are completed by combinational logic within a single cycle, and the step size register update takes effect in the next clock cycle. Step size changes do not trigger a reset of the internal state of the downstream solver; only the new step size needs to be written to the register, thus decoupling from and parallelizing with the downstream solver.

[0023] Overall technical solution

[0024] This invention implements the entire hardware-based adaptive step size generation mechanism driven by safety margin in the step size generation chain. It replaces traditional discrete transitions or software calculation schemes with a deterministic delay of a fixed single clock cycle, achieving continuous adaptive generation and synchronous injection of the step size. Using a margin calculation unit, a monotonic mapping lookup table unit, a scaling unit, a dual-limiting comparator, and synchronous injection logic as core components, the following step size generation chain is solved in hardware parallelism:

[0025] (1) Margin calculation: ,when The boundary crossing flag is triggered at this time;

[0026] (2) Monotonic mapping: using a lookup table to... Mapped to scaling factor , Time-binding lower bound ;

[0027] (3) Scale: ;

[0028] (4) Dual amplitude limiting protection: clamp dt_step within the range of [dt_min, dt_max];

[0029] (5) Synchronous injection: Write dt_step to the downstream step register, and it will take effect in the next cycle.

[0030] Specific technical solutions

[0031] (a) Safety Margin Calculation Unit. This unit receives the current system state variable S_current and the critical threshold I_th, and calculates the difference. Built-in cross-boundary comparator, when Output a boundary crossing flag signal to trigger downstream preparatory operations; single-cycle output. With boundary markers.

[0032] (ii) Monotonic Mapping Lookup Table Unit. Connected to the margin calculation unit, used to... Mapped to step scaling factor The lookup table is an on-chip ROM, implemented... The monotonically increasing mapping, covering Interval. When The output is clamped to the lower bound R_min. Single-cycle output scaling factor.

[0033] (III) Scaling Unit. Connected to the monotonic mapping lookup table unit, this unit scales the scaling factor using a base step size dt_base, according to... Generates an adaptive step size. Outputs the step size value in a single cycle.

[0034] (iv) Dual-limiting protection unit. Connected to the scaling unit, it performs dual-limiting protection on the step size: upper limit clamping to prevent divergence, and lower limit clamping to prevent stagnation. The final step size dt_step after limiting is output in a single cycle.

[0035] (v) Synchronization Injection and Step Register Unit. Connect the dual-limiting protection unit and write dt_step into the downstream step register. The downstream coefficient buffer adopts a dual-register design; when the step size is updated, only the selection signal is switched, and the coefficients do not need to be recalculated. The step size change takes effect in the next clock cycle.

[0036] Basic pipeline timing rules: Margin calculation and monotonic mapping are completed in parallel by combinational logic in cycle 1; scaling and dual-limiting protection are cascaded in the same cycle; step size register updates take effect in the next clock cycle. Step size calculation is completed in a fixed single clock cycle, with no branches, no software involvement, and no downstream coefficient recalculation.

[0037] Beneficial effects

[0038] (a) This invention has a safety margin As the sole driving variable for step size control, the step size is continuously and smoothly reduced with the state variable through monotonic mapping, allowing for early intervention before the system approaches the unstable boundary, thus upgrading from "post-event remedy" to "pre-event prevention".

[0039] (ii) This invention does not depend on specific application scenarios. By configuring different state variables S and critical thresholds I_th, the same circuit structure can be adapted to various downstream applications such as propagation solving, adaptive filtering, and learning rate scheduling without modifying the hardware.

[0040] (iii) The step size changes continuously without jumps, and the coefficient cache inside the downstream solver does not need to be reloaded or renormalized, eliminating the extra waiting delay of 1-2 clock cycles in the discrete jump scheme.

[0041] (iv) The dual limit protector adopts an asymmetric design—the upper limit of the divergent protection prevents abnormal amplification of the step size, and the lower limit of the stall protection prevents the propulsion from stalling due to an excessively small step size; The step size is constrained to the lower limit, and conservative propulsion is carried out with the minimum step size in the critical region, balancing safety and propulsion efficiency.

[0042] (v) All step size calculations are completed by combinational logic within a single cycle, and the step size register update takes effect in the next clock cycle; step size changes only require switching the dual register selection signal, without triggering downstream coefficient recalculation, and are completely decoupled from the downstream solver, supporting direct cascading without increasing downstream pipeline pauses.

[0043] (vi) The monotonic mapping lookup table supports configurable linear / piecewise / logarithmic curves, and the proportional constant C can be calibrated and written. A single chip can cover multiple scenarios through configuration without modifying the hardware.

[0044] Terminology Definition

[0045] safety margin : This refers to the difference between the current system state variable S and the critical threshold I_th. . This indicates that the system is in a safe and orderly zone. The larger it is, the further it is from the critical point; This is the critical dividing point; This indicates that the system has crossed the boundary and entered the disordered region. The state variable S is defined by the application (advancement scenario = information completeness and trace purity; filtering scenario = error magnitude; learning scenario = loss value).

[0046] Critical threshold I_th: This refers to the lower limit of the state variables that allow the system to maintain normal operation. Once this value is exceeded, the system enters an unstable state. It is calibrated by the application scenario (for propulsion scenarios, this = the minimum trace purity required for system stability; for filtering scenarios, this = the target error; for learning scenarios, this = the target loss) and written to a configurable register.

[0047] Monotonic mapping: refers to mapping the safety margin Mapped to a monotonically increasing function of the step scaling factor Implemented by on-chip lookup tables (default linear). (Configurable segmentation / logarithmic) The output is limited to the scaling factor corresponding to the stagnation protection lower bound R_min.

[0048] Base step size dt_base: refers to the base step size of the actuator, which is set by the system configuration register and applied for calibration.

[0049] Step scaling factor : refers to the ratio of the step size generated by monotonic mapping to the reference step size, satisfying .

[0050] Divergence protection upper bound R_max: refers to the maximum scaling factor of the step size relative to the base step size (default 20.0), to prevent abnormal amplification of the mapped output from causing divergence.

[0051] Stagnation protection lower bound R_min: refers to the minimum scaling factor of the step size relative to the baseline step size (default 0.01), preventing the propulsion from stalling due to excessively small step sizes when the system is far from the critical point. The step size is clamped to the minimum safe value.

[0052] Boundary crossing sign: refers to when The hardware automatically triggers a flag signal indicating that the system has crossed the critical threshold and entered the disorder zone, triggering downstream rollback preparation operations.

[0053] Step size change flag: This refers to the flag signal output by the hardware when the change in the current step size from the previous step size exceeds a preset threshold (default 10%), for reference by downstream modules.

[0054] Clamping: refers to the hardware operation of limiting signal values ​​within preset upper and lower boundaries. If the value exceeds the upper limit, it is truncated to the upper limit; if the value falls below the lower limit, it is truncated to the lower limit. In this invention, it is used to limit the step size within the range of [dt_min, dt_max]. Attached Figure Description

[0055] Figure 1This is a schematic diagram of the overall architecture of the hardware pipeline circuit for adaptive generation of safety margin monotonic mapping step size in this invention. Solid arrows indicate the direction of forward data flow; dotted-dash arrows indicate configuration control signals; dashed arrows indicate flag signals; circled ① to ⑤ sequentially indicate five modules (① safety margin calculation unit, ② monotonic mapping lookup table unit, ③ scaling unit, ④ dual-limiting protection unit, ⑤ synchronization injection and step size register unit). ① and ② are executed in the T1 stage pipeline, ③ and ④ are cascaded in the same cycle in the T2 stage, and ⑤ completes the dual-register coefficient selection in the T2 stage. The step size register is updated on the rising edge of the next clock cycle; during the update, only the selection signal is switched, and the coefficients do not need to be recalculated. Detailed Implementation

[0056] Example 1: Continuous Adaptive Step Size in Propulsion Scenarios

[0057] like Figure 1 The overall architecture shown in this embodiment uses the advancement of state variable G along the trajectory as an example to verify the functional correctness and timing performance of the safety margin monotonic mapping step size generation circuit.

[0058] Configuration parameters: Base step size dt_base=0.01, scaling constant C=0.5, maximum scaling factor R_max=20.0, minimum scaling factor R_min=0.01, critical threshold I_th=0.167.

[0059] Pipeline timing:

[0060] Period T1: The margin calculation unit receives the current state quantity G_current (range 0~1) and calculates... Meanwhile, the monotonic mapping lookup table unit is based on Index on-chip ROM, output scaling factor .

[0061] Period T1 (cascaded within the same period): Calculation of scaling unit The dual-limit protection unit clamps the result within the range of [dt_min, dt_max].

[0062] In the next clock cycle: the synchronous injection unit writes dt_step to the downstream step size register, and the downstream solver uses the new step size to perform the next evolution. The step size update only switches the dual-register selection signal, eliminating the need to recalculate coefficients and removing the additional 1-2 clock cycles of waiting delay found in discrete solutions.

[0063] Simulation results are as follows (200 steps, state variable decreases from 0.85 to 0.10, judgment at each step): For the fixed step size scheme, the number of out-of-order sampling steps is 15; for the discrete step size scheme... The out-of-order sampling steps are 31, while the safety margin monotonic mapping scheme of this invention has 0 out-of-order sampling steps. The safety margin monotonic mapping continuously reduces the step size before the state variable approaches the critical threshold, completely eliminating critical out-of-bounds errors.

[0064] Example 2: Cross-scenario configuration in adaptive filtering and learning rate scheduling

[0065] This embodiment verifies that the same circuit structure can be adapted to different downstream applications by only changing the configuration parameters.

[0066] Adaptive filtering scenario: State variable S = error amplitude |e|, critical threshold I_th = 0.05, baseline step size The proportionality constant C = 2.0. 3. Identification of unknown tap system (3000 steps), the final state MSE is the average of the last 500 steps: fixed step size final state MSE = 0.011343, the final state MSE of this invention = 0.010803, a relative improvement of about 4.7%.

[0067] Learning rate scheduling scenario: State variable S = loss value, critical threshold I_th = 0.01, baseline step size lr_base = 0.1, scaling constant C = 2.0. Non-convex gradient descent (500 steps), convergence is determined by a single-step loss below 0.05: fixed learning rate final state loss = 0.820784 (not converged). This invention converges in 4 steps. The subsequent 496 steps maintained no rebound, and the convergence speed increased by about 125 times.

[0068] The two scenarios share the same circuit structure, requiring only rewriting of the state variable definitions and critical thresholds in the configuration register, without any hardware modifications.

[0069] Example 3: Hardware Resource and Timing Comprehensive Verification

[0070] Based on the 28nm standard process and 1GHz main frequency, the equivalent gate count of each module in this circuit is estimated as follows: safety margin calculation unit approximately 0.1k gates, monotonic mapping lookup table unit (256×8bit ROM) approximately 0.3k gates, scaling unit approximately 0.2k gates, dual limiting protection unit approximately 0.1k gates, synchronization injection and step register unit approximately 0.2k gates, totaling approximately 0.9k gates.

[0071] The pipeline's critical path consists of four stages of combinational logic: subtraction → ROM lookup → multiplication → comparator. Static timing analysis shows ample setup / hold margins and no timing violations. This circuit can be directly cascaded with downstream solvers / controllers without adding downstream pipeline pauses.

Claims

1. A hardware circuit for continuous adaptive step size generation, characterized in that, include: The safety margin calculation unit is used to receive the current system state variable S and the critical threshold. Calculate the safety margin and in Output boundary crossing flag; The monotonic mapping unit, connected to the safety margin calculation unit, is used to calculate the safety margin. Generate step scaling factor using a monotonically increasing mapping. The monotonic mapping is implemented by an on-chip lookup table and the mapping curve is configurable; The scaling unit, connected to the monotonic mapping unit, uses a reference step size. With the scaling factor Generate adaptive step size ; A dual-limiting protection unit, connected to the scaling unit, clamps the adaptive step size between the maximum step size upper limit and the minimum step size lower limit, wherein... When the step size does not exceed zero, it is clamped to the lower limit of the minimum step size; The synchronous injection unit is connected to the dual amplitude limiting protection unit, and writes the adaptive step size into the downstream step size register without triggering the recalculation of internal coefficients in the downstream solver. The entire circuit calculates the delay using a fixed single clock cycle to generate an adaptive step size. All operational paths are pure combinational logic architectures with no software scheduling or microcode computation.

2. The step-size continuous adaptive generation hardware circuit according to claim 1, characterized in that, The monotonic mapping is a linear mapping. The proportional constant C is written into the configuration register by factory calibration.

3. The step-size continuous adaptive generation hardware circuit according to claim 1, characterized in that, The monotonic mapping is a piecewise linear or logarithmic curve, and the type of mapping curve is selected by the configuration register.

4. The step-size continuous adaptive generation hardware circuit according to claim 1, characterized in that, The asymmetric design of the dual-limiting protection unit: the upper limit of divergent protection corresponds to the maximum scaling factor R_max, and the lower limit of stagnant protection corresponds to the minimum scaling factor R_min. It restrains the lower boundary.

5. The step-size continuous adaptive generation hardware circuit according to claim 1, characterized in that, The synchronization injection unit includes a dual-register coefficient cache—the old coefficients and the new step size coefficients are stored in parallel. When the step size is updated, only the selection signal is switched. The step size change takes effect in the next clock cycle without any additional waiting delay.

6. The step-size continuous adaptive generation hardware circuit according to claim 1, characterized in that, The safety margin calculation, monotonic mapping, scaling and dual limiting protection are completed by combinational logic cascading within a single cycle, with a fixed single clock cycle output step size.

7. The step-size continuous adaptive generation hardware circuit according to claim 1, characterized in that, The critical threshold I_th and the baseline step size dt_base are configurable registers. By configuring them, the same circuit structure can be adapted to various downstream applications such as propagation solving, adaptive filtering, learning rate scheduling, motor control, and photovoltaic maximum power point tracking.

8. The step-size continuous adaptive generation hardware circuit according to claim 1, characterized in that, When the step size change exceeds the preset threshold, a step size change flag signal is output for reference by downstream modules.

9. The step-size continuous adaptive generation hardware circuit according to claim 1, characterized in that, The safety margin calculation unit in The boundary crossing flag output at that time triggers the downstream rollback preparation operation.

10. A step-size continuous adaptive generation method, characterized in that, Includes the following steps: Calculate safety margin ; Generate scaling factor using a monotonically increasing mapping ; Generate adaptive step size ; Dual amplitude limiting protection is applied to the adaptive step size, wherein When the threshold is not exceeded, the minimum step size is clamped down to the lower limit. The adaptive step size is synchronously injected into the downstream step size register without triggering the recalculation of internal coefficients in the downstream solver.

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