power inductor

Abstract

A power inductor includes a coil, a plurality of insulating spacer layers, and a magnetic permeable body. The coil includes two outer looped wire layers. The outer looped wire layers are stacked on each other and electrically connected. Each outer looped wire layer has an outer connection end. At least one insulating spacer layer is located between the outer looped wire layers. The magnetic permeable body covers the coil and exposes the outer connection ends of each outer looped wire layer. The magnetic permeable body includes a plurality of ferromagnetic particles. Each ferromagnetic particle includes a ferrous alloy particle and an insulating film covering the ferrous alloy particle. In this way, the insulation resistance between the outer looped wire layers and the inner looped wire layers can be effectively improved.

Description

Technical Field

[0001] This invention relates to an electronic component, and more particularly to a power inductor. Background Technology

[0002] Most common power inductors have low insulation resistance, which makes them prone to short circuits in high-current and high-voltage circuits, such as automotive circuits and high-power 3C product circuits. This can cause abnormal operation or even permanent failure of the power inductor. Summary of the Invention

[0003] This invention proposes a power inductor with high insulation resistance.

[0004] The power inductor proposed in this invention includes a coil and a magnetizing element. The coil includes two outer loop circuit layers and a plurality of insulating spacer layers, which are stacked and electrically connected to each other in the thickness direction. Each outer loop circuit layer has an external connection terminal, wherein at least one insulating spacer layer is located between these outer loop circuit layers. Each insulating spacer layer includes a plurality of first flat insulating particles, and each of the first flat insulating particles has a first major axis and a first minor axis orthogonal to the first major axis. The first major axis of a portion of the first flat insulating particles is orthogonal to the thickness direction. The magnetizing element covers the coil and exposes the external connection terminals of each outer loop circuit layer. The magnetizing element includes a plurality of ferromagnetic particles, and each ferromagnetic particle includes iron-based alloy particles and an insulating film, wherein the insulating film covers the iron-based alloy particles.

[0005] In at least one embodiment of the present invention, the ratio of the first major axis to the first minor axis of the first flat insulating particle is greater than 1 and less than 1000.

[0006] In at least one embodiment of the present invention, the first flat insulating particle comprises a magnetic alloy material.

[0007] In at least one embodiment of the present invention, two covering layers are further included, respectively covering opposite sides of the magnetizing element and the coil, and directly contacting the magnetizing element. Each of the covering layers includes a plurality of second flat insulating particles, and each of the second flat insulating particles has a second long axis and a second short axis orthogonal to the second long axis. The second long axis of some of the second flat insulating particles is orthogonal to the thickness direction.

[0008] In at least one embodiment of the present invention, the first flat insulating particles of the insulating spacer layer comprise a ceramic material, while the second flat insulating particles of the cover layer comprise a magnetic alloy material.

[0009] In at least one embodiment of the present invention, the outer loop circuit layer is located between two adjacent insulating spacers.

[0010] In at least one embodiment of the present invention, a plurality of external electrodes are further included, which partially cover the outer surface of the magnetor and are connected to the external connection terminal of the outer loop circuit layer.

[0011] In at least one embodiment of the present invention, the coil further includes an inner loop circuit layer disposed between the outer loop circuit layers and electrically connected to the outer loop circuit layers. The inner loop circuit layer is located between two insulating spacer layers.

[0012] In at least one embodiment of the present invention, each outer loop circuit layer further has a first internal connection terminal relative to the external connection terminal, while the inner loop circuit layer has two second internal connection terminals opposite to each other, wherein the first internal connection terminal of each outer loop circuit layer is connected to one of the second internal connection terminals.

[0013] In at least one embodiment of the present invention, each insulating spacer is strip-shaped, and two of the insulating spacers respectively cover and directly contact the outer loop circuit layer, and extend along the outer loop circuit layer. Each outer loop circuit layer has a pair of opposing first sidewalls, and the two insulating spacers extending along the outer loop circuit layer respectively protrude from the first sidewalls of the outer loop circuit layer.

[0014] In at least one embodiment of the present invention, a first internal connection end of an outer loop circuit layer protrudes from the end of an insulating spacer layer.

[0015] In at least one embodiment of the invention, one of the insulating spacers directly contacts the inner loop circuit layer and extends along the inner loop circuit layer. The inner loop circuit layer has a pair of second sidewalls facing each other, and the insulating spacer extending along the inner loop circuit layer protrudes from the second sidewalls.

[0016] In at least one embodiment of the present invention, one of the second internal connection ends of the inner loop circuit layer protrudes from the end of the insulating spacer layer extending along the inner loop circuit layer.

[0017] In at least one embodiment of the invention, each insulating spacer layer protrudes beyond the edge of any of the outer loop circuit layers.

[0018] Based on the above, by utilizing these insulating spacers, the insulation resistance between the outer loop circuit layer and the inner loop circuit layer can be effectively improved to avoid short circuits, thereby facilitating the application of power inductors in high-current and high-voltage circuits such as automotive circuits and high-power 3C product circuits. Attached Figure Description

[0019] Figure 1A This is a top view schematic diagram of a power inductor according to at least one embodiment of the present invention.

[0020] Figure 1B yes Figure 1A A top view of the power inductor after the external electrodes have been removed.

[0021] Figure 1C yes Figure 1A A schematic diagram of the cross section drawn along the 1C-1C section.

[0022] Figure 1D It is a local magnification Figure 1C A cross-sectional schematic diagram of the magnetoresistive element in the image.

[0023] Figure 1E It is a local magnification Figure 1C A cross-sectional schematic diagram of the insulating spacer layer.

[0024] Figure 1F It is a local magnification Figure 1C A cross-sectional schematic diagram of the covering layer.

[0025] Figure 1G yes Figure 1A A schematic diagram of the cross section drawn along the 1G-1G section of the central line.

[0026] Figures 2A to 2C , Figures 3A to 3B and Figures 4A to 4C yes Figure 1A A schematic diagram of the manufacturing method of the power inductor.

[0027] Figure 5 This is a cross-sectional schematic diagram of a power inductor according to another embodiment of the present invention. Detailed Implementation

[0028] In the following text, to clearly present the technical features of the present invention, the dimensions (e.g., length, width, thickness, area, or depth) of the elements (e.g., layers, films, substrates, and regions) in the accompanying drawings will be enlarged proportionally, and the number of some elements may be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of elements in the drawings or the dimensions and shapes presented by the elements, but should cover dimensions, shapes, and deviations from both due to actual manufacturing processes and / or tolerances. For example, a flat surface shown in the drawings may have rough and / or non-linear characteristics, and an acute angle shown in the drawings may be rounded. Therefore, the elements presented in the accompanying drawings of the present invention are primarily for illustration and are not intended to precisely depict the actual shape of the elements, nor are they intended to limit the claims of the present invention.

[0029] Figure 1A This is a top view schematic diagram of a power inductor according to at least one embodiment of the present invention. Please refer to... Figure 1AThe power inductor 100 includes a coil 110, a magnetizing element 120, and a plurality of external electrodes 130, wherein the magnetizing element 120 covers the coil 110. These external electrodes 130 partially cover the outer surface of the magnetizing element 120 and are connected to the coil 110. Figure 1A For example, these external electrodes 130 can cover the left and right sides of the magnetor 120 respectively, so that these external electrodes 130 partially cover the outer surface of the magnetor 120, but do not cover the entire outer surface of the magnetor 120.

[0030] Figure 1B yes Figure 1A A top view of the power inductor after the external electrodes have been removed. Figure 1C yes Figure 1A A schematic cross-sectional view drawn along section 1C-1C of the central axis. Please refer to [link / reference]. Figure 1B and Figure 1C The coil 110 includes two outer loop circuit layers 111a, at least one inner loop circuit layer 111b, and multiple insulating spacer layers 112. The insulating spacer layer 112 can be a ceramic material layer or a ferromagnetic material, while the outer loop circuit layer 111a and the inner loop circuit layer 111b can be made of copper, silver, or gold, or alloy materials.

[0031] An inner loop circuit layer 111b is disposed between these outer loop circuit layers 111a. These two outer loop circuit layers 111a are stacked on top of each other and electrically connected. For example, the inner loop circuit layer 111b is electrically connected to these outer loop circuit layers 111a, so that the two outer loop circuit layers 111a are electrically connected to each other through the inner loop circuit layer 111b. Notably, these two outer loop circuit layers 111a are stacked on top of each other and electrically connected in the thickness direction D1. Furthermore, in this embodiment, at least one insulating spacer layer 112 is located between these outer loop circuit layers 111a, and one of the outer loop circuit layers 111a may be located between two adjacent insulating spacer layers 112.

[0032] by Figure 1C For example, the upper outer loop circuit layer 111a is sandwiched between two adjacent insulating spacers 112, but the lower outer loop circuit layer 111a is only covered by the insulating spacers 112 on its upper surface, while the lower surface of the lower outer loop circuit layer 111a is not covered by any insulating spacers 112. Secondly, the inner loop circuit layer 111b is located between two of the insulating spacers 112, such that two of the insulating spacers 112 are located between these outer loop circuit layers 111a.

[0033] However, in other embodiments, the outer loop circuit layers 111a may not be located between adjacent insulating spacer layers 112. For example, in Figure 1C In this configuration, the uppermost insulating spacer layer 112 can be omitted so that the upper surface of the upper outer loop circuit layer 111a is not covered by the insulating spacer layer 112. Thus, the magnetizer 120 exposes not only the upper surface of the upper outer loop circuit layer 111a but also the lower surface of the lower outer loop circuit layer 111a. In other words, the magnetizer 120 may not cover the upper surface of the upper outer loop circuit layer 111a or the lower surface of the lower outer loop circuit layer 111a.

[0034] It is worth mentioning that the outer loop circuit layer 111a and the inner loop circuit layer 111b each have a width w1, and the insulating spacer layer 112 has a width w2 (shown in the figure). Figure 1C In various embodiments, the width w1 of the upper outer loop circuit layer 111a can be less than or equal to the width w2 of the insulating spacer layer 112. That is, the widths w1 and w2 satisfy w2-w1≥0μm.

[0035] Each outer loop circuit layer 111a has an external connection terminal Pa1, which is essentially a pad and is used for electrical connection to the external electrode 130 (shown in the figure). Figure 1A This allows external electrical energy to be input to the external connection terminal Pa1 via the external electrode 130. In this way, the power inductor 100 can operate, thereby enabling the circuit (such as automotive circuit or high-power 3C product circuit) in which the power inductor 100 is installed to function.

[0036] It is worth mentioning that the power inductor 100 includes two outer loop circuit layers 111a, and each outer loop circuit layer 111a has at least one external connection terminal Pa1, so the power inductor 100 will have at least two external connection terminals Pa1. Furthermore, in Figure 1B In the embodiment shown, the external connection terminal Pa1 located on the left half is covered by the rectangular insulating spacer 112 on the left side, so Figure 1B Only a single external connection terminal Pa1 is depicted.

[0037] Additionally, it should be noted that in this embodiment, the power inductor 100 includes an inner loop circuit layer 111b, so the power inductor 100 has three circuit layers: two outer loop circuit layers 111a and one inner loop circuit layer 111b. However, in other embodiments, the power inductor 100 may not include the inner loop circuit layer 111b, so that the power inductor 100 has only two circuit layers: two outer loop circuit layers 111a. Figure 1C The inner loop circuit layer 111b can be omitted.

[0038] Based on the above, the power inductor 100 of this embodiment is not limited to including an inner loop circuit layer 111b. In addition, the power inductor 100 may have four or more circuit layers, wherein the power inductor 100 may include multiple inner loop circuit layers 111b. Therefore, the power inductor 100 of this embodiment is not limited to including only a single inner loop circuit layer 111b.

[0039] It is worth mentioning that the power inductor 100 may also include multiple covering layers 140a and 140b, wherein these covering layers 140a and 140b respectively cover opposite sides of the magnetizing element 120 and the coil 110, and can directly contact the magnetizing element 120. That is, the magnetizing element 120 and the coil 110 are both located between the covering layers 140a and 140b. Therefore, the covering layers 140a and 140b will cover these outer loop circuit layers 111a and at least one insulating spacer layer 112 (e.g., Figure 1G In the middle, the uppermost insulating spacer layer 112). Furthermore, it is worth mentioning that... Figure 1B The power inductor 100 shown is also drawn after the cover layers 140a and 140b have been removed.

[0040] Figure 1D It is a local magnification Figure 1C A cross-sectional schematic diagram of the magnetor 120 is shown. Please refer to [link / reference]. Figure 1D The magnetizer 120 includes a plurality of ferromagnetic particles (not shown), each of which comprises iron-based alloy particles 121 and an insulating film 122, wherein the insulating film 122 covers the iron-based alloy particles 121. The insulating film 122 may be an oxide film, the material of which may be silicon dioxide. Alternatively, the insulating film 122 may also be formed from iron oxide-based alloy particles 121. For example, the iron-based alloy particles 121 are placed in a high-temperature furnace containing oxygen to oxidize the surface of the iron-based alloy particles 121, thereby forming the insulating film 122.

[0041] Because each iron-based alloy particle 121 is coated by the insulating film 122, the conductivity of the magnetor 120 decreases, meaning its resistance increases. Therefore, even though the magnetor 120 contains conductive iron-based alloy particles 121, its overall conductivity is not as good as that of ordinary metals, and can even be considered equivalent to that of an insulator. Secondly, because the magnetor 120 comprises multiple iron-based alloy particles 121, it exhibits ferromagnetism.

[0042] Therefore, when Figure 1C When current is transmitted between the outer loop circuit layer 111a and the inner loop circuit layer 111b, the current will not be transmitted in the high-resistance magnet 120. Instead, the magnet 120 can induce a magnetic field through the current transmitted in the outer loop circuit layer 111a and the inner loop circuit layer 111b, thereby achieving the function of an inductor.

[0043] Please see Figure 1C Of these insulating spacers 112, only one insulating spacer 112 is disposed on one side of the outer loop circuit layer 111a, and each of the other insulating spacers 112 is disposed between two adjacent layers of the outer loop circuit layer 111a and the inner loop circuit layer 111b. Thus, when the power inductor 100 is used in high-current, high-voltage circuits such as automotive circuits or high-power 3C product circuits, the insulating spacer 112 sandwiched between two adjacent layers of the outer loop circuit layer 111a and the inner loop circuit layer 111b can effectively block the current penetrating the magnetic inductor 120, thereby preventing short circuits.

[0044] Figure 1E It is a local magnification Figure 1C A schematic cross-sectional view of the insulating spacer layer 112. Please refer to... Figure 1E Each insulating spacer layer 112 includes a plurality of flat insulating particles 112p. Each of these flat insulating particles 112p has a major axis L1 and a minor axis S1 orthogonal to the major axis L1, and the major axis L1 of some flat insulating particles 112p is orthogonal to the thickness direction D1. For example, the flat insulating particles 112p may be in sheet form, and some flat insulating particles 112p may be distributed in the insulating spacer layer 112 in a sheet-like stacked manner.

[0045] It is worth mentioning that, compared to spherical insulating particles, the flat insulating particles 112p give the insulating spacer layer 112 a directional insulating property. Specifically, since the major axis L1 of the flat insulating particles 112p is orthogonal to the thickness direction D1, the permeability in the thickness direction D1 is reduced, making it difficult for the insulating spacer layer 112 to achieve saturation magnetization in the thickness direction D1. Furthermore, the increased volume density in the thickness direction D1 also improves the insulating effect of the insulating spacer layer 112 in the thickness direction D1.

[0046] In addition, in some embodiments, the ratio of the major axis L1 to the minor axis S1 of the flat insulating particle 112p can be greater than 1 and less than 1000. For example, when the major axis L1 of the flat insulating particle 112p falls between 2 μm and 100 μm, the minor axis S1 can fall between 0.1 μm and 5 μm, with a preferred range between 1 μm and 5 μm. The ratio of the major axis L1 to the minor axis S1 in this invention is not limited to the above embodiments.

[0047] In at least one embodiment of the present invention, insulating particles with an average particle size (D50) of 5 μm can be milled into flat insulating particles 112p by ball milling, such as a planetary ball mill. In some embodiments, the average thickness of these flat insulating particles 112p can fall between 0.1 μm and 5 μm, preferably between 1 μm and 5 μm. Notably, the average thickness of the aforementioned flat insulating particles 112p is substantially equivalent to the length of the minor axis S1 of the flat insulating particles 112p. The flat insulating particles 112p may comprise magnetic alloy materials, such as iron-silicon-chromium (FeSiCr) alloys, iron-silicon-aluminum (FeSiAl) alloys, or similar ferromagnetic alloys.

[0048] In the embodiment described above with flat insulating particles 112p, the breakdown voltage of the insulating spacer layer 112 can fall within the range of 20MV / m to 50MV / m. On the other hand, the bending strength of the insulating spacer layer 112 can fall within the range of 10N to 20N.

[0049] It is worth mentioning that both capping layers 140a and 140b have electrical insulating properties. For example, capping layers 140a and 140b can be made of ceramic or other insulating materials. Alternatively, at least one of the constituent materials of capping layers 140a and 140b can be the same as the constituent material of the magnetizing element 120, that is, at least one of capping layers 140a and 140b also includes multiple ferromagnetic particles (such as those in the magnetizing element 120) mentioned above. Figure 1D (As shown). Therefore, the conductivity of both cover layers 140a and 140b is like that of an insulator, that is, both cover layers 140a and 140b have the characteristics of electrical insulation.

[0050] In one embodiment, the capping layers 140a, 140b and the magnetizer 120 may have ferromagnetic particles of the same size and composition. That is, the ferromagnetic particles in the capping layers 140a, 140b and the magnetizer 120 are substantially the same size (e.g., diameter) and made of the same material. Therefore, no boundary is formed between either the capping layers 140a and 140b and the magnetizer 120. In other words, when the capping layers 140a, 140b and the magnetizer 120 have ferromagnetic particles of the same size and composition, the boundary between either the capping layers 140a and 140b and the magnetizer 120 will not be clearly visible even using an electron microscope, such as a transmission electron microscope (TEM).

[0051] However, in other embodiments, since the capping layers 140a and 140b can be made of ceramic or other insulating materials, the constituent materials of the capping layers 140a and 140b can be different from the constituent materials of the magnetizer 120, such that either the capping layers 140a and 140b forms a boundary with the magnetizer 120, which can be observed by an optical microscope or an electron microscope (e.g., TEM).

[0052] Furthermore, even if the capping layers 140a and 140b and the magnetizer 120 have ferromagnetic particles made of the same material, a boundary can still be formed between either capping layer 140a or 140b and the magnetizer 120. Specifically, when the ferromagnetic particles in the capping layers 140a and 140b and the magnetizer 120 have substantially different particle sizes, a boundary will still be formed between either capping layer 140a or 140b and the magnetizer 120. For example, when the particle size of the ferromagnetic particles in the magnetizer 120 differs from the average particle size (D50) of the ferromagnetic particles in the capping layers 140a and 140b by more than 2 micrometers (µm), a boundary that can be observed by an electron microscope will still be formed between either capping layer 140a or 140b and the magnetizer 120.

[0053] Figure 1F It is a local magnification Figure 1C Cross-sectional schematic diagrams of the overburden layers 140a and 140b are shown. Please refer to [link / reference]. Figure 1F In one embodiment, each of the cover layers 140a and 140b includes a plurality of flat insulating particles 142p, each of which has a major axis L2 and a minor axis S2 orthogonal to the major axis L2, and the major axis L2 of some of the flat insulating particles 142p is orthogonal to the thickness direction D1. For example, the flat insulating particles 142p may also be sheet-like, and some of the flat insulating particles 142p are distributed in a sheet-like stacked manner in the cover layers 140a and 140b. In particular, in this embodiment, the insulating flat insulating particles 112p of the insulating spacer layer 112 may include a ceramic material, while the flat insulating particles 142p of the cover layers 140a and 140b may include a magnetic alloy material.

[0054] Figure 1G yes Figure 1A A schematic cross-sectional view drawn along section 1G-1G of the central axis. Please refer to [link / reference]. Figure 1A and Figure 1G The magnetor 120 exposes the external connection terminals Pa1 of each outer loop circuit layer 111a, so that the external electrodes 130 are connected to these external connection terminals Pa1. Specifically, in Figure 1GIn the illustrated embodiment, two opposite sides (e.g., the left and right sides) of the magnetor 120 expose the sides of the external connection terminals Pa1, while the external electrodes 130 respectively cover the aforementioned two opposite sides of the magnetor 120. Thus, the external electrodes 130 can respectively contact and connect to the external connection terminals Pa1, enabling the power inductor 100 to receive external electrical energy and function via the external electrodes 130.

[0055] In this embodiment, the power inductor 100 is formed by stacking and laminating multiple substrates, wherein each substrate has only one circuit layer. Therefore, the aforementioned power inductor 100 with three circuit layers can be formed by stacking and laminating three substrates. The following will use a power inductor 100 with three circuit layers (see reference) as an example. Figure 1C For example, and in conjunction with Figures 2A to 2C , Figures 3A to 3B as well as Figures 4A to 4C This describes the manufacturing method of the power inductor 100.

[0056] Please see Figures 2A to 2C In the manufacturing method of the power inductor 100, a first substrate 201 is provided, wherein Figure 2A This is a bottom view of the first substrate 201, and Figure 2B yes Figure 2A A schematic diagram of the cross section drawn along section 2B-2B of the central line. Figure 2C This is a top view of the first substrate 201, and it is rotated horizontally. Figure 2A The first substrate 201 is illustrated. The first substrate 201 includes a release layer 20, an outer loop circuit layer 111a, and an insulating spacer layer 112 disposed between the release layer 20 and the outer loop circuit layer 111a.

[0057] In the fabrication of the first substrate 201, firstly, an insulating spacer layer 112 and an outer loop circuit layer 111a are sequentially formed on the release layer 20. The material of the release layer 20 can be an organic material, such as polyethylene terephthalate (PET). The insulating spacer layer 112 and the outer loop circuit layer 111a can be formed by printing, exposure and development, spraying, or deposition. The aforementioned deposition can be physical vapor deposition (PVD) or chemical vapor deposition (CVD). Then, a magnetically sensitive layer 120i is formed on the release layer 20, wherein the magnetically sensitive layer 120i can be formed by printing, exposure and development, or spraying.

[0058] The outer loop circuit layer 111a is strip-shaped, resembling... Figure 2C The outer loop circuit layer 111a is shown as an inverted C-shape. It has an external connection terminal Pa1 and a first internal connection terminal Pb1 relative to Pa1, wherein both Pa1 and Pb1 are opposite ends of the outer loop circuit layer 111a. The external connection terminal Pa1 of the first substrate 201 is covered by an insulating spacer layer 112 and is also located at... Figure 1B In the left half, the external connection terminal Pa1 is covered by the insulating spacer layer 112. The insulating spacer layer 112 extends along the outer loop circuit layer 111a, so the shape of the insulating spacer layer 112 is also strip-shaped and similar to the shape of the outer loop circuit layer 111a, for example, an inverted C-shape.

[0059] However, in other embodiments, the outer loop circuit layers 111a may not be located between adjacent insulating spacer layers 112. For example, in Figure 1C In this configuration, the uppermost insulating spacer layer 112 can be omitted. The outer loop circuit layer 111a has a pair of opposing first sidewalls S1a, and the insulating spacer layer 112 extending along the outer loop circuit layer 111a protrudes beyond these first sidewalls S1a, with the insulating spacer layer 112 directly contacting the outer loop circuit layer 111a. Furthermore, the first internal connection terminal Pb1 of the outer loop circuit layer 111a protrudes beyond the end of the insulating spacer layer 112, so the first internal connection terminal Pb1 is not completely covered by the insulating spacer layer 112 and directly contacts the release layer 20, as shown below. Figures 2A to 2C As shown.

[0060] Please see Figure 3A and Figure 3B Next, a second substrate 202 is provided and stacked and pressed onto the first substrate 201. Before the second substrate 202 is stacked and pressed onto the first substrate 201, the release layer 20 of the first substrate 201 is removed to expose the insulating spacer layer 112 and the magnetically sensitive layer 120i of the first substrate 201. Furthermore, Figure 3A This is a top view of the second substrate 202, and Figure 3B The diagram then shows a cross-sectional view of the second substrate 202 stacked and pressed onto the first substrate 201, wherein... Figure 3B The second substrate 202 shown is Figure 3A The section along the central line is drawn in section 3B-3B.

[0061] The structure of the second substrate 202 is similar to that of the first substrate 201. Specifically, the second substrate 202 includes a release layer 20, an inner loop circuit layer 111b, and an insulating spacer layer 112 disposed between the release layer 20 and the inner loop circuit layer 111b, wherein the inner loop circuit layer 111b and the outer loop circuit layer 111a can be made of the same material. One of the second internal connection terminals Pb2 of the inner loop circuit layer 111b protrudes from the end of the insulating spacer layer 112, but the other second internal connection terminal Pb2 is covered by the insulating spacer layer 112, such as... Figure 3A As shown. Therefore, the second internal connection terminal Pb2 is not completely covered by the insulating spacer layer 112 and directly contacts the release layer 20.

[0062] Secondly, the inner loop circuit layer 111b is strip-shaped, for example, inverted U-shaped, and has two opposing second internal connection ends Pb2, which are the opposite ends of the inner loop circuit layer 111b. The insulating spacer layer 112 of the second substrate 202 directly contacts the inner loop circuit layer 111b and extends along the inner loop circuit layer 111b, so the insulating spacer layer 112 is also strip-shaped and can be inverted U-shaped. The inner loop circuit layer 111b has a pair of opposing second sidewalls S1b, and the insulating spacer layer 112 extending along the inner loop circuit layer 111b protrudes from these second sidewalls S1b.

[0063] Please see Figure 2C and Figure 3A During the process of stacking and pressing the second substrate 202 onto the first substrate 201, the first substrate 201 (e.g. Figure 2C The second substrate 202 (as shown) is located below, while the third substrate 202 (as shown) is located below. Figure 3A (As shown) is located at the top. From Figure 3A and Figure 2C As can be seen, the second internal connection terminal Pb2 on the left side of the upper inner loop circuit layer 111b is aligned with the first internal connection terminal Pb1 of the lower outer loop circuit layer 111a, wherein the aforementioned second internal connection terminal Pb2 on the left side overlaps with the insulating spacer layer 112 and does not protrude from the edge of the insulating spacer layer 112.

[0064] Since the first internal connection terminal Pb1 of the lower outer loop circuit layer 111a protrudes from the end of the insulating spacer layer 112, the first internal connection terminal Pb1 will be exposed after the release layer 20 of the first substrate 201 is removed. Secondly, since the upper second internal connection terminal Pb2 is aligned with the lower first internal connection terminal Pb1, when the second substrate 202 is stacked and pressed onto the first substrate 201, the upper second internal connection terminal Pb2 can directly contact and connect with the lower first internal connection terminal Pb1, so that the outer loop circuit layer 111a and the inner loop circuit layer 111b can be electrically connected to each other.

[0065] During the lamination process of the second substrate 202 and the first substrate 201, the second substrate 202 and the first substrate 201 are heated to bond them together. However, the temperature of the second substrate 202 and the first substrate 201 during this heating process is not high, approximately below 90°C. Therefore, the magnetically sensitive layers 120i of the second substrate 202 and the first substrate 201 are not fused together, meaning that a boundary still exists between the second substrate 202 and the first substrate 201.

[0066] Please see Figure 4A and Figure 4B After the second substrate 202 is stacked and pressed onto the first substrate 201, a third substrate 203 is provided, and the third substrate 203 is then stacked and pressed onto the second substrate 202. Before the third substrate 203 is stacked and pressed onto the second substrate 202, the release layer 20 of the second substrate 202 is removed to expose the insulating spacer layer 112 and the magnetically sensitive layer 120i of the second substrate 202. Furthermore, Figure 4A This is a top view of the third substrate 203, and Figure 4B The diagram then shows a cross-sectional view of the third substrate 203 stacked and pressed onto the second substrate 202, wherein... Figure 4B The third substrate 203 shown is Figure 4A The section along the central line is drawn from section 4B-4B.

[0067] The third substrate 203 includes a release layer 20, an outer loop circuit layer 111a, and an insulating spacer layer 112 disposed between the release layer 20 and the outer loop circuit layer 111a. The structure of the third substrate 203 is similar to that of the first substrate 201, and the manufacturing methods of the third substrate 203 and the first substrate 201 are the same. For example, in the third substrate 203, both the outer loop circuit layer 111a and the insulating spacer layer 112 are strip-shaped, wherein the insulating spacer layer 112 extends along the outer loop circuit layer 111a and directly contacts the outer loop circuit layer 111a, and the insulating spacer layer 112 also protrudes from a pair of first sidewalls S1a of the outer loop circuit layer 111a. In addition, the outer loop circuit layer 111a also has an external connection terminal Pa1 and a first internal connection terminal Pb1.

[0068] Based on the above Figures 2A to 2C as well as Figures 3A to 3B The disclosed content shows that two insulating spacer layers 112 extending along the outer loop circuit layers 111a respectively protrude from the first sidewall S1a of the outer loop circuit layers 111a, and the insulating spacer layer 112 extending along the inner loop circuit layer 111b also protrudes from the second sidewall S1b of the inner loop circuit layer 111b, so that the insulating spacer layers 112 can increase the insulation resistance between the outer loop circuit layers 111a and the inner loop circuit layer 111b, thereby avoiding the occurrence of short circuits.

[0069] Each insulating spacer layer 112 is strip-shaped. Two of these insulating spacers 112 respectively cover and directly contact the outer loop circuit layers 111a, while the other insulating spacers 112 cover and directly contact the inner loop circuit layers 111b. In addition, the first internal connection terminal Pb1 of each outer loop circuit layer 111a is connected to a second internal connection terminal Pb2 of one of the inner loop circuit layers 111b.

[0070] The main difference between the third substrate 203 and the first substrate 201 is that the outer loop circuit layer 111a and the insulating spacer layer 112 are different in shape. The outer loop circuit layer 111a of the first substrate 201 is in the shape of an inverted C-shape (see [reference]). Figure 2C The outer loop circuit layer 111a of the third substrate 203 is C-shaped (see [reference]). Figure 4A Furthermore, the external connection terminal Pa1 in the third substrate 203 is... Figure 1B The external connection terminal Pa1 is located on the right half of the middle.

[0071] Please see Figure 3A and Figure 4A During the process of stacking and pressing the third substrate 203 onto the second substrate 202, the second substrate 202 (such as...) Figure 3A(as shown) is located below, while the third substrate 203 (as shown) Figure 4A (As shown) is located at the top. From Figure 3A and Figure 4A As can be seen, the first internal connection terminal Pb1 of the upper outer loop circuit layer 111a is aligned with the second internal connection terminal Pb2 on the right side of the lower inner loop circuit layer 111b, wherein the first internal connection terminal Pb1 overlaps with the insulating spacer layer 112 and does not protrude from the edge of the insulating spacer layer 112.

[0072] Because the second internal connection terminal Pb2 on the right side of the lower inner loop circuit layer 111b protrudes from the end of the insulating spacer layer 112, the second internal connection terminal Pb2 on the right side will be exposed after the release layer 20 of the second substrate 202 is removed. Secondly, because the upper first internal connection terminal Pb1 is aligned with the lower right second internal connection terminal Pb2, when the third substrate 203 is stacked and pressed onto the second substrate 202, the upper first internal connection terminal Pb1 can directly contact and connect to the lower second internal connection terminal Pb2, so that the outer loop circuit layer 111a and the inner loop circuit layer 111b can be electrically connected to each other.

[0073] Based on the above, through direct contact and connection between the first internal connection terminal Pb1 and the second internal connection terminal Pb2, the outer loop circuit layer 111a of the first substrate 201 and the third substrate 203 is electrically connected to the inner loop circuit layer 111b of the second substrate 202. Furthermore, from... Figure 2C , Figure 3A and Figure 4A It can be seen that after the outer loop circuit layer 111a of the first substrate 201 and the third substrate 203 are electrically connected to the inner loop circuit layer 111b of the second substrate 202, the inner loop circuit layer 111b and these outer loop circuit layers 111a can form a spiral coil 110.

[0074] Please see Figure 4C After the third substrate 203 is stacked and pressed onto the second substrate 202, the first substrate 201, the second substrate 202, and the third substrate 203, which are connected to each other, are then sequentially burned out and sintered to remove residual organic materials and impurities within the first substrate 201, the second substrate 202, and the third substrate 203, and to fuse the magnetically sensitive layers 120i of the three substrates into one to form a magnetically sensitive body 120 (e.g., ...). Figure 1C As shown), the insulating films 122 of these ferromagnetic particles within the magnetic induction layer 120i are interconnected due to sintering, as... Figure 1D As shown. The sintering process may include introducing oxygen to help the surface of the iron oxide-based alloy particles 121 (see [reference]). Figure 1DThis increases the insulation resistance of the magnetizing element 120, while the sintering temperature can be below 800℃.

[0075] Please see Figure 4C and Figure 1C Two cover layers 140a and 140b can be formed on opposite sides of the magnetor 120, for example, on the upper surface of the third substrate 203 and the lower surface of the first substrate 201. When the constituent materials of cover layers 140a and 140b are different from the constituent material of the magnetor 120, cover layers 140a and 140b can be formed after the aforementioned burn-off and sintering. When the constituent materials of cover layers 140a and 140b are the same as the constituent material of the magnetor 120, cover layers 140a and 140b can be formed on the upper surface of the third substrate 203 and the lower surface of the first substrate 201, respectively, before the aforementioned burn-off and sintering.

[0076] Figure 5 This is a cross-sectional schematic diagram of a power inductor according to another embodiment of the present invention. Please refer to... Figure 5 , Figure 5 The power inductor 500 is similar to the power inductor 100 in the aforementioned embodiment, wherein the power inductors 500 and 100 also include some of the same components, such as the magnetizing element 120, the outer loop circuit layer 111a, and the inner loop circuit layer 111b. Furthermore, the power inductor 500 may also include... Figure 5 External electrodes 130 and cover layers 140a and 140b are not shown. The following only describes the differences between power inductors 500 and 100; identical technical features will not be repeated.

[0077] Unlike power inductor 100, power inductor 500 includes multiple insulating spacer layers 512, wherein each insulating spacer layer 512 protrudes from the edge of either the outer loop circuit layer 111a or the inner loop circuit layer 111b. Figure 5 For example, each insulating spacer layer 512 extends to the side of the magnetor 120 and completely overlaps with the upper and lower surfaces of the magnetor 120, such that each insulating spacer layer 512 protrudes beyond the edge of either the outer loop circuit layer 111a or the inner loop circuit layer 111b, or even the entire edge. In this way, the insulating spacer layer 512 can significantly increase the insulation resistance, thereby effectively preventing short circuits between adjacent layers of the outer loop circuit layer 111a and the inner loop circuit layer 111b.

[0078] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0079] [Symbol Explanation]

[0080] 20: Release layer

[0081] 100, 500: Power inductors

[0082] 110: Coil

[0083] 111a: Outer loop circuit layer

[0084] 111b: Inner loop circuit layer

[0085] 112, 512: Insulating spacer layer

[0086] 112p, 142p: Flat insulating particles

[0087] 120: Magnet

[0088] 120i: Magnetizing layer

[0089] 121: Iron-based alloy particles

[0090] 122: Insulating film

[0091] 130: External electrode

[0092] 140a, 140b: Covering layer

[0093] 201: First substrate

[0094] 202: Second substrate

[0095] 203: Third substrate

[0096] D1: Thickness direction

[0097] L1, L2: Long axis

[0098] Pa1: External connection terminal

[0099] Pb1: First internal connection terminal

[0100] Pb2: Second internal connection terminal

[0101] S1, S2: Short axis

[0102] S1a: First sidewall

[0103] S1b: Second sidewall

[0104] w1, w2: Width.

Claims

1. A power inductor, characterized in that, include: Coil, including: Two outer loop circuit layers are stacked on top of each other and electrically connected in the thickness direction, wherein each of the outer loop circuit layers has an external connection terminal; A plurality of insulating spacer layers, wherein at least one of the insulating spacer layers is located between the plurality of outer loop circuit layers, and each of the plurality of insulating spacer layers comprises: A plurality of first flat insulating particles, each of the plurality of first flat insulating particles having a first long axis and a first short axis orthogonal to the first long axis, wherein the plurality of first long axes of a portion of the plurality of first flat insulating particles are orthogonal to the thickness direction; A magnetizing element, covering the coil and exposing the external connection terminals of each of the outer loop circuit layers, wherein the magnetizing element comprises a plurality of ferromagnetic particles, and each of the ferromagnetic particles comprises: Iron-based alloy particles; and An insulating film is used to coat the iron-based alloy particles.

2. The power inductor according to claim 1, characterized in that, The ratio of the first major axis to the first minor axis of the plurality of first flat insulating particles is greater than 1 and less than 1000.

3. The power inductor according to claim 1, characterized in that, The plurality of first flat insulating particles comprise a magnetic alloy material.

4. The power inductor according to claim 1, characterized in that, Also includes: Two covering layers respectively cover opposite sides of the magnetoresistive element and the coil, and directly contact the magnetoresistive element, and each of the plurality of covering layers includes: A plurality of second flat insulating particles, each of the plurality of second flat insulating particles having a second long axis and a second short axis orthogonal to the second long axis, wherein the plurality of second long axes of a portion of the plurality of second flat insulating particles are orthogonal to the thickness direction.

5. The power inductor according to claim 4, characterized in that, The plurality of first flat insulating particles of the plurality of insulating spacers comprise ceramic material, while the plurality of second flat insulating particles of the plurality of cover layers comprise magnetic alloy material.

6. The power inductor according to claim 1, characterized in that, The outer loop circuit layer is located between two adjacent insulating spacer layers.

7. The power inductor according to claim 1, characterized in that, Also includes: Multiple external electrodes partially cover the outer surface of the magnetor and are connected to the multiple external connection terminals of the multiple outer loop circuit layers.

8. The power inductor according to claim 1, characterized in that, The coil also includes: An inner loop circuit layer is disposed between the plurality of outer loop circuit layers and electrically connected to the plurality of outer loop circuit layers, wherein the inner loop circuit layer is located between two of the insulating spacers.

9. The power inductor according to claim 8, characterized in that, Each of the outer loop circuit layers also has a first internal connection terminal relative to the external connection terminal, while the inner loop circuit layer has two second internal connection terminals opposite to each other, wherein the first internal connection terminal of each of the outer loop circuit layers is connected to the second internal connection terminal.

10. The power inductor according to claim 9, characterized in that, Each of the insulating spacers is strip-shaped, and two of the plurality of insulating spacers respectively cover and directly contact the plurality of outer loop circuit layers and extend along the plurality of outer loop circuit layers. Each of the outer loop circuit layers has a pair of opposing first sidewalls, and the two insulating spacers extending along the plurality of outer loop circuit layers respectively protrude from the plurality of first sidewalls of the plurality of outer loop circuit layers.

11. The power inductor according to claim 10, characterized in that, The first internal connection end of the outer loop circuit layer protrudes from the end of one of the insulating spacer layers.

12. The power inductor according to claim 10, characterized in that, One of the plurality of insulating spacers directly contacts and extends along the inner loop circuit layer, wherein the inner loop circuit layer has a pair of opposing second sidewalls, and the insulating spacer extending along the inner loop circuit layer protrudes from the plurality of second sidewalls.

13. The power inductor according to claim 12, characterized in that, One of the second internal connection ends of the inner loop circuit layer protrudes from the end of the insulating spacer layer extending along the inner loop circuit layer.

14. The power inductor according to claim 12, characterized in that, Each of the insulating spacers protrudes from the edge of any of the plurality of outer loop circuit layers.

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