Series hybrid bus voltage linear active disturbance rejection control method and system

Abstract

The application provides a series hybrid bus voltage linear active disturbance rejection control method and system, and relates to the technical field of vehicle electric drive control. The series hybrid bus voltage linear active disturbance rejection control device comprises a power battery, a bidirectional DC / DC converter, a direct current bus capacitor, a free piston generator and a three-phase uncontrolled rectifier bridge. The method comprises the following steps: collecting the real-time value of the direct current bus voltage, the real-time value of the inductance current of the bidirectional DC / DC converter and the reference value of the direct current bus voltage; constructing a total disturbance observation model according to the reference value of the direct current bus voltage, and determining the total disturbance estimation value through the total disturbance observation model; generating the inductance current reference value according to the total disturbance estimation value, the real-time value of the direct current bus voltage and the reference value of the direct current bus voltage; generating the duty cycle control signal through the PI controller according to the inductance current reference value and the real-time value of the inductance current; and adjusting the bus voltage through the bidirectional DC / DC converter according to the duty cycle control signal.

Description

Technical Field

[0001] This invention relates to the field of vehicle electric drive control methods, and in particular to a series hybrid bus voltage linear active disturbance rejection control method and system. Background Technology

[0002] In the electric drive system of a series hybrid vehicle, the DC bus is the energy hub connecting various power sources and loads. Free-piston generators, as a crankshaft-less, flywheel-less, and compact range extender solution, have recently gained attention in the military vehicle field. Their pistons perform sinusoidal reciprocating linear motion, and the pulsating fundamental frequency of the output power is twice the stroke frequency. After the pulsating power is injected into the DC bus through a three-phase uncontrolled rectifier bridge, it creates periodic voltage disturbances whose frequency and amplitude change in real time with the operating conditions. Therefore, an adaptive control scheme is needed to ensure the stability of the bus voltage.

[0003] Currently, PI regulators are commonly used for DC bus voltage control. Meanwhile, active disturbance rejection (ADRR) technology has also developed into linear ADRR schemes. By linearizing each control link, the adjustable parameters are compressed into two categories: controller bandwidth and observer bandwidth, which significantly reduces the threshold for engineering implementation. Existing literature has applied this technology to the bus voltage control scenarios of DC microgrids and energy storage systems.

[0004] However, factors such as voltage gain drift caused by changes in battery state of charge and capacitor aging make it difficult for fixed-parameter PI to maintain good performance under all operating conditions. Furthermore, existing linear active disturbance rejection control applications do not involve special pulsating power sources such as free piston generators, and lack a systematic design method for observer bandwidth based on their pulsating frequency band characteristics, thus failing to meet the disturbance suppression requirements of time-varying pulsations in this scenario. Summary of the Invention

[0005] To address the issue that existing technologies suffer from voltage gain drift and capacitor aging caused by changes in battery state of charge, making it difficult for fixed-parameter PI controllers to maintain good performance under all operating conditions; and the fact that existing linear active disturbance rejection control applications do not involve special pulsating power sources such as free-piston generators, lacking a systematic design method for observer bandwidth based on their pulsating frequency band characteristics, thus failing to meet the technical requirements for time-varying disturbance suppression in this scenario.

[0006] The technical solution provided by this invention is as follows: The first aspect of the present invention provides a series hybrid bus voltage linear active disturbance rejection control method, which is applied to a series hybrid bus voltage linear active disturbance rejection control device, wherein the series hybrid bus voltage linear active disturbance rejection control device includes a power battery, a bidirectional DC / DC converter, a DC bus capacitor, a free piston generator and a three-phase uncontrolled rectifier bridge. A cascaded control structure of voltage outer loop and current inner loop is adopted. The voltage outer loop adopts a linear active disturbance rejection controller, and the current inner loop adopts a PI controller. The linear active disturbance rejection controller consists of a linear extended state observer and a linear error feedback loop, without a tracking differentiator; The methods include: S1: Collects real-time values ​​of DC bus voltage, real-time values ​​of inductor current of bidirectional DC / DC converter, and reference values ​​of DC bus voltage; S2: Based on the DC bus voltage reference value, construct a total disturbance observation model, and determine the total disturbance estimate through the total disturbance observation model; S3: Generate inductor current reference value based on total disturbance estimate, real-time DC bus voltage value and DC bus voltage reference value; S4: Based on the inductor current reference value and the inductor current real-time value, a duty cycle control signal is generated through a PI controller; S5: Adjust the bus voltage through a bidirectional DC / DC converter based on the duty cycle control signal.

[0007] A second aspect of the present invention provides a series hybrid bus voltage linear active disturbance rejection control system, comprising: processor; A memory storing computer-readable instructions, which, when executed by the processor, implement the series hybrid bus voltage linear active disturbance rejection control method as described in the first aspect.

[0008] The beneficial effects of the technical solution provided by this invention include: In this embodiment of the invention, a cascaded control structure combining voltage outer-loop linear active disturbance rejection control (ADC) and current inner-loop PI control is adopted. The voltage outer loop uses a linear ADC controller without a tracking differentiator. A linear extended state observer is used to model the uncertainties in system parameters such as pulsating current disturbances of the free-piston generator, load changes, and voltage gain drift and capacitor aging caused by changes in battery state of charge as a unified system disturbance and estimate them in real time. Then, proportional control and total disturbance feedforward compensation are achieved through a linear error feedback loop. This eliminates the dependence of traditional PI control on a precise model of the controlled object, allowing the fixed-parameter PI to maintain good performance under all operating conditions. Simultaneously, an observer bandwidth design criterion based on the free-piston generator's stroke operating frequency band is proposed. The observer bandwidth parameters are determined by combining the trade-off between disturbance suppression effect and noise amplification, enabling the observer to accurately track time-varying pulsating disturbances across the entire operating frequency band of the free-piston generator. This compensates for the lack of a systematic bandwidth design method for this specific pulsating power source in existing linear ADC applications, effectively adapting to the time-varying pulsating disturbance suppression requirements in this scenario. Attached Figure Description

[0009] Figure 1 A schematic flowchart of a series hybrid bus voltage linear active disturbance rejection control method provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the electrical topology of a series hybrid power device provided in an embodiment of the present invention.

[0010] Figure 3 The internal structure signal flow diagram of the linear extended state observer provided in the embodiments of the present invention; Figure 4 A comparison diagram of the time-domain response of PI and LADRC bus voltages provided in an embodiment of the present invention; Figure 5 A comparison chart of the three performance indicators PI and LADRC provided in this embodiment of the invention; Figure 6 A comparison diagram of the amplitude-frequency characteristics of the LADRC perturbation-output transfer function provided in an embodiment of the present invention; Figure 7 The LADRC perturbation suppression amplitude-frequency characteristic diagrams under different observer bandwidths provided in the embodiments of the present invention; Figure 8 Pareto trade-off plot of the ratio of observer bandwidth to controller bandwidth for disturbance suppression advantage and noise amplification provided in embodiments of the present invention; Figure 9 A comparison diagram of the amplitude-frequency characteristics of the disturbance-output transfer function of LADRC control provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of the structure of the series hybrid bus voltage linear active disturbance rejection control system provided by the present invention. Detailed Implementation

[0011] Reference manual attached Figure 1 The diagram shows a schematic flowchart of a series hybrid bus voltage linear active disturbance rejection control method provided by an embodiment of the present invention.

[0012] Reference manual attached Figure 2 The diagram shows an electrical topology schematic of a series hybrid power device provided in an embodiment of the present invention.

[0013] The electrical topology of the series hybrid power unit in this embodiment includes: a power battery 1, a bidirectional DC / DC converter 2, a DC bus capacitor 3, a first inverter 4, a second inverter 5, a first permanent magnet synchronous motor 6, a second permanent magnet synchronous motor 7, a free piston generator 8, a three-phase uncontrolled rectifier bridge 9, a planetary gear coupling mechanism 10, a vehicle 11, and a bus voltage controller 12.

[0014] The DC bus capacitor 3 serves as the energy transmission hub. The power supply side is divided into two branches. The power battery 1 is bidirectionally connected to the DC bus via the bidirectional DC / DC converter 2, enabling boost discharge and braking energy de-energization recharge. The three-phase AC power output from the free piston generator 8 is rectified by the labeled three-phase uncontrolled rectifier bridge 9 and injected into the DC bus, introducing periodic pulsating current disturbances. The load side is also divided into two paths. The DC bus supplies power to the first inverter 4 and the second inverter 5 respectively. The first permanent magnet synchronous motor 6 operates, and the second permanent magnet synchronous motor 7 operates. The output power of both motors converges into the planetary gear coupling mechanism 10, ultimately driving the vehicle 11 after power coupling. The bus voltage controller 12 collects the operating status of the DC bus through the dotted signal link and outputs control commands to the bidirectional DC / DC converter. By adjusting the power injection amount on the battery side, it offsets pulsating disturbances and load fluctuations, maintaining the stability of the DC bus voltage.

[0015] Reference manual attached Figure 3 The diagram shows the internal structure signal flow graph of the linear extended state observer provided in an embodiment of the present invention.

[0016] Measured DC bus voltage V dc The summation and comparison step on the left is compared with the estimated voltage value returned from the feedback. z 1. Obtain the observation error by subtracting the values. e Observation error e It is divided into two branches. One branch passes through the first correction gain module 19 and merges into the summing node of the forward channel. The other branch passes through the second correction gain module 20 and is input to the second integrator module 22. Control quantity u The total disturbance estimate, calculated by the model feedforward module 23, is also input to the forward summing node, while the total disturbance estimate output by the second integrator module 22 is also input. z 2. Feedback is also provided to the summing node. The summing node superimposes the three input signals and sends them to the first integrator module 21. The first integrator outputs the estimated DC bus voltage. z 1, z On one hand, it serves as the first output of the observer, outputting outwards; on the other hand, it feeds back to the summation and comparison stage on the left for error calculation, and also feeds back to the input link of the second integrator module 22. The second integrator module 22 finally outputs the estimated total system disturbance. z 2, z 2 is output as the second output of the observer and simultaneously fed back to the summing node of the forward channel, thus forming a complete closed-loop observation circuit to achieve synchronous real-time estimation of DC bus voltage and total system disturbance.

[0017] Reference manual attached Figure 4The figure shows a comparison of the time-domain response of the PI and LADRC bus voltages provided in the embodiments of the present invention.

[0018] Free piston generator stroke frequency Under operating conditions, the DC bus voltage time-domain response comparison charts for PI control and Linear Active Disturbance Rejection Control (LADRC) are presented. The charts are divided into three sub-charts from top to bottom: full-range bus voltage comparison, start-up step response amplification, and load step response amplification. The vertical axis of all sub-charts represents the DC bus voltage. The horizontal axis represents time. The legend indicates that dashed lines represent PI control and solid lines represent LADRC control. The gray dotted line represents the DC bus voltage reference value. The gray dashed lines represent the load step moments. The top full-process waveform diagram covers the complete operation from 0 to 1.2 seconds, clearly showing that the PI control exhibits significant voltage overshoot and oscillation during the startup phase, while the LADRC-controlled bus voltage quickly and smoothly converges to the reference value, with significantly less ripple in the steady-state phase. The middle magnified startup step response diagram magnifies the startup process from 0 to 0.12 seconds, clearly showing that the PI control exhibits an overshoot of nearly 50V accompanied by multiple damped oscillations during startup, while the LADRC-controlled bus voltage has almost no overshoot, rising monotonically and smoothly and stabilizing at the reference value. The enlarged load step response diagram at the bottom focuses on the load disturbance period from 0.25 to 0.6 seconds. At the marked load step moments, the bus voltage drop of PI control is larger and the recovery process is accompanied by obvious fluctuations, while the voltage drop of LADRC control is smaller and the recovery speed is faster. Moreover, the voltage ripple amplitude of LADRC control is lower than that of PI control throughout the steady-state operation. This fully demonstrates the superior startup dynamic performance, load disturbance rejection capability and steady-state ripple suppression effect of the LADRC solution.

[0019] Reference manual attached Figure 5 The figure shows a comparison of the three performance indicators PI and LADRC provided in the embodiments of the present invention.

[0020] This chart compares the core performance of PI control and linear active disturbance rejection control across the entire operating frequency range of a free piston generator. From left to right, the charts show three sub-charts: startup overshoot, steady-state ripple peak-to-peak value, and load step voltage sag. The horizontal axis of all sub-charts represents the stroke frequency of the free piston generator, covering its complete operating range. The vertical axis of the startup overshoot sub-chart on the left represents the startup overshoot, presented as a bar chart. The legend indicates that light gray bars represent PI control and dark gray bars represent linear active disturbance rejection control. It is evident that PI control exhibits significant startup overshoot across the entire frequency range, with the overshoot magnitude increasing slightly with increasing stroke frequency. In contrast, the startup overshoot of linear active disturbance rejection control is extremely low, demonstrating significantly superior startup dynamic performance compared to PI control. The vertical axis of the middle steady-state ripple peak-to-peak value subplot represents the steady-state ripple peak-to-peak value, presented in a line graph format. The legend indicates that the dashed line with hollow circles represents PI control, and the solid line with solid squares represents linear active disturbance rejection control (ADC). The steady-state ripple peak-to-peak value of both control methods increases with increasing stroke frequency. ADC's ripple amplitude is significantly lower than PI control across the entire frequency band, with a more pronounced ripple suppression advantage at low frequencies, which narrows as the frequency increases. The vertical axis of the right-hand load step voltage drop subplot represents the load step voltage drop amplitude, presented in a line graph format. The legend indicates that the dashed line with hollow circles represents PI control, and the solid line with solid squares represents linear ADC. PI control's voltage drop amplitude is generally higher and fluctuates with operating conditions, while linear ADC's voltage drop amplitude remains consistently lower. Linear ADC's load step disturbance rejection performance is significantly better than PI control across all operating conditions.

[0021] Reference manual attached Figure 6 The figure shows a comparison of the amplitude-frequency characteristics of the LADRC perturbation-output transfer function provided in the embodiment of the present invention.

[0022] Appendix Figure 6This chart consists of two sub-plots comparing the frequency domain disturbance rejection performance of PI control and linear active disturbance rejection control (ADR). The upper sub-plot shows the disturbance-output transfer function amplitude-frequency characteristic, with the horizontal axis representing frequency on a logarithmic scale and the vertical axis representing the magnitude of the disturbance-to-output transfer function, in decibels (dB). In the legend, light gray indicates PI control, dashed lines indicate linear ADR, and the gray shaded area marks the operating frequency band of the free piston generator. Both characteristic curves show an overall trend of first changing and then decreasing with increasing frequency. In the low-frequency range, linear ADR has a lower disturbance-to-output gain and stronger disturbance rejection capability. The performance difference between the two gradually narrows with increasing frequency, intersecting at high frequencies, with the intersection marked by the vertical dashed line. The lower sub-plot shows the disturbance rejection advantage curve of linear ADR over PI control. The horizontal axis also uses a logarithmic scale for frequency, and the vertical axis represents the difference in disturbance rejection gain between the two control methods. Positive values ​​in the graph indicate that linear ADR has a better disturbance rejection effect. The advantage curve maintains a high positive value in the low-frequency range, demonstrating a significant disturbance suppression advantage. The advantage gradually diminishes as the frequency increases, dropping to zero at the frequency corresponding to the intersection of the curves in the upper sub-graph. This critical frequency is clearly marked; beyond this critical frequency, the difference turns negative, indicating that PI control performs better in high-frequency disturbance attenuation. The operating frequency band of the free piston generator, marked by gray shading in the figure, falls entirely within the range where the difference is positive, demonstrating that linear active disturbance rejection control outperforms PI control across the entire operating frequency band of the generator.

[0023] Reference manual attached Figure 7 The figure shows the amplitude-frequency characteristics of LADRC perturbation suppression under different observer bandwidths provided in the embodiments of the present invention.

[0024] Appendix Figure 7 The title clearly indicates the analysis topic. The horizontal axis represents the frequency using a logarithmic scale, and the vertical axis represents the amplitude of the disturbance-output transfer function. The lower the amplitude, the stronger the system's disturbance suppression capability. The legend includes PI control curves, multiple sets of linear active disturbance rejection control curves with different observer bandwidths, and the gray-shaded area of ​​the FPEG band marking the operating range of the free piston generator. All characteristic curves show an overall trend of first rising and then falling, reaching the optimal level of disturbance suppression in the mid-frequency range, and gradually converging the curves of different parameters after entering the high-frequency range. As the observer bandwidth gradually increases, the disturbance-output amplitude of the linear active disturbance rejection control shifts downward overall, and the disturbance suppression capability gradually increases from the low-frequency to the mid-frequency range. Within the free piston generator operating frequency band marked by gray shading, the higher the observer bandwidth, the more significant the suppression effect on pulsating disturbances, while also demonstrating the marginal change in the disturbance suppression gain brought about by bandwidth increase.

[0025] Reference manual attached Figure 8The diagram illustrates the Pareto trade-off between the observer bandwidth to controller bandwidth ratio provided in this embodiment of the invention and the advantages of disturbance suppression and noise amplification.

[0026] The Pareto trade-off diagram refers to the Pareto multi-objective trade-off principle, a classic concept in multi-objective optimization. It refers to the design approach of selecting the overall optimal parameters by weighing the trade-offs when it is impossible to achieve the optimality of multiple objectives simultaneously.

[0027] Appendix Figure 8 The horizontal axis represents the ratio of the observer bandwidth to the controller bandwidth. The left vertical axis represents the disturbance suppression advantage of linear active disturbance rejection control (AID) compared to PI control, and the right vertical axis represents the noise amplification factor of the observer. The figure contains three curves: the solid line with a solid dot corresponds to the disturbance suppression advantage at the upper limit of the free piston generator's operating frequency band; the dashed line with a hollow square corresponds to the disturbance suppression advantage at the lower limit of the generator's operating frequency band; and the dashed line with a hollow triangle corresponds to the noise amplification degree of the observer. As the bandwidth ratio increases, both disturbance suppression advantage curves show a continuous upward trend. The disturbance suppression advantage at the lower limit of the frequency band is consistently higher than that at the upper limit, while the noise amplification factor also increases at an accelerating rate with the bandwidth ratio. The vertical dashed line in the figure marks the bandwidth ratio value selected in this invention. This position is near the inflection point of diminishing marginal returns in disturbance suppression, ensuring disturbance suppression performance across the entire operating frequency band of the generator while controlling the noise amplification degree within a reasonable range, achieving the optimal trade-off between disturbance suppression performance and noise suppression capability.

[0028] Reference manual attached Figure 9 The diagram shows a comparison of the amplitude-frequency characteristics of the disturbance-output transfer function of LADRC control provided in an embodiment of the present invention.

[0029] Appendix Figure 9 The horizontal axis represents the frequency on a logarithmic scale, and the vertical axis represents the amplitude of the disturbance-output transfer function. A lower amplitude indicates stronger disturbance rejection capability. The figure includes three sets of compensation coefficient curves corresponding to different battery states of charge (SOCs). One set represents the parameters under nominal operating conditions, while the other two sets correspond to different high and low SOC levels. The gray shaded area indicates the operating frequency band of the free-piston generator. The overall trend of the three characteristic curves is completely consistent: they all rise to a peak in the mid-frequency range and then gradually decrease as the frequency increases. The three curves almost overlap across the entire frequency band, with only a very slight difference in the high-frequency range. This indicates that the compensation coefficient mismatch caused by fluctuations in battery SOC has a very limited impact on the system's disturbance rejection performance. Especially within the operating frequency band of the free-piston generator, parameter mismatch hardly weakens the disturbance rejection effect, demonstrating the good parameter robustness of this linear active disturbance rejection control scheme.

[0030] This invention provides a method for linear active disturbance rejection control of the voltage of a series hybrid bus, characterized in that it is applied to a linear active disturbance rejection control system of the voltage of a series hybrid bus, wherein the linear active disturbance rejection control system of the voltage of the series hybrid bus includes a power battery, a bidirectional DC / DC converter, a DC bus capacitor, a free piston generator and a three-phase uncontrolled rectifier bridge.

[0031] A cascaded control structure of voltage outer loop and current inner loop is adopted. The voltage outer loop uses a linear active disturbance rejection controller, and the current inner loop uses a PI controller.

[0032] Among them, the PI controller refers to the proportional-integral controller, which is a classic industrial control algorithm. It is used both as a reference scheme and in the current inner loop design of this scheme, and can achieve zero steady-state error tracking of the controlled variable.

[0033] Among them, the bidirectional DC / DC converter refers to the bidirectional DC-DC converter, which is a power conversion device that connects the power battery and the DC bus, and can realize bidirectional energy flow.

[0034] Specifically, the controlled object in the outer voltage loop is equivalent to a first-order integral form:

[0035]

[0036]

[0037] in, u This represents the control quantity, specifically the inductor current reference value. V dt This represents the real-time value of the DC bus voltage. f ( t () represents the total system disturbance. b 0 represents the compensation coefficient of the bus voltage dynamic model. G This represents the steady-state voltage gain of the bidirectional DC / DC converter. C bus This indicates the capacitance value of the DC bus capacitor. V bat This indicates the terminal voltage of the power battery. V dc,ref This represents the reference setpoint for the DC bus voltage. The compensation coefficient is a fixed nominal value under typical battery state of charge. The deviation between the actual gain and the nominal value caused by changes in battery state of charge is automatically estimated and compensated by the linear extended state observer as part of the total disturbance. b 0. No real-time updates required.

[0038] The linear active disturbance rejection controller consists of a linear extended state observer and a linear error feedback loop, without a tracking differentiator.

[0039] Specifically, the linearly extended state observer expands the total disturbance into new state variables, forming a second-order observer, as shown in the following formula:

[0040] in, This represents the first derivative of the observed estimate of the DC bus voltage with respect to time, i.e., the instantaneous rate of change of the voltage estimate. z 1 represents the observed estimate of the DC bus voltage. The first derivative of the observed estimate of the total system disturbance with respect to time represents the instantaneous rate of change of the total disturbance estimate. z 2 represents the observed estimate of the total system disturbance. β 1 represents the gain of the first observer. β 2 represents the gain of the second observer.

[0041] Specifically, the first observer gain and the first observer gain are determined by the pole placement method, configuring the observer's error dynamic characteristic polynomial into a double-pole form:

[0042] in, s Represents the Laplace operator. ω o This represents the observer bandwidth. The solution is... , .

[0043] Specifically, the formula for the linear error feedback loop is as follows:

[0044] in, k p This indicates the proportional control gain. ,in, ω c This represents the controller bandwidth, and the control law is calculated by subtracting the disturbance estimate. z 2. Implement feedforward compensation for the total disturbance, making the closed-loop system equivalent to a time constant. A first-order overshoot-free system.

[0045] Furthermore, the observer bandwidth ω o Determined based on the stroke operating frequency band of the free piston generator:

[0046] in, f max This indicates the upper limit of the stroke frequency of a free piston generator. k This represents the bandwidth margin factor, taken as... The recommended value relationship is as follows: The observer bandwidth is determined based on a trade-off between disturbance suppression gain and noise amplification. This is the inflection point where the disturbance suppresses diminishing marginal returns.

[0047] The linear extended state observer is implemented using forward Euler discretization:

[0048] in, The variable represents the value of the current control cycle. This indicates the value of the variable in the previous control cycle. T s Indicates the control cycle. Initial value. , .

[0049] Specifically, a cascaded control structure of an outer voltage loop and an inner current loop is adopted. The outer voltage loop uses a linear active disturbance rejection controller (AID) with the DC bus voltage as the controlled variable. The inner current loop uses a PI controller to control the inductor current of the bidirectional DC / DC converter. The two loops are decoupled through bandwidth separation: the bandwidth of the inner loop is much higher than that of the outer loop, allowing the outer loop to treat the inner loop as an ideal current tracking element. This cascaded structure utilizes the inherent inductor current dynamics of the bidirectional DC / DC converter, providing both hardware-level overcurrent protection and establishing a clear first-order integral controlled object for the outer voltage loop.

[0050] If a cascaded structure is not used, and the duty cycle is directly controlled by LADRC, D To adjust The controlled object is then a second-order system (dynamic inductor current + dynamic capacitor voltage):

[0051] in, D This indicates the duty cycle of the switching transistor in a bidirectional DC / DC converter. This represents the rectified current injected into the DC bus by the free piston generator via a three-phase uncontrolled rectifier bridge. This represents the total load current drawn from the DC bus to drive the load. L This represents the energy storage inductance value of the bidirectional DC / DC converter. R This represents the parasitic resistance of the energy storage inductor in a bidirectional DC / DC converter.

[0052] LADRC refers to Linear Active Disturbance Rejection Control, which is an active disturbance rejection control algorithm based on a linearization framework. It is the core control method adopted in this scheme and can improve the disturbance rejection capability by estimating and compensating for the total disturbance of the system in real time.

[0053] At this point, LADRC needs to design a third-order extended state observer (2nd order for the system + 1st order for the perturbation), introducing 3 observer gains. , , The parameter tuning of a third-order ESO requires balancing the positions of the three poles, and higher-order ESOs amplify measurement noise more severely (noise gain and...). Proportional, not second-order ).

[0054] Among them, ESO refers to Extended State Observer, which is the core component of linear active disturbance rejection control. It can uniformly extend the unmodeled dynamics of the system and internal and external disturbances into an additional system state for real-time estimation.

[0055] After adopting the cascaded structure, the inner current loop PI closes the inductor current dynamics, simplifying the outer loop controlled object into a first-order integral type:

[0056] in, For outer loop control quantity, The known gain portion of the controlled object. The total system disturbance includes the FPEG pulsating current. Load current variation and because G and C bus Modeling errors caused by deviations from nominal values.

[0057] FPEG refers to the free piston generator, which is the application object of this control scheme. When it is working, it injects periodic pulsating current into the DC bus.

[0058] For example, removing the battery SOC= Terminal voltage at 0.8 V bat =385V ,but G =0.6417, b 0 = 32.08. b The 0 value reflects the ratio of the voltage gain to the bus capacitance of the bidirectional DC / DC converter at a specific operating point. When the battery... SOC Changes led to V bat When offset, the actual gain differs from the nominal gain. b The difference of 0 will be automatically included in the total disturbance by ESO. compensate.

[0059] Among them, SOC refers to the state of charge of the battery, which represents the proportion of the remaining power battery capacity to the rated capacity. It is a battery operating parameter that affects the system control gain.

[0060] Compensation coefficient ,in V bat This is the battery terminal voltage, which varies with the state of charge (SOC). It can be calculated from the battery's open-circuit voltage characteristic (SOC). b The variation of 0 across the entire SOC range.

[0061] At this point, only a second-order ESO is required, and the observer gain is determined solely by a single bandwidth parameter. Sure( , ), noise gain and Proportional. The cascaded structure reduces the design complexity of ESO from three parameters to a single parameter.

[0062] When the actual control gain of the system deviates from its nominal value, substituting the control law into the equation of the actual controlled object reveals that the equivalent total disturbance of the system consists of two parts: one is the system's native external total disturbance, and the other is an additional disturbance term caused by gain mismatch. The frequency characteristics of this additional disturbance term are determined by the basic control quantity. The operating bandwidth of the basic control quantity is relatively low, while the bandwidth of the extended state observer is much higher than that of the control quantity. Therefore, the observer can accurately estimate and compensate for the additional disturbance caused by this gain mismatch. Based on this characteristic, the control gain parameter can be determined as follows: select the open-circuit voltage corresponding to the typical operating state of charge of the battery, calculate the steady-state voltage gain, and then further convert it to obtain the final nominal value of the control gain. Since the extended state observer can automatically compensate for the gain offset caused by changes in the battery's state of charge, this gain parameter does not need to be updated in real time. A fixed nominal value can be used within the operating range of all battery states of charge, which also avoids the additional computational overhead caused by online estimation of battery state of charge and adaptive parameter adjustment.

[0063] In one possible implementation, the bidirectional DC / DC converter includes an energy storage inductor.

[0064] The bidirectional DC / DC converter, power battery, and DC bus capacitor are connected in sequence.

[0065] In one possible implementation, the DC bus capacitor is connected in parallel between the positive and negative terminals of the DC bus.

[0066] In one possible implementation, the duty cycle control signal is calculated based on the deviation between the inductor current reference value and the inductor current real-time value, and the switching transistor of the bidirectional DC / DC converter is modulated by PWM.

[0067] PWM stands for Pulse Width Modulation, a commonly used switching control technology in the field of power electronics. It controls the output power by adjusting the pulse duty cycle and is used to drive the switching transistors of the converter.

[0068] In one possible implementation, the bandwidth of the linearly extended state observer is determined based on the stroke operating frequency band of the free piston generator.

[0069] Specifically, the free-piston generator is a three-phase permanent magnet linear motor. Its piston performs a sinusoidal reciprocating motion, and the three-phase back electromotive force is rectified by a six-pulse uncontrolled rectifier, injecting a pulsating rectified current with a fundamental frequency twice the stroke frequency into the DC bus. The driven load is a dual permanent magnet synchronous motor system coupled by planetary gears. Both motors draw power from the DC bus through three-phase inverters. Magnetic field orientation control.

[0070] Furthermore, the system includes a power battery and a bidirectional DC / DC converter. The bidirectional DC / DC converter contains an energy storage inductor, connecting the power battery to the DC bus, and can operate in boost and buck modes. A DC bus capacitor is connected in parallel between the positive and negative terminals of the DC bus. A voltage acquisition module is used to acquire the real-time value of the DC bus voltage. A current acquisition module is used to acquire the real-time value of the inductor current of the bidirectional DC / DC converter. An embedded controller runs a cascaded control program of an outer voltage loop and an inner current loop. The outer voltage loop is a linear active disturbance rejection controller, including a linear extended state observer and a linear error feedback loop. It does not include a tracking differentiator. The linear extended state observer takes the real-time value of the DC bus voltage and the control input as inputs, and models the pulsating current disturbance of the free piston generator, the change in the driven load, and the uncertainty of system parameters as a unified system disturbance and estimates it in real time. The linear error feedback loop calculates the inductor current reference value based on the voltage reference value, the real-time value of the DC bus voltage, and the disturbance estimate. The inner current loop uses a PI controller, which calculates the duty cycle control signal based on the deviation between the inductor current reference value and the real-time inductor current value. This signal is then used to control the switching transistors of the bidirectional DC / DC converter via PWM modulation. The bandwidth of the linear expansion state observer is determined based on the stroke operating frequency band of the free piston generator.

[0071] Specifically, the linear active disturbance rejection controller (ADC) consists of two parts: a linear extended state observer (ESO) and a linear error feedback loop (LESF), without a tracking differentiator. The reference value of the DC bus voltage is typically a fixed constant or slowly varying, eliminating the need for a tracking differentiator to smooth the reference signal. Eliminating the tracking differentiator reduces the number of parameters and computational load. The ESO unifies factors such as FPEG pulsating current, drive motor load variations, voltage gain drift caused by battery internal resistance, and capacitor parameter aging into a single "total disturbance." f ( tThe total disturbance is estimated by observing the deviation of the bus voltage in real time, and feedforward compensation is performed in the LESF control law. This "estimation-compensation" mechanism eliminates the need for the controller to model each disturbance source separately, thus possessing inherent robustness. More fundamentally, the cascaded structure simplifies the equivalent controlled object of the outer loop to a first-order integral form, and the linear error feedback uses a single proportional law. ,in, u 0 indicates the output of the proportional control circuit. This indicates the controller bandwidth of the voltage outer loop. r This represents the reference input of the outer voltage loop. The closed-loop transfer function of the outer loop after ESO compensation is: In a first-order system, the step response is monotonic with no overshoot. In this case, the tracking differentiator is ineffective, and omitting it does not result in performance loss. An observer bandwidth design criterion based on the FPEG stroke operating frequency band is proposed. The ESO's tracking accuracy for disturbances depends on its bandwidth. : The higher the value, the higher the upper limit of the perturbation frequency that ESO can accurately estimate, but excessively high values... This will amplify measurement noise. This invention utilizes the physical upper limit of the FPEG stroke frequency. Give the lower bound constraint on the observer bandwidth. ( k (This is the bandwidth margin factor), which ensures that ESO exactly covers the full operating frequency band of FPEG, achieving a balance between disturbance tracking accuracy and noise suppression.

[0072] Subsequently, a linear extended state observer was designed, treating the total system disturbance as the system's extended state and the DC bus voltage as the system's base state, thus extending the original system into a two-state extended system. A Luenberger-type full-order observer was designed for this extended system. This observer outputs two estimates: an estimate of the DC bus voltage and an estimate of the total system disturbance. The convergence dynamics of the observation error between the measured DC bus voltage and its corresponding estimate are determined by two sets of gain parameters of the observer.

[0073] The gain parameter of the observer is determined using the pole placement method. First, the dynamic equation of the observation error is established, and its corresponding characteristic polynomial is obtained. The two characteristic roots of the equation are placed at the same negative real frequency point. By comparing the polynomial coefficients, the gain values ​​of the two observers can be calculated. This placement parameter is the bandwidth parameter of the linear extended state observer. A larger bandwidth parameter results in faster tracking of system disturbances, but also a more significant amplification of measurement noise. The core function of the linear extended state observer is to estimate the total system disturbance in real time based on the measured bus voltage. The quantitative relationship between the observer's estimation accuracy of the total disturbance and its bandwidth parameter will be derived later.

[0074] The extended state equation of the controlled object is:

[0075] in, Represents the first state variable. This represents the first derivative of the first state variable with respect to time. Represents the second state variable. This represents the first derivative of the second state variable with respect to time. Indicates the total disturbance with respect to time t The first derivative.

[0076] Define observation error , Subtracting the observation equation from the extended state equation yields the error dynamics:

[0077] in, Indicates the first observation error. Indicates the second observation error. This represents the first derivative of the first observation error with respect to time. This represents the first derivative of the second observation error with respect to time.

[0078] Apply the Laplace transform to the above system of equations and eliminate The estimated transfer function of ESO for the total disturbance can be obtained as follows:

[0079] in, This represents the Laplace transform form of the total disturbance estimate. This represents the Laplace transform of the actual total disturbance.

[0080] In conventional publicly available literature, the selection of observer bandwidth often relies on engineering experience or repeated trial and error. This scheme, however, utilizes the physical constraint of the free piston generator's stroke frequency to provide deterministic parameter design criteria. The tracking error of the extended state observer for sinusoidal disturbances increases with the disturbance frequency. The fundamental frequency of the free piston generator's output pulsating current is twice the stroke frequency, covering the frequency range corresponding to its entire operating stroke. By selecting the highest operating stroke frequency of the free piston generator, the highest disturbance angular frequency corresponding to the pulsating current can be determined.

[0081] By pre-setting an allowable upper limit for the relative error of disturbance estimation, and substituting the highest disturbance angular frequency of the pulsating current of the free piston generator into the amplitude-frequency relationship of the disturbance estimation error, the minimum required value of the observer bandwidth can be derived in reverse. When the observer bandwidth is set to this minimum value, the disturbance estimation error exactly reaches the pre-set allowable upper limit under the extreme operating condition of the generator's highest operating stroke frequency. For all other operating conditions with lower stroke frequencies, the frequency of the pulsating disturbance is even lower, and the corresponding disturbance estimation errors will all be less than the set allowable upper limit, ensuring that the disturbance estimation accuracy meets the design requirements across the entire operating range of the generator. Determining the observer bandwidth according to this physical constraint rule eliminates the need to rely on engineering experience or repeated trial and error, ensuring disturbance estimation accuracy across the entire operating range while avoiding excessive amplification of measurement noise caused by excessively high bandwidth values.

[0082] Furthermore, as this ratio gradually increases, the disturbance suppression advantage at the highest operating frequency continues to improve, but the amplification of measurement noise by the observer also increases simultaneously. In the initial stage of the ratio increase, the improvement in disturbance suppression performance is significant, while the increase in noise amplification is relatively gradual. When the ratio increases to the inflection point of diminishing marginal returns, the improvement in disturbance suppression advantage narrows significantly, but the degree of noise amplification rises sharply. Before the inflection point, a considerable gain in disturbance suppression performance can be obtained by paying a certain amount of noise amplification; after the inflection point, the performance gain obtained by paying the same amount of noise amplification will shrink significantly. Based on this pattern, selecting parameter values ​​corresponding to the inflection point position can obtain sufficient disturbance suppression advantage across the entire operating frequency band of the free piston generator, while controlling the degree of noise amplification within a reasonable and acceptable range. This selection corresponds perfectly to the Pareto trade-off analysis conclusion of disturbance suppression advantage and noise amplification mentioned above. Subsequently, a linear error feedback loop is designed. After the extended state observer completes convergence and can accurately estimate the system state and total disturbance, a proportional feedback control law is designed. Substituting this control law into the controlled object model, it can be seen that the closed-loop system can be equivalent to a standard first-order system. By configuring the corresponding proportional gain, the closed-loop poles are set at the position matching the controller bandwidth. At this time, the adjustment speed of the closed-loop system is directly determined by the controller bandwidth. The system dynamic response has no overshoot and no oscillation throughout the entire process, and the adjustment time is negatively correlated with the controller bandwidth.

[0083] A suitable controller bandwidth value was selected, corresponding to an appropriate closed-loop settling time. This value was chosen after considering several trade-offs: too low a bandwidth would result in a slow dynamic response, making it unable to track rapidly occurring load changes in a timely manner. Too high a bandwidth would make the system overly sensitive to measurement noise, requiring an increase in the observer bandwidth to further amplify the noise effect. The final selected closed-loop bandwidth is higher than the full operating frequency band of the free piston generator, ensuring that the extended state observer has sufficient time to complete disturbance estimation under any operating condition. Subsequently, a proportional-integral controller for the inner current loop was designed. The inductor current of the bidirectional DC-DC converter is a first-order inertial element. The proportional-integral parameters are tuned using the internal model control principle, and the corresponding proportional gain and integral gain can be directly calculated by setting an appropriate inner loop closed-loop bandwidth. The inner loop bandwidth selected in this scheme meets the bandwidth separation condition of the cascaded system, and the ratio of the inner and outer loop bandwidths meets the requirements of classical cascaded control. The effectiveness of cascaded control is based on the assumption that the inner loop is transparent to the outer loop, that is, within each control cycle of the outer loop, the inner loop has already completed tracking of the current reference value. This requires that the inner loop bandwidth must be significantly higher than the outer loop bandwidth. Classical cascaded control theory requires the inner-outer loop bandwidth ratio to reach a certain threshold to ensure that the amplitude deviation and phase delay of the inner loop closed-loop transfer function within the outer loop bandwidth range are within acceptable limits. If the bandwidth ratio is lower than this threshold, the residual amplitude attenuation and phase lag dynamics of the inner loop will couple into the outer loop, causing the disturbance estimation results of the extended state observer to be mixed with the transient error of the inner loop, reducing the accuracy of disturbance compensation. At the same time, the inner loop bandwidth cannot be set too high. The higher the bandwidth, the greater the proportional gain of the proportional-integral controller, and the stronger the amplification effect on inductor current measurement noise. When the bandwidth is too high, the duty cycle of the pulse width modulation output will oscillate at high frequencies, causing additional losses and electromagnetic interference problems in the switching devices. In addition, the inner loop bandwidth is also limited by the switching frequency of the pulse width modulation; in engineering, the inner loop bandwidth is usually required not to exceed the corresponding proportional range of the switching frequency. The final selected inner loop bandwidth value is the optimal trade-off between the inner-outer loop separation margin, noise suppression effect, and engineering feasibility. The corresponding proportional-integral control parameters can be directly calculated using the internal model control method without repeated iterative tuning. Finally, the proportional-integral controller calculates the duty cycle control signal based on the deviation between the inductor current reference value and the actual value, and drives the switching transistors of the bidirectional DC-DC converter to complete power regulation through the pulse width modulation signal.

[0084] In this embodiment of the invention, by cascading the voltage outer loop linear active disturbance rejection control and the current inner loop PI control, the pulsating current, load changes and system parameter uncertainties generated by the free piston generator are estimated and compensated in real time as the total disturbance. The observer bandwidth is determined based on the stroke operating frequency band of the free piston generator, thereby taking into account the disturbance suppression capability, dynamic response speed and noise suppression performance. This is beneficial to reduce DC bus voltage ripple and overshoot, and improve the stability, robustness and engineering applicability of the series hybrid system under different operating conditions.

[0085] The methods include: S1: Collects real-time values ​​of DC bus voltage, real-time values ​​of inductor current of bidirectional DC / DC converter, and reference values ​​of DC bus voltage.

[0086] In this embodiment of the invention, by synchronously acquiring DC bus voltage, inductor current and bus voltage reference value, accurate and complete real-time input is provided for subsequent disturbance observation, current reference value calculation and duty cycle adjustment. This is beneficial for timely reflection of bus voltage deviation and converter operating status, and improves the response speed, adjustment accuracy and closed-loop stability of the control system.

[0087] S2: Based on the DC bus voltage reference value, construct a total disturbance observation model, and determine the total disturbance estimate through the total disturbance observation model.

[0088] In one possible implementation, S2 specifically includes sub-steps S201 to S206: S201: When the inner current loop of the bidirectional DC / DC converter is closed, establish a dynamic model of the bus voltage.

[0089] It should be noted that by establishing a dynamic model of the bus voltage after the inner current loop of the bidirectional DC / DC converter is closed, the fast tracking characteristic of the inner current loop can be used to approximate it as an ideal current source, thereby simplifying the controlled object of the outer voltage loop, reducing the design complexity of the controller and observer, and improving the accuracy, stability and parameter tuning efficiency of the bus voltage control.

[0090] S202: Determine the nominal compensation coefficient in the dynamic model of the bus voltage based on the preset power battery terminal voltage, the preset DC bus capacitance value, and the DC bus voltage reference value.

[0091] It should be noted that by calculating the nominal compensation coefficient by presetting the power battery terminal voltage, DC bus capacitance value, and bus voltage reference value, a clear model gain benchmark can be provided for the linear active disturbance rejection controller without the need for real-time updates to system parameters. The actual parameter deviations are then uniformly estimated and compensated by the extended state observer, thereby reducing the amount of online calculation and improving the robustness, adaptability, and ease of engineering implementation of the controller.

[0092] S203: Based on the bus voltage dynamic model and nominal compensation coefficient, the total system disturbance is expanded into state variables, and a total disturbance observation model is constructed based on the state variables.

[0093] It should be noted that by expanding the total system disturbance into state variables and constructing a corresponding observation model, the pulsating current, load changes, and parameter uncertainties of the free piston generator can be uniformly included in the real-time estimation range without the need to establish separate accurate disturbance models. This enhances the disturbance rejection capability, parameter robustness, and adaptability to complex operating conditions of the control system.

[0094] S204: Set the error dynamic characteristic polynomial of the total perturbation observation model to a double-pole form, and determine the first observer gain and the second observer gain.

[0095] It should be noted that by configuring the error dynamic characteristic polynomial as a dual-pole form, the first observer gain and the second observer gain can be directly determined based on a unified observer bandwidth, making the parameter tuning process simpler and clearer, and ensuring that the observation error converges at the expected speed, thereby improving the speed, stability and engineering implementation consistency of the total system disturbance estimation.

[0096] S205: Obtain the historical total disturbance observation status, and determine the DC bus voltage observation error based on the historical total disturbance observation status and the real-time value of the DC bus voltage, and generate the first state correction amount and the second state correction amount based on the first observer gain and the second observer gain.

[0097] It should be noted that by using the historical total disturbance observation state and the current real-time value of the DC bus voltage to calculate the observation error, and combining the gains of the first and second observers to generate the corresponding state correction, the bus voltage estimate and the total disturbance estimate can be continuously corrected, the observation deviation can be reduced, the observation state can be accelerated to converge, thereby improving the real-time performance and accuracy of the disturbance estimation and the disturbance rejection stability of the control system.

[0098] S206: Based on the first state correction, the second state correction, the nominal compensation coefficient, and the historical total disturbance observation state, the forward Euler method is used to discretely update the DC bus voltage estimation state and the total disturbance estimation state in the total disturbance observation model to obtain the total disturbance estimate.

[0099] It should be noted that by using the forward Euler method to discretely update the DC bus voltage estimation state and the total disturbance estimation state, the continuous observation model can be transformed into a recursive operation suitable for real-time execution by the digital controller. While ensuring a simple computational structure and a small computational load, the total disturbance estimate can be obtained in a timely manner, thereby improving the real-time performance, disturbance compensation accuracy, and embedded implementation convenience of the control system.

[0100] In this embodiment of the invention, by establishing a total disturbance observation model around the DC bus voltage reference value, the generator pulsation, load fluctuation and parameter changes reflected by the bus voltage deviation can be comprehensively characterized, and the total disturbance estimate for control compensation can be output, thereby reducing the dependence on separate modeling of various disturbances and enhancing the system's regulation initiative and bus voltage maintenance capability under variable operating conditions.

[0101] S3: Generate the inductor current reference value based on the total disturbance estimate, the real-time DC bus voltage value, and the DC bus voltage reference value.

[0102] In one possible implementation, S3 specifically includes sub-steps S301 to S304: S301: Calculate the DC bus voltage control deviation based on the real-time value and reference value of the DC bus voltage.

[0103] It should be noted that by comparing the real-time value of the DC bus voltage with the reference value, the bus voltage control deviation can be accurately obtained, which can intuitively reflect the degree to which the current bus voltage deviates from the target state, providing a clear basis for subsequent feedback adjustment and helping to improve the pertinence and steady-state accuracy of voltage control.

[0104] S302: Based on the DC bus voltage control deviation, the proportional feedback quantity is calculated through the linear error feedback loop.

[0105] It should be noted that by using a linear error feedback loop to convert the bus voltage control deviation into a proportional feedback quantity, the control action can change in a timely manner according to the magnitude of the voltage deviation. This can both accelerate the convergence of the bus voltage to the reference value and facilitate the tuning of the control performance through a single proportional parameter.

[0106] S303: Based on the total disturbance estimate, the proportional feedback quantity is subjected to disturbance feedforward compensation to obtain the voltage outer loop control quantity.

[0107] It should be noted that by using the total disturbance estimate to implement feedforward compensation for the proportional feedback quantity, the control output can be actively corrected before the disturbance causes a large bus voltage deviation, thereby reducing the impact of free piston generator pulsation, load abrupt changes and parameter variations, and improving the system's dynamic disturbance rejection capability.

[0108] S304: Use the voltage outer loop control quantity as the inductor current reference value of the current inner loop of the bidirectional DC / DC converter.

[0109] It should be noted that converting the voltage outer loop control quantity into the inductor current reference value of the current inner loop enables the bus voltage regulation requirements to be realized through the rapid current tracking of the bidirectional DC / DC converter, achieving effective connection between the voltage loop and the current loop, while taking into account both response speed and operational stability.

[0110] In this embodiment of the invention, the target value of the bus voltage, the actual operating state, and the identified total disturbance are combined to generate an inductor current reference value that matches the current power balance requirements. This enables the bidirectional DC / DC converter to adjust the energy transmitted from the power battery to the DC bus in a timely manner, thereby taking into account both voltage deviation correction and disturbance cancellation, reducing bus voltage fluctuations, and improving the transient regulation quality of the system.

[0111] S4: Based on the inductor current reference value and the inductor current real-time value, a duty cycle control signal is generated through the PI controller.

[0112] In one possible implementation, S4 specifically includes sub-steps S401 to S404: S401: Calculate the inductor current deviation based on the inductor current reference value and the inductor current real-time value.

[0113] It should be noted that by comparing the inductor current reference value with the real-time value, a deviation signal that can characterize the current tracking status is obtained, enabling the controller to promptly identify the difference between the actual current delivered by the bidirectional DC / DC converter and the target demand, providing a reliable basis for subsequent duty cycle adjustment.

[0114] S402: Perform proportional calculation on the inductor current deviation to obtain the proportional control component.

[0115] It should be noted that by performing proportional calculations on the inductor current deviation, corresponding control actions can be quickly generated based on the current deviation amplitude, enabling the converter to respond quickly when the current changes abruptly or the reference value changes, thereby improving the following speed and transient regulation capability of the inner current loop.

[0116] S403: Performs integral calculation on the inductor current deviation to obtain the integral control component.

[0117] It should be noted that by continuously accumulating the inductor current deviation, a correction effect can be formed on the long-term small deviations caused by device voltage drop, parasitic resistance and model error, thereby reducing the steady-state error of the inductor current and improving the continuous accuracy of current control.

[0118] S404: Based on the proportional control component and the integral control component, a duty cycle control signal is generated through a PI controller.

[0119] Specifically, the bandwidth of the PI controller in the inner current loop. controller bandwidth with voltage outer loop Satisfying bandwidth separation conditions: This allows the outer voltage loop to be equivalent to the inner current loop as an ideal current source.

[0120] The parameters of the PI controller are tuned using the internal model control method as follows:

[0121]

[0122] in, K p,i This represents the proportional gain of the inner-loop PI controller. K i,j This represents the integral gain of the inner-loop PI controller. This represents the closed-loop bandwidth of the inner current loop.

[0123] It should be noted that by combining the proportional control component and the integral control component to generate the duty cycle control signal, the rapid deviation correction capability and the steady-state error elimination capability are coordinated, and the switching state of the bidirectional DC / DC converter can be directly adjusted to achieve smooth and accurate tracking of the inductor current.

[0124] In this embodiment of the invention, the difference between the inductor current reference value and the real-time value is converted into a duty cycle control signal by a PI controller, enabling the bidirectional DC / DC converter to balance rapid adjustment during current changes and continuous elimination of steady-state deviations, thereby accurately controlling the energy transfer between the power battery and the DC bus and providing a reliable execution basis for bus voltage stability.

[0125] S5: Adjust the bus voltage through a bidirectional DC / DC converter based on the duty cycle control signal.

[0126] In one possible implementation, S5 specifically includes sub-steps S501 and S502: S501: Compare the duty cycle control signal with the preset carrier signal to generate a pulse width modulation drive signal.

[0127] It should be noted that by comparing the duty cycle control signal with the preset carrier signal, the continuous control command can be converted into a PWM drive signal that the switching device can directly respond to, so that the pulse width changes accurately with the control requirements, which helps to improve the standardization of the modulation process, the execution accuracy and the convenience of digital control implementation.

[0128] S502: Controls the bidirectional DC / DC converter according to the pulse width modulation drive signal to regulate the bus voltage.

[0129] It should be noted that by controlling the switching state of the bidirectional DC / DC converter based on the pulse width modulation (PWM) drive signal, the magnitude and direction of power transmission between the power battery and the DC bus can be dynamically adjusted, so that the aforementioned control calculations can truly act on the power circuit, thereby suppressing bus voltage fluctuations and maintaining power supply balance.

[0130] For example, power battery 1 is connected to the DC bus via a bidirectional DC / DC converter 2. Power battery 1 has a nominal voltage of 380–400V and a rated capacity of 60Ah. It uses a first-order Thevenin equivalent circuit model and includes an open-circuit voltage source. V oc (SOC), Ohmic internal resistance and first-order RC polarization branch (time constant) ).

[0131] The bidirectional DC / DC converter 2 connects the power battery 1 to the DC bus and can operate in boost and buck modes: In boost mode, it boosts the low battery voltage to the bus voltage to discharge the battery. In buck mode, it reduces the bus voltage back to charge the battery, realizing regenerative braking energy recovery. V dc Taking boost mode as an example, in this embodiment, the energy storage inductor of the bidirectional DC / DC converter... Inductor parasitic resistance The above analysis uses the boost mode as an example; the buck mode is the same. The LADRC voltage control method is applicable to both modes.

[0132] The free piston generator 8 is a three-phase permanent magnet linear motor, in which the piston performs sinusoidal reciprocating motion. Where S=64mm is the stroke. This indicates the stroke frequency. For example, the stroke frequency range of FPEG is 5–25 Hz, and the permanent magnet linkage... polar distance The three-phase back electromotive force generated by the piston motion is rectified by a three-phase uncontrolled rectifier bridge 9 (six-pulse diode rectifier) ​​and then injected into the DC bus with a fundamental frequency of 2. pulsating rectified current .

[0133] The capacitance value of DC bus capacitor 3 Reference voltage The bus node current equation is:

[0134] in, This represents the controllable supply current injected into the DC bus of the bidirectional DC / DC converter. , This represents the total load current drawn from the bus by the first inverter 4. This is the total load current drawn from the bus by the second inverter 5.

[0135] The first permanent magnet synchronous motor 6 (rated power 80kW) and the second permanent magnet synchronous motor 7 (rated power 30kW) draw power from the DC bus through the first inverter 4 and the second inverter 5, respectively. Each motor is powered in the dq coordinate system. i d =0 Magnetic field orientation control. The DC-side current of the inverter is determined by the power conservation relationship:

[0136] in, This represents the DC input current of a single motor inverter. This represents the direct-axis component of the motor stator voltage in a synchronous rotating coordinate system. This represents the direct-axis component of the motor stator current in a synchronous rotating coordinate system. This represents the quadrature-axis component of the motor stator voltage in a synchronous rotating coordinate system. This represents the quadrature-axis component of the motor stator current in a synchronous rotating coordinate system. The two motors are coupled via planetary gear coupling mechanism 10 (planetary gear set characteristic parameters). k 1 = 2.1 k 1=3.9, final drive ratio i 0=7.8) Drive the whole vehicle 11 (the whole vehicle weighs 3300kg).

[0137] In this embodiment of the invention, the duty cycle control signal is used to change the conduction ratio of the bidirectional DC / DC converter switch, thereby adjusting the current and power exchange between the power battery and the DC bus, so that the energy supply and demand on the bus side can be restored to balance in a timely manner, and ultimately reduce the voltage deviation caused by power generation pulsation and load changes, thereby improving the operational reliability of the vehicle power supply system.

[0138] Reference manual attached Figure 10 The diagram shows a schematic of the structure of a series hybrid bus voltage linear active disturbance rejection control system provided by the present invention.

[0139] The present invention also provides a series hybrid bus voltage linear active disturbance rejection control system 20, applied to the above-mentioned series hybrid bus voltage linear active disturbance rejection control method, comprising: Processor 201.

[0140] The memory 202 stores computer-readable instructions. When the computer-readable instructions are executed by the processor 201, they implement the series hybrid bus voltage linear active disturbance rejection control method as described in the method embodiment.

[0141] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. The scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for linear active disturbance rejection control of series hybrid bus voltage, characterized in that, An application to a series hybrid bus voltage linear active disturbance rejection control device, wherein the series hybrid bus voltage linear active disturbance rejection control device includes a power battery, a bidirectional DC / DC converter, a DC bus capacitor, a free piston generator, and a three-phase uncontrolled rectifier bridge; A cascaded control structure of voltage outer loop and current inner loop is adopted, wherein the voltage outer loop adopts a linear active disturbance rejection controller and the current inner loop adopts a PI controller; The linear active disturbance rejection controller consists of a linear extended state observer and a linear error feedback loop, without a tracking differentiator. The methods include: S1: Collect the real-time value of the DC bus voltage, the real-time value of the inductor current of the bidirectional DC / DC converter, and the reference value of the DC bus voltage; S2: Based on the DC bus voltage reference value, construct a total disturbance observation model, and determine the total disturbance estimate through the total disturbance observation model; S3: Generate an inductor current reference value based on the total disturbance estimate, the real-time DC bus voltage value, and the DC bus voltage reference value; S4: Based on the inductor current reference value and the inductor current real-time value, generate a duty cycle control signal through the PI controller; S5: Adjust the bus voltage through the bidirectional DC / DC converter according to the duty cycle control signal.

2. The series hybrid bus voltage linear active disturbance rejection control method according to claim 1, characterized in that, The bidirectional DC / DC converter includes an energy storage inductor; The bidirectional DC / DC converter, the power battery, and the DC bus capacitor are connected in sequence.

3. The series hybrid bus voltage linear active disturbance rejection control method according to claim 1, characterized in that, The DC bus capacitor is connected in parallel between the positive and negative terminals of the DC bus.

4. The series hybrid bus voltage linear active disturbance rejection control method according to claim 1, characterized in that, Based on the deviation between the inductor current reference value and the inductor current real-time value, a duty cycle control signal is calculated, and the switching transistor of the bidirectional DC / DC converter is modulated by PWM.

5. The series hybrid bus voltage linear active disturbance rejection control method according to claim 1, characterized in that, The bandwidth of the linear expansion state observer is determined based on the stroke operating frequency band of the free piston generator.

6. The series hybrid bus voltage linear active disturbance rejection control method according to claim 1, characterized in that, S2 specifically includes: S201: When the inner current loop of the bidirectional DC / DC converter is closed, establish a dynamic model of the bus voltage. S202: Based on the preset power battery terminal voltage, the preset DC bus capacitance value, and the DC bus voltage reference value, determine the nominal compensation coefficient in the bus voltage dynamic model; S203: Based on the bus voltage dynamic model and the nominal compensation coefficient, the total system disturbance is expanded into state variables, and a total disturbance observation model is constructed based on the state variables; S204: Set the error dynamic characteristic polynomial of the total disturbance observation model to a double-pole form, and determine the first observer gain and the second observer gain; S205: Obtain the historical total disturbance observation status, and determine the DC bus voltage observation error based on the historical total disturbance observation status and the real-time value of the DC bus voltage, and generate a first state correction amount and a second state correction amount based on the first observer gain and the second observer gain. S206: Based on the first state correction amount, the second state correction amount, the nominal compensation coefficient, and the historical total disturbance observation state, the forward Euler method is used to discretely update the DC bus voltage estimation state and the total disturbance estimation state in the total disturbance observation model to obtain the total disturbance estimation value.

7. The series hybrid bus voltage linear active disturbance rejection control method according to claim 1, characterized in that, S3 specifically includes: S301: Calculate the DC bus voltage control deviation based on the real-time value of the DC bus voltage and the reference value of the DC bus voltage; S302: Based on the DC bus voltage control deviation, the proportional feedback quantity is calculated through the linear error feedback loop; S303: Based on the total disturbance estimate, the proportional feedback quantity is subjected to disturbance feedforward compensation to obtain the voltage outer loop control quantity; S304: Use the voltage outer loop control quantity as the inductor current reference value of the current inner loop of the bidirectional DC / DC converter.

8. The series hybrid bus voltage linear active disturbance rejection control method according to claim 1, characterized in that, S4 specifically includes: S401: Calculate the inductor current deviation based on the inductor current reference value and the inductor current real-time value; S402: Perform a proportional calculation on the inductor current deviation to obtain a proportional control component; S403: Perform an integral calculation on the inductor current deviation to obtain the integral control component; S404: Based on the proportional control component and the integral control component, the duty cycle control signal is generated by the PI controller.

9. The series hybrid bus voltage linear active disturbance rejection control method according to claim 1, characterized in that, S5 specifically includes: S501: Compare the duty cycle control signal with the preset carrier signal to generate a pulse width modulation drive signal; S502: Control the bidirectional DC / DC converter according to the pulse width modulation drive signal to adjust the bus voltage.

10. A series hybrid bus voltage linear active disturbance rejection control system, characterized in that, include: processor; A memory storing computer-readable instructions, which, when executed by the processor, implement the series hybrid bus voltage linear active disturbance rejection control method as described in any one of claims 1 to 8.

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