Feed-forward driving device with hardware bypass and energy storage cut-in

Abstract

The application relates to the field of motor drive protection, and provides a feedforward drive device with hardware bypass and energy storage cut-in, which comprises a main control microprocessor, a backup capacitor group, an electronic switch, a feedforward sensing module, a logic gate, a driver, a motor, a top layer control and energy storage substrate, a middle layer hardware interception substrate, a bottom layer power execution substrate, a support column and a bus. The device adopts an isolation layout of top layer control and energy storage, middle layer hardware interception and bottom layer power execution, the main control and the middle layer logic gate are vertically aligned in the Z axis to realize straight-through wiring, and the feedforward module integrates a pure hardware resistance-capacitance differential and a hysteresis resistance network. The feedforward module extracts the bus voltage transient change rate in real time, when the drop exceeds the limit, the hard-wired homologous branch triggers the middle layer logic gate in the same microsecond to forcibly mask the PWM instruction to cut off the load, and the electronic switch is turned on to cut in the backup capacitor for power supply. The application is independently operated in a pure physical mode, solves the problems of main control crash and switch oscillation caused by extreme load shedding, and maintains the continuity of the control timing.

Description

Technical Field

[0001] This invention relates to the field of mechatronics and motor drive control and protection, specifically to a motor feedforward drive device with hardware bypass interception and energy storage input. Background Technology

[0002] With the development of new energy technologies, microgrid power supply systems (such as solar-powered vehicles and miniature inspection equipment) are playing an increasingly important role in highly dynamic mobile devices worldwide. In these devices, the stability of the motor drive system is crucial for ensuring safe operation. To improve motor control accuracy, researchers are constantly exploring purely digital closed-loop control technologies, such as ADC sampling based on microcontrollers (MCUs) and software PID control. These technologies have achieved significant results under steady-state conditions, but still have certain limitations. For example, they are severely inadequate in handling sudden voltage fluctuations on the power supply bus when facing extreme environments such as sudden changes in light intensity or instantaneous load stall.

[0003] In recent years, software fault-tolerant and anomaly handling algorithms have been increasingly widely used in motor control. By incorporating logic parameters such as voltage threshold monitoring and interrupt protection into the code, intelligent operation management support is provided for electromechanical equipment. These digital logics can collect a large amount of sensor sampling data, helping the main control system to better understand the real-time status of the motor, thereby attempting to implement protection strategies such as shutdown or derating when voltage anomalies occur.

[0004] Currently, there are many similar digital control systems on the market, such as motor drivers based on various mainstream microcontrollers. These controllers typically rely on polling sampling to trigger software interrupts and modify the PWM register through preset calculation and comparison logic, then control high-power loads through the drive bridge. By flexibly adjusting the code and threshold strategies, these systems can, to some extent, avoid conventional overload damage and achieve closed-loop control.

[0005] However, these existing technologies still suffer from severe sampling and execution latency issues. The response speed of the software code often cannot keep up with the microsecond-level drop in bus voltage, leading to delayed failure of protection measures. Furthermore, the existing equipment's main control unit (low-voltage) and high-power load (high-voltage) lack underlying physical isolation and energy buffering. In the event of a sudden load withdrawal, it is highly susceptible to triggering a power-off reset (BOR) crash in the microcontroller, or even causing the drive transistor to burn out due to high-frequency oscillation. Therefore, developing a low-level hardware-level protection system capable of adapting to sudden changes in operating conditions, responding to voltage anomalies in real time, and maintaining the health of the main control unit has become an important direction for improving the reliability of equipment in highly dynamic environments. Summary of the Invention

[0006] This invention provides a feedforward drive device with hardware bypass and energy storage integration and its control method, which solves the problems of actuator control failure due to voltage fluctuations and main control unit easy power failure and crash in high dynamic power environment, and achieves microsecond-level physical protection without software intervention and uninterrupted power supply to the main control unit.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] A feedforward drive device with hardware bypass and energy storage integration includes a main control microprocessor (1), a backup capacitor bank (2), an electronic switch (3), a feedforward sensing module (4), a logic gate (5), a motor shaft (6), a driver (7), a motor (8), a top-level control and energy storage board (9), a middle-level hardware interception board (10), a bottom-level power execution board (11), a support column (12), and a busbar (13).

[0009] Preferably, the feedforward drive device adopts a three-layer spatial isolation layout in terms of physical structure, including a top-layer control and energy storage substrate (9), a middle-layer hardware interception substrate (10), and a bottom-layer power execution substrate (11) arranged in parallel from top to bottom; the substrates are fixedly connected to each other by support columns (12) distributed on the periphery.

[0010] The specific spatial layout and connection relationships of each substrate layer are as follows:

[0011] The top-level control and energy storage substrate (9) has a cylindrical spare capacitor bank (2) arranged side by side on the left edge of its upper surface, and a main control microprocessor (1) arranged in the central area on the right side. An electronic switch (3) is arranged in the space between the spare capacitor bank (2) and the main control microprocessor (1). All the above electronic components are fixedly connected by surface mount technology (SMT) or lead soldering to achieve the shortest electrical connection for energy input.

[0012] The middle layer hardware interception substrate (10) has a feedforward sensing module (4) and a logic gate (5) on its upper surface through a welding process. The feedforward sensing module (4) is arranged near the left busbar (13) input end; the logic gate (5) is arranged on the right side of the substrate and is precisely located directly below the top layer main control microprocessor (1).

[0013] The bottom power execution substrate (11) has a driver (7) and a motor (8) on its upper surface. The driver (7) is arranged in the middle of the substrate by welding and is precisely located directly below the middle logic gate (5). The motor (8) is horizontally fixed to the right side of the substrate by mechanical fasteners such as bolts. Its motor shaft (6) extends horizontally outward from the edge of the substrate, and the power lead of the motor (8) is electrically connected to the driver (7) through a high current terminal.

[0014] Spatial wiring for bus (13): Bus (13) is introduced from the left side of the device and is divided into two spatial branches as it extends into the device. One branch extends downward and is directly connected to the driver (7) of the bottom power execution board (11) to deliver high-power main drive energy; the other branch extends horizontally and is connected to the feedforward sensing module (4) of the middle hardware interception board (10) to provide real-time bus voltage sampling signals.

[0015] Z-axis vertical alignment: The main control microprocessor (1) and the logic gate (5) are vertically aligned on the spatial Z-axis. This three-dimensional spatial layout allows the instruction wires from the top layer and the interception wires from the middle layer to use vertical pin header connectors or through-hole rigid wires. This vertical alignment design allows the PWM instruction transmission hard line to penetrate the top and middle layers vertically in a straight line without turning, shortening the signal delay and establishing a direct truncation structure of the middle layer logic gate (5) on the top layer PWM signal in the physical topology.

[0016] Through the above three-layer suspended structure design, the vertical physical space isolation between the weak current control unit (i.e., the main control microprocessor 1 located at the top layer and the feedforward sensing module 4 and logic gate 5 in the middle layer) and the strong current execution unit (i.e., the driver 7 and motor 8 located at the bottom layer) is realized, which effectively reduces the crosstalk of the strong electromagnetic field to the weak current sampling signal and effectively reduces the electromagnetic interference when the motor (8) is running at high power; at the same time, this spatial layout enables the control command wires and hardware interception wires between the functional modules (specifically including the main control microprocessor 1, logic gate 5, driver 7 and electronic switch 3) to achieve the shortest path wiring through Z-axis alignment and penetration.

[0017] Preferably, the intercept signal output terminal of the comparison submodule is provided with a hard-wired homogeneous branch structure. One end of the branch wire is horizontally connected to the input terminal of the lower-level logic gate (5) in the middle layer, and the other end is vertically connected to the control terminal of the electronic switch (3) in the top layer. By adopting the above homogeneous branch structure, in the same microsecond when the comparison submodule outputs a low-level intercept signal, a synchronous and coordinated physical response of unloading and reconnection can be achieved: on the one hand, the lower-level logic gate (5) is driven to forcibly mask the PWM instruction to realize the physical unloading of the high-power load; on the other hand, the electronic switch (3) is turned on by homogeneous triggering.

[0018] Preferably, the backup capacitor bank (2) is connected to the power supply input terminal of the main control microprocessor (1) via the electronic switch (3). Through the above-mentioned co-current triggering mechanism, the electronic switch (3) is hardware-triggered to conduct at the same time as the load is cut off, so that the backup capacitor bank (2) is connected to the power supply circuit of the main control microprocessor (1). This hard-wired co-current triggering design realizes hardware-level synchronization between load bypass disconnection and backup energy storage access, ensuring the continuous power supply of the main control microprocessor (1) during the bus voltage instantaneous drop, avoiding power failure and reset, thereby maintaining the continuity of the system context state.

[0019] Preferably, the feedforward sensing module (4) integrates a purely analog RC differential network and a comparator submodule. The RC differential network is constructed from physical capacitors and physical resistors mounted on the middle layer hardware interception substrate (10), and is used to physically extract the bus voltage (V) in real time. bus The transient rate of change (dv / dt) of the sensor is measured. The hysteresis resistor network surrounding the comparator submodule is also a physical component, consisting of a feedback voltage divider circuit connected between the pins of the high-speed hardware comparator. Specifically, the RC differential network is constructed from physical capacitors and resistors mounted inside the feedforward sensing module, used for real-time physical extraction of the bus voltage (V). bus The transient rate of change (dv / dt) of the comparator; the comparison submodule also serves as an internal unit of the feedforward sensing module (4), containing a high-speed hardware comparator, and a hysteresis resistor network (composed of feedback voltage divider physical resistors) is soldered around the pins of the comparator. The above hardware network operates independently from the software control of the main microprocessor (1). The working mechanism of the hysteresis resistor network is as follows: at time t0, the instantaneous trigger comparator output (COMP) is triggered. OUT The gate signal flips to a low level and is sent to the motor's PWM signal. OUT The load was immediately intercepted. After the load was disconnected, the bus voltage (V) was... bus The voltage naturally rebounds; to prevent voltage fluctuations at the critical point from causing the comparator state to erroneously flip, the hysteresis resistor network is configured with a fixed hysteresis upper limit (V) in the circuit. H When the bus voltage rises to the upper hysteresis limit (V) H During the hardware interception period (t0 to t1) prior to this, the network continuously locks the comparator output to a low level; until time t1, the bus voltage crosses the hysteresis limit (V). H When the comparator hysteresis releases and resumes high-level output, the underlying logic gates then re-release the PWM signal, achieving seamless drive recovery. Attached Figure Description

[0020] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1 This is a three-dimensional structural diagram of the feedforward drive device of the present invention;

[0022] Figure 2 This is a front view of the feedforward drive device of the present invention;

[0023] Figure 3 This is a side view of the feedforward drive device of the present invention;

[0024] Figure 4 This is a top view of the feedforward drive device of the present invention;

[0025] Figure 5 This is a timing diagram of the transient voltage waveform at a key node of the present invention.

[0026] In the diagram: 1. Main control microprocessor; 2. Backup capacitor bank; 3. Electronic switch; 4. Feedforward sensing module; 5. Logic gate; 6. Motor shaft; 7. Driver; 8. Motor; 9. Top-level control and energy storage board; 10. Middle-level hardware interception board; 11. Bottom-level power execution board; 12. Support column; 13. Busbar. Detailed Implementation

[0027] Example 1: A feedforward drive device with hardware bypass and energy storage integration mainly consists of three parts: a control center, an interception and protection layer, and a power execution layer. Specifically, the device includes a main control microprocessor (1), a backup capacitor bank (2), an electronic switch (3), a feedforward sensing module (4), a logic gate (5), a motor shaft (6), a driver (7), a motor (8), a top-level control and energy storage board (9), a middle-level hardware interception board (10), a bottom-level power execution board (11), a support column (12), and a busbar (13).

[0028] In actual assembly, this equipment adopts a three-layer spatial isolation layout. From top to bottom, there are a top layer control and energy storage board (9), a middle layer hardware interception board (10), and a bottom layer power execution board (11). The periphery of each board is fixedly connected by an insulating support column (12). This three-layer suspended structure design realizes vertical physical isolation between the weak current control unit (top and middle layers) and the strong current execution unit (bottom layer) in a limited space, reducing electromagnetic interference generated when the motor (8) operates with high current. The specific spatial layout and connection relationship of each board are as follows: Three cylindrical spare capacitor groups (2) are mounted side by side on the left edge of the top layer control and energy storage board (9), and the main control microprocessor (1) is mounted on the right side. The electronic switch (3) is arranged between the two. The middle layer hardware interception board (10) also adopts SMT process, with the feedforward sensing module (4) arranged on the left side of the board to obtain the voltage fluctuation of the bus (13) nearby; the logic gate (5) is arranged on the right side of the board. A high-power driver (7) is welded to the middle of the bottom power actuation substrate (11). The motor (8) is horizontally fixed to the right side of the substrate by mechanical fasteners, and its motor shaft (6) extends horizontally outward from the edge of the substrate. The power lead of the motor (8) is electrically connected to the output terminal of the driver (7).

[0029] For the routing of the busbar (13), this device adopts a left-side suspended entry method. After entering the device, it is divided into two paths: the main branch extends to the lower right and connects to the driver (7) located in the middle of the bottom layer; the sampling branch is short-circuited to the feedforward sensing module (4) on the left side of the middle layer. In particular, on the spatial Z-axis, the main control microprocessor (1) of the top layer and the logic gate (5) of the middle layer are vertically aligned. This three-dimensional spatial layout breaks the conventional flying wire routing around the board, so that the PWM command line issued from the top layer can penetrate vertically downward in a straight line to the logic gate (5) of the middle layer. This constitutes a choke structure that directly cuts off the PWM command throat in the physical topology. When the logic gate (5) receives the low-level interception signal from the feedforward sensing module (4) on the left side and conducts it laterally along the substrate, it can cut off the command instantly in the middle layer, and then transfer the controlled signal to the driver (7) of the bottom layer.

[0030] The feedforward sensing module (4) is not a software module that relies on the code of the main microprocessor (1), but a pure analog hardware network built from physical surface-mount capacitors and resistors. It integrates a resistor-capacitor differential network and a comparator submodule containing a high-speed hardware comparator. The pins of the comparator are surrounded by a hysteresis voltage divider resistor network for setting the recovery dead zone. The output of the comparator submodule has a hard-wired homogeneous branch structure: one end is connected horizontally to the side input of the logic gate (5); the other end is vertically upward through the middle substrate and directly connected to the control electrode of the top electronic switch (3). The energy output of the spare capacitor bank (2) is directly connected in parallel to the side power supply pin of the main microprocessor (1) through the electronic switch (3).

[0031] To achieve co-triggered triggering of a single signal, this embodiment employs specific electrical polarity selection for the logic gate (5) and the electronic switch (3). Specifically, the logic gate (5) uses a dual-input AND gate chip, one end of which receives a normal PWM square wave from the main control microprocessor, and the other end (masking end) receives a signal from the feedforward sensing module; the electronic switch (3) uses a P-channel MOSFET (P-MOS).

[0032] Under normal operating conditions, the feedforward sensing module outputs a high level, the AND gate normally allows the PWM wave to pass, and the P-MOS transistor gate remains off at a high level. When a transient trigger interception occurs on the bus, the feedforward sensing module outputs a low-level interception signal (0). When this low level reaches the AND gate, since "0 AND any signal = 0", the PWM command is instantly forcibly masked, achieving shutdown and unloading. At the same time, this low level reaches the P-MOS transistor gate, which just meets the low-level conduction characteristic of the P-channel MOS transistor, instantly opening the energy storage circuit. Thus, a single low-level hardwire from the same source perfectly realizes the synchronous physical response of "turning off the high-voltage drive" and "turning on the low-voltage energy storage".

[0033] The specific working process of this embodiment is as follows: Under normal closed-loop driving conditions, the power supply of the bus (13) is stable. The high-frequency PWM square wave output by the main control microprocessor (1) passes smoothly through the conducting logic gate (5) and is sent to the driver (7) to control the operation of the motor (8). For example, in the high dynamic driving conditions of the solar car, when the motor (8) is suddenly overloaded and starts or encounters shading that causes the voltage of the bus (13) to drop transiently, the physical differential network inside the feedforward sensing module (4) instantly captures the abnormal dv / dt slope (such as Figure 5At time t0, the slope signal triggers the comparator to flip and output a low-level intercept signal. Based on the same branch structure, the signal performs two physical actions within the same microsecond: first, it triggers the middle logic gate (5) to forcibly mask and cut off the downward PWM command, forcing the motor (8) to stop and unload instantly; second, it synchronously turns on the top electronic switch (3), and the backup capacitor bank (2) instantly injects energy into the main control microprocessor (1) to maintain its power supply. After the high-power load is cut off, the bus voltage begins to rebound naturally. In order to prevent the voltage fluctuation during the rebound from causing system switch oscillation, the hardware hysteresis resistor network intervenes and locks the intercept signal in the interval from t0 to t1. The main control microprocessor (1) relies on the capacitor to continuously supply power throughout the intercept interval, avoiding power failure and reset. When the bus voltage recovers to the hysteresis safety limit (V) at time t1, H After that, the comparator is physically reset, and logic gate (5) re-issues the PWM instruction. Since the main control microprocessor (1) maintains the continuity of control timing and running data, the system is able to smoothly return to the normal closed-loop drive state.

[0034] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as defined by the appended claims and their equivalents.

Claims

1. A feedforward drive device with hardware bypass and energy storage integration, characterized in that: The device includes a main control microprocessor (1), a backup capacitor bank (2), an electronic switch (3), a feedforward sensing module (4), a logic gate (5), a motor shaft (6), a driver (7), a motor (8), a top-level control and energy storage board (9), a middle-level hardware interception board (10), a bottom-level power execution board (11), a support column (12), and a busbar (13). The device has the following electrical topology connections: the PWM of the main control microprocessor (1) The signal output terminal is electrically connected to the signal input terminal of the logic gate (5), the signal output terminal of the logic gate (5) is connected to the control input terminal of the driver (7), and the power output terminal of the driver (7) is connected to the motor (8); the bus (13) is electrically connected to the power input terminal of the bottom driver (7) and the voltage sampling terminal of the middle feedforward sensing module (4) respectively; the feedforward sensing module (4) has an interception signal output terminal, which is electrically connected to the masking terminal of the logic gate (5) and the control terminal of the electronic switch (3) through the same branch pipeline; the spare capacitor bank (2) is connected to the power supply terminal of the main control microprocessor (1) through the electronic switch (3); the device adopts a three-layer spatial isolation layout in physical structure: The top-level control and energy storage substrate (9), the middle-level hardware interception substrate (10), and the bottom-level power execution substrate (11) are arranged in parallel from top to bottom. Each substrate is fixedly connected by support columns (12) distributed around the perimeter. The top-level control and energy storage substrate (9) is equipped with the spare capacitor bank (2), the main control microprocessor (1), and the electronic switch (3). The middle-level hardware interception substrate (10) is equipped with the feedforward sensing module (4) and the logic gate (5). The bottom-level power execution substrate (11) is equipped with the driver (7) and the motor (8), thereby realizing the physical isolation between the weak current control unit and the strong current execution unit.

2. The feedforward drive device with hardware bypass and energy storage integration according to claim 1, characterized in that: A spare capacitor bank (2) is arranged side by side on the left edge of the upper surface of the top control and energy storage substrate (9), a main control microprocessor (1) is arranged in the right area, and an electronic switch (3) is arranged between the two; the motor (8) is horizontally fixed on the right side of the bottom power execution substrate (11), and its motor shaft (6) extends horizontally outward from the edge of the substrate.

3. The feedforward drive device with hardware bypass and energy storage integration according to claim 1, characterized in that: The main control microprocessor (1) and the logic gate (5) are vertically aligned on the Z-axis in space. This vertical alignment design enables the transmission hard line of the PWM signal to penetrate the top and middle layers vertically in a straight line, establishing the physical structure of the middle layer logic gate (5) directly truncating the top layer PWM signal.

4. The feedforward drive device with hardware bypass and energy storage integration according to claim 1, characterized in that: The bus (13) is introduced from the left side of the device and then splits into two spatial branches; the main branch extends to the lower right and connects to the driver (7) located in the middle of the bottom layer; the sampling branch is short-circuited to the feedforward sensing module (4) located on the left side of the middle layer.

5. A feedforward drive device with hardware bypass and energy storage integration according to claim 1, characterized in that: The feedforward sensing module (4) integrates a resistor-capacitor differential network composed of physical capacitors and physical resistors, as well as a comparator submodule containing a high-speed hardware comparator. The above network and module constitute a purely physical hardware analog circuit, which is used to directly extract the transient rate of change of the bus voltage and output the level signal without going through the main control microprocessor (1).

6. A feedforward drive device with hardware bypass and energy storage integration according to claim 5, characterized in that: The high-speed hardware comparator pins are surrounded by a hysteresis resistor network consisting of feedback voltage divider physical resistors; the hysteresis resistor network is used to build a fixed hysteresis upper limit during the bus voltage recovery phase, locking the output state of the comparator submodule to prevent switching oscillation.

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