A decoding error correction circuit and method

Abstract

The application discloses a decoding error correction circuit and method, comprising: a differential signal detection module for comparing the voltage difference between the first and second nodes with a preset offset voltage and outputting a differential detection signal; a dynamic threshold adjustment module for dynamically adjusting the comparison threshold according to the level state of the first decoding signal; a glitch signal filtering and pulse width reduction module for charging or discharging the timing capacitor according to the level of the first decoding signal, and comparing with a preset reference voltage to filter out the glitch signal with a pulse width less than a preset time length, and reducing the pulse width of the normal communication signal with a pulse width not less than the preset time length. The application effectively filters out bus oscillation interference, and has simple circuit structure, low cost, adaptive communication rate and wide application range.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically to a decoding and error correction circuit and method. Background Technology

[0002] In fields such as air conditioning, security, and smart homes, communication between the host and slave units mostly adopts the HBS (HomeBUS) communication protocol. This protocol has advantages such as supporting twisted-pair cables for both communication and power supply; that is, the twisted-pair cable can be used for both communication and power supply to downstream devices, and it supports non-polarity connections; it also greatly facilitates on-site construction and installation. Taking the central air conditioning field as an example, in large shopping malls or office buildings, typically one outdoor unit connects to multiple indoor units, with a maximum of 64 indoor units. When two outdoor units are networked, it connects two outdoor units to 128 indoor units, with a distance generally exceeding 1000 meters. This places high demands on the communication chip because the large number of communication nodes, long communication distances, and the mixing of communication lines with power lines result in large parasitic parameters on the communication bus, making it susceptible to interference from power lines. If the communication chip misinterprets the interference on the bus and outputs a signal with interference spikes to the MCU, and the MCU cannot identify the interference signal, it will lead to a high communication error rate or even communication failure.

[0003] In existing HBS communication solutions, some glitches can be filtered out by adding an RC filter circuit to the DATA OUT pin of the decoding port. However, this involves many external components, a complex circuit structure, and can cause DATA OUT pulse width distortion, thus limiting its application.

[0004] Due to the long distance and large number of nodes on the communication bus, the parasitic parameters on the bus are large. The HBS protocol has unique characteristics: the communication chip uses a 5V power supply; the transmitted signal has a high level of "5V", a middle level of "2.5V", and a low level of "0V"; both signal transmission and reception are capacitively coupled, so the signal amplitude transmitted to the bus becomes a high level of "2.5V", a middle level of "0V", and a low level of "-2.5V". A polling naming mechanism is used, allowing only named devices to send signals; signals are differentially coupled to the bus via capacitive coupling; internal units that do not send signals will change the DATA IN of the communication chip. When a pin is set high, the output level of the two pins that are sending signals is set to 2.5V. In order not to affect the signal transmission of other devices, this 2.5V signal has no driving capability (if it had driving capability, the bus signal could not be set high or low by other internal units, and normal communication would not be possible). The high level "5V" is pulled up by the power transistor and has driving capability, and the low level "0V" is pulled down by the power transistor and has driving capability. When the differential signal on the bus drops from a high level to an intermediate level, or rises from a low level to an intermediate level, it has no driving capability. The bus voltage difference is set to 0 by the built-in KΩ level resistor. At this time, it will form RC oscillation with the parasitic capacitance on the bus, causing glitches in the bus waveform, chip misinterpretation, and communication abnormalities.

[0005] When the indoor unit's fan is working, the motor will generate glitch interference, which will be coupled to the communication bus. Alternatively, when the outdoor unit's compressor is working, it will couple interference to the bus through the power line. At this time, regardless of whether there is a signal on the bus, this interference will be superimposed on the bus, causing the decoding chip to misunderstand the code and resulting in communication abnormalities.

[0006] Existing solutions, such as adding an RC filter circuit (composed of resistors, capacitors, transistors, and diodes) to the DATA OUT pin, suffer from high cost, complex external circuitry, and unsatisfactory performance, resulting in significant application limitations. Common software-based remedial strategies involve retransmitting signals if communication failure is caused by interference, leading to a high error rate; persistent bus interference can also cause communication failure. Common solutions include reducing the number of communication nodes and adjusting the communication line wiring, but these require strict on-site installation and limit application areas. Summary of the Invention

[0007] The purpose of this invention is to provide a decoding error correction circuit and method, which adds decoding error correction function to the existing communication chip, restores the bus interference glitches and mis-coded signals caused by the above problems to the normal signal, keeps the signal pulse width unchanged, filters out interference glitches, and improves communication quality.

[0008] To achieve the above technical objectives, the present invention provides a decoding error correction circuit for decoding signals on a differential bus. The circuit comprises: a differential signal detection module that compares the voltage difference between the differential communication buses with a preset offset voltage and outputs a differential detection signal accordingly; a decoding signal output module that outputs a first decoding signal based on the differential detection signal; a dynamic threshold adjustment module that dynamically adjusts the comparison threshold of the differential signal detection module based on the level of the first decoding signal; a glitch signal filtering and pulse width restoration module that charges or discharges a timing capacitor based on the level of the first decoding signal and compares the capacitor voltage of the timing capacitor with a preset reference voltage; and a data output module that outputs a low-level data output signal when the capacitor voltage is greater than the reference voltage and outputs a high-level data output signal when the capacitor voltage is less than the reference voltage.

[0009] This invention provides a decoding error correction circuit that automatically adjusts the threshold of the decoding circuit through a dynamic threshold adjustment circuit. When the decoding module outputs a high level for the first time, the threshold is automatically increased. This has the advantage of shielding the RC oscillation when the differential signal transitions from a high or low level to an intermediate level. After the first low level output, the threshold voltage is automatically decreased, achieving dynamic balance.

[0010] As a further improvement, the dynamic threshold adjustment module is connected to the differential signal detection module to increase the comparison threshold after the first decoded signal flips from low to high; and to decrease the comparison threshold after the first decoded signal flips from high to low; the decoded signal output module is connected to the output terminal of the differential signal detection module, the glitch signal filtering and pulse width restoration module is connected to the decoded signal output module to filter out glitch signals with a pulse width less than a preset duration, and to restore the pulse width of normal communication signals with a pulse width not less than the preset duration; the data output module is connected to the glitch signal filtering and pulse width restoration module.

[0011] As a further improvement, the differential signal detection module includes a seventh resistor between the first input terminal and the second input terminal for setting the offset voltage; the first input terminal and the second input terminal are respectively connected to the differential communication bus via a DC blocking capacitor and an attenuation resistor; when the absolute value of the voltage difference between the first node and the second node is less than the offset voltage, the voltages of the first output terminal and the second output terminal are equal, and the decoding signal output module outputs a high-level first decoding signal; when the absolute value of the voltage difference is greater than the offset voltage, one of the voltages of the first and second output terminals increases and the other decreases, the voltage of the first output terminal is higher than the threshold voltage provided by the dynamic threshold adjustment module, and the decoding signal output module outputs a low-level first decoding signal.

[0012] As a further improvement, the dynamic threshold adjustment module includes an eighth resistor, a first current source, and a second current source. When the control signal is high, the second current source is set to zero, and the current flowing through the eighth resistor is the current of the first current source. The voltage divider point voltage of the dynamic threshold adjustment module is the power supply voltage minus the product of the current of the first current source and the eighth resistor. When the control signal is low, the current of the second current source flows through the switching transistor, and the current flowing through the eighth resistor decreases to the difference between the current of the first current source and the current of the second current source. The voltage divider point voltage is the power supply voltage minus the product of the current difference and the eighth resistor. The threshold voltage output by the dynamic threshold adjustment module is the voltage divider point voltage minus the base-emitter voltage of the transistor. The level of the control signal follows the changes in the data output signal.

[0013] As a further improvement, the glitch signal filtering and pulse width restoration module includes the timing capacitor, the charging current source, the discharging current source, the first switching transistor, the second switching transistor, and the first comparator; the current of the charging current source, the current of the discharging current source, and the current of the bias current source are equal, and the current of the bias current source is adjusted by an external resistor; the voltages of the first reference voltage source, the second reference voltage source, and the third reference voltage source are equal.

[0014] As a further improvement, when the first decoding signal is low, the first switch is turned on and the second switch is turned off, and the charging current source charges the timing capacitor; when the first decoding signal is high, the second switch is turned on and the first switch is turned off, and the discharging current source discharges the timing capacitor; the reference voltage is half the voltage of the first reference voltage source; the preset duration is the time required for the timing capacitor to charge from zero voltage to the reference voltage, and the preset duration is determined by the capacitance value of the timing capacitor and the current value of the charging current source; and the preset duration is not greater than half the pulse width of the normal communication signal.

[0015] As a further improvement, when a glitch signal appears on the differential communication bus and the low-level pulse width of the first decoded signal caused by the glitch signal is less than the preset duration, the capacitor voltage is less than the reference voltage, and the data output module maintains the output of the data output signal at a high level to filter out the glitch signal.

[0016] As a further improvement, when a glitch signal appears on the differential communication bus, and when the first decoded signal is a normal low-level communication signal, the data output module outputs a high-level data output signal within the preset duration. After the preset duration, when the capacitor voltage is greater than the reference voltage, the data output module outputs a low-level data output signal. After the first decoded signal returns to a high level, the discharge current source discharges the timing capacitor, and the data output module maintains the output of a low-level data output signal during the period when the capacitor voltage is greater than the reference voltage, in order to compensate for the filtered low-level pulse width.

[0017] As a further improvement, the glitch signal filtering and pulse width restoration module also includes a charging limiting module, which includes a second comparator and a current limiting switch. When the capacitor voltage reaches the voltage of the second reference voltage source, the second comparator outputs a high-level signal and controls the current limiting switch to set the current of the charging current source to zero, stopping the charging of the timing capacitor. When the capacitor voltage is lower than the voltage of the second reference voltage source, the current limiting switch does not work, and the charging and discharging of the timing capacitor is determined by the first decoded signal.

[0018] As a further improvement, the differential communication bus is a communication bus using the Home Bus communication protocol, the decoding and error correction circuit is integrated into the communication chip, and the communication chip also includes an external pin, which is used to connect an adjustable resistor in parallel with the external resistor, so as to adjust the preset duration by adjusting the current of the bias current source.

[0019] Accordingly, this application also provides a decoding error correction method, comprising the following steps: detecting the voltage difference between a first node and a second node on a differential communication bus, comparing the voltage difference with a preset offset voltage, and outputting a differential detection signal; outputting a first decoding signal based on the differential detection signal, and dynamically adjusting the comparison threshold based on the level state of the first decoding signal to filter out interference glitches with amplitudes smaller than normal signals; charging or discharging a timing capacitor based on the level of the first decoding signal to obtain the capacitor voltage of the timing capacitor; comparing the capacitor voltage with a preset reference voltage to filter out glitches with pulse widths smaller than a preset duration, and restoring the pulse width of normal communication signals with pulse widths not less than the preset duration; outputting a low-level data output signal when the capacitor voltage is greater than the reference voltage, and outputting a high-level data output signal when the capacitor voltage is less than the reference voltage.

[0020] As a further improvement, the step of dynamically adjusting the comparison threshold includes: increasing the comparison threshold after the first decoded signal flips from low to high; decreasing the comparison threshold after the first decoded signal flips from high to low; the reference voltage is half of the voltage of the first reference voltage source, and the preset duration is the time required for the timing capacitor to charge from zero voltage to the reference voltage; the preset duration is not greater than half of the pulse width of the normal communication signal; after the first decoded signal returns to high, the timing capacitor is discharged by a discharge current source, and the data output signal is maintained at a low level while the capacitor voltage is greater than the reference voltage, in order to compensate for the filtered low-level pulse width.

[0021] The circuit and method of this invention can filter out bus oscillation interference and coupled glitch interference (filter out low-level glitch of output signal OUT1, and ensure that the high-level pulse width of the final output signal DATA OUT is restored to the normal range), ensure that the signal is restored to normal, and realize the decoding and error correction function. Attached Figure Description

[0022] Figure 1 This is a circuit schematic diagram of the dynamic threshold adjustment module of the present invention; Figure 2 This is a circuit schematic diagram of the glitch signal filtering and pulse width restoration module of the present invention; Figure 3 A schematic diagram illustrating the changes in the decoded waveform caused by the oscillation of the parasitic capacitance bus waveform; Figure 4 A schematic diagram illustrating the changes in the decoded waveform caused by interference glitches on the bus during compressor operation; Figure 5 Schematic diagram when there are no parasitic parameters and no interference; Figure 6 Schematic diagram showing the oscillation of the OUT1 output signal caused by parasitic parameters; Figure 7 A schematic diagram showing interference spikes generated by compressors, fans, etc., coupled to a differential bus. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] like Figures 1 to 7As shown, this invention provides a decoding error correction circuit for decoding signals on a differential bus. It includes: a differential signal detection module, a dynamic threshold adjustment module, a decoded signal output module, a glitch signal filtering and pulse width restoration module, and a data output module. The first and second input terminals of the differential signal detection module are respectively connected to the first and second nodes of the differential communication bus. The differential signal detection module compares the voltage difference between the first and second nodes with a preset offset voltage and outputs a differential detection signal at its first and second output terminals based on the comparison result. The dynamic threshold adjustment module is connected to the differential signal detection module and dynamically adjusts the comparison threshold of the differential signal detection module according to the level state of the first decoded signal output by the decoded signal output module, so as to filter out glitches and restore the signal pulse width after the first decoded signal flips from low to high. The comparison threshold is increased; and it is used to decrease the comparison threshold after the first decoded signal flips from high level to low level; the decoded signal output module is connected to the output terminal of the differential signal detection module, and is used to output the first decoded signal according to the differential detection signal; the glitch signal filtering and pulse width restoration module is connected to the decoded signal output module, and is used to charge or discharge the timing capacitor according to the level of the first decoded signal, and compare the capacitor voltage of the timing capacitor with a preset reference voltage to filter out glitch signals with a pulse width less than a preset duration, and restore the pulse width of normal communication signals with a pulse width not less than the preset duration; the data output module is connected to the glitch signal filtering and pulse width restoration module, and is used to output a low-level data output signal when the capacitor voltage is greater than the reference voltage, and output a high-level data output signal when the capacitor voltage is less than the reference voltage.

[0025] This invention provides a decoding error correction circuit that automatically adjusts the threshold of the decoding circuit through a dynamic threshold adjustment circuit. When the decoding module outputs a high level for the first time, the threshold is automatically increased. This has the advantage of shielding the RC oscillation when the differential signal transitions from a high or low level to an intermediate level. After the first low level output, the threshold voltage is automatically decreased, achieving dynamic balance.

[0026] As a further improvement, the differential signal detection module includes a seventh resistor between the first input terminal and the second input terminal for setting the offset voltage; the first input terminal and the second input terminal are respectively connected to the differential communication bus via a DC blocking capacitor and an attenuation resistor; when the absolute value of the voltage difference between the first node and the second node is less than the offset voltage, the voltages of the first output terminal and the second output terminal are equal, and the decoding signal output module outputs a high-level first decoding signal; when the absolute value of the voltage difference is greater than the offset voltage, one of the voltages of the first and second output terminals increases and the other decreases (due to the non-polarized connection, the voltage of the first output terminal increases and the voltage of the second output terminal decreases, or the voltage of the second output terminal increases and the voltage of the first output terminal decreases), the voltage of the first output terminal is higher than the threshold voltage provided by the dynamic threshold adjustment module, and the decoding signal output module outputs a low-level first decoding signal.

[0027] As a further improvement, the dynamic threshold adjustment module includes an eighth resistor, a first current source, and a second current source. When the control signal is high, the second current source is set to zero, and the current flowing through the eighth resistor is the current of the first current source. The voltage divider point voltage of the dynamic threshold adjustment module is the power supply voltage minus the product of the current of the first current source and the eighth resistor. When the control signal is low, the current of the second current source flows through the switching transistor, and the current flowing through the eighth resistor decreases to the difference between the current of the first current source and the current of the second current source. The voltage divider point voltage is the power supply voltage minus the product of the current difference and the eighth resistor. The threshold voltage output by the dynamic threshold adjustment module is the voltage divider point voltage minus the base-emitter voltage of the transistor. The level of the control signal follows the changes in the data output signal.

[0028] As a further improvement, the glitch signal filtering and pulse width restoration module includes the timing capacitor, the charging current source, the discharging current source, the first switching transistor, the second switching transistor, and the first comparator; the current of the charging current source, the current of the discharging current source, and the current of the bias current source are equal, and the current of the bias current source is adjusted by an external resistor; the voltages of the first reference voltage source, the second reference voltage source, and the third reference voltage source are equal.

[0029] As a further improvement, when the first decoding signal is low, the first switch is turned on and the second switch is turned off, and the charging current source charges the timing capacitor; when the first decoding signal is high, the second switch is turned on and the first switch is turned off, and the discharging current source discharges the timing capacitor; the reference voltage is half the voltage of the first reference voltage source; the preset duration is the time required for the timing capacitor to charge from zero voltage to the reference voltage, and the preset duration is determined by the capacitance value of the timing capacitor and the current value of the charging current source; and the preset duration is not greater than half the pulse width of the normal communication signal.

[0030] As a further improvement, when a glitch signal appears on the differential communication bus and the low-level pulse width of the first decoded signal caused by the glitch signal is less than the preset duration, the capacitor voltage is less than the reference voltage, and the data output module maintains the output of the data output signal at a high level to filter out the glitch signal.

[0031] As a further improvement, when a glitch signal appears on the differential communication bus, and when the first decoded signal is a normal low-level communication signal, the data output module outputs a high-level data output signal within the preset duration. After the preset duration, when the capacitor voltage is greater than the reference voltage, the data output module outputs a low-level data output signal. After the first decoded signal returns to a high level, the discharge current source discharges the timing capacitor, and the data output module maintains the output of a low-level data output signal during the period when the capacitor voltage is greater than the reference voltage, in order to compensate for the filtered low-level pulse width.

[0032] As a further improvement, the glitch signal filtering and pulse width restoration module also includes a charging limiting module, which includes a second comparator and a current limiting switch. When the capacitor voltage reaches the voltage of the second reference voltage source, the second comparator outputs a high-level signal and controls the current limiting switch to set the current of the charging current source to zero, stopping the charging of the timing capacitor. When the capacitor voltage is lower than the voltage of the second reference voltage source, the current limiting switch does not work, and the charging and discharging of the timing capacitor is determined by the first decoded signal.

[0033] As a further improvement, the differential communication bus is a communication bus using the Home Bus communication protocol, the decoding and error correction circuit is integrated into the communication chip, and the communication chip also includes an external pin, which is used to connect an adjustable resistor in parallel with the external resistor, so as to adjust the preset duration by adjusting the current of the bias current source.

[0034] Accordingly, this application also provides a decoding error correction method, comprising the following steps: detecting the voltage difference between a first node and a second node on a differential communication bus, comparing the voltage difference with a preset offset voltage, and outputting a differential detection signal; outputting a first decoding signal based on the differential detection signal, and dynamically adjusting the comparison threshold based on the level state of the first decoding signal to filter out interference glitches with amplitudes smaller than normal signals; charging or discharging a timing capacitor based on the level of the first decoding signal to obtain the capacitor voltage of the timing capacitor; comparing the capacitor voltage with a preset reference voltage to filter out glitches with pulse widths smaller than a preset duration, and restoring the pulse width of normal communication signals with pulse widths not less than the preset duration; outputting a low-level data output signal when the capacitor voltage is greater than the reference voltage, and outputting a high-level data output signal when the capacitor voltage is less than the reference voltage.

[0035] In the technical solution of the present invention, dynamic threshold adjustment filters out interference spikes with amplitudes smaller than normal signals; the spike signal filtering and signal restoration module filters out interference with amplitudes close to or exceeding normal signals.

[0036] As a further improvement, the step of dynamically adjusting the comparison threshold includes: increasing the comparison threshold after the first decoded signal flips from low to high; decreasing the comparison threshold after the first decoded signal flips from high to low; the reference voltage is half of the voltage of the first reference voltage source, and the preset duration is the time required for the timing capacitor to charge from zero voltage to the reference voltage; the preset duration is not greater than half of the pulse width of the normal communication signal; after the first decoded signal returns to high, the timing capacitor is discharged by a discharge current source, and the data output signal is maintained at a low level while the capacitor voltage is greater than the reference voltage, in order to compensate for the filtered low-level pulse width.

[0037] The circuit and method of this invention can filter out bus oscillation interference and coupled glitch interference (filter out low-level glitch of output signal OUT1, and ensure that the high-level pulse width of the final output signal DATA OUT is restored to the normal range), ensure that the signal is restored to normal, and realize the decoding and error correction function.

[0038] In a preferred embodiment, the decoding error correction function circuit and method provided by the present invention can filter out interference spikes generated by RC oscillation on the bus or interference spikes generated when the compressor is working, without affecting the pulse width after decoding. It has the advantages of high fidelity, adaptive communication rate, no impact on communication efficiency, ability to filter out spike interference of different pulse widths, and wide applicability, thereby improving communication quality and reducing the difficulty of on-site construction wiring.

[0039] Background information: Communication module based on HBS protocol: When the chip sends a low level "0", the amplitude of the differential signal on the bus is high "+5V or -5V", with +5V and -5V alternating; when the chip sends a high level "1", the amplitude of the differential signal on the bus is "0V", defined as the intermediate level; therefore, when the decoding module detects that the amplitude of the differential signal on the bus is greater than a certain value, it outputs a low level "0", and when the amplitude of the differential signal is less than a certain value, it outputs a high level "1".

[0040] The circuit and method provided by this invention automatically adjust the threshold of the decoding circuit through a dynamic threshold adjustment circuit. When the decoding module outputs a high level for the first time, the threshold is automatically increased. This has the advantage of shielding the RC oscillation when the differential signal transitions from a high or low level to an intermediate level. After the first low level output, the threshold voltage is automatically decreased to achieve dynamic balance. As mentioned above, since the differential signal on the bus is "0V" when it transitions to the intermediate level (those skilled in the art will understand that the intermediate level of the amplitude of the bus differential signal is defined as "0V", and the logic low level output by the decoding module is defined as "0"), it has no driving capability and the level cannot quickly drop from high to 0V. Due to the parasitic capacitance on the bus, there will be RC damped oscillation during the transition. However, the amplitude of the oscillation is lower than the signal. If no processing is done, this oscillation will be decoded, causing the decoded signal to oscillate. Figure 3 When the dynamic threshold is automatically increased, if the oscillation amplitude is less than the decoding threshold, the decoding module will not output a low level "0" incorrectly.

[0041] Because these oscillations follow a certain pattern, occurring during the transition of the differential signal to the intermediate level, and because the driving capability is relatively strong when the differential signal changes from the intermediate level to +5V or -5V, oscillations will not occur. The dynamic threshold adjustment circuit raises the threshold when the decoding module outputs a high value for the first time, and restores the threshold to normal after the output goes low, thereby shielding oscillation glitches on the bus.

[0042] Module for glitch signal filtering and pulse width restoration (reference) Figure 2This system can effectively filter out voltage spikes on bus signals caused by electromagnetic interference from equipment such as fans and compressors. Since these spikes are also differential signals with amplitudes close to or higher than normal communication signals, they cannot be filtered out by a dynamic threshold adjustment circuit. However, these spike signals have a significant characteristic: their pulse width is usually quite narrow, much smaller than the communication signal pulse width. Therefore, a spike signal filtering module can effectively filter out this type of interference. However, the spike filtering module cannot distinguish between interference and useful signals; it filters them all according to a preset program. Without intervention, this can cause changes in the pulse width of normal communication signals (because they are filtered out by the spike filtering module). Therefore, a pulse width restoration signal is configured synchronously. This signal determines whether it is interference or a normal communication signal by detecting the pulse width. When the signal pulse width is below a certain value (defined as t1), it is considered interference and pulse width restoration is not performed. When the signal pulse width is greater than this value, it is considered a normal signal and pulse width restoration is performed. The signal pulse width is defined as t, and a reasonable definition of t1 ≤ 0.2t can filter out the aforementioned interference. The circuit of this invention can filter out bus oscillation interference and coupled glitch interference (filter out low-level glitch of output signal OUT1, and ensure that the high-level pulse width of the final output signal DATA OUT is restored to the normal range), ensuring that the signal is restored to normal and realizing the decoding and error correction function.

[0043] In a preferred embodiment of the present invention, such as Figure 1 The diagram shows the internal circuit connection of this dynamic threshold adjustment module, which mainly consists of three modules. STAGE1 is the differential signal detection module, with resistors R3=R4, R1=R2, R5=R6=R8, and R7 is the resistor for setting the offset voltage. IN1 and IN2 are connected to the bus through capacitors and attenuation resistors, so the voltage between IN1 and IN2 is less than 5V. The 2.5V power supply provides the reference source. R7 is used to set the offset voltage V1 of the comparator. When the voltage difference between IN1 and IN2 is less than V1, the voltages at the output terminals a and b of STAGE1 are equal, which is VDD-IS1. R5 is less than the voltages at points c and f (where c and f are equal), so comparator 1's port C and comparator 2 output low levels, and OUT1 outputs high levels. When the absolute value of the difference between IN1 and IN2 is greater than V1, taking the case where IN2 voltage is V1 greater than IN1 voltage, the emitter current of Q2 is large, and part of the current flows through R7 to the collector of Q3, so the current of Q1 decreases, that is, the voltage at port a increases, and the voltage at port b decreases; the voltage at point a increases, which is higher than the voltage at point e, so comparator 1's output C is high, and OUT1 outputs low levels.

[0044] STAGE2 is a dynamic threshold adjustment module. When QA is high, IS2 is pulled to 0, and the current flowing through R8 is IS1. At this time, the voltage at point g is VDD-IS1. When QA is low, IS2 flows through Q23, so the current flowing through R8 drops to IS1-IS2, and the voltage at point g increases to VDD-(IS1-IS2). R8. The voltage at points e and f = the voltage at point g - Vbe. The QA voltage follows the changes in DATA OUT, enabling dynamic adjustment of the voltages at e and f, thereby achieving the dynamic threshold adjustment function.

[0045] Since the voltages e and f are dynamically adjusted, which in turn affects the voltages a and b, according to the above calculation formula, the voltage difference between IN1 and IN2 also needs to be dynamically adjusted to ensure the voltage change of OUT1.

[0046] STAGE3 is the decoding signal output module, and its working principle is as described above.

[0047] like Figure 2 As shown, STAGE4 is the glitch signal filtering and pulse width restoration module. The IS3 current can be adjusted through resistor R21, IS3=IS4=IS5; voltage sources VREF1=VREF2=VREF0, and resistors R22=R23. The working principle is as follows: When OUT1 is low, the collector of Q34 is pulled low, so Q36 is turned off, and IS4=0; Q44 works normally, and the IS5 current charges capacitor C1, with the voltage across C1 denoted as VC. Similarly, when OUT1 is high, Q44 is turned off, Q36 works normally, and IS5 is 0, while the IS4 current discharges capacitor C1.

[0048] STAGE5 is the DATA OUT signal output module, which is the final output signal of the chip. Its working principle is that when the VC voltage is greater than VR, the DATA OUT outputs a low level, and when the VC voltage is lower than VR, the DATA OUT outputs a high level.

[0049] STAGE6 is a capacitor C1 charging limiting module. Its working principle is that when the charging voltage of capacitor C1 reaches VREF2, comparator OUT3 outputs a high-level signal, which controls Q58 to set IS5 to 0, and stops charging C1 (discharging is not affected). When the voltage of C1 is lower than VREF2, Q58 does not work, and the charging and discharging of C1 is determined by OUT1.

[0050] The three modules work together on the principle that VR voltage = 0.5. VREF1, C1 voltage is charged from 0 to 0.5. The time t1 required for VREF1 (this t1 is the same as the t1 mentioned earlier, and can be understood here as the time required to filter out the maximum glitch pulse width) is determined by the capacitance of C1 and the current of IS5. The capacitance of C1 is fixed, and IS5 can be adjusted by the resistor R21. That is, for the finished chip, a reserved pin is provided, and adjusting the resistance value of this pin to ground can adjust the current of IS5 and thus adjust the charging time t1 (which determines the maximum glitch pulse width that can be filtered out).

[0051] When a glitch signal appears on the differential bus, it passes through the IN1 and IN2 ports, causing OUT1 to erroneously output a low level. IS5 charges capacitor C1. As long as the pulse width of the glitch is less than t1, the VC voltage is less than VR, and the chip's final output signal DATAOUT is high, preventing a erroneous low-level output. After the glitch signal disappears, OUT1 outputs a normal high level, IS5 is reset to 0, and IS4 discharges C1 (since the high-level output time of OUT1 is greater than t1, the voltage of C1 can be discharged to 0V). DATAOUT still outputs a high level, thus filtering out the glitch signal.

[0052] For normal signals, the filtered low-level pulse width is compensated by setting VR voltage to 1 / 2 VREF1. The principle is as follows: When OUT1 outputs a low level (0V), DATA OUT outputs a high level within time t1. After time t1, VC voltage is higher than VR voltage, and DATA OUT outputs a low level. Since OUT1 continuously outputs a low level (0V), IS5 continues to charge capacitor C1. When capacitor C1 is charged to VREF1 (VREF2 = VREF1), charging stops, and the voltage of C1 remains at VREF1. When OUT1 outputs a high-level signal, IS4 starts discharging C1. Since the voltage VC of C1 is higher than VR, DATA OUT still outputs a low level, thus compensating for the filtered low-level pulse width. The charging current of capacitor C1 is equal to the discharging current, so the time taken to discharge from VREF1 to 1 / 2 VREF is equal to the time taken to charge from 0 to 1 / 2 VREF, achieving the function of restoring the low-level pulse width.

[0053] By adjusting the value of the resistor connected in parallel with R21 through the external pin of the chip, the t1 time can be adjusted, which means that glitches of different pulse widths can be filtered out.

[0054] Technical effect reference Figures 3 to 7 : Figure 3This is a waveform diagram illustrating how bus parasitic capacitance causes bus waveform oscillations, resulting in large and small waves in the decoded waveform, according to an embodiment of the present invention. When the bus differential signal drops from a high level to a mid-level, or rises from a low level to a mid-level, it oscillates with the bus parasitic capacitance due to the lack of driving capability. Chips without dynamic threshold adjustment circuitry will decode this oscillating waveform, resulting in low-level glitches in the DATA OUT signal.

[0055] Figure 4 This is a waveform diagram showing interference spikes on the bus during compressor operation in an embodiment of the present invention, which cause large and small waves in the decoded waveform. These interference spikes are irregular and have large amplitudes, approaching or exceeding the normal signal. The dynamic threshold adjustment circuit cannot filter out these spike interferences. Without a spike signal filtering and signal restoration module, the DATA OUT signal has low-level spikes.

[0056] Figure 5 This is a waveform diagram of the DATA OUT signal lagging behind the DATA IN signal for a preset duration in an embodiment of the present invention when there are no parasitic parameters or interference. As described above, using the circuit of the present invention, the normal communication signal will be output after a delay of t1 time. Since it is a whole delay, the pulse width does not change and the signal is not distorted.

[0057] Figure 6 This is a waveform diagram showing the OUT1 output signal oscillation caused by parasitic parameters in this embodiment of the invention. After processing by the glitch signal filtering and pulse width restoration module, the DATA OUT signal has no oscillation, the pulse width is normal, and it lags behind the DATA IN signal by a preset duration. Without an automatic threshold adjustment circuit, the OUT1 output signal will oscillate, but this oscillation signal will be filtered out by the glitch signal filtering and pulse width restoration module. Therefore, the DATA OUT signal does not oscillate, but is simply delayed by the duration t1.

[0058] Figure 7 This is a waveform diagram illustrating how interference spikes generated by the compressor, fan, etc., in this embodiment of the invention couple to the differential bus, causing oscillations in the OUT1 output signal. After processing by the spike signal filtering and pulse width restoration module, the DATA OUT signal exhibits no oscillation, a normal pulse width, and lags behind the DATA IN signal by a preset duration. Figure 7 and Figure 4 Compared to the previous year, after interference from compressors and other sources was processed by the glitch signal filtering and pulse width restoration module, the DATA OUT signal showed no oscillation.

[0059] Meanwhile, the present invention also provides a decoding error correction method, the steps of which correspond to the decoding error correction circuit described above, including: Step S1: Detect the voltage difference between the first node and the second node on the differential communication bus, compare the voltage difference with a preset offset voltage, and output a differential detection signal; Step S2: Output the first decoding signal based on the differential detection signal, and dynamically adjust the comparison threshold used in the comparison step in step 1 based on the level state of the first decoding signal. Step S3: Charge or discharge the timing capacitor according to the level of the first decoding signal to obtain the capacitor voltage of the timing capacitor; Step S4: Compare the capacitor voltage with a preset reference voltage to filter out glitches with a pulse width shorter than a preset duration, and restore the pulse width of normal communication signals with a pulse width not shorter than a preset duration. Step S5: Output a low-level data output signal when the capacitor voltage is greater than the reference voltage, and output a high-level data output signal when the capacitor voltage is less than the reference voltage.

[0060] In step S2, dynamically adjusting the comparison threshold includes: increasing the comparison threshold after the first decoded signal flips from low to high; and decreasing the comparison threshold after the first decoded signal flips from high to low. In step S4, the reference voltage is half of the first reference voltage source voltage, and the preset duration is the time required for the timing capacitor to charge from zero voltage to the reference voltage, and the preset duration is not greater than half of the pulse width of the normal communication signal.

[0061] This invention also provides a communication chip, including a transmitting module and the decoding and error correction circuit described in the above embodiments. The input terminal of the decoding and error correction circuit is used to connect to a differential communication bus, and the output terminal is used to connect to a microcontroller. This communication chip uses a home bus communication protocol, is powered by a differential communication bus, and the differential communication bus supports non-polarity connections. This communication chip can be applied to communication between master and slave devices in fields such as central air conditioning, security, and smart homes.

[0062] Compared with the prior art, the present invention has the following beneficial effects: First, this invention automatically adjusts the threshold of the decoding circuit through a dynamic threshold adjustment module: when the decoding module outputs a high level for the first time, it automatically raises the threshold, thereby shielding the RC oscillation generated when the differential signal transitions from a high or low level to an intermediate level—since the amplitude of such oscillation is smaller than the signal amplitude, raising the threshold results in an oscillation amplitude smaller than the decoding threshold, preventing the decoding module from erroneously outputting a low level; and after the first low level output, it automatically lowers the threshold voltage, achieving dynamic balance. This effectively filters out bus oscillation interference.

[0063] Secondly, this invention filters out bus spike voltages caused by electromagnetic interference from equipment such as fans and compressors through a spike signal filtering and pulse width restoration module. Although these spikes are differential signals with amplitudes close to or higher than normal communication signals, they cannot be filtered out by dynamic threshold adjustment. However, their pulse widths are usually much smaller than the communication signal pulse widths, so they can be identified by timing the charging and discharging of the timing capacitor. At the same time, a pulse width restoration mechanism is configured to determine whether the signal pulse width is interference or a normal communication signal by detecting the signal pulse width. When the signal pulse width is lower than a preset duration, it is determined to be interference and not restored. When the signal pulse width is greater than the preset duration, it is determined to be a normal signal and the pulse width is restored, thereby ensuring that the pulse width remains unchanged.

[0064] Third, this invention is implemented in pure hardware circuit, which does not occupy microcontroller resources, does not affect communication efficiency, and does not require a large number of external components compared to existing RC filtering schemes. The circuit structure is simple and the cost is low.

[0065] Fourth, the present invention can adjust the external resistance value through the external pin of the chip, thereby adjusting the charging current and preset duration, thereby filtering out glitches with different pulse widths, and has the advantages of adaptive communication speed and wide applicability.

[0066] Fifth, while improving communication quality and reducing the bit error rate, this invention also reduces the requirements for on-site construction wiring methods, thereby reducing the difficulty of on-site construction.

[0067] It should be understood that the scope of protection sought in this application is not limited to the non-limiting embodiments, which are merely illustrative examples. The substantive scope of protection claimed in this application is further embodied in the scope provided by the independent claims and their dependent claims.

Claims

1. A decoding and error correction circuit for decoding signals on a differential bus, characterized in that, include: The differential signal detection module compares the voltage difference between the differential communication buses with a preset offset voltage and outputs a differential detection signal accordingly. The decoding signal output module outputs a first decoding signal based on the differential detection signal. The dynamic threshold adjustment module dynamically adjusts the comparison threshold of the differential signal detection module based on the level of the first decoding signal. The glitch signal filtering and pulse width restoration module charges or discharges the timing capacitor based on the level of the first decoding signal and compares the capacitor voltage with a preset reference voltage to filter out glitch signals with a pulse width shorter than a preset duration and restore the pulse width of normal communication signals with a pulse width not shorter than the preset duration. The data output module outputs a low-level data output signal when the capacitor voltage is greater than the reference voltage, and outputs a high-level data output signal when the capacitor voltage is less than the reference voltage.

2. The decoding and error correction circuit according to claim 1, characterized in that: The dynamic threshold adjustment module is connected to the differential signal detection module to increase the comparison threshold after the first decoded signal flips from low to high; and to decrease the comparison threshold after the first decoded signal flips from high to low. The decoded signal output module is connected to the output of the differential signal detection module, the glitch signal filtering and pulse width restoration module is connected to the decoded signal output module, and the data output module is connected to the glitch signal filtering and pulse width restoration module.

3. The decoding and error correction circuit according to claim 2, characterized in that: The differential signal detection module includes a seventh resistor between the first input terminal and the second input terminal for setting the offset voltage; the first input terminal and the second input terminal are respectively connected to the differential communication bus via a DC blocking capacitor and an attenuation resistor; when the absolute value of the voltage difference between the first node and the second node is less than the offset voltage, the voltages of the first output terminal and the second output terminal are equal, and the decoding signal output module outputs a high-level first decoding signal; when the absolute value of the voltage difference is greater than the offset voltage, one of the voltages of the first and second output terminals increases and the other decreases, the voltage of the first output terminal is higher than the threshold voltage provided by the dynamic threshold adjustment module, and the decoding signal output module outputs a low-level first decoding signal.

4. The decoding and error correction circuit according to claim 3, characterized in that: The dynamic threshold adjustment module includes an eighth resistor, a first current source, and a second current source. When the control terminal signal is high, the second current source is set to zero, and the current flowing through the eighth resistor is the current of the first current source. The voltage divider of the dynamic threshold adjustment module is the power supply voltage minus the product of the current of the first current source and the eighth resistor. When the control terminal signal is low, the current from the second current source flows through the switching transistor, and the current flowing through the eighth resistor is reduced to the difference between the current from the first current source and the current from the second current source. The voltage divider point voltage is the power supply voltage minus the product of the current difference and the eighth resistor. The threshold voltage output by the dynamic threshold adjustment module is the voltage divider point voltage minus the base-emitter voltage of the transistor. The level of the control terminal signal follows the change of the data output signal.

5. The decoding error correction circuit according to claim 1, characterized in that: The glitch signal filtering and pulse width restoration module includes the timing capacitor, the charging current source, the discharging current source, the first switching transistor, the second switching transistor, and the first comparator; the current of the charging current source, the current of the discharging current source, and the current of the bias current source are equal, and the current of the bias current source is adjusted by an external resistor; the voltages of the first reference voltage source, the second reference voltage source, and the third reference voltage source are equal.

6. The decoding error correction circuit according to claim 5, characterized in that: When the first decoding signal is low, the first switch is turned on and the second switch is turned off, and the charging current source charges the timing capacitor; when the first decoding signal is high, the second switch is turned on and the first switch is turned off, and the discharging current source discharges the timing capacitor. The reference voltage is half the voltage of the first reference voltage source; The preset duration is the time required for the timing capacitor to charge from zero voltage to the reference voltage. The preset duration is determined by the capacitance value of the timing capacitor and the current value of the charging current source. The preset duration is not greater than half of the pulse width of a normal communication signal.

7. A decoding error correction circuit according to claim 6, characterized in that: When a glitch signal appears on the differential communication bus, and the low-level pulse width of the first decoded signal caused by the glitch signal is less than the preset duration, the capacitor voltage is less than the reference voltage, and the data output module maintains the output of the data output signal at a high level to filter out the glitch signal.

8. The decoding error correction circuit according to claim 7, characterized in that: When a glitch signal appears on the differential communication bus, and the first decoded signal is a normal low-level communication signal, the data output module outputs a high-level data output signal within the preset duration. After the preset duration, the capacitor voltage is greater than the reference voltage, and the data output module outputs a low-level data output signal. After the first decoded signal returns to a high level, the discharge current source discharges the timing capacitor, and the data output module maintains the output of a low-level data output signal during the period when the capacitor voltage is greater than the reference voltage, in order to compensate for the filtered low-level pulse width.

9. A decoding error correction circuit according to claim 5, characterized in that: The glitch signal filtering and pulse width restoration module also includes a charging limiting module, which includes a second comparator and a current limiting switch. When the capacitor voltage reaches the voltage of the second reference voltage source, the second comparator outputs a high-level signal and controls the current limiting switch to set the current of the charging current source to zero, stopping the charging of the timing capacitor. When the capacitor voltage is lower than the voltage of the second reference voltage source, the current limiting switch does not work, and the charging and discharging of the timing capacitor is determined by the first decoding signal.

10. A decoding error correction circuit according to claim 9, characterized in that: The differential communication bus is a communication bus using the home bus communication protocol. The decoding and error correction circuit is integrated into the communication chip. The communication chip also includes an external pin, which is used to connect an adjustable resistor in parallel with the external resistor, so as to adjust the preset duration by adjusting the current of the bias current source.

11. A decoding error correction method, characterized in that, Includes the following steps: The voltage difference between the first node and the second node on the differential communication bus is detected, and the voltage difference is compared with a preset offset voltage to output a differential detection signal. The first decoding signal is output based on the differential detection signal, and the comparison threshold on which the comparison is based is dynamically adjusted according to the level state of the first decoding signal to filter out interference spikes with amplitude smaller than normal signals. The timing capacitor is charged or discharged according to the level of the first decoded signal to obtain the capacitor voltage of the timing capacitor; The capacitor voltage is compared with a preset reference voltage to filter out glitches with a pulse width shorter than a preset duration, and to restore the pulse width of normal communication signals with a pulse width not shorter than the preset duration. A low-level data output signal is output when the capacitor voltage is greater than the reference voltage, and a high-level data output signal is output when the capacitor voltage is less than the reference voltage.

12. The decoding and error correction method according to claim 11, characterized in that: The step of dynamically adjusting the comparison threshold includes: increasing the comparison threshold after the first decoded signal flips from low to high; decreasing the comparison threshold after the first decoded signal flips from high to low; the reference voltage is half of the voltage of the first reference voltage source, and the preset duration is the time required for the timing capacitor to charge from zero voltage to the reference voltage; the preset duration is not greater than half of the pulse width of the normal communication signal; after the first decoded signal returns to high level, the timing capacitor is discharged by the discharge current source, and the data output signal is maintained at a low level during the period when the capacitor voltage is greater than the reference voltage, in order to compensate for the filtered low-level pulse width.

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