Semiconductor device including source connection structure

Abstract

A semiconductor device includes first source / drain regions spaced apart from each other in a first direction, first gate structures spaced apart from each other in the first direction and extending in a second direction substantially perpendicular to the first direction, second source / drain regions respectively spaced apart from the first source / drain regions in a third direction substantially perpendicular to the first and second directions, second gate structures respectively spaced apart from the first gate structures in the third direction and extending in the second direction, and a source connection structure connecting one of the first source / drain regions and one of the second source / drain regions to each other, wherein the source connection structure overlaps the second source / drain regions and the second gate structures in a plan view.

Description

Cross-reference to related applications

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0058061, filed on May 2, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a semiconductor device. Background Technology

[0003] With the increasing demand for high performance, high speed, and / or versatility in semiconductor devices, the integration density of semiconductor devices has increased. To overcome the limitations in operating characteristics caused by the shrinking size of planar metal-oxide-semiconductor field-effect transistors (MOSFETs), efforts have been made to develop semiconductor devices including transistors with three-dimensional channel structures. Furthermore, in line with the trend towards higher integration density in semiconductor devices, three-dimensional stacked FETs (3DSFETs) in which transistors are vertically stacked have been proposed. Summary of the Invention

[0004] The present disclosure is conceived in order to provide a semiconductor device with improved integration and electrical characteristics.

[0005] According to various aspects of the present disclosure, a semiconductor device includes: a first semiconductor structure; and a second semiconductor structure located on the first semiconductor structure, wherein the first semiconductor structure includes: an active region extending in a first direction; a first gate electrode extending in the active region in a second direction intersecting the first direction; a plurality of first channel layers spaced apart from each other in a third direction substantially perpendicular to the first and second directions in the active region, and each surrounded by the first gate electrode; a first source / drain region connected to the plurality of first channel layers on both sides of the first gate electrode; a first bonding insulating layer located on the first gate electrode; a first source contact plug connected to the first source / drain region and extending in a third direction; a first interconnect extending in the first direction within the first bonding insulating layer and connected to one of the first source contact plugs; and a first gate contact plug connected to the first gate electrode and Furthermore, extending upward in a third direction, the second semiconductor structure includes: a second gate electrode extending in a second direction; a plurality of second channel layers spaced apart from each other in a third direction and respectively surrounded by the second gate electrode; second source / drain regions connected to the plurality of second channel layers on both sides of the second gate electrode; a second bonding insulating layer disposed below the second gate electrode and bonded to a first bonding insulating layer; a second source contact plug connected to an upper region of the second source / drain regions and extending upward in a third direction; a source connection plug connecting a lower region of one of the second source / drain regions to a first interconnect and extending upward in a third direction through the second bonding insulating layer; and a second gate contact plug connected to the second gate electrode and the first gate contact plug and extending upward in a third direction, wherein the first active structure including the plurality of first channel layers and the first source / drain regions overlaps with the first interconnect in a third direction.

[0006] According to various aspects of the present disclosure, a semiconductor device includes: first source / drain regions spaced apart from each other in a first direction; a first gate structure spaced apart from each other in the first direction and extending in a second direction substantially perpendicular to the first direction; second source / drain regions spaced apart from the first source / drain regions in a third direction substantially perpendicular to the first and second directions; a second gate structure spaced apart from the first gate structure in a third direction and extending in the second direction; and a source connection structure connecting one of the first source / drain regions and one of the second source / drain regions to each other, wherein the source connection structure overlaps with the second source / drain regions and the second gate structure in a plan view.

[0007] According to various aspects of the present disclosure, a semiconductor device includes: a first semiconductor structure; and a second semiconductor structure located on the first semiconductor structure, wherein the first semiconductor structure includes: a first active structure extending in a first direction; a first gate electrode intersecting the first active structure and extending in a second direction intersecting the first direction; and a first bonding insulating layer located on the first gate electrode, and wherein the second semiconductor structure includes: a second active structure extending in the first direction; a second gate electrode intersecting the second active structure and extending in the second direction; and a second bonding insulating layer disposed below the second gate electrode and bonded to the first bonding insulating layer, and the semiconductor device further includes: a gate connection structure electrically connecting the first gate electrode to the second gate electrode; and a source connection structure electrically connecting a region of the first active structure to a region of the second active structure, wherein the source connection structure is disposed between the first active structure and the second active structure in a third direction substantially perpendicular to the first and second directions, and overlaps with the first and second active structures in a plan view. Attached Figure Description

[0008] The above and other aspects, features and advantages of the present disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings: Figure 1 This is a circuit diagram of a semiconductor device according to an embodiment; Figure 2 This is a plan view illustrating a semiconductor device according to an embodiment; Figure 3A and Figure 3B This is a cross-sectional view of a semiconductor device according to an embodiment; Figure 4 This is a perspective view showing a semiconductor device according to an embodiment; Figure 5A and Figure 5B This is a perspective view showing a semiconductor device according to an embodiment; Figure 6A and Figure 6B This is a cross-sectional view of a semiconductor device according to an embodiment; Figure 7 This is a cross-sectional view showing a semiconductor device according to an embodiment; and Figures 8A to 8I This is a diagram illustrating the process sequence used to explain the method of manufacturing a semiconductor device according to an embodiment. Detailed Implementation

[0009] In the following description, embodiments of the concept of this disclosure will be illustrated with reference to the accompanying drawings. Unless otherwise stated, terms such as “above,” “upper,” “upper surface,” “lower,” “lower,” “lower surface,” “side surface,” etc., will be understood to be based on the accompanying drawings.

[0010] The embodiments described below can be combined with each other and are described as one embodiment.

[0011] Figure 1 This is a circuit diagram of a semiconductor device according to an embodiment.

[0012] Reference Figure 1 The semiconductor device may include a NAND circuit. The NAND circuit may include a first pull-up device TR1 and a second pull-up device TR2 connected in parallel with each other, and a first pull-down device TR3 and a second pull-down device TR4 connected in series with each other. The first pull-up device TR1 and the second pull-up device TR2 may be connected to a first power supply V. DD The second pull-down device TR4 can be connected to the second power supply V. SS .

[0013] The gates of the first pull-up device TR1 and the first pull-down device TR3 can be connected to each other to provide the first input terminal IN. A Furthermore, the gates of the second pull-up device TR2 and the second pull-down device TR4 can be connected to each other to provide the second input terminal IN. B One of the source / drain regions of each of the first pull-up device TR1 and the second pull-up device TR2, and one of the source / drain regions of the first pull-down device TR3, can be connected to each other to provide the output terminal V. OUT .

[0014] However, as Figure 1 The NAND circuit shown is merely an example of the circuits included in the embodiment, and semiconductor devices can provide various circuits.

[0015] Figure 2 This is a plan view illustrating a semiconductor device according to an embodiment. Figure 2 The image shows only some components of the semiconductor device.

[0016] Figure 3A and Figure 3B This is a cross-sectional view showing a semiconductor device according to an embodiment. Figure 3A It shows Figure 2 The semiconductor device is a cross-section taken along line I-I', and Figure 3B It shows Figure 2 The semiconductor device is a cross-section taken along lines II-II' and III-III'.

[0017] Figure 4 This is a perspective view showing a semiconductor device according to an embodiment.

[0018] Reference Figures 2 to 4 The semiconductor device 100 includes a first semiconductor structure S1 and a second semiconductor structure S2 vertically joined together. Each of the first semiconductor structure S1 and the second semiconductor structure S2 may include a plurality of transistors, and the transistors of the first semiconductor structure S1 and the second semiconductor structure S2 may be electrically connected to each other. The first semiconductor structure S1 and the second semiconductor structure S2 may include transistors of different conductivity types. For example, the first semiconductor structure S1 may be an nFET region and the second semiconductor structure S2 may be a pFET region.

[0019] The semiconductor device 100 in this embodiment may include a semiconductor device formed by forming Figure 1 The transistors of the NAND circuit. The first semiconductor structure S1 may include... Figure 1 The first pull-down device TR3 and the second pull-down device TR4, and the second semiconductor structure S2 may include Figure 1 The first pull-up device TR1 and the second pull-up device TR2. However, in some embodiments, the first semiconductor structure S1 and the second semiconductor structure S2 may be regions in which transistors with the same conductivity type but different electrical characteristics are arranged.

[0020] The first semiconductor structure S1 may include: a substrate 101 including an active region 105; a first gate structure 160A extending to intersect the active region 105 and including a first gate electrode 165A; a first channel structure 140A arranged vertically spaced apart from each other on the active region 105 and each including a first channel layer to a fourth channel layer 141, 142, 143 and 144; a first source / drain region 150A contacting the first channel structure 140A; a first source contact plug 170A connected to the first source / drain region 150A; a first interconnect MI1 and a second interconnect MI2 connected to the first source contact plug 170A; and a first gate contact plug 175A connected to the first gate electrode 165A. The first semiconductor structure S1 may also include a device isolation layer 110, a first interlayer insulating layer 190 and a first bonding insulating layer 192.

[0021] The second semiconductor structure S2 may include: a substrate insulating layer 107; a second gate structure 160B, each including a second gate electrode 165B; a second channel structure 140B, arranged vertically spaced apart from each other on the substrate insulating layer 107 and each including a first channel layer to a fourth channel layer 141, 142, 143 and 144; a second source / drain region 150B, contacting the second channel structure 140B; a second source contact plug 170B, connected to the second source / drain region 150B; an upper interconnect 180, connected to the second source contact plug 170B; a first upper contact 182, located on the upper interconnect 180; a source connection plug SV, connected to the lower region of the second source / drain region 150B; a second gate contact plug 175B, connected to the second gate electrode 165B; and a second upper contact 184, connected to the second gate electrode 165B. The second semiconductor structure S2 may further include a device isolation layer 110, a second bonding insulating layer 194, a second interlayer insulating layer 196, a third interlayer insulating layer 198, and a through-hole element FV.

[0022] Semiconductor device 100 may include a transistor having a 3D stacked field-effect transistor (3DSFET) structure in which a transistor of a first semiconductor structure S1 and a transistor of a second semiconductor structure S2 are vertically stacked. In semiconductor device 100, a first gate electrode 165A and a second gate electrode 165B may be disposed between the first channel layers 141, 142, 143, and 144 of the first channel structure 140A and the second channel structure 140B, and are disposed above and below the first channel structure 140A and the second channel structure 140B. Therefore, semiconductor device 100 may include a multi-bridge channel FET (MBCFET). TM Transistors with a gate-enclosed structure, and fully enclosed gate field-effect transistors.

[0023] Substrate 101 may have an upper surface extending in both the X and Y directions. Substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. Substrate 101 may be configured as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer.

[0024] Substrate 101 may include an active region 105 defined in an upper region by device isolation layer 110. Active region 105 may be configured to extend in a first direction (e.g., the X direction). Depending on the technology, active region 105 may also be referred to as a component separate from substrate 101. Active region 105 may partially protrude from below the first gate structure 160A above the device isolation layer 110, and a portion of the upper surface of active region 105 may be located at a level higher than the upper surface of device isolation layer 110. Active region 105 may be formed of the same material as substrate 101, or may include an epitaxial layer grown from substrate 101. However, active region 105 may be partially recessed on both sides of the first gate structure 160A, and first source / drain regions 150A may be disposed on active region 105.

[0025] Each active region 105 may include a well region containing impurities. For example, the well region may include p-type impurities (such as boron (B), gallium (Ga), or aluminum (Al)) or n-type impurities (such as phosphorus (P), arsenic (As), or antimony (Sb)). For example, the well region may be located at a predetermined depth from the upper surface of each of the active regions 105. However, in some embodiments, the active region 105 may not include impurities.

[0026] Device isolation layer 110 may define an active region 105 within substrate 101. Device isolation layer 110 may be formed, for example, by a shallow trench isolation (STI) process. Device isolation layer 110 may expose at least the upper surface of the active region 105 and may also expose a portion of the upper surface of the active region 105. According to an embodiment, device isolation layer 110 may have a curved upper surface with a higher level closer to the active region 105. Device isolation layer 110 may be formed of an insulating material. Device isolation layer 110 may be, for example, an oxide, a nitride, or a combination thereof.

[0027] The substrate insulating layer 107 may be a substrate substrate 101' formed during the manufacturing process by removing and / or oxidizing the semiconductor material (see [link]). Figure 8E The substrate insulating layer 107 can be disposed on the second channel structure 140B and the second source / drain region 150B and can be configured to fill the space between the second source contact plug 170B.

[0028] The substrate insulating layer 107 may be formed of an insulating material and may include, for example, oxides, nitrides, or combinations thereof. In some embodiments, the substrate insulating layer 107 may include the same material as the device isolation layer 110 and / or the third interlayer insulating layer 198, in which case the interface with the device isolation layer 110 and / or the third interlayer insulating layer 198 may be obvious or may not be obvious. According to embodiments, the substrate insulating layer 107 may include multiple insulating layers.

[0029] In the first semiconductor structure S1 and the second semiconductor structure S2, some components may be arranged vertically symmetrically with respect to the bonding surface BS. The bonding surface BS may be the interface between the first semiconductor structure S1 and the second semiconductor structure S2, and may be the interface between the first bonding insulating layer 192 and the second bonding insulating layer 194. For example, the first gate structure 160A, the first channel structure 140A, and the first source / drain region 150A of the first semiconductor structure S1 may be arranged symmetrically with respect to the second gate structure 160B, the second channel structure 140B, and the second source / drain region 150B of the second semiconductor structure S2 based on the bonding surface BS. Therefore, unless otherwise stated, the description of any component of the first semiconductor structure S1 can be equivalently applied to the corresponding component of the second semiconductor structure S2. However, components arranged symmetrically to each other do not necessarily have the same shape and may have the same shape or different shapes.

[0030] The first gate structure 160A can be arranged to extend in one direction (e.g., in the Y direction) over the active region 105. The first gate structures 160A can be arranged to be spaced apart from each other in the X direction. The channel region of the transistor can be formed in a first channel structure 140A intersecting with the first gate electrode 165A of the first gate structure 160A. Each of the first gate structures 160A may include a gate dielectric layer 162, a gate spacer layer 164, a first gate electrode 165A, and a gate capping layer 167.

[0031] The second gate structure 160B can be arranged to extend on the lower surface of the substrate insulating layer 107 in one direction (e.g., in the Y direction). The second gate structure 160B can be arranged to at least partially overlap with the first gate structure 160A in the Z direction. In this specification, the overlap in the Z direction can have the same characteristics as in (such as...) Figure 2In a planar diagram, the overlapping has the same meaning. For example, the second gate structure 160B may have the same width in the X direction as the first gate structure 160A and may be arranged to completely overlap with the first gate structure 160A in the Z direction. The second gate structures 160B may be arranged to be spaced apart from each other in the X direction. The channel region of the transistor may be formed in a second channel structure 140B that intersects with the second gate electrode 165B of the second gate structure 160B. The second gate structure 160B may each include a gate dielectric layer 162, a gate spacer layer 164, a second gate electrode 165B, and a gate capping layer 167.

[0032] In the first semiconductor structure S1, the gate dielectric layer 162 may be disposed between the active region 105 and the first gate electrode 165A, and between the first channel structure 140A and the first gate electrode 165A, and may be disposed to cover at least a portion of the surface of the first gate electrode 165A. For example, the gate dielectric layer 162 may be disposed around all surfaces of the first gate electrode 165A except for the top surface. The gate dielectric layer 162 may extend between the first gate electrode 165A and the gate spacer layer 164, but is not limited thereto. Similarly, in the second semiconductor structure S2, the gate dielectric layer 162 may be disposed between the substrate insulating layer 107 and the second gate electrode 165B, and between the second channel structure 140B and the second gate electrode 165B.

[0033] The gate dielectric layer 162 may include oxides, nitrides, or high-k materials. High-k materials can refer to dielectric materials having a higher dielectric constant than silicon oxide (SiO2). Examples of high-k materials include, for instance, alumina (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), and zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2) and hafnium silicon oxide (HfSi) x O y ), Lanthanum oxide (La₂O₃), Lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y Hafnium aluminum oxide (HfAl) x O y At least one of praseodymium oxide (Pr₂O₃) and praseodymium oxide (Pr₂O₃). According to an embodiment, the gate dielectric layer 162 may be formed of a multilayer structure.

[0034] The first gate electrode 165A and the second gate electrode 165B may comprise conductive materials, such as metal nitrides (e.g., titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN)) and / or metallic materials (e.g., aluminum (Al), tungsten (W), or molybdenum (Mo)), or semiconductor materials (e.g., doped polycrystalline silicon). The first gate electrode 165A and the second gate electrode 165B may comprise the same or different materials. For example, the first gate electrode 165A may comprise an n-metal, and the second gate electrode 165B may comprise a p-metal. According to an embodiment, the first gate electrode 165A and the second gate electrode 165B may be formed with a multilayer structure. The first gate electrode 165A may be connected to the first gate contact plug 175A via its upper surface. The second gate electrode 165B may be connected to the second gate contact plug 175B via its lower surface.

[0035] A gate spacer layer 164 may be disposed on both side surfaces of the first gate electrode 165A on the first channel structure 140A. The gate spacer layer 164 may insulate the first source / drain region 150A and the first gate electrode 165A. According to an embodiment, the shape of the upper portion of the gate spacer layer 164 may be modified, and the gate spacer layer 164 may be formed to have a multilayer structure. Similarly, the gate spacer layer 164 may be disposed below the second channel structure 140B on both side surfaces of the second gate electrode 165B. The gate spacer layer 164 may include at least one of oxides, nitrides, and oxide oxynitrides, and may be formed from, for example, a low-k film.

[0036] A gate capping layer 167 may be disposed on the first gate electrode 165A. In some embodiments, the lower surface of the gate capping layer 167 may have a downwardly convex shape. Similarly, the gate capping layer 167 may be disposed below the second gate electrode 165B. The gate capping layer 167 may include an insulating material and may include at least one of, for example, oxides, nitrides, and oxynitrides.

[0037] A first channel structure 140A may be disposed on the active region 105 in the region where the active region 105 intersects with the first gate structure 160A. A second channel structure 140B may be disposed below the substrate insulating layer 107 in the region where the substrate insulating layer 107 intersects with the second gate structure 160B. The first channel structure 140A may form a first active structure AS1 together with the first source / drain region 150A, and the second channel structure 140B may form a second active structure AS2 together with the second source / drain region 150B. The first active structure AS1 may be described as also including the active region 105. The first active structure AS1 and the second active structure AS2 may extend in the X direction and may be spaced apart from each other in the Z direction. The first active structure AS1 and the second active structure AS2 may be arranged to at least partially overlap in the Z direction. For example, the first active structure AS1 and the second active structure AS2 may have the same width in the Y direction and may be arranged to completely overlap each other in the Z direction.

[0038] Each of the first channel structure 140A and the second channel structure 140B may include first to fourth channel layers 141, 142, 143, and 144 (two or more channel layers) arranged to be spaced apart from each other in a direction perpendicular to the upper surface of the active region 105 (e.g., in the Z direction). The first to fourth channel layers 141, 142, 143, and 144 may be connected to the first source / drain region 150A and the second source / drain region 150B while being spaced apart from the upper surface of the active region 105. The first to fourth channel layers 141, 142, 143, and 144 may have a width in the Y direction equal to or less than the width of the active region 105, and may have a width in the X direction the same as or similar to the width of the first gate structure 160A and the second gate structure 160B. The width of the first to fourth channel layers 141, 142, 143, and 144 in the Y direction may increase toward the channel layers below, but is not limited thereto. The number and shape of the channel layers 141, 142, 143, and 144 in each of the first channel structure 140A and the second channel structure 140B may be varied in the embodiments.

[0039] The first to fourth channel layers 141, 142, 143 and 144 can be formed of a semiconductor material and may include at least one of silicon (Si), silicon germanium (SiGe) and germanium (Ge). The first to fourth channel layers 141, 142, 143 and 144 can be formed of, for example, the same material as the substrate 101.

[0040] The first source / drain region 150A can be arranged to contact the first channel structure 140A on both sides of the first gate structure 160A. The first source / drain region 150A can be arranged to cover the side surfaces in the X direction of each of the first to fourth channel layers 141, 142, 143, and 144 of the first channel structure 140A. The upper surface of the first source / drain region 150A can be disposed at the same level as or higher than the lower surface of the first gate electrode 165A on the first channel structure 140A, and this level can be varied in embodiments.

[0041] The second source / drain region 150B can be arranged to contact the second channel structure 140B on both sides of the second gate structure 160B. The second source / drain region 150B can be arranged to cover the side surface of each of the first to fourth channel layers 141, 142, 143 and 144 of the second channel structure 140B in the X direction.

[0042] The first source / drain region 150A and the second source / drain region 150B may include polygonal regions in a cross-section along the Y direction outside the first gate structure 160A and the second gate structure 160B. The shapes of the first source / drain region 150A and the second source / drain region 150B may be different from each other. However, in embodiments, the shapes of the first source / drain region 150A and the second source / drain region 150B are not limited to those of other regions. Figure 3B The shapes shown are such that the first source / drain region 150A and the second source / drain region 150B can each have a curved polygonal shape, an elliptical shape, or a circular shape. The first source / drain region 150A can be connected to the first source contact plug 170A above it. The second source / drain region 150B can be connected to the second source contact plug 170B above it.

[0043] The first source / drain region 150A and the second source / drain region 150B may comprise a semiconductor material (e.g., at least one of silicon (Si) and germanium (Ge)) and may also comprise impurities. For example, the first source / drain region 150A may have a lower germanium (Ge) concentration than the second source / drain region 150B. For example, the first source / drain region 150A may comprise at least one of phosphorus (P), arsenic (As), and antimony (Sb) as n-type impurities, and the second source / drain region 150B may comprise at least one of boron (B), gallium (Ga), and indium (In) as p-type impurities. Each of the first source / drain region 150A and the second source / drain region 150B may comprise a plurality of epitaxial layers with different compositions.

[0044] In some embodiments, the semiconductor device 100 may further include an internal spacer layer disposed between the side surfaces of the first source / drain region 150A and / or the second source / drain region 150B in the X direction and the gate dielectric layer 162. The internal spacer layer may include an insulating material.

[0045] A first interlayer insulating layer 190 may be disposed on the first source / drain region 150A, a second interlayer insulating layer 196 may be disposed below the second source / drain region 150B, and a third interlayer insulating layer 198 may be disposed on the substrate insulating layer 107 and the second source contact plug 170B. The first to third interlayer insulating layers 190, 196, and 198 may comprise insulating materials (e.g., at least one of oxides, nitrides, and oxynitrides), and may include, for example, low-k materials. According to an embodiment, at least one of the first to third interlayer insulating layers 190, 196, and 198 may comprise multiple insulating layers.

[0046] A first bonding insulating layer 192 may be disposed on the first interlayer insulating layer 190 and the first gate structure 160A, and a second bonding insulating layer 194 may be disposed below the second interlayer insulating layer 196 and the second gate structure 160B. The first bonding insulating layer 192 and the second bonding insulating layer 194 may be layers for bonding the first semiconductor structure S1 and the second semiconductor structure S2, and may be layers for dielectric-dielectric bonding. The first bonding insulating layer 192 and the second bonding insulating layer 194 may include insulating materials, such as at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN. In some embodiments, the first bonding insulating layer 192 and the second bonding insulating layer 194 may include different materials. For example, the first bonding insulating layer 192 may include SiO and the second bonding insulating layer 194 may include SiCN, or vice versa.

[0047] The first source contact plug 170A can be connected to the upper region of the first source / drain region 150A and can apply an electrical signal to the first source / drain region 150A. The first source contact plug 170A can pass through the first bonding insulation layer 192 and the first interlayer insulation layer 190. Among the first source contact plugs 170A, the first source contact plug 170A connected to the first interconnect MI1 is configured such that its upper region is removed by the first interconnect MI1, so that the level of its upper end in the final structure can be lower than the level of the upper ends of the other first source contact plugs 170A. However, in some embodiments, the first interconnect MI1 can be configured to be connected to the side surface of the first source contact plug 170A. In this case, the level of the upper ends of the first source contact plugs 170A can be uniform.

[0048] The second source contact plug 170B can be connected to the upper region of the second source / drain region 150B and can apply an electrical signal to the second source / drain region 150B. The second source contact plug 170B can pass through the substrate insulating layer 107.

[0049] The first source contact plug 170A and the second source contact plug 170B may have sloping side surfaces with a width at the lower part narrower than the width at the upper part according to the aspect ratio, but are not limited thereto. The relative width, height, etc. of the first source contact plug 170A and the second source contact plug 170B may be varied in embodiments. The first source contact plug 170A and the second source contact plug 170B may be arranged by recessing the first source / drain region 150A and the second source / drain region 150B from the upper surface. The first source contact plug 170A may extend downward from the upper part to, for example, below the lower surface of the uppermost fourth channel layer 144 of the first channel structure 140A, but are not limited thereto.

[0050] The source connection plug SV can be connected to the lower region of at least one of the second source / drain regions 150B. The source connection plug SV can be configured to extend through the second bonding insulation layer 194 and the second interlayer insulation layer 196 and to partially recess the second source / drain region 150B from the lower surface. The source connection plug SV can have, but is not limited to, sloping side surfaces where the width of its lower portion is wider than the width of its upper portion according to the aspect ratio.

[0051] The first gate contact plug 175A can be connected to the upper surface of the first gate electrode 165A through the first bonding insulating layer 192 and the gate capping layer 167. The second gate contact plug 175B can be connected to the lower surface of the second gate electrode 165B through the second bonding insulating layer 194 and the gate capping layer 167. The first gate contact plug 175A can be connected to the second gate contact plug 175B respectively to electrically connect the first gate electrode 165A and the second gate electrode 165B that are spaced apart from each other in the Z direction. The first gate contact plug 175A and the second gate contact plug 175B connected to each other can form a gate connection structure GI.

[0052] The gate connection structure GI can, for example, completely overlap with the first gate electrode 165A and the second gate electrode 165B in the Z direction. In this embodiment, the gate connection structure GI can be located in the region overlapping with the device isolation layer 110 in the Z direction. The first gate contact plug 175A and the second gate contact plug 175B can have a shape in which the bevels of their side surfaces are symmetrical with respect to the bonding surface BS. In some embodiments, the first gate contact plug 175A and the second gate contact plug 175B can be configured such that the first gate electrode 165A and the second gate electrode 165B are partially recessed.

[0053] The first source contact plug 170A and the second source contact plug 170B, the source connection plug SV, and the first gate contact plug 175A and the second gate contact plug 175B may comprise conductive materials, such as metallic materials like aluminum (Al), tungsten (W), or molybdenum (Mo). According to an embodiment, the first source contact plug 170A, the second source contact plug 170B, and the source connection plug SV may comprise a metal semiconductor compound layer, such as a metal silicide layer, disposed at the interface with the first source / drain region 150A and the second source / drain region 150B, and may further comprise a barrier layer forming the side surfaces of the first source contact plug 170A, the second source contact plug 170B, and the source connection plug SV and extending into the metal semiconductor compound layer. Similarly, the first gate contact plug 175A and the second gate contact plug 175B may further comprise a metal semiconductor compound layer and a barrier layer located at the interface with the first gate electrode 165A and the second gate electrode 165B. The barrier layer may include, for example, metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN).

[0054] The first interconnect MI1 and the second interconnect MI2 can be connected to the first source contact plug 170A and can extend in a horizontal direction within the first bonding insulation layer 192. In an embodiment, the first interconnect MI1 and the second interconnect MI2 can be arranged to pass completely through the first bonding insulation layer 192 or partially through the first bonding insulation layer 192 from the upper surface of the first bonding insulation layer 192.

[0055] The first interconnect MI1 can extend in the X direction to connect one of the first source contact plugs 170A to the source connection plug SV. The first interconnect MI1 can Figure 2 In the planar diagram, it overlaps with the first active structure AS1 and the second active structure AS2. For example... Figure 3A and Figure 4As shown, the first interconnect MI1 can be configured to extend parallel to the first active structure AS1 and the second active structure AS2, which are spaced apart from each other along the Z direction. The first interconnect MI1 can also overlap with the active region 105 in the plan view. Figure 3A and Figure 4 As shown, the first interconnect MI1 can extend between the first gate electrode 165A and the second gate electrode 165B, which are spaced apart from each other along the Z direction.

[0056] The first interconnect MI1, together with the first source contact plug 170A and the source connection plug SV connected thereto, can form a source connection structure SI. The source connection structure SI can electrically connect a region of the first active structure AS1 to a region of the second active structure AS2. In this embodiment, the source connection structure SI can electrically connect the first source / drain region 150A and the second source / drain region 150B that do not overlap in the Z direction. The source connection structure SI can, for example,... Figure 3A The upper region of the rightmost first source / drain region 150A of the first semiconductor structure S1 and the lower region of the second source / drain region 150B at the center of the second semiconductor structure S2 are connected. The entire source connection structure SI can be Figure 2 In the planar view, it overlaps with the first active structure AS1 and the second active structure AS2. The source connection structure SI may overlap with the first source / drain region 150A and the first gate structure 160A in the planar view. The source connection structure SI may overlap with the second source / drain region 150B and the second gate structure 160B in the planar view.

[0057] The second interconnect MI2 can extend in the Y direction to connect one of the first source contact plugs 170A to the through-hole component FV. The second interconnect MI2 can Figure 2 In the plan view, between the first gate structure 160A and the second gate structure 160B adjacent along the X direction, the area extends in the Y direction from the region overlapping with the first active structure AS1 and the second active structure AS2, and can extend to the outside of the first active structure AS1 and the second active structure AS2.

[0058] The upper interconnect 180 and the first upper contact 182 can be sequentially arranged on the second source contact plug 170B to form an electrical path. The upper interconnect 180 and the first upper contact 182 can be arranged within the third interlayer insulation layer 198. However, in embodiments, the interconnect structure including vias and interconnects electrically connected to the second source contact plug 170B can be modified.

[0059] The second upper contact 184 can be connected to the upper region of the second gate electrode 165B. For example... Figure 3B As shown, the second upper contact 184 can be arranged to pass through the third interlayer insulating layer 198, the device isolation layer 110, and the gate dielectric layer 162. A through-via FV can pass through the entire second semiconductor structure S2 from the upper surface to the lower surface and connect to the second interconnect MI2. The upper end of the through-via FV can be located at a level higher than the upper end of the second source contact plug 170B. However, in some embodiments, the through-via FV may not pass through the entire second semiconductor structure S2, and the upper end of the through-via FV may be located at the same level as the upper end of the second source contact plug 170B, or it may be located within the third interlayer insulating layer 198. Additional vias and interconnects can also be arranged on the first upper contact 182 and the through-via FV.

[0060] like Figure 4 As shown, the first upper contacts 182 located on both sides of the first upper contact 182 can be connected to the first power supply V. DD And the first upper contact 182 in the center can be connected to the output terminal V. OUT The second upper contact 184 can be connected to the first input terminal IN. A Second input terminal IN B Furthermore, the through-hole component FV can be connected to the second power supply V. SS .

[0061] The first interconnect MI1 and the second interconnect MI2, the upper interconnect 180, the first upper contact 182, the second upper contact 184 and the through-hole FV may include at least one of the following conductive materials (e.g., tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru), titanium (Ti) or molybdenum (Mo)).

[0062] like Figure 2 and Figure 4 As shown, based on the first active structure AS1 and the second active structure AS2 extending in the X direction, and the first gate electrode 165A and the second gate electrode 165B extending in the Y direction while intersecting with the first active structure AS1 and the second active structure AS2, the semiconductor device 100 can have a minimized planar area. In the components that electrically connect the transistors of the first semiconductor structure S1 and the second semiconductor structure S2, the gate connection structure GI can overlap with the first gate electrode 165A and the second gate electrode 165B, and the source connection structure SI can overlap with the first active structure AS1 and the second active structure AS2. Figure 2As shown in the plan view, all other components except the second interconnect MI2 and the through-hole FV can be arranged to overlap with the first active structure AS1 and the second active structure AS2, as well as the first gate structure 160A and the second gate structure 160B.

[0063] This arrangement improves the integration density of the semiconductor device 100 and reduces the length of the interconnect structure, thereby minimizing resistance. Specifically, it minimizes the planar area of ​​the semiconductor device 100 in the Y direction. Furthermore, since the semiconductor device 100 is formed by joining the first semiconductor structure S1 and the second semiconductor structure, the manufacturing processes for the nFET region and the pFET region can be performed separately, allowing for the selection of materials or processes optimized for each device, thereby improving electrical characteristics.

[0064] In the following description of the embodiments, references to the above will be omitted. Figures 2 to 4 The given description is redundant.

[0065] Figure 5A and Figure 5B This is a perspective view showing a semiconductor device according to an embodiment.

[0066] Reference Figure 5A In semiconductor device 100a, with Figures 2 to 4 In different embodiments, the gate connection structure GIA can extend vertically from one side of the first gate electrode 165A and the second gate electrode 165B. The gate connection structure GIA can contact the side surfaces of the first gate electrode 165A and the second gate electrode 165B. For example, the gate connection structure GIA can be configured to... Figure 3B A single gate contact plug extends from the upper surface of the second semiconductor structure S2 through the second semiconductor structure S2 and connects to the first gate electrode 165A in a cross-sectional view. In some embodiments, the gate connection structure GIa may include a first gate contact plug 175A and a second gate contact plug 175B that respectively contact the side surfaces of the first gate electrode 165A and the second gate electrode 165B, and the first gate contact plug 175A and the second gate contact plug 175B may be arranged to be connected to each other.

[0067] Reference Figure 5B In semiconductor device 100b, with Figures 2 to 4In different embodiments, the gate connection structure GIb can be configured to overlap with the first active structure AS1 and the second active structure AS2 in the Z direction. For example, the gate connection structure GIb can be configured to overlap with the first channel structure 140A and the second channel structure 140B in the Z direction. In this embodiment, both the gate connection structure GIb and the source connection structure SI can be arranged to overlap with the first active structure AS1 and the second active structure AS2 in the Z direction. The gate connection structure GIb and the source connection structure SI are components that electrically connect the transistors of the first semiconductor structure S1 and the second semiconductor structure S2.

[0068] As referenced above Figure 5A and Figure 5B As described, in the embodiments, the gate connection structure can be varied within a range in which the gate connection structure overlaps with the first gate electrode 165A and the second gate electrode 165B in the Z direction or is located on one side of the extension direction of the first gate electrode 165A and the second gate electrode 165B.

[0069] Figure 6A and Figure 6B This is a cross-sectional view showing a semiconductor device according to an embodiment. Figure 6A and Figure 6B Each shows with Figure 3A The corresponding area.

[0070] Reference Figure 6A In the semiconductor device 100c, the source connection plug SVc can be configured to pass through the second source / drain region 150B. The source connection plug SVc can be connected to the first interconnect MI1 at its lower end, and together with the first interconnect MI1 and the first source contact plug 170A connected thereto, it can form a source connection structure SIc.

[0071] A second source contact plug 170B connected to the upper region may be disposed within a portion of the second source / drain region 150B, and a source connection plug SVc passing through the second source / drain region 150B may be disposed within a portion of the second source / drain region 150B. However, in some embodiments, the source connection plug SVc may be arranged throughout the entire second source / drain region 150B instead of the second source contact plug 170B. In this case, the shape of the interconnect structure (such as the height of the upper end of the first source contact plug 170A) may be changed considering the circuit configuration.

[0072] Reference Figure 6B In the semiconductor device 100d, the source connection structure SId may include a first source contact plug 170A and a source connection plug SV. That is, with Figures 2 to 4In different embodiments, the source connection structure SId may not include the first interconnect MI1. In this embodiment, the source connection plug SV can be directly connected to the first source contact plug 170A through its lower surface. In this case, in order to construct... Figure 1 In the circuit, the connection shape of the vertically arranged transistors can be changed to match... Figures 2 to 4 The connection shapes differ in the embodiments.

[0073] As referenced above Figure 6A and Figure 6B As described, in the embodiments, the structure of the source connection structure can be changed within a range in which the source connection structure overlaps with the first active structure AS1 and the second active structure AS2 in the Z direction. Furthermore, Figure 6A and Figure 6B The embodiments can be the same as those described above. Figure 5A and Figure 5B The embodiments are combined in different ways.

[0074] Figure 7 This is a cross-sectional view showing a semiconductor device according to an embodiment. Figure 7 It shows the relationship with Figure 3A The corresponding area.

[0075] Reference Figure 7 In the semiconductor device 100e, the first semiconductor structure S1 may further include a first bonding pad BM1, and the second semiconductor structure S2 may further include a second bonding pad BM2. The first bonding pad BM1 and the second bonding pad BM2 may be connected to each other to provide an electrical path between the first semiconductor structure S1 and the second semiconductor structure S2. The first bonding pad BM1 may be connected to a lower interconnect structure (e.g., a first source contact plug 170A and a first interconnect line MI1), and the second bonding pad BM2 may be connected to an upper interconnect structure (e.g., a source connection plug SV). In this embodiment, the source connection structure SIe may further include the first bonding pad BM1 and the second bonding pad BM2.

[0076] The first bonding pad BM1 and the second bonding pad BM2 may include a conductive material such as copper (Cu). The bonding of the first bonding pad BM1 and the second bonding pad BM2 may be, for example, a copper (Cu) to copper (Cu) bonding, and therefore, the first semiconductor structure S1 and the second semiconductor structure S2 may be bonded by a hybrid bonding including copper (Cu) to copper (Cu) bonding and dielectric to dielectric bonding.

[0077] Figures 8A to 8I This is a diagram illustrating the sequential process of a method for manufacturing a semiconductor device according to an embodiment. Figures 8A to 8I It shows the manufacturing process. Figures 2 to 4An example of a method for manufacturing a semiconductor device. Figures 8A to 8I Each showed the same as Figure 3A The corresponding cross section.

[0078] Reference Figure 8A The process of forming the first semiconductor structure S1 can begin. The sacrificial layer 118 and the first channel layer to the fourth channel layer 141, 142, 143 and 144 can be alternately stacked on the substrate 101 to form an initial active structure and a sacrificial gate structure 200.

[0079] The substrate 101 may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The substrate 101 may include a bulk wafer, an epitaxial layer, an SOI layer, or a SeOI layer.

[0080] Sacrificial layer 118 can be used through subsequent processes such as Figure 3A The gate dielectric layer 162 and the first gate electrode 165A shown are replaced by the layer shown. The sacrificial layer 118 may be formed of a material having etch selectivity relative to the first to fourth channel layers 141, 142, 143, and 144. The first to fourth channel layers 141, 142, 143, and 144 may include materials different from those of the sacrificial layer 118. The sacrificial layer 118 and the first to fourth channel layers 141, 142, 143, and 144 include a semiconductor material comprising at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge), but may include different materials and may or may not include impurities. For example, the sacrificial layer 118 may include silicon germanium (SiGe), and the first to fourth channel layers 141, 142, 143, and 144 may include silicon (Si). The sacrificial layer 118 and the first to fourth trench layers 141, 142, 143 and 144 can be formed by performing an epitaxial growth process from the substrate 101.

[0081] Next, the first to fourth channel layers 141, 142, 143 and 144, the sacrificial layer 118, and the upper region of the substrate 101 can be patterned to form an active region 105 extending in the X direction and an initial active structure, and a device isolation layer 110 can be formed (see [link to documentation]). Figure 3B The device isolation layer 110 can be formed by the following steps: depositing an insulating material to fill the periphery of the initial active structure, and then removing a portion of the deposited insulating material from above, such that at least the upper surface of the active region 105 is exposed.

[0082] The sacrificial gate structure 200 can be formed therein through subsequent processes such as Figure 3AThe diagram shows a sacrificial structure in the region where the gate dielectric layer 162, the first gate electrode 165A, and the gate capping layer 167 are arranged on the first channel structure 140A. The sacrificial gate structure 200 can have a line shape extending in one direction while intersecting with the aforementioned initial active structure. The sacrificial gate structure 200 can extend, for example, in the Y direction.

[0083] Each of the sacrificial gate structures 200 may include a first sacrificial gate layer 202 and a second sacrificial gate layer 205 sequentially stacked, and a mask patterning layer 206. The first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be patterned using the mask patterning layer 206. The first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be, but are not limited to, an insulating layer and a conductive layer, respectively, and the first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be formed as a single layer. For example, the first sacrificial gate layer 202 may include silicon oxide, and the second sacrificial gate layer 205 may include polysilicon. The mask patterning layer 206 may include silicon oxide and / or silicon nitride.

[0084] Reference Figure 8B A portion of the initial active structure can be removed from the outside of the sacrificial gate structure 200, and a first source / drain region 150A can be formed.

[0085] The sacrificial layer 118 and the first to fourth channel layers 141, 142, 143, and 144 exposed from the sacrificial gate structure 200 can be removed. In this operation, after removing the sacrificial layer 118 and the first to fourth channel layers 141, 142, 143, and 144, the exposed active region 105 can be partially recessed from the upper surface, but is not limited thereto. Through this operation, the first to fourth channel layers 141, 142, 143, and 144 can form a first channel structure 140A having a finite length in the X direction.

[0086] The first source / drain region 150A can be formed by growing from the active region 105 via, for example, a selective epitaxial growth process. The first source / drain region 150A can include impurities through in-situ doping. Therefore, a first active structure AS1 can be formed comprising a first channel structure 140A and the first source / drain region 150A alternately arranged in the X direction. The first active structure AS1 can have a shape extending in the X direction. According to this description, the first active structure AS1 can also be referred to as a component further comprising the active region 105.

[0087] Reference Figure 8C A first interlayer insulating layer 190 can be formed, and the sacrificial layer 118 and the sacrificial gate structure 200 can be removed.

[0088] The sacrificial layer 118 and the sacrificial gate structure 200 can be selectively removed relative to the gate spacer layer 164, the first interlayer insulating layer 190, the first channel structure 140A, and the first source / drain region 150A. First, the sacrificial gate structure 200 can be removed to form the upper gap region UR, and then the sacrificial layer 118 exposed through the upper gap region UR can be removed to form the lower gap region LR. For example, when the sacrificial layer 118 comprises silicon germanium (SiGe) and the first channel structure 140A comprises silicon (Si), the sacrificial layer 118 can be selectively removed by performing a wet etching process.

[0089] Reference Figure 8D After forming the first gate structure 160A and the first source contact plug 170A, the first interconnect MI1 can be formed.

[0090] A gate dielectric layer 162 and a first gate electrode 165A may be formed to fill the upper gap region UR and the lower gap region LR. The gate dielectric layer 162 may be formed to conformally cover the inner surfaces of the upper gap region UR and the lower gap region LR. The first gate electrode 165A may be formed to completely fill the upper gap region UR and the lower gap region LR. Then, the first gate electrode 165A, together with the gate dielectric layer 162, is removed from the upper portion of the upper gap region UR by a predetermined depth. Finally, a gate capping layer 167 may be formed.

[0091] A first bonding insulating layer 192 may be formed on the first gate structure 160A, and a first source contact plug 170A may be formed that passes through the first bonding insulating layer 192 and the first interlayer insulating layer 190 and connects to the first source / drain region 150A. Together with the first source contact plug 170A, or in a separate process, a first gate contact plug 175A may be formed that passes through the first bonding insulating layer 192 and the gate cap layer 167 and connects to the first gate electrode 165A (see [link to relevant documentation]). Figure 3B ).

[0092] A first interconnect MI1 can be formed such that it extends from the upper surface through at least a portion of the first bonding insulating layer 192 and connects to the first source contact plug 170A. The first interconnect MI1 can be formed after removing a portion of the upper region of the first source contact plug 170A, or the first interconnect MI1 can be formed such that it covers the upper end of the first source contact plug 170A. The first interconnect MI1 can be connected to... Figure 3B Together with the second interconnect MI2, a first semiconductor structure S1 can be fabricated.

[0093] Reference Figure 8E The process for forming the second semiconductor structure S2 can then begin. On the substrate 101', a second channel structure 140B, a holding layer 130, a second source / drain region 150B, and a sacrificial gate structure 200' can be formed.

[0094] First, the above references can be executed in the same way. Figure 8A The process described. Although not specifically shown, an active region may also be formed in the upper region of the substrate 101'. The sacrificial layer 118 and the first channel layers to the fourth channel layers 141, 142, 143 and 144 may be alternately stacked on the substrate 101', and a sacrificial gate structure 200' may be formed on the stacked structure.

[0095] Next, with reference Figure 8B The above process is performed in the same manner, but the substrate 101' is recessed relatively deeply on both sides of the sacrificial gate structure 200', and a placement holding layer 130 may also be formed before the second source / drain region 150B is formed. For example, in order to form the placement holding layer 130, a separate sacrificial spacer layer may be formed in the recessed region formed by removing the sacrificial layer 118 and the first to fourth channel layers 141, 142, 143 and 144, and this separate sacrificial spacer layer may be used.

[0096] The placement and holding layer 130 can be formed by growing from the substrate 101' via, for example, a selective epitaxial growth process. The placement and holding layer 130 may include a semiconductor material having a different composition than the second source / drain region 150B. The second source / drain region 150B can be formed, for example, by growing from the side surface of the second channel structure 140B, the substrate 101', and the placement and holding layer 130 via a selective epitaxial growth process.

[0097] Reference Figure 8F It can form a second gate structure 160B and a source connection plug SV.

[0098] First, the above references can be executed in the same way. Figure 8C The described process forms the second interlayer insulating layer 196, and the sacrificial layer 118 and sacrificial gate structure 200' can be removed. Next, the above-described process can be performed in the same manner. Figure 8D The described process forms a second gate structure 160B, a second bonding insulating layer 194, and a second gate contact plug 175B that passes through the second bonding insulating layer 194 and the gate capping layer 167 and connects to the second gate electrode 165B (see [link to documentation]). Figure 3B ).

[0099] A source connection plug SV can be formed such that the source connection plug SV passes through the second bonding insulation layer 194 and the second interlayer insulation layer 196 to connect to one of the second source / drain regions 150B.

[0100] Reference Figure 8G The first semiconductor structure S1 and the second semiconductor structure S2 can be joined together.

[0101] The first semiconductor structure S1 and the second semiconductor structure S2 can be joined by bonding the first bonding insulating layer 192 and the second bonding insulating layer 194 via annealing and / or applying pressure. The second semiconductor structure S2 can be inverted on the first semiconductor structure S1 such that the second bonding insulating layer 194 faces downward, and then bonding can be performed.

[0102] When the first semiconductor structure S1 and the second semiconductor structure S2 are joined, the first interconnect MI1 and the source connection plug SV can contact each other and be electrically connected to each other.

[0103] Reference Figure 8H In the bonding structure of the first semiconductor structure S1 and the second semiconductor structure S2, the substrate 101' can be removed and a substrate insulating layer 107 can be formed.

[0104] The substrate 101' can be partially removed by processes such as grinding, lapping, and / or polishing to thin the substrate 101', and the remaining areas can be removed by etching and / or oxidation processes. In some embodiments, the substrate 101' may not be completely removed and may be partially retained.

[0105] The substrate insulating layer 107 can be formed by depositing an insulating material in the area where the substrate 101' is removed and performing a planarization process. In some embodiments, the substrate insulating layer 107 can be formed by oxidizing at least a portion of the substrate 101'. The substrate insulating layer 107 can be formed to expose the placement holding layer 130. The substrate insulating layer 107 may include, for example, silicon oxide.

[0106] Reference Figure 8I It can remove the placement retaining layer 130 and form a second source contact plug 170B.

[0107] The placement and holding layer 130 exposed from the substrate insulating layer 107 can be selectively removed, and a second source contact plug 170B can be formed to connect the second source / drain region 150B. The second source contact plug 170B can be formed after removing a portion of the second source / drain region 150B from the upper surface. In some embodiments, the second source contact plug 170B may include a region having a shape corresponding to the placement and holding layer 130.

[0108] Next, refer to Figure 3A A third interlayer insulating layer 198 can be formed on the second source contact plug 170B, and upper interconnects 180 and first upper contacts 182 can be formed sequentially. Figure 3B The second upper contact 184 is formed simultaneously with the first upper contact 182 or can be formed in a separate process. Figure 3B The second upper contact 184 can be formed in a separate process. Figure 3B FV through hole to make Figure 3B The through-hole element FV passes through the second semiconductor structure S2. As a result, it is possible to manufacture... Figure 3A Semiconductor device 100.

[0109] According to one aspect of the concept of this disclosure, a method for manufacturing a semiconductor device includes: forming a first semiconductor structure including a first active structure extending in a first direction, a first gate electrode extending in a second direction intersecting the first active structure and the first direction, a first bonding insulating layer on the first gate electrode, a first source contact plug electrically connected to the first active structure, and an interconnect connected to one of the first source contact plugs and extending in the first direction; forming a second semiconductor structure including a second active structure extending in the first direction, a second gate electrode intersecting the second active structure and extending in the second direction, a second bonding insulating layer disposed below the second gate electrode and bonded to the first bonding insulating layer, and a source connection plug electrically connected to the second active structure; bonding the first bonding insulating layer and the second bonding insulating layer to bond the first semiconductor structure and the second semiconductor structure; and forming an interconnect structure electrically connected to the second active structure and the second gate electrode on the bonding structure of the first semiconductor structure and the second semiconductor structure, wherein, in the bonding, the interconnect is connected to the source connection plug, and the interconnect overlaps with the first active structure in a plan view.

[0110] In an embodiment, the first active structure may include a first source / drain region and a first channel structure arranged alternately in a first direction, and the second active structure may include a second source / drain region and a second channel structure arranged alternately in the first direction.

[0111] In an embodiment, forming the first semiconductor structure may include: alternately stacking a first sacrificial layer and a plurality of first channel layers on a substrate; patterning the stacked structure of the first sacrificial layer and the plurality of first channel layers and an upper region of the substrate to form an initial active structure extending in a first direction; forming a first sacrificial gate structure extending in a second direction on the initial active structure; removing a portion of the initial active structure from the outside of the first sacrificial gate structure and forming a first source / drain region; removing the first sacrificial layer and the first sacrificial gate structure and forming a first gate structure; forming a first bonding insulating layer on the first gate structure; forming a first source contact plug to connect the first source contact plug to the first source / drain region; and forming an interconnect on one of the first source contact plugs.

[0112] In one embodiment, interconnects may be formed such that the interconnects pass through at least a portion of the first bonding insulating layer from the upper surface.

[0113] In an embodiment, the first gate structure may include a first gate electrode, and the method may further include forming first gate contact plugs that are connected to the first gate electrode through a first bonding insulating layer.

[0114] In an embodiment, forming the second semiconductor structure may include: alternately stacking a second sacrificial layer and a plurality of second channel layers on a substrate; forming a second sacrificial gate structure extending in a second direction on the stacked structure of the second sacrificial layer and the plurality of second channel layers; removing a portion of the stacked structure from the outside of the second sacrificial gate structure and forming a placement holding layer and a second source / drain region; removing the second sacrificial layer and the second sacrificial gate structure and forming a second gate structure; forming a second bonding insulating layer on the second gate structure; and forming a source connection plug on one of the second source / drain regions.

[0115] In an embodiment, the method may further include removing the substrate after bonding the first semiconductor structure and the second semiconductor structure.

[0116] In an embodiment, the method may further include depositing an insulating material in the region where the substrate is removed to form a substrate insulating layer; and removing the placement holding layer.

[0117] In an embodiment, the second gate structure may include a second gate electrode, and the method may further include forming a second gate contact plug that is connected to the second gate electrode through a second bonding insulating layer.

[0118] In one embodiment, the interconnect may overlap with the second active structure in a planar view.

[0119] By optimizing the arrangement of the interconnect structure in a 3DSFET that electrically connects the upper transistor to the lower transistor, a semiconductor device with improved integration and electrical characteristics can be provided.

[0120] The various advantages and effects of the present disclosure are not limited to those described above and will be more readily understood in the process of describing specific embodiments of the present disclosure.

[0121] Although embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of the concept of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: First semiconductor structure; as well as A second semiconductor structure is located on top of the first semiconductor structure. The first semiconductor structure includes: The active region extends in the first direction; A first gate electrode extends over the active region in a second direction intersecting the first direction; Multiple first channel layers are spaced apart from each other in the active region in a third direction substantially perpendicular to the first and second directions, and are each surrounded by the first gate electrode; A first source / drain region is connected to the plurality of first channel layers on both sides of the first gate electrode; A first bonding insulating layer is located on the first gate electrode; A first source contact plug is connected to the first source / drain region and extends upward in the third party; A first interconnect extending within the first bonding insulating layer in the first direction and connected to one of the first source contact plugs; and A first gate contact plug, which is connected to the first gate electrode and extends upward on the third party, and The second semiconductor structure includes: The second gate electrode extends in the second direction; Multiple second channel layers, which are spaced apart from each other in the third direction and are each surrounded by the second gate electrode; The second source / drain region is connected to the plurality of second channel layers on both sides of the second gate electrode; A second bonding insulating layer is disposed below the second gate electrode and bonded to the first bonding insulating layer; A second source contact plug is connected to the upper region of the second source / drain region and extends upward therefrom; A source connection plug that connects a lower region of one of the second source / drain regions to the first interconnect and extends upward through the second bonding insulation layer in the third region; and A second gate contact plug is connected to the second gate electrode and the first gate contact plug and extends upward from the third. The first active structure, including the plurality of first channel layers and the first source / drain region, overlaps with the first interconnect in the third direction.

2. The semiconductor device according to claim 1, wherein, The second active structure, including the plurality of second channel layers and the second source / drain regions, overlaps with the first interconnect in the third direction.

3. The semiconductor device according to claim 1, wherein, The first gate electrode and the second gate electrode overlap each other in the third direction.

4. The semiconductor device according to claim 3, wherein, The first interconnect extends between one of the first gate electrodes and one of the second gate electrodes.

5. The semiconductor device according to claim 3, wherein, The first gate contact plug and the second gate contact plug overlap with the first gate electrode and the second gate electrode in the third direction.

6. The semiconductor device according to claim 1, wherein, The first gate contact plugs are respectively connected to the upper surface of the first gate electrode, and the second gate contact plugs are respectively connected to the lower surface of the second gate electrode.

7. The semiconductor device according to claim 1, wherein: The first semiconductor structure further includes a second interconnect extending in the second direction within the first bonding insulating layer and connected to one of the first source contact plugs. The second semiconductor structure further includes a through-hole extending upward through the third party and through the second bonding insulating layer to the second interconnect.

8. The semiconductor device according to claim 7, wherein, The upper end of the through-hole is at a level higher than the upper end of the second source contact plug.

9. The semiconductor device according to claim 7, wherein, The second interconnect extends outward from the first active structure in the plan view.

10. The semiconductor device according to claim 1, wherein, The second semiconductor structure further includes a substrate insulating layer disposed on the plurality of second channel layers and filling the space between the second source contact plugs.

11. The semiconductor device according to claim 1, wherein, The first gate electrode and the second gate electrode are arranged to be substantially symmetrical based on the interface between the first bonding insulating layer and the second bonding insulating layer.

12. The semiconductor device according to claim 1, wherein, The first source / drain region includes a first type of conductive impurity, and the second source / drain region includes a second type of conductive impurity.

13. A semiconductor device, comprising: The first source / drain regions are spaced apart from each other in the first direction; A first gate structure, which is spaced apart from each other in the first direction and extends in a second direction substantially perpendicular to the first direction; The second source / drain region is spaced apart from the first source / drain region in a third direction that is substantially perpendicular to the first direction and the second direction, respectively. A second gate structure is spaced apart from the first gate structure in the third direction and extends in the second direction; as well as A source-to-drain connection structure that connects one of the first source / drain regions and one of the second source / drain regions to each other. In the plan view, the source connection structure overlaps with the second source / drain region and the second gate structure.

14. The semiconductor device according to claim 13, wherein, The source connection structure overlaps with the first source / drain region and the first gate structure in the plan view.

15. The semiconductor device according to claim 13, wherein: The first source / drain region includes a first lower source / drain region to a third lower source / drain region arranged sequentially in the first direction. The second source / drain region includes a first upper source / drain region to a third upper source / drain region sequentially arranged in the first direction, and The source connection structure connects the upper region of the third lower source / drain region and the lower region of the second upper source / drain region.

16. The semiconductor device according to claim 15, wherein, The source connection structure includes: A first source contact plug extends upward on the third third region and is connected to the third lower source / drain region; A source connection plug that extends upward from the third party below the second upper source / drain region and connects to the second upper source / drain region; and An interconnect line connects the upper end of the first source contact plug to the lower end of the source connection plug.

17. The semiconductor device according to claim 13, wherein, The source connection structure includes: A first source contact plug, which extends upward on the third party and connects to at least one of the first source / drain regions in the first source / drain regions; and A source connection plug that extends upward through the at least one second source / drain region in the second source / drain region and is connected to the at least one first source contact plug.

18. A semiconductor device, comprising: First semiconductor structure; as well as A second semiconductor structure is located on top of the first semiconductor structure. The first semiconductor structure includes: A first active structure, which extends in a first direction; A first gate electrode, which intersects the first active structure and extends in a second direction intersecting the first direction; and A first bonding insulating layer is located on the first gate electrode, and The second semiconductor structure includes: A second active structure extends in the first direction; A second gate electrode, which intersects with the second active structure and extends in the second direction; and A second bonding insulating layer is disposed below the second gate electrode and bonded to the first bonding insulating layer, and The semiconductor device further includes: A gate connection structure, wherein the first gate electrode is electrically connected to the second gate electrode; and A source-connection structure electrically connects a region of the first active structure to a region of the second active structure. The source connection structure is disposed between the first active structure and the second active structure in a third direction substantially perpendicular to the first direction and the second direction, and overlaps with the first active structure and the second active structure in a planar view.

19. The semiconductor device according to claim 18, wherein, The gate connection structure is arranged in the third direction between the first gate electrode and the second gate electrode, and overlaps with the first gate electrode and the second gate electrode in the plan view.

20. The semiconductor device according to claim 18, wherein, The gate connection structure is connected to the side surface of the first gate electrode in the second direction and the side surface of the second gate electrode in the second direction.

Images