Floating gate flash memory coupling medium layer protection method and device
Patent Information
- Application Number
- CN202611230601.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-13
- Publication Date
- 2026-11-03
AI Technical Summary
In existing flash memory manufacturing processes, water vapor during high-temperature annealing tends to diffuse downwards, leading to an abnormal thickening of the coupling dielectric layer, which affects device size and electrical performance.
In the shallow trench isolation structure, an inner passivation layer and an isolation medium layer are introduced. Through atomic layer deposition and chemical mechanical planarization processes, water vapor diffusion is blocked and the coupling medium layer is protected.
It effectively suppresses abnormal thickening of the coupling dielectric layer, maintains device dimensional stability and electrical performance, and improves data retention capability and reliability.
Smart Images
Figure CN123035676A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a method and device for protecting the coupling dielectric layer of a floating gate type flash memory. Background Technology
[0002] In NorD-type flash memory devices, the coupling oxide layer is a critical dielectric layer located between the semiconductor substrate and the floating gate. Its quality and thickness directly determine the device's yield and reliability, including data retention. This coupling oxide layer plays a vital role in device operation, primarily in three aspects: first, regulating the coupling voltage applied from the control gate (CG) to the floating gate; second, allowing hot electrons to penetrate and enter the floating gate during programming; and third, preventing charge leakage during data retention, thereby maintaining the stability of the "0" or "1" storage state. Therefore, the quality and thickness of the coupling oxide layer have a decisive impact on the yield and reliability of NorD-type flash memory devices.
[0003] In existing flash memory manufacturing processes (such as 40nm embedded flash memory), after the shallow trench isolation (STI) structure is filled, a high-temperature annealing process containing water vapor is typically required. However, in actual production, it has been found that water vapor diffuses downwards very easily during annealing, causing additional oxidation to the floating gate and semiconductor substrate, resulting in unexpected and abnormal thickening of the coupling oxide layer (especially noticeable near the shallow trench isolation structure). This abnormal thickening significantly deviates from the device's design parameters, leading to a degradation in the device's electrical performance.
[0004] Therefore, the industry urgently needs to optimize existing semiconductor manufacturing processes to effectively block water vapor diffusion during annealing to suppress abnormal thickening of the coupling oxide layer, without adversely affecting peripheral logic devices on the same wafer. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to provide a method and device for protecting the coupling dielectric layer of a floating gate flash memory, so as to solve the problem that in the existing manufacturing process, the high-temperature annealing process after filling the shallow trench isolation structure contains water vapor, which causes the reactive gas to diffuse easily to the bottom layer, causing an unexpected abnormal thickening of the coupling dielectric layer between the substrate and the floating gate, thereby causing device size drift, coupling voltage misalignment and electrical performance degradation.
[0006] To address the aforementioned technical problems, this invention provides a method for protecting the coupling dielectric layer of a floating-gate type flash memory, comprising at least:
[0007] Step 1: Provide a semiconductor substrate, the semiconductor substrate including a flash memory region, the flash memory region having a floating gate and a coupling dielectric layer located between the semiconductor substrate and the floating gate, and the semiconductor substrate having a shallow trench isolation structure;
[0008] Step 2: Form an inner lining medium layer in the shallow trench isolation structure;
[0009] Step 3: Deposit a liner passivation layer on the surface of the liner medium layer;
[0010] Step 4: Fill the shallow trench isolation structure, to which the inner lining passivation layer has been deposited, with an isolation medium layer;
[0011] Step 5: Perform annealing treatment, using the inner lining passivation layer to prevent the reaction gas during the annealing process from diffusing into the coupling medium layer;
[0012] Step 6: Perform a planarization process, during which part of the inner liner passivation layer in the flash memory area is removed.
[0013] Preferably, in step one, the process of forming the shallow trench isolation structure includes: sequentially depositing a first hard mask layer and a second hard mask layer as a hard mask on the surface of the semiconductor substrate.
[0014] Preferably, in step one, the first hard mask layer includes a pad oxide layer, and the second hard mask layer includes a pad nitride layer.
[0015] Preferably, in step one, the process of forming the shallow trench isolation structure further includes etching trenches in the semiconductor substrate using photolithography and anisotropic dry etching.
[0016] Preferably, in step two, the inner lining medium layer includes an inner lining oxide layer.
[0017] Preferably, in step three, the inner liner passivation layer comprises a silicon nitride layer.
[0018] Preferably, in step three, the inner liner passivation layer is deposited using an atomic layer deposition process.
[0019] Preferably, in step three, the thickness of the inner liner passivation layer is 40 to 60 angstroms.
[0020] Preferably, in step four, the isolation medium layer comprises an oxide layer.
[0021] Preferably, in step four, filling the isolation dielectric layer includes: depositing a first isolation dielectric layer using an atomic layer deposition process and performing a back etching process, and depositing a second isolation dielectric layer using a high aspect ratio process or a high-density plasma chemical vapor deposition process.
[0022] Preferably, in step five, the annealing treatment includes a high-temperature annealing treatment containing water vapor, and the reaction gas includes the water vapor.
[0023] Preferably, in step six, the planarization process includes a chemical mechanical planarization process.
[0024] Preferably, after step six, the method further includes: etching the isolation dielectric layer to the required height using a dielectric etching process, and removing the second hard mask layer.
[0025] To address the aforementioned technical problems, the present invention also provides a floating-gate flash memory device, manufactured using the aforementioned floating-gate flash memory coupling dielectric layer protection method, comprising:
[0026] A semiconductor substrate, wherein a shallow trench isolation structure is formed therein;
[0027] A floating gate is formed on the semiconductor substrate;
[0028] A coupling dielectric layer is located between the semiconductor substrate and the floating gate;
[0029] An inner lining medium layer is located on the inner surface of the shallow trench isolation structure;
[0030] An inner passivation layer is located on the surface of the inner dielectric layer;
[0031] An isolation medium layer is filled in the shallow trench isolation structure located within the inner liner passivation layer;
[0032] The inner passivation layer is used to prevent the diffusion of reactive gases into the coupling medium layer during the annealing process.
[0033] As described above, the floating-gate type flash memory coupling dielectric layer protection method and device of the present invention have the following beneficial effects:
[0034] This invention introduces an inner passivation layer, which effectively blocks the diffusion of moisture during high-temperature annealing, suppresses abnormal thickening of the coupling dielectric layer, maintains the dimensional stability and coupling voltage of the device, and has a simple process and ideal protection effect. Attached Figure Description
[0035] Figure 1 The diagram shows a process flow diagram of the floating gate type flash memory coupling dielectric layer protection method of the present invention;
[0036] Figure 2 The diagram shows a cross-sectional structure of the deposition liner medium layer stage of the present invention;
[0037] Figure 3 The diagram shows a cross-sectional structure of the deposition liner passivation layer stage of the present invention.
[0038] Figure 4 The diagram shows a cross-sectional structure of the deposition stage of the first isolation medium layer of the present invention.
[0039] Figure 5 The diagram shows a cross-sectional structure of the deposition stage of the second isolation medium layer of the present invention.
[0040] Figure 6 The diagram shown is a cross-sectional structural schematic of the planarization process stage of the present invention.
[0041] Figure 7 The diagram shows a cross-sectional structure of the etching isolation dielectric layer stage of the present invention;
[0042] Figure 8 The diagram shown is a cross-sectional structural schematic of the stage of removing the second hard mask layer according to the present invention. Detailed Implementation
[0043] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0044] Please refer to Figures 1 to 8 , Figure 1 This is a schematic diagram of the process flow for the floating-gate flash memory coupling dielectric layer protection method provided in the embodiments of this disclosure. Figures 2 to 8 This is a cross-sectional structural diagram of the various manufacturing stages of the embodiments of this disclosure. The disclosed embodiments provide a method for protecting the coupling dielectric layer of a floating-gate flash memory. This method can be executed by a semiconductor manufacturing system, which may include multiple process modules, such as a chemical vapor deposition chamber, an atomic layer deposition chamber, a lithography machine, a plasma etching equipment, a wet cleaning tank, a rapid thermal annealing furnace, and a chemical mechanical planarization equipment. By introducing a protective layer with barrier properties at specific process stages, the underlying dielectric layer can be prevented from being subjected to unintended oxidation during subsequent high-temperature thermal processing, thereby maintaining the dimensional stability of the device structure and improving the electrical performance, data retention capability, and overall reliability of the semiconductor device. The method will be described in detail below with reference to specific process steps and accompanying drawings.
[0045] Please refer to Figure 1 A method for protecting the coupling dielectric layer of a floating-gate flash memory includes at least the following:
[0046] Step 1: Provide a semiconductor substrate 101, which includes a flash memory region. The flash memory region has a floating gate 103 and a coupling dielectric layer 102 located between the semiconductor substrate 101 and the floating gate 103. The semiconductor substrate 101 also has a shallow trench isolation structure.
[0047] In some embodiments, in step one, the process of forming the shallow trench isolation structure includes: sequentially depositing a first hard mask layer and a second hard mask layer 104 as hard masks on the surface of a semiconductor substrate 101.
[0048] In some embodiments, in step one, the first hard mask layer includes a pad oxide layer, and the second hard mask layer 104 includes a pad nitride layer 104.
[0049] In some embodiments, the process of forming the shallow trench isolation structure in step one further includes etching trenches in the semiconductor substrate 101 by photolithography and anisotropic dry etching.
[0050] Please refer to Figure 2 A semiconductor substrate 101 is provided to serve as a physical basis carrier for subsequent semiconductor device fabrication. The semiconductor substrate 101 may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. An SOI substrate includes an insulating layer located beneath a thin semiconductor layer serving as the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.
[0051] In addition to the flash memory region, the semiconductor substrate 101 may also include a peripheral region for forming peripheral circuitry that supports the operation of the memory array, such as logic devices, static random access memory, high-voltage driving devices, or input / output interface devices. The floating gate 103 serves as a node for storing charge, and its material may include doped or undoped polysilicon, or it may be a metal or metal alloy to adjust the work function. The coupling dielectric layer 102 serves as a tunneling oxide layer or a gate dielectric layer, and its material may include silicon dioxide grown by a thermal oxidation process, or it may include silicon oxynitride, high-dielectric-constant dielectric materials such as hafnium oxide, aluminum oxide, zirconium oxide, or a stacked structure of these materials.
[0052] Shallow trench isolation structures are used to provide electrical isolation between adjacent active regions in a semiconductor substrate 101, preventing leakage or signal crosstalk between different devices. In forming the shallow trench isolation structure, a first hard mask layer and a second hard mask layer 104 are deposited on the surface of the semiconductor substrate 101, and a bottom anti-reflective coating and a photoresist layer are coated. The photoresist layer is exposed and developed using a photolithography machine to form a patterned photoresist layer, which is then used as a mask for anisotropic dry etching, thereby forming trenches in the semiconductor substrate 101.
[0053] Step 2: Form an inner lining medium layer 105 in the shallow trench isolation structure.
[0054] In some embodiments, in step two, the inner liner medium layer 105 includes an inner liner oxide layer 105.
[0055] Please continue to refer to Figure 2 Before filling the trench, the inner oxide layer 105, i.e. the inner dielectric layer 105 in the figure, can be formed on the inner wall of the shallow trench isolation structure by in-situ steam generation process or furnace tube thermal oxidation process. The thin pad layer can repair the lattice damage caused to the semiconductor substrate 101 by the previous dry etching process, reduce the interface defect density, and provide interface compatibility for the subsequent deposition of dielectric thin film.
[0056] Step 3: Deposit a liner passivation layer 106 on the surface of the liner medium layer 105.
[0057] In some embodiments, in step three, the inner passivation layer 106 includes a silicon nitride layer.
[0058] In some embodiments, in step three, an atomic layer deposition process is used to deposit an inner passivation layer 106.
[0059] In some embodiments, in step three, the thickness of the inner liner passivation layer 106 is 40 to 60 angstroms.
[0060] Please refer to Figure 3An inner passivation layer 106 is deposited on the surface of the inner dielectric layer 105. The material of the inner passivation layer 106, besides silicon nitride, can also be selected from dielectric materials with barrier properties such as silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxycarbide, aluminum oxide, hafnium oxide, titanium oxide, or composites of these materials. Silicon nitride is used because its dense amorphous molecular structure can block the diffusion of moisture, oxygen, and other small molecule reactive gases. Atomic layer deposition (ALD) technology allows for atomic-level thin film growth through alternating introduction of precursor and reactive gases, utilizing surface self-limiting reactions to achieve uniform coverage within shallow trench isolation structures with complex morphologies. The thickness setting needs to balance the barrier effect with compatibility with subsequent processes. If the inner passivation layer 106 is too thin, it will not provide sufficient barrier effect, leading to oxidation of the underlying structure; if the thickness is too thick, it will increase the difficulty and time cost of subsequent etching processes, and a thicker film will introduce excessive internal stress, potentially causing wafer warping or film peeling or cracking during subsequent heat treatment. By controlling the thickness within a reasonable range, it is possible to ensure excellent water vapor barrier performance while also considering the operability of the process and the mechanical stability of the wafer. In addition to atomic layer deposition, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, high-density plasma-enhanced chemical vapor deposition, or physical vapor deposition can also be used to form the inner passivation layer 106.
[0061] Step 4: Fill the shallow trench isolation structure with the deposited inner passivation layer 106 with an isolation medium layer.
[0062] In some embodiments, in step four, the isolation dielectric layer includes an oxide layer.
[0063] In some embodiments, step four, filling the isolation dielectric layer includes: depositing a first isolation dielectric layer 107 using an atomic layer deposition process and performing a back etching process, and depositing a second isolation dielectric layer 108 using a high aspect ratio process or a high density plasma chemical vapor deposition process.
[0064] Please refer to Figure 4 and Figure 5 In addition to conventional oxides, the materials for the insulating dielectric layer can also include insulating materials such as silicon nitride, silicon oxynitride, silicon carbonitride, fluorine-doped silicate glass, carbon-doped silicate glass, borophosphorus silicate glass, spin-coated dielectric materials, etc.
[0065] The specific filling process can be completed in an integrated deposition and etching system, firstly as follows: Figure 4As shown, an oxide liner layer 107 with excellent conformability is formed on the sidewalls and bottom of the shallow trench isolation structure using atomic layer deposition (ALD). A subsequent etch-back process, such as a chemical dry etching process based on fluorine- and amino gases (e.g., SiCoNi etching), is performed to refine the morphology of the deposited first isolation layer 107. This etch-back process generates solid byproducts in a plasma environment, which are then removed by thermal sublimation. This enlarges the opening at the top of the trench without damaging the underlying structure, preventing voids during subsequent filling.
[0066] Then as Figure 5 As shown, the remaining trench space is filled using a high aspect ratio process or a high-density plasma chemical vapor deposition process to form a second isolation dielectric layer 108. The first isolation dielectric layer 107 and the second isolation dielectric layer 108 together constitute the isolation dielectric layer. The high aspect ratio process typically uses ozone and tetraethyl orthosilicate as reactant gases and is carried out in a thermochemical vapor deposition chamber. It has excellent gap-filling capability and can seamlessly fill the shallow trench isolation structure space with a high aspect ratio from bottom to top. This composite filling method can avoid the generation of micropores or gaps in trenches with large aspect ratios at the miniaturization process node, ensuring the physical density and electrical isolation effect of the shallow trench isolation structure. In other embodiments, a flowable chemical vapor deposition process can also be used to fill the isolation dielectric layer. The film deposited by this process has liquid-like fluidity and can fill complex trench structures. It is then converted into a solid oxide layer by UV curing or thermal annealing.
[0067] Step 5: Perform annealing treatment, using the inner lining passivation layer 106 to block the diffusion of reaction gases during the annealing process into the coupling medium layer 102.
[0068] In some embodiments, step five includes a high-temperature annealing process containing water vapor, and the reaction gas includes water vapor.
[0069] High-temperature annealing can be performed in rapid thermal annealing equipment or conventional furnace tube equipment. The purpose of this annealing process is to repair lattice damage caused during etching and filling of the shallow trench isolation structure, release internal stress in the thin film, and promote further densification of the isolation dielectric layer, thereby improving its insulation performance. In an annealing environment containing water vapor, water vapor is typically generated by the reaction of hydrogen and oxygen at high temperatures using in-situ steam generation technology. During annealing, reacting gases such as water vapor have strong diffusion capabilities and readily penetrate to the underlying layers. Because an inner passivation layer 106 is deposited on the surface of the inner dielectric layer 105 as a physical barrier, this layer prevents water vapor from penetrating to the underlying coupling dielectric layer 102, thus preventing secondary oxidation at the interface between the coupling dielectric layer 102, the floating gate 103, and the semiconductor substrate 101. In the baseline annealing process without a protective layer, the coupling dielectric layer 102 experiences unexpected and significant abnormal thickening due to the downward diffusion of water vapor, with a larger increase near the shallow trench isolation structure. However, after introducing the inner passivation layer 106 for protection, the thickness increase of the coupling dielectric layer 102 after annealing is effectively controlled, remaining essentially near the initial designed thickness. This method not only simplifies the process steps but also effectively suppresses the abnormal dimensional drift and thickening of the coupling dielectric layer 102 through a blocking mechanism, maintaining the equivalent thickness and capacitance characteristics of the device design and ensuring that the flash memory device has stable coupling voltage and data retention capabilities.
[0070] Step 6: Perform a planarization process, during which part of the passivation layer 106 in the flash memory area is removed.
[0071] In some embodiments, step six, the planarization process includes a chemical mechanical planarization process.
[0072] In some embodiments, after step six, the method further includes: etching the isolation dielectric layer to the desired height using a dielectric etching process, and removing the second hard mask layer 104.
[0073] Please refer to Figure 6 The chemical mechanical planarization (CMP) process is performed on a dedicated polishing machine, using a polishing slurry containing abrasive particles such as silicon dioxide or cerium dioxide and chemical additives, along with a rotating polishing pad, to globally planarize the wafer surface. This process removes excess first and second isolation dielectric layers 107 and 108 from the outside of the shallow trench isolation structure until the underlying second hard mask layer 104 is exposed, making the top surface of the shallow trench isolation structure substantially flush with the surface of the semiconductor substrate 101. During the CMP process, the polishing progress is monitored in real time using an optical endpoint detection system or a motor current monitoring system to ensure that the polishing stops at the precise location, and the inner passivation layer 106 covering the outside and top is removed simultaneously, leaving only this layer inside the trench.
[0074] Then, please refer to Figure 7The shallow trench isolation structure is subjected to wet etching back and other media etching processes, such as wet immersion in dilute hydrofluoric acid or buffer oxide etching solution combined with microwave oxide dry etching, to precisely etch downwards and adjust the height of the first isolation medium layer 107 and the second isolation medium layer 108 to the required target height.
[0075] Finally, please refer to Figure 8 The pad nitride layer 104, which serves as the second hard mask layer 104, is completely removed by a wet removal process such as hot phosphoric acid solution. Since hot phosphoric acid has a high etching rate for silicon nitride materials and an extremely high etching selectivity for oxide materials, it can expose the top surface of the bottom floating gate 103 without damaging the underlying isolation structure, thus completing the isolation and structural shaping of the flash memory array region.
[0076] A floating-gate flash memory device, manufactured using the floating-gate flash memory coupling dielectric layer protection method of any of the above embodiments, includes:
[0077] Semiconductor substrate 101, a shallow trench isolation structure is formed therein;
[0078] A floating gate 103 is formed on a semiconductor substrate 101;
[0079] A coupling dielectric layer 102 is located between the semiconductor substrate 101 and the floating gate 103;
[0080] The inner lining medium layer 105 is located on the inner surface of the shallow trench isolation structure;
[0081] The inner passivation layer 106 is located on the surface of the inner dielectric layer 105;
[0082] An isolation medium layer is filled in a shallow trench isolation structure located within the inner liner passivation layer 106;
[0083] The inner passivation layer 106 is used to prevent the diffusion of reactive gases into the coupling medium layer 102 during the annealing process.
[0084] Combination Figure 8 The structure shown retains the inner passivation layer 106 covering the inner wall of the shallow trench isolation structure. This film not only preserves the pre-isolation manufacturing process but also continuously provides a reliable physical barrier throughout the device's entire operational lifecycle and subsequent thermal cycling processes. It prevents oxygen or moisture from diffusing to the interface between the sensitive coupling dielectric layer 102 and the floating gate 103, maintaining the integrity of the device structure and optimizing the built-in electric field distribution, thereby ensuring the long-term stability of the overall electrical performance of the flash memory device.
[0085] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0086] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for protecting the coupling dielectric layer of a floating-gate type flash memory, characterized in that, At least including: Step 1: Provide a semiconductor substrate, the semiconductor substrate including a flash memory region, the flash memory region having a floating gate and a coupling dielectric layer located between the semiconductor substrate and the floating gate, and the semiconductor substrate having a shallow trench isolation structure; Step 2: Form an inner lining medium layer in the shallow trench isolation structure; Step 3: Deposit a liner passivation layer on the surface of the liner medium layer; Step 4: Fill the shallow trench isolation structure, to which the inner lining passivation layer has been deposited, with an isolation medium layer; Step 5: Perform annealing treatment, using the inner lining passivation layer to block the diffusion of reaction gases during the annealing process into the coupling medium layer; Step 6: Perform a planarization process, during which part of the inner liner passivation layer in the flash memory area is removed.
2. The method for protecting the coupling dielectric layer of a floating gate type flash memory according to claim 1, characterized in that: In step one, the process of forming the shallow trench isolation structure includes: sequentially depositing a first hard mask layer and a second hard mask layer as a hard mask on the surface of the semiconductor substrate.
3. The method for protecting the coupling dielectric layer of a floating gate type flash memory according to claim 2, characterized in that: In step one, the first hard mask layer includes a pad oxide layer, and the second hard mask layer includes a pad nitride layer.
4. The floating gate type flash memory coupling dielectric layer protection method according to claim 2, characterized in that: In step one, the process of forming the shallow trench isolation structure further includes etching trenches in the semiconductor substrate using photolithography and anisotropic dry etching.
5. The method for protecting the coupling dielectric layer of a floating gate type flash memory according to claim 1, characterized in that: In step two, the inner lining medium layer includes an inner lining oxide layer.
6. The method for protecting the coupling dielectric layer of a floating gate type flash memory according to claim 1, characterized in that: In step three, the inner liner passivation layer includes a silicon nitride layer.
7. The method for protecting the coupling dielectric layer of a floating-gate type flash memory according to claim 1, characterized in that: In step three, the inner liner passivation layer is deposited using an atomic layer deposition process.
8. The method for protecting the coupling dielectric layer of a floating gate type flash memory according to claim 1, characterized in that: In step three, the thickness of the inner liner passivation layer is 40 to 60 angstroms.
9. The method for protecting the coupling dielectric layer of a floating-gate type flash memory according to claim 1, characterized in that: In step four, the isolation medium layer includes an oxide layer.
10. The method for protecting the coupling dielectric layer of a floating-gate type flash memory according to claim 1, characterized in that: In step four, filling the isolation dielectric layer includes: depositing a first isolation dielectric layer using an atomic layer deposition process and performing a back etching process, and depositing a second isolation dielectric layer using a high aspect ratio process or a high-density plasma chemical vapor deposition process.
11. The method for protecting the coupling dielectric layer of a floating gate type flash memory according to claim 1, characterized in that: In step five, the annealing process includes a high-temperature annealing process containing water vapor, and the reaction gas includes the water vapor.
12. The method for protecting the coupling dielectric layer of a floating gate type flash memory according to claim 1, characterized in that: In step six, the planarization process includes a chemical mechanical planarization process.
13. The method for protecting the coupling dielectric layer of a floating gate type flash memory according to claim 2, characterized in that: After step six, the process further includes: etching the isolation dielectric layer to the required height using a dielectric etching process, and removing the second hard mask layer.
14. A floating-gate flash memory device, characterized in that, Manufactured using the floating-gate type flash memory coupling dielectric layer protection method as described in any one of claims 1 to 13, comprising: A semiconductor substrate, wherein a shallow trench isolation structure is formed therein; A floating gate is formed on the semiconductor substrate; A coupling dielectric layer is located between the semiconductor substrate and the floating gate; An inner lining medium layer is located on the inner surface of the shallow trench isolation structure; An inner passivation layer is located on the surface of the inner dielectric layer; An isolation medium layer is filled in the shallow trench isolation structure located within the inner liner passivation layer; The inner passivation layer is used to prevent the diffusion of reactive gases into the coupling medium layer during the annealing process.