Chip package structure and chip package method

Abstract

The present disclosure relates to the field of semiconductor, and provides a chip packaging structure and a chip packaging method. The chip packaging structure comprises: a first semiconductor structure and a second semiconductor structure; wherein the first semiconductor structure comprises a logic chip, and the second semiconductor structure comprises a memory chip. The first semiconductor structure and the second semiconductor structure are stacked on a first redistribution layer in a first direction; wherein the first semiconductor structure is located on the first redistribution layer, and the second semiconductor structure is located on a side of the first semiconductor structure away from the first redistribution layer. The first semiconductor structure and the second semiconductor structure are connected through a second redistribution layer; wherein the first semiconductor structure and the second semiconductor structure directly contact the second redistribution layer.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a chip packaging structure and a chip packaging method. Background Technology

[0002] With the rapid development of integrated circuit technology, chip packaging technology, as the core link connecting semiconductor dies to external systems, has an increasingly significant impact on device performance, reliability, and integration density. Although existing packaging technologies have achieved basic functional protection, they still need to be optimized to adapt to higher integration and performance requirements. Summary of the Invention

[0003] In view of this, the present disclosure provides a chip packaging structure and a chip packaging method.

[0004] In a first aspect, embodiments of this disclosure provide a chip packaging structure, including: a first semiconductor structure and a second semiconductor structure; the first semiconductor structure includes: a logic chip; the second semiconductor structure includes: a memory chip; the first semiconductor structure and the second semiconductor structure are stacked on a first redistribution layer along a first direction; wherein, the first semiconductor structure is located on the first redistribution layer, and the second semiconductor structure is located on the side of the first semiconductor structure away from the first redistribution layer; the first semiconductor structure and the second semiconductor structure are connected through a second redistribution layer; wherein, the first semiconductor structure and the second semiconductor structure are in direct contact with the second redistribution layer.

[0005] In some embodiments of this disclosure, the first semiconductor structure further includes: a first lead; the second semiconductor structure further includes: a second lead; the first lead is disposed on the periphery of the logic chip; the first lead extends along the first direction; the two ends of the first lead are respectively connected to the first redistribution layer and the second redistribution layer; the second lead is disposed on the periphery of the memory chip; the two ends of the second lead are respectively connected to the top surface of the memory chip and the second redistribution layer.

[0006] In some embodiments of this disclosure, solder balls are disposed on the surface of the first redistribution layer away from the first semiconductor structure; the logic chip is connected to the solder balls through the first redistribution layer.

[0007] In some embodiments of this disclosure, the chip packaging structure further includes: a first molding compound and a second molding compound; the first molding compound encapsulates the logic chip and the first lead; the second molding compound encapsulates the memory chip and the second lead.

[0008] In some embodiments of this disclosure, a third wiring layer and pads are disposed on the surface of the logic chip near the first wiring layer; the logic chip is bonded to the first wiring layer through the third wiring layer and the pads.

[0009] In some embodiments of this disclosure, the second semiconductor structure includes a plurality of the memory chips; in the second semiconductor structure, the plurality of memory chips are stacked along the first direction, and adjacent memory chips are staggered relative to each other.

[0010] Secondly, embodiments of this disclosure provide a chip packaging method, comprising: providing a first semiconductor structure and a second semiconductor structure; wherein the first semiconductor structure includes a logic chip; the second semiconductor structure includes a memory chip; forming a first redistribution layer; disposing the first semiconductor structure on the first redistribution layer along a first direction, and disposing the second semiconductor structure on the side of the first semiconductor structure away from the first redistribution layer; wherein the first semiconductor structure and the second semiconductor structure are connected through a second redistribution layer; the first semiconductor structure and the second semiconductor structure are in direct contact with the second redistribution layer.

[0011] In some embodiments of this disclosure, the step of disposing the first semiconductor structure on the first redistribution layer includes: forming a first lead extending along the first direction at a position near the boundary of the first redistribution layer; bonding the logic chip to the first redistribution layer; wherein the first lead is distributed around the logic chip; and forming a first molding compound layer that encapsulates the logic chip and the first lead, thereby forming the first semiconductor structure.

[0012] In some embodiments of this disclosure, after bonding the logic chip to the first redistribution layer, the chip packaging method further includes: grinding the surface of the first semiconductor structure away from the first redistribution layer to reduce the thickness of the logic chip, and shortening the length of the first lead.

[0013] In some embodiments of this disclosure, the step of disposing the second semiconductor structure on the side of the first semiconductor structure away from the first redistribution layer includes: forming the second redistribution layer on the surface of the first semiconductor structure away from the first redistribution layer; bonding the memory chip to the second redistribution layer; and forming a second molding compound layer that encapsulates the memory chip and the second leads, thereby forming the second semiconductor structure.

[0014] In some embodiments of this disclosure, the chip packaging method further includes: disposing solder balls on the surface of the first redistribution layer away from the first semiconductor structure; wherein the logic chip is connected to the solder balls through the first redistribution layer.

[0015] It is understandable that the first semiconductor structure and the second semiconductor structure are directly connected using a second wiring layer, without any other structures (such as a substrate or solder balls). In this way, on the one hand, the thickness of the chip package structure along the first direction can be significantly reduced, better meeting the requirements of miniaturization; on the other hand, the structure that needs to be formed between the first semiconductor structure and the second semiconductor structure is simplified, thereby simplifying the process steps. Attached Figure Description

[0016] Figure 1 A schematic diagram of the chip packaging structure provided in the embodiments of this disclosure. Figure 1 ;

[0017] Figure 2 A schematic diagram of the chip packaging structure provided in the embodiments of this disclosure. Figure 2 ;

[0018] Figure 3 Flowchart of the chip packaging method provided in the embodiments of this disclosure Figure 1 ;

[0019] Figure 4 Flowchart of the chip packaging method provided in the embodiments of this disclosure Figure 2 ;

[0020] Figure 5 Flowchart of the chip packaging method provided in the embodiments of this disclosure Figure 3 ;

[0021] Figure 6 Schematic diagram of the chip packaging method provided in the embodiments of this disclosure Figure 1 ;

[0022] Figure 7 Schematic diagram of the chip packaging method provided in the embodiments of this disclosure Figure 2 ;

[0023] Figure 8 Schematic diagram of the chip packaging method provided in the embodiments of this disclosure Figure 3 ;

[0024] Figure 9 Schematic diagram of the chip packaging method provided in the embodiments of this disclosure Figure 4 ;

[0025] Figure 10 Schematic diagram of the chip packaging method provided in the embodiments of this disclosure Figure 5 ;

[0026] Figure 11 Schematic diagram of the chip packaging method provided in the embodiments of this disclosure Figure 6 . Detailed Implementation

[0027] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0028] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0029] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0030] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0031] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0033] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0034] Figure 1 This is a schematic diagram of the chip packaging structure provided in the embodiments of this disclosure. Figure 1 ,like Figure 1 As shown, the chip packaging structure includes a first semiconductor structure 10 and a second semiconductor structure 20. The first semiconductor structure 10 includes a logic chip, and the second semiconductor structure 20 includes a memory chip. The first semiconductor structure 10 and the second semiconductor structure 20 are interconnected; thus, the second semiconductor structure 20 can serve as a memory structure (e.g., RAM) for the first semiconductor structure 10.

[0035] refer to Figure 1In this embodiment, a package-on-package (POP) structure is adopted, meaning that the first semiconductor structure 10 and the second semiconductor structure 20 are stacked on top of each other in different planes. This reduces the planar dimensions of the chip package structure, making the package size close to that of a die, thus meeting miniaturization requirements and making it suitable for use in mobile devices and other electronic devices. Furthermore, it enables vertical interconnection between the first semiconductor structure 10 and the second semiconductor structure 20, thereby reducing wiring length and parasitic effects in the chip package structure and optimizing signal transmission efficiency.

[0036] In some embodiments of this disclosure, the logic chip in the first semiconductor structure 10 can be a SOC chip (System-on-a-Chip). Correspondingly, the memory chip in the second semiconductor structure 20 can be a DDR (Dynamic Random Access Memory) chip, including an LPDDR (Low Power Double Data Rate Synchronous Dynamic Random Access Memory) chip. Using a POP (Package-on-Package) structure for the SOC chip and LPDDR chip allows for application in high-performance mobile devices, such as smartphones, smartwatches, AR (Augmented Reality) devices, or VR (Virtual Reality) devices.

[0037] In some embodiments of this disclosure, the logic chip in the first semiconductor structure 10 may also be an MCU (Microcontroller Unit), a CPU (Central Processing Unit), or a GPU (Graphics Processing Unit). The memory chip in the second semiconductor structure 20 may also be a NAND Flash (non-volatile flash memory).

[0038] Figure 2 This is a schematic diagram of the chip packaging structure provided in the embodiments of this disclosure. Figure 2 ,like Figure 2 As shown, the chip packaging structure includes a first semiconductor structure 10 and a second semiconductor structure 20. The first semiconductor structure 10 includes a logic chip 101, and the second semiconductor structure 20 includes a memory chip 201.

[0039] In this embodiment of the disclosure, reference is made to Figure 2 The chip packaging structure also includes a first redistribution layer 301 and a second redistribution layer 302. A first semiconductor structure 10 and a second semiconductor structure 20 are stacked on the first redistribution layer 301 along a first direction Z. The first semiconductor structure 10 is located on the first redistribution layer 301, and the second semiconductor structure 20 is located on the side of the first semiconductor structure 10 away from the first redistribution layer 301. The first semiconductor structure 10 and the second semiconductor structure 20 are connected through the second redistribution layer 302.

[0040] It should be noted that the ReDistribution Layer (RDL) is used to redistribute the positions of the chip's input / output (I / O) contacts to optimize signal transmission paths, increase integration density, and adapt to different package types.

[0041] In this embodiment of the present disclosure, signal transmission can be achieved between the first semiconductor structure 10 and the second semiconductor structure 20 through a second redistribution layer 302. The first redistribution layer 301 is used to achieve signal transmission between the first semiconductor structure 10 and other external structures.

[0042] In this embodiment of the disclosure, reference is made to Figure 2 The surfaces of the first semiconductor structure 10 and the second semiconductor structure 20 facing each other are in direct contact with the second redistribution layer 302. That is, only the second redistribution layer 302 is provided between the first semiconductor structure 10 and the second semiconductor structure 20, and no substrate or solder balls or other structures are provided. Therefore, the thickness of the chip package structure along the first direction Z can be significantly reduced.

[0043] It is understood that the first semiconductor structure 10 and the second semiconductor structure 20 are directly connected by a second redistribution layer 302 without any other structures (such as a substrate or solder balls). In this way, on the one hand, the thickness of the chip package structure along the first direction Z can be significantly reduced, which better meets the requirements of miniaturization; on the other hand, the structure that needs to be formed between the first semiconductor structure 10 and the second semiconductor structure 20 is simplified, thereby simplifying the process steps.

[0044] In some embodiments of this disclosure, reference is made to Figure 2 The first semiconductor structure 10 also includes a first lead 102. The first lead 102 is disposed on the periphery of the logic chip 101. The first lead 102 extends along a first direction Z (i.e., the vertical direction), therefore, the first lead 102 can be referred to as a vertical wire.

[0045] In this embodiment of the disclosure, reference is made to Figure 2 The two ends of the first lead 102 are connected to the first rewiring layer 301 and the second rewiring layer 302, respectively. That is to say, the first rewiring layer 301 and the second rewiring layer 302 are directly interconnected through the first lead 102. In this way, the signal transmission path between the first rewiring layer 301 and the second rewiring layer 302 can be shortened and the signal transmission rate can be improved.

[0046] It should be noted that compared to other interconnect structures, such as through-hole (TIV) or solder balls, vertical leads have a smaller size in the horizontal plane (i.e., a plane perpendicular to the first direction Z). Furthermore, the pitch between vertical leads is smaller, allowing for a denser distribution. Therefore, in this embodiment, using vertical leads (i.e., the first lead 102) as the interconnect structure between the first redistribution layer 301 and the second redistribution layer 302 reduces the size of the chip package structure in the horizontal plane and can accommodate more input / output (I / O) interfaces, improving signal transmission rate and bandwidth.

[0047] In some embodiments of this disclosure, reference is made to Figure 2 The second semiconductor structure 20 also includes a second lead 202. The second lead 202 is disposed on the periphery of the memory chip 201.

[0048] In this embodiment of the disclosure, reference is made to Figure 2 The two ends of the second lead 202 are respectively connected to the top surface of the memory chip 201 and the second wiring layer 302. That is to say, the top surface of the memory chip 201 and the second wiring layer 302 are directly interconnected through the first lead 102. In this way, the signal transmission path between the circuit structure near the top surface of the memory chip 201 and the second wiring layer 302 can be shortened, thereby improving the signal transmission rate.

[0049] In this embodiment of the disclosure, reference is made to Figure 2 The first lead 102 and the second lead 202 may be made of metallic materials, including but not limited to one or more of copper (Cu), aluminum (Al), silver (Ag) and titanium (Ti).

[0050] In some embodiments of this disclosure, reference is made to Figure 2 Solder balls 401 are disposed on the surface of the first wiring layer 301 away from the first semiconductor structure 10. The logic chip 101 is connected to the solder balls 401 through the first wiring layer 301.

[0051] In this embodiment of the disclosure, reference is made to Figure 2 The solder ball 401 may be made of a tin alloy (such as Sn-Ag / Cu). The solder ball 401 can be soldered onto the substrate or to other chips to achieve signal conduction and mechanical fixation. Through the first redistribution layer 301 and the solder ball 401, the first semiconductor structure 10 and the second semiconductor structure 20 can achieve signal transmission with the substrate or other chips.

[0052] In some embodiments of this disclosure, reference is made to Figure 2The chip packaging structure also includes a first molding compound 103 and a second molding compound 203. The first molding compound 103 encapsulates the logic chip 101 and the first lead 102, and the second molding compound 203 encapsulates the memory chip 201 and the second lead 202. The materials of the first molding compound 103 and the second molding compound 203 may include epoxy resin, polyimide, polyethylene (PE), polypropylene (PP), and other molding materials.

[0053] In some embodiments of this disclosure, reference is made to Figure 2 On the surface of the logic chip 101 near the first wiring layer 301, a third wiring layer 303 and pads 402 are disposed. The logic chip 101 is bonded to the first wiring layer 301 through the third wiring layer 301 and pads 402. The bonding process may include flip-chip bonding or hybrid bonding.

[0054] In some embodiments of this disclosure, reference is made to Figure 2 The second semiconductor structure 20 includes a plurality of memory chips 201. In the second semiconductor structure 20, the plurality of memory chips 201 are stacked along a first direction Z, and adjacent memory chips 201 are staggered. On the one hand, the stacked plurality of memory chips 201 can achieve a larger storage capacity with a smaller planar size, thus improving integration; on the other hand, the staggered arrangement of adjacent memory chips 201 is beneficial for optimizing the interconnect structure and also for chip heat dissipation.

[0055] Based on a concept similar to the chip packaging structure described above, this disclosure also provides a chip packaging method. It should be noted that... Figures 6 to 11 This is a structural diagram of each step in the chip packaging method, used to illustrate each step.

[0056] Figure 3 This is a schematic flowchart of an optional chip packaging method provided in this disclosure. Figure 3 As shown, the chip packaging method includes steps S101 to S103, which will be explained in conjunction with each step.

[0057] S101. A first semiconductor structure and a second semiconductor structure are provided; wherein the first semiconductor structure includes a logic chip; and the second semiconductor structure includes a memory chip.

[0058] In this embodiment of the disclosure, reference is made to Figure 2 The first semiconductor structure 10 includes a logic chip 101, and the second semiconductor structure 20 includes a memory chip 201. The second semiconductor structure 20 can serve as a memory structure (e.g., a memory) for the first semiconductor structure 10.

[0059] In some embodiments of this disclosure, the logic chip 101 in the first semiconductor structure 10 is a SOC chip (System-on-a-Chip); correspondingly, the memory chip 201 in the second semiconductor structure 20 is a DDR (Dynamic Random Access Memory) chip, including LPDDR (Low Power Double Data Rate Synchronous Dynamic Random Access Memory) chip. Therefore, the chip packaging structure formed by the embodiments of this disclosure can be applied to high-performance mobile devices, such as smartphones, smartwatches, AR (Augmented Reality) devices, or VR (Virtual Reality) devices.

[0060] S102, Form the first rewiring layer.

[0061] In this embodiment of the disclosure, reference is made to Figure 2 The first redistribution layer 301 is a separate redistribution layer and does not include a substrate. The first redistribution layer 301 is bonded to the logic chip 101 in the first semiconductor structure 10. The first redistribution layer 301 can be formed on the substrate and then the substrate can be removed. This avoids placing the substrate in the chip package structure and can reduce the thickness of the chip package structure along the first direction Z.

[0062] S103. Along the first direction, a first semiconductor structure is disposed on a first redistribution layer, and a second semiconductor structure is disposed on the side of the first semiconductor structure away from the first redistribution layer; wherein the first semiconductor structure and the second semiconductor structure are connected through the second redistribution layer; the first semiconductor structure and the second semiconductor structure are in direct contact with the second redistribution layer.

[0063] In this embodiment of the disclosure, reference is made to Figure 2 The first semiconductor structure 10 and the second semiconductor structure 20 are stacked on top of each other in different planes. In this way, on the one hand, the planar size of the chip package structure can be reduced, making the package size close to that of a die, thereby meeting the miniaturization requirements and making it suitable for electronic devices such as mobile devices; on the other hand, the vertical interconnection of the first semiconductor structure 10 and the second semiconductor structure 20 can be realized, thereby reducing the wiring length and parasitic effects in the chip package structure and optimizing signal transmission efficiency.

[0064] Continue to refer to Figure 2 Signal transmission can be achieved between the first semiconductor structure 10 and the second semiconductor structure 20 through the second wiring layer 302. The facing surfaces of the first semiconductor structure 10 and the second semiconductor structure 20 are in direct contact with the second wiring layer 302. That is to say, only the second wiring layer 302 is provided between the first semiconductor structure 10 and the second semiconductor structure 20, and no substrate or solder balls or other structures are provided, thereby significantly reducing the thickness of the chip package structure along the first direction Z.

[0065] It is understood that the first semiconductor structure 10 and the second semiconductor structure 20 are directly connected by a second redistribution layer 302 without any other structures (such as a substrate or solder balls). In this way, on the one hand, the thickness of the chip package structure along the first direction Z can be significantly reduced, which better meets the requirements of miniaturization; on the other hand, the structure that needs to be formed between the first semiconductor structure 10 and the second semiconductor structure 20 is simplified, thereby simplifying the process steps.

[0066] In some embodiments of this disclosure, the chip packaging method further includes Figure 3 Step S104 shown will be explained in conjunction with each step.

[0067] S104. Solder balls are disposed on the surface of the first wiring layer away from the first semiconductor structure; wherein the logic chip is connected to the solder balls through the first wiring layer.

[0068] In this embodiment of the disclosure, reference is made to Figure 11 The solder ball 401 may be made of a tin alloy (such as Sn-Ag / Cu). The solder ball 401 can be soldered onto the substrate or to other chips to achieve signal conduction and mechanical fixation. Through the first redistribution layer 301 and the solder ball 401, the first semiconductor structure 10 and the second semiconductor structure 20 can achieve signal transmission with the substrate or other chips.

[0069] In some embodiments of this disclosure, the process of disposing the first semiconductor structure on the first redistribution layer includes: Figure 4 Steps S201 to S203 shown will be explained in conjunction with each step.

[0070] S201. A first lead extending in a first direction is formed at a position near the boundary on the first rewiring layer.

[0071] In this embodiment of the disclosure, reference is made to Figure 6 A first lead 102 is formed near the boundary on the first redistribution layer 301. The first lead 102 extends along a first direction Z (i.e., the vertical direction), therefore, the first lead 102 can be referred to as a vertical wire. The first lead 102 can be made of a metallic material, including but not limited to one or more of copper (Cu), aluminum (Al), silver (Ag), and titanium (Ti).

[0072] S202, The logic chip is bonded to the first wiring layer; wherein the first leads are distributed on the periphery of the logic chip.

[0073] In this embodiment of the disclosure, combined with Figure 6 and Figure 7On the surface of the logic chip 101, a third wiring layer 303 and pads 402 are provided. The logic chip 101 is bonded to the first wiring layer 301 through the third wiring layer 303 and pads 402. The bonding process may include flip-chip bonding or hybrid bonding.

[0074] S203, A first molding compound is formed to encapsulate the logic chip and the first lead, thereby forming a first semiconductor structure.

[0075] In this embodiment of the disclosure, reference is made to Figure 8 The first molding compound 103 encapsulates the logic chip 101 and the first lead 102, providing support and protection for them. The material of the first molding compound 103 may include epoxy resin, polyimide, polyethylene (PE), polypropylene (PP), and other molding materials.

[0076] In some embodiments of this disclosure, the process of disposing the second semiconductor structure on the side of the first semiconductor structure away from the first redistribution layer includes: Figure 5 Steps S204 to S206 shown will be explained in conjunction with each step.

[0077] S204. A second wiring layer is formed on the surface of the first semiconductor structure away from the first wiring layer.

[0078] In this embodiment of the disclosure, reference is made to Figure 9 The second redistribution layer 302 is formed on the surface of the first semiconductor structure 10 away from the first redistribution layer 301. That is, the first semiconductor structure 10 is in direct contact with the second redistribution layer 302 without any other structures (such as substrates or solder balls). In this way, on the one hand, the thickness of the chip package structure along the first direction Z can be significantly reduced, which better meets the requirements of miniaturization; on the other hand, the required structure is simplified, thereby simplifying the process steps.

[0079] In this embodiment of the disclosure, reference is made to Figure 9 The first lead 102, distributed around the logic chip 101, connects the first wiring layer 301 and the second wiring layer 302 respectively. In other words, the first wiring layer 301 and the second wiring layer 302 are directly interconnected through the first lead 102. This shortens the signal transmission path between the first wiring layer 301 and the second wiring layer 302 and improves the signal transmission rate.

[0080] It should be noted that compared to other interconnect structures, such as through-hole (TIV) or solder balls, vertical leads have a smaller size in the horizontal plane (i.e., a plane perpendicular to the first direction Z). Furthermore, the pitch between vertical leads is smaller, allowing for a denser distribution. Therefore, in this embodiment, using vertical leads (i.e., the first lead 102) as the interconnect structure between the first redistribution layer 301 and the second redistribution layer 302 reduces the size of the chip package structure in the horizontal plane and can accommodate more input / output (I / O) interfaces, improving signal transmission rate and bandwidth.

[0081] S205, Bond the memory chip to the second wiring layer.

[0082] In this embodiment of the disclosure, reference is made to Figure 10 The memory chip 201 is bonded to the second wiring layer 302, so that the second semiconductor structure 20 is also in direct contact with the second wiring layer 302 without any other structures (such as substrates or solder balls). In this way, on the one hand, the thickness of the chip package structure along the first direction Z can be significantly reduced, which better meets the requirements of miniaturization; on the other hand, the required structure is simplified, thereby simplifying the process steps.

[0083] In some embodiments of this disclosure, reference is made to Figure 10 The second semiconductor structure 20 includes a plurality of memory chips 201. In the second semiconductor structure 20, the plurality of memory chips 201 are stacked along a first direction Z, and adjacent memory chips 201 are staggered. On the one hand, the stacked plurality of memory chips 201 can achieve a larger storage capacity with a smaller planar size, thus improving integration; on the other hand, the staggered arrangement of adjacent memory chips 201 is beneficial for optimizing the interconnect structure and also for chip heat dissipation.

[0084] S206, A second molding compound is formed to encapsulate the memory chip and the second lead, thereby forming a second semiconductor structure.

[0085] In this embodiment of the disclosure, reference is made to Figure 10 The second molding layer 203 encapsulates the memory chip 201 and the second lead 202, providing support and protection for both. The material of the second molding layer 203 may include epoxy resin, polyimide, polyethylene (PE), polypropylene (PP), and other molding materials.

[0086] In some embodiments of this disclosure, in Figure 4 Following step S202, the chip packaging method further includes step S207, which will be explained in conjunction with each step.

[0087] S207. Grind the surface of the first semiconductor structure away from the first redistribution layer to reduce the thickness of the logic chip and shorten the length of the first lead.

[0088] In this embodiment of the disclosure, reference is made to Figure 8 and Figure 9 By grinding the surface of the first semiconductor structure 10 away from the first redistribution layer 301, the thickness of the logic chip 101 can be reduced, and the length of the first lead 102 can be shortened. In this way, on the one hand, the thickness of the chip package structure along the first direction Z can be reduced, which better meets the requirements of miniaturization; on the other hand, the length of the connection between the first redistribution layer 301 and the second redistribution layer 302 (i.e., the first lead 102) is shortened, which can improve signal transmission efficiency and reduce signal transmission power consumption.

[0089] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0090] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A chip packaging structure, characterized in that, include: First semiconductor structure and second semiconductor structure; The first semiconductor structure includes a logic chip; the second semiconductor structure includes a memory chip. The first semiconductor structure and the second semiconductor structure are stacked on a first redistribution layer along a first direction; wherein the first semiconductor structure is located on the first redistribution layer, and the second semiconductor structure is located on the side of the first semiconductor structure away from the first redistribution layer; The first semiconductor structure and the second semiconductor structure are connected by a second rewiring layer; wherein the first semiconductor structure and the second semiconductor structure are in direct contact with the second rewiring layer.

2. The chip packaging structure according to claim 1, characterized in that, The first semiconductor structure further includes: a first lead; the second semiconductor structure further includes: a second lead; The first lead is disposed on the periphery of the logic chip; the first lead extends along the first direction; the two ends of the first lead are respectively connected to the first redistribution layer and the second redistribution layer; The second lead is disposed on the periphery of the memory chip; the two ends of the second lead are respectively connected to the top surface of the memory chip and the second redistribution layer.

3. The chip packaging structure according to claim 1, characterized in that, Solder balls are disposed on the surface of the first redistribution layer away from the first semiconductor structure; The logic chip is connected to the solder balls through the first wiring layer.

4. The chip packaging structure according to claim 2, characterized in that, The chip packaging structure further includes: a first molding layer and a second molding layer; The first molding compound encapsulates the logic chip and the first lead; The second molding compound encapsulates the memory chip and the second lead.

5. The chip packaging structure according to claim 1, characterized in that, The logic chip has a third wiring layer and pads on its surface near the first wiring layer; the logic chip is bonded to the first wiring layer through the third wiring layer and the pads.

6. The chip packaging structure according to claim 5, characterized in that, The second semiconductor structure includes a plurality of the memory chips; In the second semiconductor structure, a plurality of the memory chips are stacked along the first direction, and adjacent memory chips are staggered.

7. A chip packaging method, characterized in that, include: A first semiconductor structure and a second semiconductor structure are provided; wherein the first semiconductor structure includes a logic chip; and the second semiconductor structure includes a memory chip. Form the first wiring layer; Along a first direction, the first semiconductor structure is disposed on the first redistribution layer, and the second semiconductor structure is disposed on the side of the first semiconductor structure away from the first redistribution layer; wherein the first semiconductor structure and the second semiconductor structure are connected through a second redistribution layer; the first semiconductor structure and the second semiconductor structure are in direct contact with the second redistribution layer.

8. The chip packaging method according to claim 7, characterized in that, The step of placing the first semiconductor structure on the first redistribution layer includes: A first lead extending in the first direction is formed near the boundary on the first redistribution layer. The logic chip is bonded to the first redistribution layer; wherein the first leads are distributed around the logic chip. A first molding compound is formed to encapsulate the logic chip and the first lead, thereby forming the first semiconductor structure.

9. The chip packaging method according to claim 8, characterized in that, After bonding the logic chip to the first redistribution layer, the chip packaging method further includes: The surface of the first semiconductor structure away from the first redistribution layer is ground to reduce the thickness of the logic chip and shorten the length of the first lead.

10. The chip packaging method according to claim 8 or 9, characterized in that, The step of disposing the second semiconductor structure on the side of the first semiconductor structure away from the first redistribution layer includes: A second redistribution layer is formed on the surface of the first semiconductor structure away from the first redistribution layer; The memory chip is bonded to the second wiring layer; A second molding compound is formed to encapsulate the memory chip and the second lead, thereby forming the second semiconductor structure.

11. The chip packaging method according to claim 7, characterized in that, The chip packaging method further includes: Solder balls are disposed on the surface of the first redistribution layer away from the first semiconductor structure; wherein the logic chip is connected to the solder balls through the first redistribution layer.

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