High-density hbf memory structure and forming method thereof, electronic device

Abstract

The application provides a high-density HBF storage structure and a forming method thereof and an electronic device. The high-density HBF storage structure comprises a plurality of three-dimensional NAND chips stacked along a vertical direction. The three-dimensional NAND chip comprises word line layers and isolation layers alternately stacked along the vertical direction, and a plurality of stepped contacts extending along the vertical direction. The plurality of word line layers extend along a first direction and are arranged in a stepped manner at one end; the first direction is perpendicular to the vertical direction. Each stepped contact is connected to the stepped end of the corresponding word line layer. The high-density HBF storage structure further comprises a through-silicon via structure extending along the vertical direction. At least one three-dimensional NAND chip is electrically connected through the through-silicon via structure. The through-silicon via structure is arranged in an isolation region and / or a redundant region in the three-dimensional NAND chip. By arranging the through-silicon via structure in the isolation region and / or the redundant region, the chip area occupied by the through-silicon via structure can be effectively reduced while retaining the original functions of the region.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a high-density HBF memory structure, a method for forming the same, and an electronic device. Background Technology

[0002] Among related technologies, High Bandwidth Flash (HBF) achieves an order-of-magnitude increase in flash memory bandwidth through 3D stacking and wide interface technology. This effectively matches the storage bandwidth requirements of scenarios such as AI accelerators and high-performance computing (HPC), and is considered one of the key technological paths to overcome the bandwidth bottleneck of traditional flash memory interfaces. As the number of stacked layers in 3D NAND flash memory chips increases, the lateral dimension of the stepped contact (SCT) area must expand accordingly, resulting in a larger wafer area. Furthermore, to reduce contact resistance and process complexity, additional redundant steps are typically retained in the SCT area, further exacerbating area waste. Simultaneously, since HBF technology requires vertical interconnection via through-silicon vias (TSVs), the location of the TSVs generates additional area overhead. These issues limit further increases in HBF storage density. Summary of the Invention

[0003] This application provides a high-density HBF memory structure and its formation method, as well as an electronic device. By setting through-silicon via (TSV) structures in the isolation region and / or redundant region, the effective chip area required for the deployment of the TSV structure can be effectively reduced while retaining the original functions of the region.

[0004] The technical solution of this application embodiment is implemented as follows:

[0005] This application provides a high-density HBF memory structure, comprising: a plurality of three-dimensional NAND chips stacked vertically; each three-dimensional NAND chip comprising: word line layers and isolation layers alternately stacked along the vertical direction, and a plurality of stepped contacts extending along the vertical direction; the plurality of word line layers extending along a first direction, with one end arranged in a stepped manner; the first direction being perpendicular to the vertical direction; each stepped contact being connected to the stepped end of the corresponding word line layer; the high-density HBF memory structure further comprising: a through-silicon via (TSV) structure extending along the vertical direction; at least one of the three-dimensional NAND chips being electrically connected through the TSV structure; the TSV structure being disposed in the isolation region and / or redundant region of the three-dimensional NAND chip.

[0006] In some embodiments of this application, the redundant region includes: a stepped contact redundant region; the stepped contact redundant region is located above the stepped end of the word line layer and is a region where no stepped contact is provided.

[0007] In some embodiments of this application, the isolation region includes an isolation slot region located between two adjacent storage planes.

[0008] In some embodiments of this application, the isolation region further includes a slit region located between two adjacent storage blocks.

[0009] In some embodiments of this application, the three-dimensional NAND chip further includes: a channel via structure; the channel via structure extends along the vertical direction and penetrates word line layers and isolation layers that are alternately stacked along the vertical direction; wherein, the channel via structure includes: a charge storage layer, a tunneling dielectric layer and a channel layer that surround the chip sequentially from the outside to the inside; the through-silicon via structure is located between two adjacent channel via structures along the second direction; the first direction intersects the second direction and is perpendicular to the vertical direction.

[0010] This application embodiment also provides a method for forming a high-density HBF memory structure, the method comprising: forming a plurality of three-dimensional NAND chips; wherein, the three-dimensional NAND chip comprises: word line layers and isolation layers alternately stacked along the vertical direction, and a plurality of stepped contacts extending along the vertical direction; the plurality of word line layers extend along a first direction and are arranged in a stepped manner at one end; each stepped contact is connected to the stepped end of the corresponding word line layer; the first direction is perpendicular to the vertical direction; forming a through-silicon via (TSV) structure in at least one of the three-dimensional NAND chips; wherein, the TSV structure is disposed in an isolation region and / or a redundant region in the three-dimensional NAND chip; and stacking the plurality of three-dimensional NAND chips along the vertical direction.

[0011] In some embodiments of this application, forming multiple three-dimensional NAND chips includes: alternately depositing the word line layer and the isolation layer on a substrate to form a stacked structure; etching the stacked structure to form multiple first vias; forming multiple stepped contacts within the first vias; etching the stacked structure to form multiple second vias; and forming a channel structure within the second vias; wherein the channel structure includes a charge storage layer, a tunneling dielectric layer, and a channel layer that surround the chip sequentially from the outside to the inside.

[0012] In some embodiments of this application, the redundant region includes: a stepped contact redundant region; the stepped contact redundant region is located above the stepped end of the word line layer and is a region without the stepped contacts; forming a through-silicon via (TSV) structure in at least one of the three-dimensional NAND chips includes: etching the stacked structure vertically upwards along the stepped contact redundant region to form a third via; forming the TSV structure within the third via; wherein the TSV structure penetrates the stacked structure;

[0013] In some embodiments of this application, the isolation region further includes: an isolation trench region located between two adjacent storage planes; the step of forming a through-silicon via (TSV) structure in at least one of the three-dimensional NAND chips includes: etching the isolation trench region to form a third via; forming the TSV structure within the third via; wherein the TSV structure penetrates the isolation trench region.

[0014] In some embodiments of this application, the isolation region includes: a slit region located between two adjacent memory blocks; the formation of a through-silicon via (TSV) structure in at least one of the three-dimensional NAND chips includes: etching the slit region to form a third via; forming the TSV structure within the third via; wherein the TSV structure extends through the slit region.

[0015] This application also provides an electronic device, which includes a high-density HBF memory structure manufactured according to any of the above embodiments, or a high-density HBF memory structure manufactured by a method for forming a high-density HBF memory structure as described in any of the above embodiments.

[0016] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0017] By incorporating through-silicon vias (TSVs) in isolated and / or redundant regions, the effective chip area required for TSV deployment can be effectively reduced while preserving the original functionality of the regions. This also reduces the additional area overhead associated with vertical interconnect structures, further optimizing the internal space layout of the chip. Consequently, the overall storage density of high-bandwidth flash memory (HBF) chips can be significantly increased, enabling miniaturized and high-capacity integrated designs.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0020] Figure 1 This is a schematic diagram of the high-density HBF memory structure provided in the embodiments of this application. Figure 1 ;

[0021] Figure 2 This is a schematic diagram of the high-density HBF memory structure provided in the embodiments of this application. Figure 2 ;

[0022] Figure 3This is a schematic diagram of the high-density HBF memory structure provided in the embodiments of this application. Figure 3 ;

[0023] Figure 4 This is a schematic diagram of the high-density HBF memory structure provided in the embodiments of this application. Figure 4 ;

[0024] Figure 5 A schematic flowchart illustrating the method for forming a high-density HBF memory structure provided in this application embodiment;

[0025] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0026] The reference numerals and names in the figure are as follows:

[0027] 10-Through silicon via structure; 20-Stacked structure; 21-Word line layer; 22-Isolation layer; 23-Trench structure; 30-Isolation trench area; 40-Slit area; 50-Redundancy area; 51-Stepped contact; 60-Memory plane; 61-Control circuit; 70-Memory block; 100-3D NAND chip. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0030] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0031] In this document, when a layer / component is referred to as being "above" another layer / component, the layer / component may be directly above the other layer / component, or there may be an intermediate layer / component between them. Furthermore, in one orientation, a layer / component is "above" another layer / component; when the orientation is reversed, the layer / component may be "below" the other layer / component.

[0032] Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the embodiments of this application is for the purpose of describing the embodiments of this application only and is not intended to limit this application.

[0033] Current mainstream storage solutions mostly use independent NAND flash memory chips interconnected with a controller via a PCB board. Limited by factors such as interface width, number of package pins, circuit layout, and I / O power consumption, their transmission bandwidth is relatively low, making it difficult to meet the demands of high-speed data access. To address this, High Bandwidth Flash (HBF) has been proposed. Through 3D stacking and wide interface technology, relying on a 3D stacked structure combined with through-silicon vias (TSVs) vertical interconnects, it effectively improves the overall transmission bandwidth and energy efficiency of storage chips, becoming an important development direction for next-generation in-memory computing architectures. However, in practical applications, as the number of 3D NAND stacking layers continues to increase, the lateral size of the word line step contact area continues to expand, occupying a large amount of wafer area. At the same time, the redundant step structures added to reduce contact resistance and simplify the manufacturing process further increase wafer area loss. Furthermore, the TSV (through-silicon via) interconnect structure in the HBF structure also generates additional area overhead, thus limiting the improvement of storage density.

[0034] Based on this, this application provides a high-density HBF storage structure 200. Figure 1 This is a schematic diagram of a structure in which multiple three-dimensional NAND chips 100 are stacked along the vertical Z-axis. Figure 2 This is a schematic diagram of the structure of multiple storage planes 60 and isolation trench area 30. Figure 3 This is a schematic diagram of the structure of multiple storage blocks 70 and the slit region 40. (Refer to...) Figures 1 to 3 As shown, the high-density HBF memory structure 200 includes: multiple three-dimensional NAND chips 100 stacked along the vertical Z direction.

[0035] It should be noted that, referring to Figures 1 to 3As shown, traditional 3D NAND chips 100 are widely used non-volatile memory devices. Leveraging mature 3D stacking technology, they achieve large-capacity data storage and are widely compatible with various consumer electronics and conventional storage devices. The HBF memory architecture vertically stacks multi-layer 3D NAND chips 100 through through-silicon vias (TSVs), combined with integrated control logic through chip bonding. It boasts an ultra-wide parallel transmission interface, ultra-high bandwidth, and excellent input / output efficiency, efficiently supporting high-end applications such as AI computing, large model data loading, and in-memory computing.

[0036] In the embodiments of this application, reference is made to Figures 1 to 3 As shown, the three-dimensional NAND chip includes: word line layers 21 and isolation layers 22 alternately stacked along the vertical direction Z, and a plurality of stepped contacts 51 extending along the vertical direction; the plurality of word line layers 21 extend along the first direction X, and one end is arranged in a stepped shape; each stepped contact 51 is connected to the stepped end of the corresponding word line layer 21; the first direction X is perpendicular to the vertical direction Z.

[0037] It should be noted that, referring to Figures 1 to 3 As shown, multiple word line layers 21 extend along the first direction X and are arranged in a stepped manner at their ends, which can orderly distinguish the ends of each word line layer 21. This facilitates the leading out of stepped contacts 51 along the vertical direction Z at the stepped structure, enabling independent routing of each word line layer. This facilitates the electrical conduction between the word lines and external circuits, while also adapting to the routing layout requirements of the three-dimensional stacked storage structure, organizing the circuit layout structure, and ensuring that the overall circuit connection of the storage array is orderly and smooth.

[0038] In the embodiments of this application, reference is made to Figures 1 to 3 As shown, the high-density HBF memory structure 200 further includes: a through-silicon via (TSV) structure extending along the vertical direction Z; at least one three-dimensional NAND chip 100 electrically connected through the TSV structure 10; the TSV structure 10 being disposed in an isolation region (including...) within the three-dimensional NAND chip 100. Figure 2 The isolation trench area 30 shown is Figure 3 The slit region 40 and / or redundant region 50 are shown.

[0039] Understandably, referring to Figures 1 to 3 As shown, through-silicon via (TSV) structures 10 are set in the isolation region and / or redundant region 50. In this way, while retaining the original functions of the original region, the effective chip area required for the TSV structure layout can be effectively reduced, the additional area overhead caused by the vertical interconnect structure can be reduced, and the internal space layout of the chip can be further optimized, thereby significantly improving the overall storage density of the HBF memory chip and realizing the miniaturization and high-capacity integrated design of the chip.

[0040] In some embodiments of this application, reference is made to Figures 1 to 3As shown, the redundant region 50 includes: a stepped contact redundant region; the stepped contact redundant region is the region located above the stepped end of the word line layer 21 and where no stepped contact 51 is provided.

[0041] It should be noted that, referring to Figures 1 to 3 As shown, the stepped contact area is located above the stepped end of the multi-layer word line layer 21. The redundant stepped contact area can reduce the contact resistance and accommodate the photolithography horizontal alignment deviation with the help of the redundant steps, ensuring that the contact hole is always within the effective step range, avoiding electrical failure caused by offset, effectively relaxing the photolithography precision requirements, simplifying process control and improving production yield.

[0042] In some embodiments of this application, reference is made to Figures 1 to 3 As shown, the isolation area includes an isolation slot area 30 located between two adjacent storage planes 60.

[0043] It should be noted that, referring to Figures 1 to 3 As shown, the isolation trench region 30 can separate different memory planes 60 from each other, achieving electrical isolation between the memory planes 60. This effectively prevents problems such as signal crosstalk, leakage, and short circuits in adjacent memory planes 60. It can also divide independent process processing areas, allowing each memory plane 60 to complete its process fabrication independently and ensuring the independent and stable operation of each memory plane 60. By placing the through-silicon via (TSV) structure 10 in the isolation trench region 30, the effective chip area required for the TSV structure layout can be effectively reduced, thereby significantly improving the overall storage density of the HBF memory chip.

[0044] In some embodiments of this application, reference is made to Figures 1 to 3 As shown, the three-dimensional NAND chip 100 also includes a slit region 40 located between two adjacent memory blocks 70.

[0045] It should be noted that, referring to Figures 1 to 3 As shown, the slit region 40 provides both physical and electrical isolation for adjacent memory blocks 70, blocking inter-block leakage and signal crosstalk, and dividing the memory into independent functional areas. This ensures that the read and write operations of each memory block 70 do not interfere with each other, and also facilitates partitioned processing and yield screening during chip manufacturing, thereby improving the overall stability of the device operation. By placing the through-silicon via (TSV) structure 10 in the slit region 40, the additional area overhead caused by the TSV structure 10 can be reduced, thereby increasing the overall storage density of the HBF memory chip.

[0046] In some embodiments of this application, Figure 4 This is a schematic diagram showing the stepped end arrangement of multiple character lines. (Refer to...) Figure 1 and Figure 4As shown, the stepped contact redundancy region includes: multiple sub-redundancy regions; the vertically above area corresponding to the stepped end of each word line layer 21 is a sub-redundancy region; and a through-silicon via structure 10, which penetrates any sub-redundancy region or simultaneously penetrates two adjacent sub-redundancy regions.

[0047] It should be noted that, referring to Figure 1 and Figure 4 As shown, the stepped contact redundancy area is divided into several sub-redundancy areas. A sub-redundancy area corresponds to the position directly above the stepped end of each word line layer 21. This sub-redundancy area is located in the empty space at the end of the word line layer 21 where no stepped contact 51 is installed, serving as spare space. This space can both reserve alignment tolerances for the photolithography process and accommodate redundant stepped contacts 51, optimizing contact resistance and adapting to process errors. The through-silicon via (TSV) structure 10 can penetrate any sub-redundancy area or simultaneously penetrate two adjacent sub-redundancy areas. This reduces the chip area occupied by the TSV structure 10 and increases the storage density of the HBF chip. For example... Figure 4 The stepped ends of the four word line layers 21 arranged along the first direction X are shown, and the through-silicon via structure 10 simultaneously penetrates two adjacent sub-redundant regions.

[0048] In some embodiments of this application, reference is made to Figures 1 to 3 As shown, the three-dimensional NAND chip 100 includes: a channel hole structure 23; the channel hole structure 23 extends along the vertical direction Z and penetrates the word line layer 21 and the isolation layer 22 that are alternately stacked along the vertical direction Z; wherein, the channel hole structure 23 includes: a charge storage layer, a tunneling dielectric layer and a channel layer that are sequentially surrounded from the outside to the inside; a through-silicon via structure 10 is located between two adjacent channel hole structures 23 along the second direction Y; the first direction X intersects the second direction Y and is perpendicular to the vertical direction Z.

[0049] It should be noted that, referring to Figures 1 to 3 As shown, the via structure 23 includes a charge storage layer, a tunneling dielectric layer, and a channel layer arranged sequentially from the outside to the inside. The charge storage layer can be made of silicon nitride (Si3N4) to capture and retain charge for data storage; the tunneling dielectric layer can be made of silicon oxide (SiO2) to enable electron tunneling and charge injection and release; the channel layer can be made of polycrystalline silicon to act as a conductive path. The through-silicon via structure 10 is arranged between two adjacent via structures 23 in the second direction Y, filled with copper (Cu) for conductivity, and supplemented with an outer layer of silicon oxide (SiO2) for insulation and protection, achieving vertical interconnection, simplifying the layout without encroaching on the space used by the memory cells.

[0050] In some embodiments of this application, reference is made to Figure 2As shown, the high-density HBF storage structure 200 also includes: a plurality of control circuits 61; the control circuits 61 are located on one side of the corresponding storage plane 60 along the first direction X; the control circuits 61 are configured to drive the storage array to perform read operations and write operations.

[0051] It should be noted that, referring to Figure 2 As shown, multiple control circuits 61 are arranged on one side of the storage plane 60 along the first direction X, with a neat and orderly overall layout, capable of independently controlling the corresponding storage units. The control circuits 61 can output drive control signals to precisely drive the storage array to complete various basic storage operations such as data writing and data reading, and coordinate and regulate the working status of the storage units to ensure that the data access process is stable and orderly.

[0052] This application also provides a method for forming a high-density HBF memory structure 200, referring to... Figure 1 and Figure 5 As shown, the method for forming the high-density HBF storage structure 200 includes steps S101-S103.

[0053] Step S101: Form multiple three-dimensional NAND chips.

[0054] In the embodiments of this application, reference is made to Figures 1 to 3 As shown, multiple three-dimensional NAND chips 100 are formed on a substrate; wherein, the three-dimensional NAND chip 100 includes: word line layers 21 and isolation layers 22 alternately stacked along the vertical direction Z, and multiple stepped contacts 51 extending along the vertical direction; the multiple word line layers 21 extend along the first direction X, and one end is arranged in a stepped shape; the first direction X is perpendicular to the vertical direction Z; each stepped contact 51 is connected to the stepped end of the corresponding word line layer 21.

[0055] Step S102: Form a through-silicon via (TSV) structure in at least one three-dimensional NAND chip; wherein the TSV structure is disposed in an isolation region and / or a redundant region in the three-dimensional NAND chip.

[0056] In the embodiments of this application, reference is made to Figures 1 to 3 As shown, a through-silicon via (TSV) structure 10 is formed in at least one three-dimensional NAND chip 100; wherein the TSV structure 10 is disposed in an isolation region and / or a redundant region 50 in the three-dimensional NAND chip. The TSV structure 10 is typically filled with copper (Cu) for conductivity, and an outer layer is provided with a dielectric material for insulation and protection. The dielectric material can be silicon oxide (SiO2).

[0057] Step S103: Stack multiple three-dimensional NAND chips vertically.

[0058] In the embodiments of this application, reference is made to Figures 1 to 3As shown, multiple 3D NAND chips 100 are stacked vertically along the Z-axis to form an HBF memory architecture; the multiple 3D NAND chips 100 can be interconnected through a through-silicon via (TSV) structure 10. The HBF memory architecture has an ultra-wide parallel transmission interface, ultra-high transmission bandwidth and excellent input / output energy efficiency, and can efficiently support high-end application scenarios such as AI computing power, large model data loading and in-memory computing.

[0059] Understandably, referring to Figures 1 to 3 As shown, through-silicon via (TSV) structures 10 are set in the isolation or redundant regions 50. This effectively reduces the chip area required for the TSV structure layout while retaining the original functions of the regions, reduces the additional area overhead caused by vertical interconnect structures, further optimizes the internal space layout of the chip, and thus significantly improves the overall storage density of the HBF memory chip, achieving chip miniaturization and high-capacity integrated design.

[0060] In some embodiments of this application, reference is made to Figures 1 to 3 As shown, Figure 5 The illustrated step S101 may specifically include steps S201-S205.

[0061] Step S201: Alternately deposit word line layers and isolation layers on the substrate to form a stacked structure.

[0062] In the embodiments of this application, reference is made to Figures 1 to 3 As shown, word line layers 21 and isolation layers 22 are alternately deposited on a substrate to form a stacked structure 20. The substrate material is not specifically limited. As an example, the substrate can be made of semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be such as a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. The word line layer 21 can be composed of one or more conductive materials, including one or more of titanium (Ti), titanium nitride (TiN), and tungsten (W). The isolation layer 22 can be made of an insulating material, specifically silicon oxide (SiO2), silicon nitride (Si3N4), and silicon oxynitride (SiON).

[0063] Step S202: Etch the stacked structure to form multiple first through holes.

[0064] In the embodiments of this application, reference is made to Figures 1 to 3As shown, the stacked structure 20 is etched to form multiple first through holes. The first through holes are used to subsequently form stepped contacts 51.

[0065] Step S203: Form multiple stepped contacts within the first through hole.

[0066] In the embodiments of this application, reference is made to Figures 1 to 3 As shown, conductive material is deposited in the first through hole to form multiple stepped contacts 51; the conductive material can be tungsten (W), copper (Cu) and cobalt (Co) etc.

[0067] Step S204: Etch the stacked structure to form multiple second vias.

[0068] In the embodiments of this application, reference is made to Figures 1 to 3 As shown, the stacked structure 20 is etched to form a second through-hole. The second through-hole is used to subsequently form the channel hole structure 23.

[0069] Step S205: Form a channel hole structure in the second through hole.

[0070] In the embodiments of this application, reference is made to Figures 1 to 3 As shown, a channel structure 23 is formed within the second via; wherein, the channel structure 23 includes: a charge storage layer, a tunneling dielectric layer, and a channel layer, which are arranged sequentially from the outside to the inside. The charge storage layer can be made of silicon nitride (Si3N4) and is used to capture and retain charge to realize data storage; the tunneling dielectric layer is a tunneling dielectric layer and can be made of silicon oxide (SiO2) to realize electron tunneling transport and complete charge injection and release; the channel layer can be made of polycrystalline silicon material and acts as a conductive path.

[0071] In some embodiments of this application, reference is made to Figures 1 to 3 As shown, the redundant region 50 includes: a stepped contact redundant region; the stepped contact redundant region is the region located above the stepped end of the word line layer 21 and where no stepped contact 51 is provided. Figure 5 The illustrated step S102 may specifically include steps S301-S302.

[0072] Step S301: Etch the stacked structure vertically upwards along the redundant area of ​​the stepped contact to form the third through hole.

[0073] In the embodiments of this application, reference is made to Figure 1 As shown, the stacked structure 20 is etched vertically upwards along the redundant area of ​​the stepped contact to form a third via. The third via is used to subsequently form the through-silicon via structure 10.

[0074] Step S302: Form a through-silicon via structure within the third via.

[0075] In the embodiments of this application, reference is made to Figure 1As shown, a through-silicon via (TSV) structure 10 is formed within the third via. This reduces the chip area occupied by the TSV structure 10 and increases the storage density of the HBF chip.

[0076] In some embodiments of this application, the isolation region includes an isolation slot region 30 located between two adjacent storage planes 60. Step S102 may further include steps S303-S304.

[0077] Step S303: Etch the isolation trench area to form the third through hole.

[0078] In the embodiments of this application, reference is made to Figure 2 As shown, the isolation trench area 30 is etched to form a third via. The third via is used to subsequently form the through-silicon via structure 10.

[0079] Step S304: Form a through-silicon via structure within the third via.

[0080] In the embodiments of this application, reference is made to Figure 2 As shown, a through-silicon via (TSV) structure 10 is formed within the third via; wherein the TSV structure 10 penetrates the isolation trench region 30. By placing the TSV structure 10 in the isolation trench region 30, the effective chip area required for the TSV structure layout can be effectively reduced, thereby significantly improving the overall storage density of the HBF memory chip.

[0081] In some embodiments of this application, the isolation region further includes a slit region 40 located between two adjacent storage blocks 70. Figure 5 The step S102 shown may further include steps S305-S306.

[0082] Step S305: Etch the slit area to form the third through hole.

[0083] In the embodiments of this application, reference is made to Figure 3 As shown, the slit region 40 is etched to form a third via. The third via is used to subsequently form the through-silicon via structure 10.

[0084] Step S306: Form a through-silicon via structure within the third via.

[0085] In the embodiments of this application, reference is made to Figure 3 As shown, a through-silicon via (TSV) structure 10 is formed within the third via; wherein the TSV structure 10 penetrates the slit region 40. By placing the TSV structure 10 in the slit region 40, the additional area overhead caused by the TSV structure 10 can be reduced, thereby increasing the overall storage density of the HBF memory chip.

[0086] Based on the same inventive concept, and referring to Figure 6As shown, this application embodiment also provides an electronic device 300, which includes a high-density HBF memory structure 200 according to any of the above embodiments, or a high-density HBF memory structure 200 manufactured by the method of forming the high-density HBF memory structure 200 according to any of the above embodiments. The electronic device 300 can be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device can include memory in a computer, etc., and is not limited thereto.

[0087] It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments of this application are merely for description and do not represent the superiority or inferiority of the embodiments. It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0088] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this application can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined to obtain new method or device embodiments without conflict.

[0089] The above are merely specific implementations of the embodiments of this application, but the protection scope of the embodiments of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be covered within the protection scope of the embodiments of this application.

Claims

1. A high-density HBF storage structure, characterized in that, The high-density HBF storage structure includes: multiple three-dimensional NAND chips stacked vertically; The three-dimensional NAND chip includes: word line layers and isolation layers alternately stacked along the vertical direction, and a plurality of stepped contacts extending along the vertical direction; Multiple word line layers extend along a first direction, with one end arranged in a stepped manner; the first direction is perpendicular to the vertical direction; Each of the stepped contacts is connected to the stepped end of the corresponding word line layer; The high-density HBF memory structure further includes: a through-silicon via structure extending along the vertical direction; At least one of the three-dimensional NAND chips is electrically connected via a through-silicon via (TSV) structure; The through-silicon via (TSV) structure is disposed in the isolation region and / or redundant region of the three-dimensional NAND chip.

2. The high-density HBF storage structure according to claim 1, characterized in that, The redundant area includes: the stepped contact redundant area; The redundant area of ​​the stepped contact is the area located above the stepped end of the word line layer where no stepped contact is provided.

3. The high-density HBF storage structure according to claim 1, characterized in that, The isolation area includes an isolation slot area located between two adjacent storage planes.

4. The high-density HBF storage structure according to claim 1, characterized in that, The isolation area also includes a slit area located between two adjacent storage blocks.

5. The high-density HBF storage structure according to claim 1, characterized in that, The three-dimensional NAND chip also includes: a channel hole structure; The channel hole structure extends along the vertical direction and penetrates the alternating layers of word lines and isolation layers along the vertical direction; wherein, the channel hole structure includes: a charge storage layer, a tunneling dielectric layer and a channel layer that surround the structure from the outside to the inside. The through-silicon via structure is located between two adjacent channel via structures along the second direction; the first direction intersects the second direction and is perpendicular to the vertical direction.

6. A method for forming a high-density HBF memory structure, characterized in that, The method for forming the high-density HBF memory structure includes: Multiple three-dimensional NAND chips are formed; wherein, the three-dimensional NAND chip includes: word line layers and isolation layers alternately stacked along a vertical direction, and multiple stepped contacts extending along the vertical direction; the multiple word line layers extend along a first direction and are arranged in a stepped shape at one end; each stepped contact is connected to the stepped end of the corresponding word line layer; the first direction is perpendicular to the vertical direction; A through-silicon via (TSV) structure is formed in at least one of the three-dimensional NAND chips; wherein the TSV structure is disposed in an isolation region and / or a redundant region in the three-dimensional NAND chip; Multiple three-dimensional NAND chips are stacked along the vertical direction.

7. The method for forming a high-density HBF memory structure according to claim 6, characterized in that, The formation of multiple three-dimensional NAND chips includes: The word line layer and the isolation layer are alternately deposited on the substrate to form a stacked structure; The stacked structure is etched to form a plurality of first through-holes; Multiple stepped contact points are formed within the first through hole; The stacked structure is etched to form multiple second through holes; A channel hole structure is formed within the second through hole; wherein the channel hole structure includes a charge storage layer, a tunneling dielectric layer, and a channel layer that surround the hole sequentially from the outside to the inside.

8. The method for forming a high-density HBF memory structure according to claim 7, characterized in that, The redundant area includes: a stepped contact redundant area; the stepped contact redundant area is the area located above the stepped end of the word line layer and where no stepped contact is provided; The formation of a through-silicon via (TSV) structure in at least one of the three-dimensional NAND chips includes: The stacked structure is etched vertically above the redundant area of ​​the stepped contact to form a third through hole; The through-silicon via (TSV) structure is formed within the third via; wherein the TSV structure penetrates the stacked structure.

9. The method for forming a high-density HBF memory structure according to claim 7, characterized in that, The isolation region includes: an isolation slot region located between two adjacent storage planes; The formation of a through-silicon via (TSV) structure in at least one of the three-dimensional NAND chips includes: The isolation groove area is etched to form a third through hole; The through-silicon via structure is formed within the third through-hole; wherein the through-silicon via structure penetrates the isolation trench region.

10. The method for forming a high-density HBF memory structure according to claim 7, characterized in that, The isolation area also includes: a narrow slit area located between two adjacent storage blocks; The formation of a through-silicon via (TSV) structure in at least one of the three-dimensional NAND chips includes: The slit region is etched to form a third through-hole; The through-silicon via structure is formed within the third through-hole; wherein the through-silicon via structure penetrates the slit region.

11. An electronic device, characterized in that, The electronic device includes a high-density HBF memory structure according to any one of claims 1-5, or a high-density HBF memory structure manufactured by a method for forming a high-density HBF memory structure according to any one of claims 6-10.

Images