Semiconductor device structure and method of forming the same

Abstract

Embodiments of the present application disclose semiconductor device structures and methods of forming the same. A dielectric material layer comprising at least a lower capacitor level dielectric layer, an upper etch stop dielectric layer, and an upper capacitor level dielectric layer is formed over a substrate. A capacitor structure is formed, comprising an array of columnar capacitor portions within the dielectric material layer located in a plan view in a column array region, a moat-shaped capacitor portion laterally surrounding the array of columnar capacitor portions, a gap capacitor portion, and a capacitor top portion contiguous with top ends of the columnar capacitor portions and covering the dielectric material. The upper etch stop dielectric layer laterally surrounds the array of columnar capacitor portions and comprises a gap via located at a gap of the array of columnar capacitor portions in a plan view.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor device structures and methods of forming the same. Background Technology

[0002] The fabrication of high aspect ratio metal-insulator-metal capacitors (MIMCAPs) presents challenges due to the tendency of thin structures to collapse during fabrication. Methods and structures to improve the structural stability of high aspect ratio MIMCAPs are needed. Summary of the Invention

[0003] According to one aspect of the present application, a method for forming a semiconductor device structure is provided, comprising: depositing a dielectric material layer on a substrate, wherein the dielectric material includes, from bottom to top, a lower capacitor-level dielectric layer, an etch-stop dielectric layer, and an upper capacitor-level dielectric layer; etching an array of pillar cavities through the dielectric material layer; depositing and patterning at least one bottom electrode assembly layer on the sidewalls of each pillar cavity array and above the upper capacitor-level dielectric layer, such that a top surface segment of the upper capacitor-level dielectric layer is exposed around each pillar cavity array, and an array of capped tubular bottom electrode portions is retained in each pillar cavity array; in a plan view, etching gap vias in the etch-stop dielectric layer at the gaps in the array of capped tubular bottom electrode portions; and depositing additional bottom electrode assembly layers, node dielectric layers, and top electrode layers above the patterned portions of the etch-stop dielectric layer and at least one bottom electrode assembly layer.

[0004] According to another aspect of the embodiments of this application, a method for forming a semiconductor device structure is provided, comprising: depositing a dielectric material layer over a substrate, wherein the dielectric material layer includes, from bottom to top, a lower capacitor-level dielectric layer, a lower etch-stop dielectric layer, an intermediate capacitor-level dielectric layer, an upper etch-stop dielectric layer, and an upper capacitor-level dielectric layer; forming an array of covered tubular bottom electrode portions through the dielectric material layer within a pillar array region; etching the upper capacitor-level dielectric layer from the pillar array region; forming spacer material portions around and inside the array of covered tubular bottom electrode portions, wherein discrete top surface segments of the upper etch-stop dielectric layer are exposed at gaps in the array of covered tubular bottom electrode portions; forming vias in the upper etch-stop dielectric layer in the pillar array region; selectively removing the intermediate capacitor-level dielectric layer to the upper etch-stop dielectric layer from the pillar array region; and depositing a node dielectric layer and a top electrode layer over the upper etch-stop dielectric layer and the array of covered tubular bottom electrode portions.

[0005] According to another aspect of the embodiments of this application, a semiconductor device structure is provided, comprising: a dielectric material layer overlying a substrate, wherein the dielectric material includes, from bottom to top, a lower capacitor-level dielectric layer, an etch-stop dielectric layer, and an upper capacitor-level dielectric layer; and a capacitor structure including an array of columnar capacitor portions within the dielectric material layer located in a columnar array region in a planar view, and further including a capacitor top portion adjacent to the top of the array of each columnar capacitor portion and overlying the dielectric material layer, wherein the etch-stop dielectric layer laterally surrounds the array of columnar capacitor portions, and includes gap vias located at the gaps in the array of columnar capacitor portions in a planar view. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 This is a vertical cross-sectional view of an exemplary structure after a dielectric material layer and a metal interconnect structure have been formed over a substrate according to embodiments of the present disclosure.

[0008] Figure 2A This is a vertical cross-sectional view of an exemplary structure following the formation of an array of cylindrical cavities and trenches passing through a subset of dielectric material layers, according to embodiments of the present disclosure. Figure 2B yes Figure 2A A top view of an exemplary structure. Vertical plane A-A' is... Figure 2A The vertical cross-sectional view. Figure 2C It is along Figure 2B Another vertical cross-sectional view of an exemplary structure in the vertical plane C-C'.

[0009] Figure 3 This is a vertical cross-sectional view of an exemplary structure after the deposition of the bottom electrode assembly layer according to an embodiment of the present disclosure.

[0010] Figure 4 This is a vertical cross-sectional view of an exemplary structure after the deposition of a sacrificial filler material layer and the formation of a patterned photoresist layer, according to embodiments of the present disclosure.

[0011] Figure 5 This is a vertical cross-sectional view of an exemplary structure after etching the unmasked portion of the sacrificial filler layer and the unmasked horizontal extension of the bottom electrode assembly layer, according to embodiments of the present disclosure.

[0012] Figure 6A This is a vertical cross-sectional view of an exemplary structure after removing the remaining portion of the sacrificial filler material layer, according to an embodiment of the present disclosure. Figure 6B yes Figure 6A A top view of an exemplary structure. Vertical plane A-A' is... Figure 6A The vertical cross-sectional view. Figure 6C It is along Figure 6B Another vertical cross-sectional view of an exemplary structure in the vertical plane C-C'.

[0013] Figure 7A This is a vertical cross-sectional view of an exemplary structure after removing the unmasked portion of the upper capacitor layer dielectric layer according to an embodiment of the present disclosure. Figure 7B yes Figure 7A A top view of an exemplary structure. Vertical plane A-A' is... Figure 7A The vertical cross-sectional view. Figure 7C It is along Figure 7B Another vertical cross-sectional view of an exemplary structure in the vertical plane C-C'.

[0014] Figure 8 This is a vertical cross-sectional view of an exemplary structure after the deposition of a spacer material layer according to an embodiment of the present disclosure.

[0015] Figure 9A This is a vertical cross-sectional view of an exemplary structure following an anisotropic etched spacer material layer according to an embodiment of the present disclosure. Figure 9B yes Figure 9A A top view of an exemplary structure. Vertical plane A-A' is... Figure 9A The vertical cross-sectional view. Figure 9C It is along Figure 9B Another vertical cross-sectional view of an exemplary structure in the vertical plane C-C'.

[0016] Figure 10A This is a vertical cross-sectional view of an exemplary structure after etching the unmasked portion of the upper stop dielectric layer according to an embodiment of the present disclosure. Figure 10B yes Figure 10A A top view of an exemplary structure. Vertical plane A-A' is... Figure 10A The vertical cross-sectional view. Figure 10C It is along Figure 10B Another vertical cross-sectional view of an exemplary structure in the vertical plane C-C'.

[0017] Figure 11A This is a vertical cross-sectional view of an exemplary structure after removing the remaining portions of the spacer material layer and the intermediate capacitor layer dielectric layer according to an embodiment of the present disclosure. Figure 11B yes Figure 11A A top view of an exemplary structure. Vertical plane A-A' is... Figure 11A The vertical cross-sectional view. Figure 11C It is along Figure 11BAnother vertical cross-sectional view of an exemplary structure in the vertical plane C-C'. Figure 11D Before removing the bottommost dielectric layer of the intermediate capacitor layer, in the process of forming Figures 11A-11C A perspective view of a region of an exemplary structure during an isotropic etching step.

[0018] Figure 12 This is a vertical cross-sectional view of an exemplary structure after the deposition of an additional bottom electrode assembly layer according to an embodiment of the present disclosure.

[0019] Figure 13 This is a vertical cross-sectional view of an exemplary structure after the deposition of a node dielectric layer according to an embodiment of the present disclosure.

[0020] Figure 14 This is a vertical cross-sectional view of an exemplary structure after the deposition of a top electrode layer according to an embodiment of the present disclosure.

[0021] Figure 15 This is a vertical cross-sectional view of an exemplary structure after the deposition of a dielectric capping layer, according to an embodiment of the present disclosure.

[0022] Figure 16 This is a vertical cross-sectional view of an exemplary structure following a patterned dielectric capping layer, according to an embodiment of the present disclosure.

[0023] Figure 17 This is a vertical cross-sectional view of an exemplary structure after the dielectric cap spacer has been formed, according to an embodiment of the present disclosure.

[0024] Figure 18 This is a vertical cross-sectional view of an exemplary structure following the patterning of the top electrode layer, node dielectric layer, and bottom electrode assembly layer according to embodiments of the present disclosure.

[0025] Figure 19 This is a vertical cross-sectional view of an exemplary structure after the formation of the upper dielectric material layer according to an embodiment of the present disclosure.

[0026] Figure 20 This is a vertical cross-sectional view of an exemplary structure after the formation of the upper electrode connection metal interconnect structure according to an embodiment of the present disclosure.

[0027] Figure 21 This is a vertical cross-sectional view of an alternative configuration of an exemplary structure according to an embodiment of the present disclosure.

[0028] Figure 22 This is a first flowchart illustrating the steps of forming a device structure according to an embodiment of the present disclosure.

[0029] Figure 23 This is a second flowchart illustrating the steps of forming a device structure according to an embodiment of the present disclosure. Detailed Implementation

[0030] The following disclosure provides multiple embodiments illustrating various possible implementations of the disclosed subject matter. Specific components and configurations are described to provide technical clarity and illustrative support, but are not intended to limit the scope of this disclosure. Unless explicitly stated otherwise, elements identified by the same reference numerals refer to the same parts and are assumed to have the same material composition and fall within the same thickness range. Unless explicitly excluded, all features disclosed in any embodiment should be understood to be present in derivative embodiments. Therefore, the features described in connection with any embodiment or drawings provide written description support for use in any other embodiment. Unless explicitly limited to a single instance, embodiments including multiple instances of the described features are contemplated. Similarly, embodiments in which non-essential features are omitted may be considered even if not specifically shown, provided that such configurations are known to those skilled in the art.

[0031] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” and “lower,” “above,” and “higher,” and similar expressions are used to indicate the relative positions of the elements shown in the figures. This spatial description is relative to a given orientation of the structure, not absolute; for example, if the structure is rotated, a surface described as the “top surface” in one direction may become the “bottom surface.” The claims should be interpreted in the context of a correctly oriented configuration of the structure. If the entire volume of the first element is contained within a conceptual volume defined by a minimum area surface surrounding the second element, and is topologically equivalent to a sphere, then the first physical element is “embedded” within the second physical element. Any openings on the outer surface of the second element are considered to be covered by a minimum area patch that closes the opening without altering the topology. These spatial descriptors are intended to cover alternative orientations that may arise during use or manufacture, not just those shown in the figures. Unless otherwise stated, components with the same reference numerals are considered to have the same material composition and comparable thickness ranges. Similarly, unless explicitly stated otherwise, each material region is assumed to have a uniform composition.

[0032] As used herein, removal of the first material is "selective" for the second material if the removal rate of the first material is at least three times greater than the removal rate of the second material. Unless otherwise specified, "selective removal" means that the selectivity ratio may be equal to or greater than 3, 10, 100, or even 1000. The first and second surfaces are "perpendicularly coincident" if one surface lies directly above or below another surface such that a vertical or substantially vertical plane encompasses both surfaces. A vertical plane is defined as a two-dimensional surface consisting of an uncountable infinite number of vertical lines having a uniform one-dimensional horizontal cross-section that remains invariant under vertical translation. If the cross-section is linear, the plane is Euclidean; otherwise, it is non-Euclidean. A substantially vertical line is a line that deviates less than 5 degrees from a perfectly vertical direction. A substantially vertical plane comprises a continuous set of such lines.

[0033] The various embodiments disclosed herein relate to semiconductor device structures, particularly high aspect ratio metal-insulator-metal capacitor (MIMCAP) structures and methods for forming the same. Embodiments of this disclosure provide a structurally robust MIMCAP structure comprising an array of pillar-shaped capacitor portions embedded within a dielectric material layer. The MIMCAP structure includes a top portion adjacent to the pillar-shaped portions, a gap capacitor portion, and a trench-shaped portion, collectively enhancing electrical connectivity and structural stability. The capacitor structure includes a composite bottom electrode, node dielectric, and top electrode, configured to optimize performance in a high aspect ratio configuration. Various aspects of this disclosure will now be described with reference to the accompanying drawings.

[0034] The disclosed MIMCAP structure includes a perforated etch-stop dielectric layer, specifically an upper etch-stop dielectric layer, which contains gap perforations at the gaps in the column array. The perforated etch-stop dielectric layer includes a perforated etch-stop matrix and a continuous extension laterally surrounding and providing structural support to the capped tubular bottom electrode portion. During a selective etching process (which removes the intermediate capacitor-level dielectric layer located between the lower etch-stop dielectric layer and the perforated etch-stop dielectric layer), the perforated etch-stop matrix mechanically supports and prevents the collapse of the high aspect ratio columnar capped tubular bottom electrode portion. The gap perforations provided by the perforated etch-stop matrix at the gap locations in the array of capped tubular bottom electrode portions provide channels through which etchant passes, facilitating selective etching of the intermediate capacitor-level dielectric layer while maintaining the structural integrity of the array during fabrication.

[0035] Reference Figure 1This illustration shows an exemplary structure according to an embodiment of the present disclosure. The exemplary structure includes a substrate 9, which may be a semiconductor wafer, such as a single-crystal silicon wafer. A semiconductor device, such as a field-effect transistor, may be formed on the top surface of the substrate 9. A metal interconnect structure 40 embedded in a dielectric material layer 30 may be formed above the substrate 9. The metal interconnect structure 40 provides electrical connections to the semiconductor device on the substrate 9. The metal interconnect structure 40 may include metal lines and metal via structures.

[0036] According to one aspect of this disclosure, a via-level, a line-level, and an overlay back-end process device layer can be used to provide a metal-insulator-metal capacitor (MIMCAP) device. For example, the metal interconnect level below the via-level may include a lower dielectric layer 3A with embedded lower metal interconnect structures (41, 42). The lower metal interconnect structures (41, 42) may include a lower metal line 41 and a capacitor bottom contact plate 42, the lower metal line 41 being electrically connected to a semiconductor device on a substrate 9, and the capacitor bottom contact plate 42 being formed in the capacitor region and configured to contact the bottom electrode of a subsequently formed capacitor. A lower etch-stop dielectric layer 3B may be formed over the lower dielectric layer 3A.

[0037] The dielectric material layer group 30 for embedding the lower portion of the capacitor structure can be sequentially deposited above the lower etch-stop dielectric layer 3B. The dielectric material layer group 30 may include, from bottom to top, a lower capacitor-level dielectric layer 31, a lower etch-stop dielectric layer 32, an intermediate capacitor-level dielectric layer 33, an upper etch-stop dielectric layer 34, and an upper capacitor-level dielectric layer 35. In some embodiments, the dielectric material layer group 30 may include one or more additional etch-stop dielectric layers and / or capacitor-level dielectric layers.

[0038] The materials of the lower dielectric layer 3A, the lower capacitor-level dielectric layer 31, the intermediate capacitor-level dielectric layer 33, and the upper capacitor-level dielectric layer 35 can be independently selected from silicate glass-based dielectric materials, including undoped silicate glass, doped silicate glass, non-porous organosilicon glass, and porous organosilicon glass. The thicknesses of the lower dielectric layer 3A, the lower capacitor-level dielectric layer 31, and the intermediate capacitor-level dielectric layer 33 can be independent. Each of the lower dielectric layer 3A, the lower capacitor-level dielectric layer 31, and the intermediate capacitor-level dielectric layer 33 can have a corresponding thickness selected from about 60 nm to about 1000 nm, but smaller or larger thicknesses can also be used. The thickness of the upper capacitor-level dielectric layer 35 can be in the range of about 30 nm to about 300 nm, but smaller or larger thicknesses can also be used.

[0039] The lower etch stop dielectric layer 3B, the lower etch stop dielectric layer 32, and the upper etch stop dielectric layer 34 comprise corresponding materials different from the materials of the corresponding overlying dielectric material layers (31, 33, or 35). In an illustrative example, each of the lower etch stop dielectric layer 3B, the lower etch stop dielectric layer 32, and the upper etch stop dielectric layer 34 may include a respective etch stop dielectric material independently selected from silicon nitride, silicon carbide, silicon carbonitride, dielectric metal oxides (such as aluminum oxide, tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, lanthanum oxide, yttrium oxide, etc.), silicon oxynitride, etc. In an illustrative example, each of the lower etch stop dielectric layer 3B, the lower etch stop dielectric layer 32, and the upper etch stop dielectric layer 34 may include silicon nitride. The thicknesses of the lower etch stop dielectric layer 3B, the lower etch stop dielectric layer 32, and the upper etch stop dielectric layer 34 may be independent. Each of the lower etch stop dielectric layer 3B, the lower etch stop dielectric layer 32, and the upper etch stop dielectric layer 34 may have a corresponding thickness selected from about 3 nm to about 60 nm, for example from 6 nm to 30 nm, but smaller or larger thicknesses may also be used. The bottom surface of the lower etch stop dielectric layer 3B may be located in a first horizontal plane HP1. The top surface of the lower etch stop dielectric layer 32 may be located in a second horizontal plane HP2. The top surface of the upper etch stop dielectric layer 34 may be located in a third horizontal plane HP3.

[0040] Reference Figures 2A to 2C A mask layer may be formed over the upper capacitor-level dielectric layer 35. The mask layer may include a photoresist layer. The photoresist layer (not shown) may be applied over the upper capacitor-level dielectric layer 35 and may be photolithographically patterned to form an array of discrete openings and trench-shaped openings laterally surrounding the array of discrete openings. An anisotropic etching process may be performed to transfer the opening pattern in the photoresist layer through the upper capacitor-level dielectric layer 35, the upper etch-stop dielectric layer 34, the intermediate capacitor-level dielectric layer 33, the lower etch-stop dielectric layer 32, and the lower capacitor-level dielectric layer 31. The anisotropic etching process may include a series of anisotropic etching steps to provide suitable etch chemicals to each of the upper capacitor-level dielectric layer 35, the upper etch-stop dielectric layer 34, the intermediate capacitor-level dielectric layer 33, the lower etch-stop dielectric layer 32, and the lower capacitor-level dielectric layer 31. The capacitor bottom contact plate 42 can be used as an etching stop structure for the terminal etching step in anisotropic etching processes.

[0041] An array 29 of pillar cavities can be formed below an array of discrete openings, and trenches 27 can be formed below trench-shaped openings in a photoresist layer. Each pillar cavity 29 can have a horizontal cross-sectional shape that is circular, elliptical, or any generally curved two-dimensional shape with a closed perimeter. The trenches 27 laterally surround the array of pillar cavities 29. The region surrounded by the inner sidewalls of the trenches 27 is referred to herein as the pillar array region 300. The maximum lateral dimension (hereinafter referred to as the lateral dimension) of each pillar cavity 29 can range from about 50 nm to about 400 nm, but smaller or larger lateral dimensions may also be used. The width of the trenches 27, defined by the lateral distance between a pair of opposing inner and outer sidewalls, can range from 50 nm to 400 nm, but smaller or larger widths may also be used.

[0042] In one embodiment, the array of cylinders 29 can be formed as a two-dimensional periodic array of cylinders 29, wherein, in a plan view, the separation direction of the second nearest neighbor pair of cylinders 29 differs from the separation direction of the nearest neighbor pair of cylinders. As used herein, a nearest neighbor pair of elements within an element array refers to a pair of adjacent elements that provide a minimum lateral spacing distance of at least 80 nm to ensure sufficient spacing for subsequent deposition of spacer material layers. As used herein, a second nearest neighbor pair of elements within an element array refers to a pair of adjacent elements that provide a second minimum lateral spacing distance. As used herein, a plan view refers to a two-dimensional top view of the structure observed perpendicular to the top surface of the substrate 9.

[0043] In the illustrative example, the array of cavities 29 can be formed as a two-dimensional rectangular array of cavities 29, with the pitch of the cavities 29 along a first horizontal direction hd1 and along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1 ranging from 120 nm to 900 nm, such that the nearest neighbor distance between adjacent cavities 29 is at least 80 nm. In this embodiment, the separation direction of the nearest neighbor pair of cavities 29 can be the first horizontal direction hd1 and the second horizontal direction hd2. The separation direction of the second nearest neighbor pair of cavities 29 can be a horizontal direction rotated 45 degrees clockwise from the first horizontal direction hd1, or another horizontal direction rotated 45 degrees clockwise from the second horizontal direction. The bottom surface of the cavities 29 and the bottom surface of the trench 27 can be located within the first horizontal plane HP1. Therefore, the top surface section of the capacitor bottom contact plate 42 can be physically exposed below each cavity 29. The topological annular top surface section of the capacitor bottom contact plate 42 can be physically exposed below the trench 27. The photoresist layer can then be removed, for example, by ashing.

[0044] Although the exemplary structure is shown as a rectangular array configuration comprising 4×4 cylindrical cavities 29, embodiments of this disclosure can be implemented with any M×N rectangular array of cylindrical cavities 29, where M can be any integer greater than 1 and N can be any integer greater than 1.

[0045] Reference Figure 3 At least one bottom electrode assembly layer (61, 62) may be conformally deposited in the array of cavities 29, in the trenches 27, and over the dielectric material layer groups (31, 32, 33, 34, 35). At least one bottom electrode assembly layer (61, 62) includes at least one conductive material layer, such as at least one metallic material layer. In one embodiment, at least one bottom electrode assembly layer (61, 62) may include a first bottom electrode assembly layer 61 and a second bottom electrode assembly layer 62.

[0046] In one illustrative example, the first bottom electrode assembly layer 61 may include a tantalum nitride layer comprising stoichiometric tantalum nitride material deposited via a first atomic layer deposition process, and the second bottom electrode assembly layer 62 may include a titanium nitride layer comprising stoichiometric titanium nitride material deposited via a second atomic layer deposition process. The thickness of the first bottom electrode assembly layer 61 may range from about 4 nm to about 100 nm, but smaller or larger thicknesses may also be used. The thickness of the second bottom electrode assembly layer 62 may range from about 4 nm to about 100 nm, but smaller or larger thicknesses may also be used. A cylindrical void 29' may be present in each cylindrical cavity 29. A trench-shaped void 27' may be present in the trench 27.

[0047] Reference Figure 4 After depositing at least one bottom electrode assembly layer (61, 62), a sacrificial filler layer 171L can be deposited in the voids within the array of cavities 29 and the trenches 27. The sacrificial filler layer 171L comprises a sacrificial filler material that can subsequently be selectively removed from the material of at least one bottom electrode assembly layer (61, 62). For example, the sacrificial filler layer 171L may comprise a semiconductor material, such as amorphous silicon, a carbon-based material (such as amorphous carbon or diamond-like carbon (DLC)), a porous or non-porous silicate glass, or a polymer material.

[0048] A mask layer may be formed over the sacrificial filler layer 171L. The mask layer may include a patterned photoresist layer 173. The patterned photoresist layer 173 may be formed by depositing a blanket photoresist layer (i.e., an unpatterned photoresist layer) and by photolithographically patterning the blanket photoresist layer to form an opening. According to one aspect of the disclosure, in a plan view, the periphery of the opening may be formed between a first continuous surface including all inner sidewalls of the trench 27 and a second continuous surface including all outer sidewalls of the trench 27. In one embodiment, in a plan view, the periphery of the opening may be located approximately in the middle of the trench 27 between the inner and outer sidewalls of the trench 27. The periphery of the opening may laterally surround the entire area of ​​the pillar array region 300. Typically, the patterned photoresist layer 173 may be formed over the top surface of the sacrificial filler layer 171L such that the top surface of the sacrificial filler layer 171L is exposed below the opening in the patterned photoresist layer 173 within the region of the array of pillar cavities 29.

[0049] Reference Figure 5 Unmasked portions of the sacrificial filler layer 171L can be removed by performing an etching process. The etching process may include anisotropic etching. In one embodiment, the duration of the anisotropic etching process can be selected such that the top surface of the horizontal extension of the bottom electrode assembly layers (61, 62) is physically exposed. Each remaining discrete portion of the sacrificial filler layer 171L in the corresponding pillar 29 includes a sacrificial filler pillar structure 171'. Typically, the unmasked portions of the sacrificial filler layer 171L can be etched below an opening in the patterned photoresist layer 173. The horizontal extension of the sacrificial filler layer 171L is removed from a region having a periphery that laterally surrounds the pillar 29 in plan view. The periphery can be formed by an opening in the patterned photoresist layer 173 and can be located between the inner periphery and the outer periphery of the trench 27 in plan view. Thus, the horizontal extension segment of the sacrificial filler layer 171L is removed from the pillar array region 300. At least one perforated top surface portion of the bottom electrode assembly layer (61, 62) is physically exposed. As used herein, a perforated element refers to an element having at least one perforation extending from the front surface of the element to the rear surface of the element.

[0050] Subsequently, an etching process can be performed to selectively remove the unmasked horizontal extensions of the bottom electrode assembly layers (61, 62) to the sacrificial filler pillar structure 171' and the sacrificial filler layer 171L. The etching process for etching the unmasked horizontal extensions of the bottom electrode assembly layers (61, 62) can include at least one anisotropic etching process or at least one isotropic etching process. In an illustrative example, if the first bottom electrode assembly layer 61 comprises a tantalum nitride layer, and if the second bottom electrode assembly layer comprises a titanium nitride layer, the unmasked portions of the second bottom electrode assembly layer 62 can be etched using a reactive ion etching process performed with chlorine-based chemicals (such as a mixture of Cl2 and BCl3), and the unmasked portions of the first bottom electrode assembly layer 61 can be etched using a reactive ion etching process performed with fluorine-based chemicals (such as a mixture of CF4 and O2).

[0051] Typically, a portion of at least one bottom electrode assembly layer (61, 62) can be etched using a sacrificial filler layer 171L as an etching mask. The top surface segment of the perforated upper capacitor level dielectric layer 35 is exposed around the array of pillar cavities 29 within the pillar array region 300. The remaining portion of at least one bottom electrode assembly layer (61, 62) retained within the array of pillar cavities 29 comprises an array of capped tubular bottom electrode portions 10B. Each capped tubular bottom electrode portion 10B includes a corresponding tubular sub-portion extending vertically and a corresponding cap-shaped sub-portion adjacent to the bottom end of the corresponding tubular sub-portion. The cap-shaped sub-portion of each capped tubular bottom electrode portion 10B contacts a top surface segment of the capacitor bottom contact plate 42. The array of capped tubular bottom electrode portions 10B is formed through dielectric material layers (31, 32, 33, 34, 35) within the pillar array region 300.

[0052] The top surface segment of the perforation of the upper capacitor level dielectric layer 35 is exposed around the array of cylindrical cavities 29. An array of capped tubular bottom electrode portions 10B is retained within the cylindrical cavities 29. In one embodiment, each cylindrical cavity 29 may be filled with a combination of a corresponding capped tubular bottom electrode portion 10B and a sacrificial filler pillar structure 171'. In one embodiment, the array of capped tubular bottom electrode portions 10B is arranged as a periodic two-dimensional array. The patterned photoresist layer 173 can then be removed.

[0053] Reference Figures 6A-6CThe remaining portion of the sacrificial filler layer 171L and the sacrificial filler pillar structure 171' can be selectively removed to the material of at least one bottom electrode assembly layer (61, 62). Optionally, the removal of the remaining portion of the sacrificial filler layer 171L and the sacrificial filler pillar structure 171' can be selective for the material of the upper capacitor layer dielectric layer 35. In an illustrative example, if the remaining portion of the sacrificial filler layer 171L and the sacrificial filler pillar structure 171' comprises amorphous silicon, a wet etching process using potassium hydroxide can be used to remove the remaining portion of the sacrificial filler layer 171L and the sacrificial filler pillar structure 171'. The inner wall of the tubular sub-section of the tubular bottom electrode portion 10B and the top surface of the cap sub-section of the tubular bottom electrode portion 10B are exposed to the cylindrical voids 29' in the pillar cavity 29. The inner wall of the tubular sub-section of at least one bottom electrode assembly layer (61, 62) and the top surface of the cap-like sub-section of at least one top electrode assembly layer are exposed to the trench-shaped void 27' in the trench groove 27.

[0054] Reference Figures 7A to 7C An etching process can be performed to remove unmasked portions of the upper capacitor level dielectric layer 35 from within the pillar array region 300. Portions of the upper capacitor level dielectric layer 35 within the pillar array region 300 surrounding the array of capped tubular bottom electrode portions 10B can be selectively removed down to the material of the upper etch stop dielectric layer 34. Therefore, during the etching process, portions of the upper capacitor level dielectric layer 35 not masked by at least one bottom electrode assembly layer (61, 62) are etched. The top surface of the upper etch stop dielectric layer 34 is exposed within the pillar array region 300. Top surface sections of the outer sidewalls of the array of capped tubular bottom electrode portions 10B are exposed in via cavities formed by removing etched portions of the upper capacitor level dielectric layer 35.

[0055] Reference Figure 8A spacer material layer 151L, comprising spacer material, can be conformally deposited in the cylindrical voids 29' within the cylindrical cavity 29, in the trench-shaped voids 27' within the trench 27, and above the physical exposed surfaces of the upper etch stop dielectric layer 34, the capped tubular bottom electrode portion 10B, and at least one bottom electrode assembly layer (61, 62). Typically, the spacer material layer 151L can be conformally deposited within the voids of the array of capped tubular bottom electrode portions 10B, around the upper region of the capped tubular bottom electrode portions 10B, and above the upper etch stop dielectric layer 34. The spacer material layer 151L includes material that can be selectively removed relative to the material of the upper etch stop dielectric layer 34, the capped tubular bottom electrode portion 10B, and at least one bottom electrode assembly layer (61, 62). In an illustrative example, the spacer material layer 151L comprises a material selected from undoped silicate glass, doped silicate glass, or organosilicon glass.

[0056] According to aspects of this disclosure, the thickness of the spacer material layer 151L can be greater than the minimum lateral dimension of each cylindrical gap 29' in the cylindrical cavity 29 (or, if the cylindrical gap 29' has a circular horizontal cross-sectional shape, it can be the diameter), greater than the width of the trench-shaped gap 27' in the trench cavity 27, greater than half the nearest neighbor distance within the array of the covered tubular bottom electrode portions 10B, and less than half the second nearest neighbor distance within the array of the covered tubular bottom electrode portions 10B. Therefore, the spacer material layer 151L includes recessed regions located at the gaps in the array of the covered tubular bottom electrode portions 10B. As used herein, a “gap” in an array of elements refers to a region or space located between adjacent elements in the array, specifically a volume surrounded by a minimum convex body that surrounds the outer boundary of the nearest neighbor element, excluding the volume occupied by the element itself. Against the backdrop of an array of capped tubular bottom electrode portions 10B, the gap is a three-dimensional space between the outer walls of adjacent capped tubular bottom electrode portions 10B, vertically defined by the top surface of the upper etch stop dielectric layer 34 and the topmost surface of the capped tubular portion 10B, and laterally defined in a planar view by a convex body formed around the outer periphery of the nearest adjacent capped tubular bottom electrode portion 10B. The sidewalls of the spacer material layer 151L and the recessed surfaces of the spacer material layer 151L can be physically exposed around each recessed region in the spacer material layer 151L, which is formed at the corresponding gap of the array of capped tubular bottom electrode portions 10B.

[0057] In one embodiment, the thickness of the spacer material layer 151L can be in the range of about 40 nm to about 90 nm, but smaller or larger thicknesses can also be used. The sidewalls of the spacer material layer 151L surrounding the gaps in the array of covered tubular bottom electrode portions 10B can be laterally offset from the outer sidewalls of the covered tubular bottom electrode portions 10B by a lateral offset distance (lod), which is the same as the thickness of the spacer material layer 151L. In one embodiment, the uniform lateral offset distance lod is greater than half the nearest neighbor distance within the array of covered tubular bottom electrode portions 10B and less than half the second nearest neighbor distance within the array of covered tubular bottom electrode portions 10B.

[0058] Reference Figures 9A-9C An etching process (e.g., anisotropic etching) can be performed to vertically recess the spacer material layer 151L. The spacer material layer 151L can be recessed to the thickness of its horizontal extension. A portion of the spacer material layer 151L covering the top surface of at least one bottom electrode assembly layer (61, 62) can be removed from the outside of the pillar array region 300. Furthermore, a portion of the spacer material layer 151L covering the volume of the pillar cavity 29 can be removed, physically exposing the top surface (which may be an annular surface) of the capped tubular bottom electrode portion 10B. Additionally, during the anisotropic etching process, the recessed horizontal extension of the spacer material layer 151L located in the region laterally surrounded by the sidewalls of the spacer material layer 151L at the gaps in the array of capped tubular bottom electrode portions 10B is removed. Discrete top sections of the upper etch-stop dielectric layer 34 are physically exposed below the voids through the continuous remaining portion of the spacer material layer 151L (which constitutes the spacer matrix 151' of the perforation).

[0059] Typically, the remaining portion of the spacer material layer 151L after the anisotropic etching process includes spacer material portions (151, 151', 151M) formed around and inside the capped tubular bottom electrode portion 10B. The spacer material portions (151, 151', 151M) include a perforated spacer matrix 151', which is the remaining portion of the spacer material layer 151L located outside the array of capped tubular bottom electrode portions 10B. Furthermore, the spacer material portions (151, 151', 151M) include a perforated spacer matrix 151', which is formed outside the capped tubular bottom electrode portion 10B. Additionally, the spacer material portions (151, 151', 151M) include a spacer material trench filling structure 151M that fills the volume within the trench 27.

[0060] In one embodiment, the total number of perforations in the perforated spacer matrix 151' may be the sum of the total number of capped tubular bottom electrode portions 10B and the total number of gaps within the array of capped tubular bottom electrode portions 10B. In contrast, the total number of perforations in each of the lower capacitor-level dielectric layer 31, lower etch-stop dielectric layer 32, intermediate capacitor-level dielectric layer 33, upper etch-stop dielectric layer 34, and upper capacitor-level dielectric layer 35 may be the same as the sum of the total number of capped tubular bottom electrode portions 10B and the number of trenches 27 (which is 1). In one embodiment, the total number of perforations in the perforated spacer matrix 151' may be greater than the total number of perforations in each of the lower capacitor-level dielectric layer 31, lower etch-stop dielectric layer 32, intermediate capacitor-level dielectric layer 33, upper etch-stop dielectric layer 34, and upper capacitor-level dielectric layer 35.

[0061] Typically, the perforated spacer matrix 151' includes openings located in the gaps of the array of capped tubular bottom electrode portions 10B in a plan view. Discrete top surface segments of the upper etch-stop dielectric layer 34 are exposed in the gaps of the array of capped tubular bottom electrode portions 10B. Discrete top surface segments of the upper etch-stop dielectric layer 34 are exposed within the openings of the perforated spacer matrix 151'. In one embodiment, the inner sidewall of the perforated spacer matrix 151' is formed directly on a cylindrical surface segment of the outer sidewall of the capped tubular bottom electrode portion 10B, and the outer sidewall of the perforated spacer matrix 151' is laterally offset from the inner sidewall of the perforated spacer matrix 151' by a uniform lateral offset distance lod.

[0062] Reference Figures 10A-10C A selective etching process can be performed to selectively etch the unmasked portions of the upper etch stop dielectric layer 34 for the spacer material portions (151, 151', 151M), the capped tubular bottom electrode portion 10B, and the material of the second bottom electrode assembly layer 62. The selective etching process can be selective or non-selective for the material of the intermediate capacitor layer dielectric layer 33. The duration of the selective etching process can be selected such that the etching distance in the selective etching process is greater than the thickness of the upper etch stop dielectric layer 34. In a plan view, gap through-holes can be etched in the upper etch stop dielectric layer 34 at the gaps in the array of capped tubular bottom electrode portions 10B. The selective etching process for forming through-holes in the upper etch stop dielectric layer 34 at the gaps in the array of capped tubular bottom electrode portions 10B can include isotropic etching processes and / or anisotropic etching processes.

[0063] In a non-limiting illustrative example, the spacer material portions (151, 151', 151M) comprise silicon oxide materials (such as undoped silicate glass, doped silicate glass, or organosilicon glass), and the upper etch-stop dielectric layer 34 comprises silicon nitride. The selective etching process may include a wet etching process using a mixture of hydrofluoric acid (HF) and glycerol. The glycerol additive improves the selectivity of the silicon nitride-to-silicon oxide etching process by increasing the viscosity of the solution and altering the chemical interactions, thereby reducing the etching rate of the silicon oxide spacer material portions (151, 151', 151M) while effectively etching the upper etch-stop dielectric layer 34 of silicon nitride to form vias. For example, depending on process conditions (such as temperature and etching duration), a dilute HF solution (e.g., 1% HF by volume) mixed with glycerol in a ratio ranging from 1:10 to 1:100 (HF:glycerol) can be used to achieve a silicon nitride-to-silicon oxide selectivity of at least 10:1.

[0064] According to an aspect of this disclosure, the upper etch-stop dielectric layer 34 comprises silicon nitride, and the wet etching process uses a mixture of hydrofluoric acid and glycerol to form a capacitor structure comprising an array of capped tubular bottom electrode portions 10B within a pillar array region 300. According to an aspect of this disclosure, the wet etching process removes a vertical stack comprising an intermediate capacitor-level dielectric layer 33, an upper etch-stop dielectric layer 34, and an upper capacitor-level dielectric layer 35, wherein the intermediate capacitor-level dielectric layer 33 comprises silicon oxide, the upper etch-stop dielectric layer 34 comprises silicon nitride, and the upper capacitor-level dielectric layer 35 comprises silicon oxide with a thickness ranging from 1 µm to 2 µm. According to an aspect of this disclosure, a patterning process forms an array of pillar cavities 29 and trenches 27, followed by deposition of a bottom electrode assembly layer (61, 62) comprising titanium nitride. According to an aspect of this disclosure, an etching process removes the horizontally extended portions of the bottom electrode assembly layer (61, 62) comprising titanium nitride. According to an aspect of this disclosure, a deposition process forms an intermediate capacitor-level dielectric layer 33, which includes silicon oxide with a thickness ranging from 30 nm to 300 nm. According to an aspect of this disclosure, a dry etching process removes portions of the intermediate capacitor-level dielectric layer 33 including silicon oxide to expose an upper etch-stop dielectric layer 34 including silicon nitride. According to an aspect of this disclosure, a wet etching process uses a mixture of hydrofluoric acid and glycerol, with the hydrofluoric acid concentration ranging from 12.5% ​​to 24.5%, to remove portions of the upper etch-stop dielectric layer 34 including silicon nitride. According to an aspect of this disclosure, the wet etching process uses hydrofluoric acid with a concentration ranging from 12.5% ​​to 24.5% to fuse portions of the intermediate capacitor-level dielectric layer 33 including silicon oxide.

[0065] In embodiments where the upper etch-stop dielectric layer 34 comprises silicon nitride deposited via plasma-enhanced chemical vapor deposition (PECVD), a wet etching process using a mixture of hydrofluoric acid (HF) and glycerol typically achieves etch rates of 5 to 20 nm per minute for PECVD silicon nitride at room temperature (approximately 25°C). The low density and porous structure of PECVD silicon nitride, compared to silicon nitride deposited by other methods such as low-pressure chemical vapor deposition (LPCVD), affects the etch rate, resulting in a faster etch rate with the HF-glycerol solution. The etch rate of silicon oxide is lower than that of silicon nitride. Typically, during wet etching processes using a mixture of hydrofluoric acid (HF) and glycerol, the etch rate of silicon oxide can be less than 1 nm / min, ensuring that the integrity of the spacer material portions (151, 151', 151M) is not compromised. In this case, high selectivity is required to form vias in the upper etch-stop dielectric layer 34. Typically, the sidewall of the new via through the upper etch-stop dielectric layer 34 can be laterally offset from the outer sidewall of the proximal capped tubular bottom electrode portion 10B by a lateral spacing, which is in the range of 10% to 90% of the lateral offset distance lod, for example 20% to 80% and / or 30% to 70%. The remaining portion of the upper etch-stop dielectric layer 34 located within the pillar array region 300 is referred to as the etch-stop matrix 34M of the via.

[0066] The perforated etch stop substrate 34M includes perforations located at the gaps in the array of capped tubular bottom electrode portions 10B. In one embodiment, the total number of perforations in the perforated etch stop substrate 34M may be the sum of the total number of capped tubular bottom electrode portions 10B and the total number of gaps within the array of capped tubular bottom electrode portions 10B. In contrast, the total number of perforations in each of the lower capacitor level dielectric layer 31, lower etch stop dielectric layer 32, intermediate capacitor level dielectric layer 33, upper etch stop dielectric layer 34, and upper capacitor level dielectric layer 35 may be the same as the sum of the total number of capped tubular bottom electrode portions 10B and the number of trenches 27 (which is 1).

[0067] According to aspects of this disclosure, the capacitor bottom contact plate 42 comprises copper, and a wet etching process can use dilute hydrofluoric acid to form a high aspect ratio metal-insulator-metal capacitor structure 100, which may lead to structural failure of the capped tubular bottom electrode portion 10B. In one embodiment, the node dielectric layer 70L comprises a vertical stack of an intermediate capacitor-level dielectric layer 33 (comprising silicon oxide), an upper etch-stop dielectric layer 34 (comprising silicon nitride), and an upper capacitor-level dielectric layer 35 (comprising silicon oxide with a thickness in the range of 1 µm to 2 µm), and a wet etching process can remove the vertical stack from the dielectric material layer 30. In one embodiment, the intermediate capacitor-level dielectric layer 33 comprises silicon oxide with a thickness in the range of 30 nm to 300 nm, and a deposition process can form the intermediate capacitor-level dielectric layer 33 over the bottom electrode assembly layers (61, 62). In one embodiment, the upper etch stop dielectric layer 34 comprises silicon nitride, and the wet etching process may use a mixture of hydrofluoric acid and glycerol, with the hydrofluoric acid concentration ranging from 12.5% ​​to 24.5%, to remove a portion of the upper etch stop dielectric layer 34. In another embodiment, the upper etch stop dielectric layer 34 comprises silicon nitride, and the wet etching process may use a mixture of hydrofluoric acid and glycerol, with the hydrofluoric acid concentration ranging from 1% to 24.5%, to remove a portion of the upper etch stop dielectric layer 34.

[0068] In one embodiment, the intermediate capacitor layer dielectric layer 33 comprises silicon oxide, and the wet etching process can use hydrofluoric acid with a concentration in the range of 12.5% ​​to 24.5% to fuse portions of the intermediate capacitor layer dielectric layer 33 to form a cross-linked structure. In one embodiment, the upper etch stop dielectric layer 34 comprises silicon nitride or silicon carbide, and the wet etching process can use a mixture of hydrofluoric acid and glycerol, with the hydrofluoric acid concentration in the range of 12.5% ​​to 24.5%, to remove the upper etch stop dielectric layer 34. In one embodiment, the intermediate capacitor layer dielectric layer 33 comprises silicon oxide, and the wet etching process can achieve an etching rate in the range of 500 nm / min to 2000 nm / min. In one embodiment, the upper etch stop dielectric layer 34 comprises silicon nitride, and the wet etching process can achieve an etching rate in the range of 50 nm / min to 200 nm / min. In one embodiment, the upper etch stop dielectric layer 34 comprises silicon carbide, and the wet etching process can achieve an etching rate in the range of 3 nm / min to 10 nm / min. In one embodiment, the mixture of hydrofluoric acid and glycerol contains a high concentration of hydrofluoric acid, and the wet etching process can reduce the etch selectivity of the upper etch stop dielectric layer 34. In another embodiment, the mixture of hydrofluoric acid and glycerol contains a low concentration of hydrofluoric acid, and the wet etching process can slow down the etching of the upper etch stop dielectric layer 34.

[0069] In one embodiment, the total number of perforations in the etch-stop substrate 34M can be greater than the total number of perforations in each of the lower capacitor level dielectric layer 31, lower etch-stop dielectric layer 32, intermediate capacitor level dielectric layer 33, upper etch-stop dielectric layer 34, and upper capacitor level dielectric layer 35. The upper etch-stop dielectric layer 34 has more perforations in the region surrounded by the trench-shaped capacitor portion 10M (i.e., within the pillar array region 300) than the lower etch-stop dielectric layer 32 in the same region.

[0070] refer to Figures 11A to 11D The spacer material portions (151, 151', 151M) and the intermediate capacitor layer dielectric layer 33 (which covers the lower etch stop dielectric layer 32 and is located below the upper etch stop dielectric layer 34) can be selectively removed from the upper etch stop dielectric layer 34 (which includes a perforated etch stop substrate 34M), the lower etch stop dielectric layer 32, the capped tubular bottom electrode portion 10B and the second bottom electrode assembly layer 62. Figure 11D This is a perspective view of a portion of an exemplary structure immediately before the bottommost part of the intermediate capacitor level dielectric layer 33 is removed from the tubular bottom electrode portion 10B with a cap. The etching process is performed after the material of the intermediate capacitor level dielectric layer 33 has been removed (i.e., in the area having...). Figures 11A-11C After the processing steps of the exemplary structure shown in the diagram, the top surface of the lower etch stop dielectric layer 32 can be physically exposed around the capped tubular bottom electrode portion 10B. In the illustrative example, if the spacer material portions (151, 151', 151M) and the intermediate capacitor level dielectric layer 33 comprise silicon oxide material, a wet etching process using dilute hydrofluoric acid can be used to selectively etch the spacer material portions (151, 152', 151M) and the intermediate capacitor level dielectric layer 33 for the materials of the upper etch stop dielectric layer 34, the lower etch stop dielectric layer 32, the capped tubular bottom electrode portion 10B, and the second bottom electrode assembly layer 62. Typically, after etching gap perforations in the upper etch stop dielectric layer 34 using an etching process with etching chemicals selective for the material of the upper etch stop dielectric layer 34, the spacer material pillars 151 and the perforated spacer substrate 151' are removed.

[0071] According to an aspect of this disclosure, the perforated etch stop matrix 34M provides mechanical support for the array of capped tubular bottom electrode portions 10B, thereby preventing the capped tubular bottom electrode portions 10B from breaking during the etching process. The perforations in the perforated etch stop matrix 34M at the gaps in the array of capped tubular bottom electrode portions 10B allow the etchant of the etching process to etch the spacer material portions (151, 151', 151M) and the intermediate capacitor level dielectric layer 33 during the etching process, reaching the material of the intermediate capacitor level dielectric layer 33. Typically, the remaining portions of the spacer material layer 151L and the intermediate capacitor level dielectric layer 33 can be removed by performing a selective etching process. The perforated etch stop matrix 34M (which is a portion of the upper etch stop dielectric layer 34) laterally surrounds the array of capped tubular bottom electrode portions 10B and includes gap perforations located at the gaps in the array of capped tubular bottom electrode portions 10B in a plan view.

[0072] Typically, portions of the intermediate capacitor layer dielectric layer 33 located in the pillar array region 300 can be removed by supplying an etchant that selectively etches the material of the intermediate capacitor layer 33 onto the material of the upper etch stop dielectric layer 34, the material of the array of capped tubular bottom electrode portions 10B, and at least one bottom electrode assembly layer (61, 62). Cylindrical outer wall sections of the array of capped tubular bottom electrode portions 10B are exposed between the lower etch stop dielectric layer 32 and the upper etch stop dielectric layer 34. In one embodiment, the volume of the void formed by removing the material of the intermediate capacitor layer dielectric layer 33 can be fused to form a single continuous cavity.

[0073] The capped tubular bottom electrode portion 10B has a first vertical range VE1, which extends vertically from a horizontal reference plane HPR including the top surface of the capped tubular bottom electrode portion 10B to a first horizontal plane HP1 including the bottom surface of the capped tubular bottom electrode portion 10B. The first horizontal plane HP1 may include the top surface of the capacitor bottom contact plate 42. The matrix cavity 33' formed in the volume of the material portions of the removed intermediate capacitor level dielectric layer 33, upper etch stop dielectric layer 34, and upper capacitor level dielectric layer 35 has a second vertical range VE2, which extends vertically from the horizontal reference plane HPR to the second horizontal plane HP2 including the top surface of the lower etch stop dielectric layer 32. The upper portion of the matrix cavity 33', which is covered by a third horizontal plane HP3 (including the top surface of the upper etch stop dielectric layer 34), may have a third vertical range VE3, which extends vertically from the horizontal reference plane HPR to the third horizontal plane HP3.

[0074] The perforated etch stop substrate 34M may include at least one perforation therethrough. In one embodiment, each perforation in the perforated etch stop substrate 34M may have a corresponding set of at least three convex sidewalls, the at least three convex sidewalls being adjacent to each other along a vertically extending edge. In the illustrated example, each perforation in the perforated etch stop substrate 34M may have a corresponding set of four convex sidewalls, the four convex sidewalls being adjacent to each other along a vertically extending edge.

[0075] Reference Figure 12 For example, an additional bottom electrode assembly layer, referred to herein as a third bottom electrode assembly layer 63, can be conformally deposited using atomic layer deposition and / or chemical vapor deposition processes. The third bottom electrode assembly layer 63 can be deposited on the inner cylindrical sidewall of the capped tubular bottom electrode portion 10B, on a cylindrical segment of the outer cylindrical sidewall of the capped tubular bottom electrode portion 10B, and on the sidewall of the via in the upper etch stop dielectric layer 34 (i.e., on the sidewall of the via in the etch stop substrate 34M of the via). Furthermore, the third bottom electrode assembly layer 63 can be deposited on the top and bottom surfaces of the etch stop substrate 34M of the via.

[0076] The third bottom electrode assembly layer 63 comprises a metallic material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), titanium (Ti), tantalum (Ta), molybdenum (Mo), tungsten (W), cobalt (Co), ruthenium (Ru), etc. The thickness of the third bottom electrode assembly layer 63 can range from about 4 nm to about 100 nm, such as from about 6 nm to about 30 nm, but smaller or larger thicknesses are also possible. The combination of at least one bottom electrode assembly layer (61, 62) and an additional bottom electrode assembly (i.e., bottom electrode assembly 63) constitutes a composite bottom electrode material layer 60L.

[0077] Reference Figure 13 The node dielectric layer 70L can be conformally deposited on the physically exposed surface of the composite bottom electrode material layer 60L. The node dielectric layer 70L can include any node dielectric material known in the art. For example, the node dielectric layer 70L can include dielectric materials selected from silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), or combinations thereof. The thickness of the node dielectric layer 70 can range from about 2 nm to about 50 nm, but smaller or larger thicknesses can also be used.

[0078] Reference Figure 14The top electrode layer 80L can be conformally deposited over the node dielectric layer 70L. The top electrode layer 80L includes at least one conductive material, such as at least one metallic material. For example, the top electrode layer 80L may include at least one metallic material selected from TiN, TaN, MoN, WN, Ti, Ta, Mo, W, Co, Ru, etc. The thickness of the horizontal extension of the node dielectric layer 70L overlying the horizontal extension of the top electrode layer 80L outside the pillar array region 300 can be in the range of about 10 nm to about 300 nm, such as from about 30 nm to about 100 nm, but smaller or larger thicknesses can also be used.

[0079] According to aspects of this disclosure, a sealed cavity 24' completely sealed by the top electrode layer 80L can be formed within a volume sealed by the top electrode layer 80L. The sealed cavity 24' can be located entirely between the lower etch stop dielectric layer 32 and the upper etch stop dielectric layer 34. In the case where a plurality of through-holes extend vertically through the etch stop substrate 34M, the sealed cavity 24' can extend continuously around the capped tubular bottom electrode portion 10B such that the sealed cavity 24' is located below each through-hole in the through-hole etch stop substrate 34M.

[0080] Reference Figure 15 At least one continuous dielectric capping layer (91L, 92L) can be deposited over the top electrode layer 80L. For example, a stack of a first continuous dielectric capping layer 91L and a second continuous dielectric capping layer 92L can be deposited over the top electrode layer 80L. The first continuous dielectric capping layer 91L may comprise a silicon oxide-based dielectric material, such as undoped silicate glass, doped silicate glass, or organosilicon glass. The second continuous dielectric capping layer 92L may comprise silicon nitride or silicon carbonitride. The thickness of the first continuous dielectric capping layer 91L can range from about 30 nm to about 600 nm, but smaller or larger thicknesses are also possible. The thickness of the second continuous dielectric capping layer 92L can also range from about 30 nm to about 600 nm, but smaller or larger thicknesses are also possible.

[0081] Reference Figure 16 A mask layer can be applied over at least one continuous dielectric capping layer (91L, 92L). The mask layer may include a photoresist layer 197 applied over at least one continuous dielectric capping layer (91L, 92L) and may be photolithographically patterned to form a patterned photoresist material portion covering the entire area of ​​the pillar array region 300 and the trench 27. The sidewalls of the patterned photoresist material portion may be located outside the area formed by the outer sidewalls of the trench 27.

[0082] An anisotropic etching process can be performed to remove unmasked portions of at least one continuous dielectric capping layer (91L, 92L). The patterned portion of the at least one continuous dielectric capping layer (91L, 92L) includes at least one dielectric capping layer (91, 92). In one embodiment, the at least one dielectric capping layer (91, 92) may include a vertical stack of a first dielectric capping layer 91 and a second dielectric capping layer 92. The sidewalls of the second dielectric capping layer 92 may be perpendicularly aligned with the sidewalls of the first dielectric capping layer 91. The sidewalls of the at least one dielectric capping layer (91, 92) may overlay a horizontal extension of the top electrode layer 80L, the node dielectric layer 70L, and the composite bottom electrode layer 60L. The photoresist layer 197 can then be removed, for example, by ashing.

[0083] Reference Figure 17 A dielectric spacer material layer (such as a silicon nitride layer, silicon carbide layer, or silicon carbonitride layer) can be conformally deposited and can be etched (e.g., anisotropic etching) to form a dielectric cap spacer 93. The dielectric cap spacer 93 laterally surrounds at least one dielectric cap layer (91, 92). The lateral thickness of the dielectric cap spacer 93, measured between the inner and outer sidewalls, can range from about 100 nm to about 1000 nm, but smaller or larger thicknesses can also be used.

[0084] Reference Figure 18 An anisotropic etching process can be performed to remove portions of the top electrode layer 80L, node dielectric layer 70L, and composite bottom electrode layer 60L that are not masked by the combination of at least one dielectric capping layer (91, 92) and dielectric cap spacer 93. The patterned portion of the top electrode layer 80L, located beneath the combination of at least one dielectric capping layer (91, 92) and dielectric cap spacer 93, includes a top electrode 80. The patterned portion of the node dielectric layer 70L, located beneath the combination of at least one dielectric capping layer (91, 92) and dielectric cap spacer 93, includes a node dielectric 70. The patterned portion of the composite bottom electrode layer 60L, located beneath the combination of at least one dielectric capping layer (91, 92) and dielectric cap spacer 93, includes a composite bottom electrode 60. In one embodiment, the composite bottom electrode 60 may include a stack of layers of a first bottom electrode assembly layer 61, a second bottom electrode assembly layer 62, and a third bottom electrode assembly layer 63.

[0085] An exemplary structure includes a dielectric material layer 30 overlying a substrate 9. Typically, the dielectric material layer 30 includes, from bottom to top, a lower capacitor-level dielectric layer 31, an etch-stop dielectric layer (such as an upper etch-stop dielectric layer 34), and an upper capacitor-level dielectric layer 35. A capacitor structure 100 including an array of columnar capacitor portions 10P is located within the dielectric material layer 30 in a columnar array region 300 in a plan view. The capacitor structure 100 also includes a capacitor top portion 10T adjacent to the top of the columnar capacitor portions 10P and overlying the dielectric material layer 30. The array of columnar capacitor portions 10P has a first vertical range VE1.

[0086] According to an aspect of this disclosure, the capacitor structure 100 includes a gap capacitor portion 10I that laterally surrounds a first subset of columnar capacitor portions 10P and has a second vertical range VE2 smaller than the first vertical range VE1. An etch stop dielectric layer (such as an upper etch stop dielectric layer 34) laterally surrounds an array of columnar capacitor portions 10P and includes gap vias located at the gaps in the array of columnar capacitor portions 10P in a plan view.

[0087] In one embodiment, the gap capacitor portion 10I includes: a lower gap capacitor sub-portion 10IL, which lies below a horizontal plane including a bottom surface of an etch stop dielectric layer (such as an upper etch stop dielectric layer 34); an upper gap capacitor sub-portion 10IU, which overlies another horizontal plane including a top surface of an etch stop dielectric layer; and an intermediate gap capacitor sub-portion 10IM, which extends through an etch stop dielectric layer (such as an upper etch stop dielectric layer 34) and has a smaller area in a plan view than the lower gap capacitor sub-portion 10IL. In one embodiment, the capacitor structure 100 includes a trench-shaped capacitor portion 10M that laterally surrounds an array of columnar capacitor portions 10P and is adjacent to a top portion 10T of the capacitor.

[0088] Reference Figure 19 Upper-level dielectric layers (36, 37, 38) may be deposited over at least one dielectric capping layer (91, 92). The upper-level dielectric layers (36, 37, 38) may, for example, include a first upper-level dielectric layer 36, an upper-level etch-stop dielectric layer 37, and a second upper-level dielectric layer 38. In an illustrative example, each of the first upper-level dielectric layer 36 and the second upper-level dielectric layer 38 may include a respective silicon oxide-based dielectric material, such as undoped silicate glass, doped silicate glass, or organosilicon glass, and the upper-level etch-stop dielectric layer 37 may include a dielectric etch-stop material, such as silicon nitride, silicon carbonitride, silicon oxynitride, or at least one dielectric metal oxide.

[0089] Reference Figure 20 The upper electrode connection metal interconnect structure (86, 88) may be formed through the upper layer dielectric material layers (36, 37, 38). The upper electrode connection metal interconnect structure (86, 88) may include an upper electrode connection via structure 86 and an upper electrode connection metal line 88. The upper electrode connection via structure 86 extends vertically through the first upper layer dielectric material layer 36 and at least one dielectric capping layer (91, 92) and contacts the top surface of the top electrode 80. The upper electrode connection metal line 88 is formed through the upper layer etch stop dielectric layer 37 and the second upper layer dielectric material layer 38. Depending on the thickness of the deposited material of the top electrode 80 (as measured below the dielectric capping spacer 93), the upper electrode connection via structure 86 may include (or may not include) a downwardly projecting portion that extends below the horizontal extension of the top electrode 80 covering the capped tubular bottom electrode portion 10B.

[0090] Reference Figure 21 An alternative configuration of the exemplary structure according to embodiments of the present disclosure is shown. In an alternative configuration of the exemplary structure, the thickness of the horizontal extension of the top electrode 80 may be increased to provide a flat top surface extending laterally over the entire array of the covered tubular bottom electrode portions 10B. In this embodiment, the upper electrode connection through-hole structure 86 does not include a downwardly projecting portion extending below the horizontal extension of the top electrode 80 covering the covered tubular bottom electrode portions 10B.

[0091] Generally, various embodiments of this disclosure provide a device structure including: a dielectric material layer 30 overlying a substrate 9, wherein the dielectric material layer 30 includes, from bottom to top, a lower capacitor-level dielectric layer 31, an etch-stop dielectric layer 34, and an upper capacitor-level dielectric layer 35; and a capacitor structure 100 including an array of columnar capacitor portions 10P located in the columnar array region in the plan view within the dielectric material layer 30, and further including a capacitor top portion 10T adjacent to the top of the columnar capacitor portions 10P and overlying the dielectric material segment 30, wherein the etch-stop dielectric layer 34 laterally surrounds the array of columnar capacitor portions 10P, and includes gap vias located at the gaps in the array of columnar capacitor portions 10P in the plan view.

[0092] In one embodiment, the capacitor structure 100 includes a trench-shaped capacitor portion 10M that laterally surrounds an array of columnar capacitor portions 10P and is adjacent to a top portion 10T of the capacitor.

[0093] In one embodiment, the dielectric material layer 30 includes: an additional etch-stop dielectric layer 32 overlying the lower capacitor-level dielectric layer 31; and an intermediate capacitor-level dielectric layer 33 overlying the additional etch-stop dielectric layer 32 and located below the etch-stop dielectric layer 34, wherein the etch-stop dielectric layer 34 has more perforations in the region surrounded by the trench-shaped capacitor portion 10M than the additional etch-stop dielectric layer 32 in the region surrounded by the trench-shaped capacitor portion 10M.

[0094] In one embodiment, the array of columnar capacitor portions 10P has a first vertical range VE1; the capacitor structure 100 includes a gap capacitor portion 106I that laterally surrounds a first subset of the columnar capacitor portions 10P and has a second vertical range VE2 that is smaller than the first vertical range VE1.

[0095] In one embodiment, the gap capacitor portion 10I includes: a lower gap capacitor sub-portion 10IL, which is located below a horizontal plane including the bottom surface of the etch stop dielectric layer 34; an upper gap capacitor sub-portion 10IU, which is overlaid on another horizontal plane including the top surface of the etch stop dielectric layer 34; and an intermediate gap capacitor sub-portion 10IM, which passes through the etch stop dielectric layer 34 and has a smaller area in a plan view than the lower gap capacitor sub-portion 10IL.

[0096] According to aspects of this disclosure, capacitor structure 100 includes a high aspect ratio metal-insulator-metal capacitor structure, and the forming process may include cross-linked structures within the column array region 300.

[0097] In one embodiment, substrate 9 includes a capacitor bottom contact plate 42 comprising copper, and a deposition process can form the capacitor bottom contact plate 42 below the dielectric material layer 30. In one embodiment, a lower etch-stop dielectric layer 32 comprises silicon nitride, and a deposition process can form the lower etch-stop dielectric layer 32 above the capacitor bottom contact plate 42. In one embodiment, a lower capacitor-level dielectric layer 31 comprises silicon oxide, and a deposition process can form the lower capacitor-level dielectric layer 31 above the lower etch-stop dielectric layer 32. In one embodiment, bottom electrode assembly layers (61, 62) comprise titanium nitride, and a deposition process can form a capped tubular bottom electrode portion 10B within an array of cylindrical cavities 29 defined by a first lateral dimension and a second lateral dimension. In one embodiment, an intermediate capacitor-level dielectric layer 33 comprises silicon oxide, and a wet etching process can fuse portions of the intermediate capacitor-level dielectric layer 33 on different sides of the capped tubular bottom electrode portion 10B to form a cross-linked structure. In one embodiment, the upper etch-stop dielectric layer 34 comprises silicon nitride or silicon carbide, and a wet etching process can partially remove the upper etch-stop dielectric layer 34 to expose an intermediate capacitor-level dielectric layer 33 comprising silicon oxide. In one embodiment, the top electrode layer 80L comprises titanium nitride, and a deposition process can form the top electrode layer 80L over the node dielectric layer 70L. In one embodiment, the dielectric capping layer 91L comprises silicon oxide, and a deposition process can form the dielectric capping layer 91L over the top electrode layer 80L. In one embodiment, the dielectric capping layer 92L comprises silicon nitride, and a deposition process can form the dielectric capping layer 92L over the dielectric capping layer 91L. In one embodiment, the dielectric capping layer 91L comprises silicon oxide, and a chemical mechanical polishing process can planarize the dielectric capping layer 91L. In one embodiment, the capacitor structure 100 includes a cross-linked structure, and the formation process can be configured for use in a CMOS image sensor.

[0098] Generally, various embodiments of this disclosure provide methods and structures for forming a high aspect ratio metal-insulator-metal capacitor structure 100. In one embodiment of this disclosure, the dielectric material layer 30 includes a lower capacitor-level dielectric layer 31, an upper etch-stop dielectric layer 34, and an upper capacitor-level dielectric layer 35 and is deposited over a substrate 9. In one embodiment of this disclosure, an array of cylindrical cavities 29 is etched through the dielectric material layer 30. In one embodiment of this disclosure, at least one bottom electrode assembly layer (61, 62) is deposited and patterned on the sidewalls of the array of cylindrical cavities 29 to form a capped tubular bottom electrode portion 10B. In one embodiment of this disclosure, gap vias are formed in the upper etch-stop dielectric layer 34 at the gaps in the array of capped tubular bottom electrode portions 10B. In one embodiment of this disclosure, an additional bottom electrode assembly layer 63, a node dielectric layer 70L, and a top electrode layer 80L are deposited over the upper etch-stop dielectric layer 34. In one embodiment of this disclosure, the capacitor structure 100 includes an array of columnar capacitor portions 10P within a dielectric material layer 30 in a columnar array region 300, wherein the upper etch-stop dielectric layer 34 has gap perforations.

[0099] See Figure 22 The first flowchart of this disclosure illustrates the steps for forming a device structure.

[0100] Refer to step 2210 and Figure 1 A dielectric material layer 30 can be deposited above the substrate 9. The dielectric material layer 30 includes, from bottom to top, a lower capacitor-level dielectric layer 31, an etch-stop dielectric layer 34, and an upper capacitor-level dielectric layer 35.

[0101] Refer to steps 2220 and Figures 2A-2C It can etch the array of pillar cavities 29 through the dielectric material layer 30.

[0102] Refer to steps 2230 and Figures 3-7C At least one bottom electrode assembly layer (61, 62) can be deposited and patterned on the sidewall of the cylinder 29 and above the upper capacitor level dielectric layer 35, such that the top surface segment of the upper capacitor level dielectric layer 35 is exposed around the array of cylinders 29, and an array of capped tubular bottom electrode portions 10B is retained in the cylinder 29.

[0103] Refer to step 2240 and Figures 8-10B Gap perforations can be etched in the etch-stop dielectric layer 34 at the gaps in the array of the capped tubular bottom electrode portion 10B in the plan view.

[0104] Refer to step 2250 and Figures 11A-21An additional bottom electrode assembly layer 63, a node dielectric layer 70L, and a top electrode layer 80L may be deposited over the patterned portion of the etch stop dielectric layer 34 and at least one bottom electrode assembly layer (61, 62).

[0105] See Figure 23 The second flowchart of this disclosure illustrates the steps for forming the device structure.

[0106] Refer to step 2310 and Figure 1 A dielectric material layer 30 can be deposited above the substrate 9. The dielectric material layer 30 includes, from bottom to top, a lower capacitor-level dielectric layer 31, a lower etch-stop dielectric layer 32, a middle capacitor-level dielectric layer 33, an upper etch-stop dielectric layer 34, and an upper capacitor-level dielectric layer 35.

[0107] Refer to step 2320 and Figures 2A-6C The array of the capped tubular bottom electrode portion 10B can be patterned through the dielectric material layer 30 within the column array region 300.

[0108] Refer to steps 2330 and Figures 7A to 7C The upper capacitor layer dielectric layer 35 can be etched from the pillar array region 300.

[0109] Refer to steps 2340 and Figures 8-9C Spacer material portions (151, 151', 151M) can be formed around and inside the capped tubular bottom electrode portion 10B. Discrete top surface segments of the upper etch-stop dielectric layer 34 are exposed at the gaps in the array of the capped tubular bottom electrode portions 10B.

[0110] Refer to step 2350 and Figures 10A-10C Through-holes can be formed in the upper etch stop dielectric layer 34 in the pillar array region 300.

[0111] Refer to step 2360 and Figures 11A-11D The intermediate capacitor layer dielectric layer 33 can be selectively removed from the pillar array region 300 to the upper etch stop dielectric layer 34.

[0112] Refer to step 2370 and Figures 12-21 The node dielectric layer 70L and the top electrode layer 80L can be deposited above the array of the upper etch stop dielectric layer 34 and the capped tubular bottom electrode portion 10B.

[0113] According to an aspect of this disclosure, a method for forming a device structure is provided, the method comprising: depositing a dielectric material layer 30 over a substrate 9, wherein the dielectric material layer 30 includes, from bottom to top, a lower capacitor-level dielectric layer 31 comprising silicon oxide, a lower etch-stop dielectric layer 32 comprising silicon nitride, an intermediate capacitor-level dielectric layer 33 comprising silicon oxide, an upper etch-stop dielectric layer 34 comprising silicon nitride, and an upper capacitor-level dielectric layer 35 comprising silicon oxide; etching an array of pillar cavities 29 and trenches 27 through the dielectric material layer 30 within a pillar array region 300; depositing a bottom electrode assembly layer (61, 62) comprising titanium nitride over the array of pillar cavities 29 and trenches 27; and depositing a bottom electrode assembly layer (61, 62) comprising titanium nitride over the bottom electrode assembly layer 30. An intermediate capacitor-level dielectric layer 33 comprising silicon oxide is deposited over the electrode assembly layers (61, 62) and the upper etch-stop dielectric layer 34; a portion of the intermediate capacitor-level dielectric layer 33 comprising silicon oxide is etched to expose the upper etch-stop dielectric layer 34; a portion of the upper etch-stop dielectric layer 34 comprising silicon nitride is etched using a mixture of hydrofluoric acid and glycerol and a wet etching process using hydrofluoric acid concentration in the range of 1% to 24.5%; a portion of the intermediate capacitor-level dielectric layer 33 comprising silicon oxide is fused to form a cross-linked structure; and a node dielectric layer 70L and a top electrode layer 80L are deposited over the array of the upper etch-stop dielectric layer 34 and the capped tubular bottom electrode portion 10B.

[0114] Various embodiments of this disclosure provide a high aspect ratio metal-insulator-metal capacitor (MIMCAP) structure and a method of forming the same. The MIMCAP structure of this disclosure includes an array of columnar capacitor portions embedded within a dielectric material layer. The dielectric material layer may include, from bottom to top, a lower capacitor-level dielectric layer, an upper etch-stop dielectric layer, and an upper capacitor-level dielectric layer. In one embodiment, the MIMCAP structure may include a capacitor top adjacent to the array of columnar capacitor portions, a gap capacitor portion, and a trench-shaped portion laterally surrounding the array of columnar capacitor portions. The MIMCAP structure may include a composite bottom electrode, a node dielectric, and a top electrode. The etch-stop matrix of the perforations within the upper etch-stop dielectric layer includes gap perforations at the gaps in the array of columnar capacitor portions to provide a selective etch process during manufacturing.

[0115] A perforated etch-stop matrix laterally surrounds and provides structural support to an array of high aspect ratio capped tubular bottom electrode portions. The perforated etch-stop matrix of this disclosure mechanically supports the array of high aspect ratio capped tubular bottom electrode portions during selective etching processes. Selective etching processes can be performed to remove intermediate capacitor-level dielectric layers located between lower and upper etch-stop dielectric layers. The gap perforations in the perforated etch-stop matrix allow etchant to pass through during selective etching processes to remove portions of the intermediate capacitor-level dielectric layers. Therefore, the MIMCAP structures of embodiments of this disclosure can reduce structural defects in the capped tubular bottom electrode portions. Thus, the MIMCAP structures of various embodiments of this disclosure improve manufacturability and yield in semiconductor device fabrication.

[0116] According to an aspect of this disclosure, the upper etch-stop dielectric layer 34 includes a perforated etch-stop matrix 34M having gap vias within the pillar array region 300. According to an aspect of this disclosure, the gap vias in the perforated etch-stop matrix 34M allow isotropic etchant to pass through to remove the intermediate capacitor-level dielectric layer 33, which includes silicon oxide. According to an aspect of this disclosure, during the isotropic etching process, the perforated etch-stop matrix 34M mechanically supports an array of capped tubular bottom electrode portions 10B. According to an aspect of this disclosure, the gap vias provide selective etching of the intermediate capacitor-level dielectric layer 33 while preventing the collapse of the high aspect ratio capped tubular bottom electrode portions 10B.

[0117] In some embodiments, a method of forming a semiconductor device structure includes: depositing a dielectric material layer over a substrate, wherein the dielectric material comprises, from bottom to top, a lower capacitor-level dielectric layer, an etch-stop dielectric layer, and an upper capacitor-level dielectric layer; etching an array of cavities through the dielectric material layer; depositing and patterning at least one bottom electrode assembly layer on the sidewalls of each of the arrays of cavities and over the upper capacitor-level dielectric layer, such that a top surface segment of the upper capacitor-level dielectric layer is exposed around each of the arrays of cavities, and an array of capped tubular bottom electrode portions is retained in each of the arrays of cavities; in a plan view, etching gap vias in the etch-stop dielectric layer at the gaps in the array of capped tubular bottom electrode portions; and depositing an additional bottom electrode assembly layer, a node dielectric layer, and a top electrode layer over the patterned portions of the etch-stop dielectric layer and the at least one bottom electrode assembly layer.

[0118] In some embodiments, the method further includes: depositing a sacrificial filler material layer in the voids within the array of cylinders after depositing the at least one bottom electrode assembly layer; removing a portion of the sacrificial filler material layer from a region having a periphery that laterally surrounds the array of cylinders in the plan view; and using the sacrificial filler material layer as an etch mask to etch a portion of the at least one bottom electrode assembly layer, thereby exposing a top surface segment of the upper capacitor level dielectric layer around the array of cylinders.

[0119] In some embodiments, the method further includes: removing the sacrificial filler layer; and etching portions of the upper capacitor-level dielectric layer not masked by the at least one bottom electrode assembly layer, wherein the top surface of the etch-stop dielectric layer is exposed.

[0120] In some embodiments, the method further includes: forming a patterned photoresist layer over the top surface of the sacrificial filler layer, such that the top surface of the sacrificial filler layer is exposed below an opening in the patterned photoresist layer within the region of the array of cylinders; and etching an unmasked portion of the sacrificial filler layer below the opening in the patterned photoresist layer, thereby physically exposing the top surface segment of the perforation of the at least one bottom electrode assembly layer.

[0121] In some embodiments, the method further includes: removing a portion of the upper capacitor level dielectric layer around the array of the covered tubular bottom electrode portions, thereby exposing the top surface of the etch stop dielectric layer; and forming a perforated spacer matrix around the array of the covered tubular bottom electrode portions, wherein, in the plan view, the perforated spacer matrix includes openings located at gaps in the array of the covered tubular bottom electrode portions.

[0122] In some embodiments, the method further includes: conformally depositing a spacer material layer within the gaps in the array of the covered tubular bottom electrode portions, around the upper region of the array of each of the covered tubular top electrode portions, and above the etch-stop dielectric layer; and anisotropically etching the spacer material layer, wherein the remaining portion of the spacer material layer located outside the array of the covered tubular bottom electrode portions comprises the perforated spacer matrix.

[0123] In some embodiments, the inner sidewall of the perforated spacer matrix is ​​directly formed on a cylindrical surface segment of the outer sidewall of the array of each of the covered tubular bottom electrode portions; and the outer sidewall of the perforated spacer matrix is ​​laterally offset from the inner sidewall of the perforated spacer matrix by a uniform lateral offset distance.

[0124] In some embodiments, the array of the covered tubular bottom electrode portions is arranged as a periodic two-dimensional array; and the uniform lateral offset distance is greater than 1 / 2 of the nearest neighbor distance within the array of the covered tubular bottom electrode portions and less than 1 / 2 of the second nearest neighbor distance within the array of the covered tubular top electrode portions.

[0125] In some embodiments, an additional remaining portion of the spacer material layer located within the array of the capped tubular bottom electrode portions includes spacer material pillars; and the method includes removing the spacer material pillars and the perforated spacer matrix after etching gap perforations in the etch stop dielectric layer using an etching process having etching chemicals selective for the material of the etch stop dielectric layer.

[0126] In some embodiments, the dielectric material layer includes an additional etch-stop dielectric layer and an intermediate capacitor-level dielectric layer located between the lower capacitor-level dielectric layer and the etch-stop dielectric layer; the method includes etching a portion of the intermediate capacitor-level dielectric layer by providing an etchant to the material of the etch-stop dielectric layer to selectively etch the material of the intermediate capacitor-level dielectric layer; a cylindrical outer wall section of the array of capped tubular bottom electrode portions is exposed between the additional etch-stop dielectric layer and the etch-stop dielectric layer; and the additional bottom electrode assembly layer is deposited on the sidewall of the cylindrical outer wall section.

[0127] In some embodiments, a method of forming a semiconductor device structure includes: depositing a dielectric material layer over a substrate, wherein the dielectric material layer comprises, from bottom to top, a lower capacitor-level dielectric layer, a lower etch-stop dielectric layer, an intermediate capacitor-level dielectric layer, an upper etch-stop dielectric layer, and an upper capacitor-level dielectric layer; forming an array of covered tubular bottom electrode portions through the dielectric material layer within a pillar array region; etching the upper capacitor-level dielectric layer from the pillar array region; forming spacer material portions around and inside the array of covered tubular bottom electrode portions, wherein discrete top surface segments of the upper etch-stop dielectric layer are exposed at gaps in the array of covered tubular bottom electrode portions; forming vias in the upper etch-stop dielectric layer in the pillar array region; selectively removing the intermediate capacitor-level dielectric layer from the pillar array region to the upper etch-stop dielectric layer; and depositing a node dielectric layer and a top electrode layer over the upper etch-stop dielectric layer and the array of covered tubular bottom electrode portions.

[0128] In some embodiments, the method further includes: etching an array of pillar cavities through the dielectric material layer; and depositing and patterning at least one bottom electrode assembly layer, wherein the remaining portion of the at least one top electrode assembly layer retained within the array of pillar cavities comprises an array of the capped tubular bottom electrode portions.

[0129] In some embodiments, the method further includes: conformally depositing a spacer material layer in the array of the capped tubular bottom electrode portions and above the upper etch-stop dielectric layer; anisotropically etching the spacer material layer, wherein the remaining portion of the spacer material layer comprises spacer material portions; and forming a perforated spacer matrix in one of the spacer material portions outside the array of each of the capped tubular bottom electrode portions.

[0130] In some embodiments, the discrete top surface segments of the upper etch-stop dielectric layer are exposed within openings in the perforated spacer matrix.

[0131] In some embodiments, the method further includes depositing an additional bottom electrode assembly layer on the inner cylindrical sidewall of each of the arrays of the covered tubular bottom electrode portions, on the cylindrical section of the outer cylindrical sidewall of the covered tubular top electrode portion, and on the sidewall of the perforation in the upper etch-stop dielectric layer.

[0132] In some embodiments, a semiconductor device structure includes: a dielectric material layer overlying a substrate, wherein the dielectric material comprises, from bottom to top, a lower capacitor-level dielectric layer, an etch-stop dielectric layer, and an upper capacitor-level dielectric layer; and a capacitor structure including an array of columnar capacitor portions within the dielectric material layer located in a columnar array region in a plan view, and further including a capacitor top portion adjacent to and overlying the top of the array of each of the columnar capacitor portions, wherein the etch-stop dielectric layer laterally surrounds the array of columnar capacitor portions, and includes gap vias located at the gaps in the array of columnar capacitor portions in a plan view.

[0133] In some embodiments, the capacitor structure includes a trench-shaped capacitor portion that laterally surrounds an array of columnar capacitor portions and is adjacent to the top portion of the capacitor.

[0134] In some embodiments, the dielectric material layer includes: an additional etch-stop dielectric layer overlying the lower capacitor-level dielectric layer; and an intermediate capacitor-level dielectric layer overlying the additional etch-stop dielectric layer and located below the etch-stop dielectric layer, wherein the etch-stop dielectric layer has more perforations in the region surrounded by the trench-shaped capacitor portion than the additional etch-stop dielectric layer in the region surrounded by the trench-shaped capacitor portion.

[0135] In some embodiments, each of the arrays of the columnar capacitor portions has a first vertical range; the capacitor structure includes a gap capacitor portion that laterally surrounds a first subset of the array of the columnar capacitor portions and has a second vertical range smaller than the first vertical range.

[0136] In some embodiments, the gap capacitor portion includes: a lower gap capacitor sub-portion located below a horizontal plane including the bottom surface of the etch stop dielectric layer; an upper gap capacitor sub-portion covering another horizontal plane including the top surface of the etch stop dielectric layer; and an intermediate gap capacitor sub-portion extending through the etch stop dielectric layer and having a smaller area in a plan view than the lower gap capacitor sub-portion.

[0137] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Unless expressly stated otherwise herein, each embodiment described using the term "comprising" also inherently discloses other embodiments in which the word "comprising" is replaced by "consistent with" or "comprises from". When two or more elements are listed as alternatives in the same or different paragraphs, a Markus group comprising the list of those two or more elements is also implicitly disclosed. In this disclosure, whenever the auxiliary verb "may" is used to describe the formation of an element or the execution of a process step, embodiments in which that element or process step is not performed are also explicitly contemplated, provided that the resulting apparatus or device can provide equivalent results. Therefore, when omitting the execution of the formation or processing step of an element can provide the same or equivalent results, the auxiliary verb "may" used to describe the execution of the element formation or processing step should also be interpreted as "may" or "may or may not". Equivalent results include slightly better results and slightly worse results. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that they can be modified, replaced, and altered in various ways within this disclosure without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device structure, comprising: A dielectric material layer is deposited above a substrate, wherein the dielectric material comprises, from bottom to top, a lower capacitor-level dielectric layer, an etch-stop dielectric layer, and an upper capacitor-level dielectric layer; An array of column cavities etched through the dielectric material layer; At least one bottom electrode assembly layer is deposited and patterned on the sidewalls of each of the column cavity arrays and above the upper capacitor level dielectric layer, such that the top surface segment of the upper capacitor level dielectric layer is exposed around each of the column cavity arrays, and an array of capped tubular bottom electrode portions is retained in each of the column cavity arrays. In the plan view, etch gap perforations are etched in the etch-stop dielectric layer at the gaps in the array of the capped tubular bottom electrode portions; and An additional bottom electrode assembly layer, a node dielectric layer, and a top electrode layer are deposited over the patterned portion of the etch stop dielectric layer and the at least one bottom electrode assembly layer.

2. The method according to claim 1, further comprising: After depositing the at least one bottom electrode assembly layer, a sacrificial filler material layer is deposited in the voids within the array of cylindrical cavities; A portion of the sacrificial filler material layer is removed from the region having the periphery of an array that laterally surrounds the column cavity in the plan view; as well as Using the sacrificial filler layer as an etching mask, a portion of the at least one bottom electrode assembly layer is etched, thereby exposing the top surface segment of the upper capacitor level dielectric layer around the array of cylinders.

3. The method according to claim 2, further comprising: Remove the sacrificial filler layer; as well as Etch the portion of the upper capacitor layer dielectric layer not covered by the at least one bottom electrode assembly layer, wherein the top surface of the etch-stop dielectric layer is exposed.

4. The method according to claim 2, further comprising: A patterned photoresist layer is formed above the top surface of the sacrificial filler layer, such that the top surface of the sacrificial filler layer is exposed below an opening in the patterned photoresist layer within the region of the array of cylindrical cavities; as well as Etch the unmasked portion of the sacrificial filler layer below the opening in the patterned photoresist layer to physically expose the top surface segment of the perforation of the at least one bottom electrode assembly layer.

5. The method according to claim 1, further comprising: Remove a portion of the upper capacitor-level dielectric layer around the array of the capped tubular bottom electrode portions, thereby exposing the top surface of the etch-stop dielectric layer; as well as A perforated spacer matrix is ​​formed around the array of the covered tubular bottom electrode portions, wherein, in the plan view, the perforated spacer matrix includes openings located at the gaps in the array of the covered tubular bottom electrode portions.

6. The method according to claim 5, further comprising: A spacer material layer is conformally deposited in the gaps of the array of the capped tubular bottom electrode portions, around the upper region of the array of each of the capped tubular top electrode portions, and above the etch stop dielectric layer. as well as The spacer material layer is anisotropically etched, wherein the remaining portion of the spacer material layer located outside the array of the capped tubular bottom electrode portion includes the perforated spacer matrix.

7. The method according to claim 6, wherein: The inner wall of the perforated spacer matrix is ​​formed directly on the cylindrical surface segment of the outer wall of the array of each of the covered tubular bottom electrode portions. as well as The outer sidewall of the perforated spacer matrix is ​​laterally offset from the inner sidewall of the perforated spacer matrix by a uniform lateral offset distance.

8. The method according to claim 1, wherein: The dielectric material layer includes an additional etch stop dielectric layer and an intermediate capacitor layer located between the lower capacitor layer dielectric layer and the etch stop dielectric layer; The method includes etching a portion of the intermediate capacitor level dielectric layer by providing an etchant to the material of the etch stop dielectric layer to selectively etch the material of the intermediate capacitor level dielectric layer; The cylindrical outer wall section of the array of the capped tubular bottom electrode portions is exposed between the additional etch stop dielectric layer and the etch stop dielectric layer; and The additional bottom electrode assembly layer is deposited on the sidewall of the cylindrical outer sidewall section.

9. A method for forming a semiconductor device structure, comprising: A dielectric material layer is deposited above a substrate, wherein the dielectric material layer comprises, from bottom to top, a lower capacitor-level dielectric layer, a lower etch-stop dielectric layer, a middle capacitor-level dielectric layer, an upper etch-stop dielectric layer, and an upper capacitor-level dielectric layer. An array of capped tubular bottom electrode portions is formed within the column array region, passing through the dielectric material layer; The upper capacitor layer dielectric layer is etched from the pillar array region; Spacer material portions are formed around and inside the array of the covered tubular bottom electrode portions, wherein discrete top surface segments of the upper etch-stop dielectric layer are exposed at the gaps in the array of the covered tubular bottom electrode portions. A via is formed in the upper etch-stop dielectric layer in the pillar array region; Selectively remove the intermediate capacitor layer dielectric layer from the pillar array region to the upper etch stop dielectric layer; and A node dielectric layer and a top electrode layer are deposited above the array of the upper etch stop dielectric layer and the capped tubular bottom electrode portion.

10. A semiconductor device structure, comprising: A dielectric material layer is overlaid on a substrate, wherein the dielectric material comprises, from bottom to top, a lower capacitor-level dielectric layer, an etch-stop dielectric layer, and an upper capacitor-level dielectric layer; and A capacitor structure includes an array of columnar capacitor portions within the dielectric material layer located in a columnar array region in a plan view, and further includes a capacitor top portion adjacent to and covering the top of the array of each of the columnar capacitor portions within the dielectric material layer. The etch-stop dielectric layer laterally surrounds the array of columnar capacitor portions and includes gap perforations located at the gaps in the array of columnar capacitor portions in a plan view.

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