A PNP type bipolar transistor and a method of manufacturing the same

Abstract

The application discloses a PNP type bipolar transistor and a manufacturing method thereof. The bipolar transistor comprises a P type substrate, an N type well region formed in the P type substrate, P type well regions located on both sides of the N type well region, a deep trench structure, a first oxide layer covering the sidewall and bottom of the deep trench structure, an emitter conductive layer filled in the deep trench structure, and a second oxide layer. The sidewall of the deep trench structure is gradually narrowed from the top to the bottom, and at least the part located in the N type well region has a sidewall inclination angle. The first oxide layer is provided with a gradient region, the thickness of the gradient region is gradually thinned from bottom to top, and the gradient region serves as a tunneling oxide layer between the emitter and the base. The emitter conductive layer is boron-containing polysilicon and serves as the emitter. The second oxide layer and the first oxide layer cooperatively form a gradient gradient type oxide layer as the tunneling oxide layer. By taking the deep trench body as the emitter and taking the gradient gradient type oxide layer as the tunneling oxide layer, the current amplification factor is improved, the device area is reduced, and the injection efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a PNP bipolar transistor and its manufacturing method. Background Technology

[0002] BJTs (Bipolar Junction Transistors) are fundamental active devices widely used in integrated circuits. In the BCD (Bipolar-CMOS-DMOS, a bipolar-complementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor integrated circuit platform), PNP (Positive-Negative-Positive, referring to a transistor structure composed of P-type-N-type semiconductors) BJTs are often used in key modules of power integrated circuits such as high-voltage side drive, current sensing, and bandgap reference.

[0003] In existing technologies, PNP-type BJTs typically employ a planar structure. The PN junction between the emitter and base is defined by photolithography through lateral layout, forming the emitter area within an N-type well region. Electrical isolation between the emitter, base, and collector is achieved through STI (Shallow Trench Isolation). During device operation, holes are injected into the N-type well region through the emitter. Due to the shortest path effect, current concentration is prone to occur at the emitter edge.

[0004] However, the existing planar PNP BJT structure described above has the following shortcomings:

[0005] (i) Area efficiency is limited. To ensure the current amplification factor Beta (β, current amplification factor), the emitter area between the emitter and the base needs to be large, resulting in a large area occupied by the lateral layout of the device, which is not conducive to improving the chip integration density.

[0006] (ii) Current concentration effect exists. The current in the traditional planar PNP structure is two-dimensional diffusion, which has a corner concentration effect. Under high current, the Beta is prone to degradation.

[0007] (iii) Limited injection efficiency. The emitter and base are directly connected through a PN junction (the interface / junction region between a P-type semiconductor and an N-type semiconductor). Some electrons will attempt to be injected from the base region into the emitter, which limits the injection efficiency.

[0008] Furthermore, DTI (Deep Trench Isolation) technology has been widely used in semiconductor manufacturing for electrical isolation between devices. DTI typically includes a deep trench, an oxide liner on the inner sidewalls of the trench, and a conductive material (such as polysilicon) filling the trench. Some literature reports using trench structures to form diffusion layers for emitters or collectors; however, these emitter junctions are still based on direct PN junction contact, without addressing the tunneling injection mechanism through an ultrathin oxide layer, and do not solve problems such as limited injection efficiency and current pooling effects. Summary of the Invention

[0009] This invention aims to solve at least one of the technical problems existing in the prior art. To this end, this invention proposes a PNP bipolar transistor that can solve the technical problems of limited area efficiency, current pooling effect, and low injection efficiency in existing PNP bipolar transistors.

[0010] This invention also proposes a method for manufacturing a PNP bipolar transistor.

[0011] A PNP bipolar transistor according to a first aspect of the present invention includes a P-type substrate; an N-type well region formed in the P-type substrate and P-type well regions located on both sides of the N-type well region; a deep trench structure having sidewalls that gradually narrow from top to bottom in a tapered shape, and having a sidewall inclination angle at least in the portion located in the N-type well region; a first oxide layer covering the sidewalls and bottom of the deep trench structure, the first oxide layer having a gradient region having a thickness that gradually decreases from bottom to top; an emitter conductive layer filling the interior of the deep trench structure and serving as the emitter of the PNP bipolar junction transistor, the gradient region serving as a tunneling oxide layer between the emitter and the base region; and a second oxide layer, a portion of which is located between the first oxide layer and the P-type substrate, and a portion of which is located between the first oxide layer and the N-type well region, the second oxide layer also covering the outer surface of the deep trench structure in the N-type well region that is not covered by the first oxide layer.

[0012] The following benefits are provided: A PNP bipolar transistor has the following core structure: a P-type substrate, in which an N-type well region and P-type well regions located on both sides of the N-type well region are formed; a deep trench structure, the sidewalls of which are tapered from top to bottom, and at least the portion located in the N-type well region has a sidewall inclination angle; a first oxide layer, covering the sidewalls and bottom of the deep trench structure, having a gradient region whose thickness gradually decreases from bottom to top; an emitter conductive layer, filling the interior of the deep trench structure, serving as the emitter of the PNP bipolar junction transistor, the gradient region serving as a tunneling oxide layer between the emitter and the base region; a portion of a second oxide layer located between the first oxide layer and the P-type substrate, a portion of the second oxide layer located between the first oxide layer and the N-type well region, and the second oxide layer also covering the outer surface of the deep trench structure in the N-type well region that is not covered by the first oxide layer. By using the tapered sidewalls of the deep trench structure as the emitter junction contact surface, the effective area of ​​the emitter junction is significantly increased within a limited lateral area. Combined with the high doping concentration of boron-containing polycrystalline silicon, the current amplification factor is significantly improved, while the lateral occupied area is greatly reduced, which is beneficial to improving chip integration. The gradient region forms an ultrathin tunneling oxide layer between the emitter and the base region. Utilizing the quantum tunneling effect, holes are efficiently injected into the base region while effectively blocking electron reverse injection, overcoming the low injection efficiency problem caused by the direct connection of traditional PN junctions. In addition, the gradual thickness of the gradient region ensures a smooth transition of the electric field distribution and suppresses peak electric fields. Combined with the tapered sidewalls, the current is evenly distributed radially, reducing the edge-gathering effect, thereby comprehensively improving the device's amplification performance, reliability, and high-current operating stability.

[0013] According to some embodiments of the present invention, the deep trench structure is divided into a first part and a second part in the vertical direction. The first part is a vertical trench, and the second part is above the first part. The second part is a funnel-shaped trench that is wider at the top and narrower at the bottom. The second part is located in the N-type well region. The first part passes through the N-type well region and extends into the P-type substrate. The portion of the first oxide layer corresponding to the second part is the gradient region.

[0014] According to some embodiments of the present invention, the device further includes an N+ contact region formed within the N-type well region, the N+ contact region serving as a base contact region; it also includes a P+ contact region formed on the surface of the P-type substrate, the P+ contact region serving as a collector contact region; the emitter is electrically connected to a high potential, the base contact region is electrically connected to a medium potential, and the collector contact region is electrically connected to a low potential.

[0015] According to some embodiments of the present invention, the thickness of the first oxide layer is 29nm-31nm, the thickness of the second oxide layer is 1.5nm to 2.5nm, and the total thickness of the second oxide layer and the first oxide layer at the height region corresponding to the gradient region gradually decreases from bottom to top.

[0016] According to some embodiments of the present invention, the width of the first portion is 1.34 micrometers to 1.66 micrometers, the height of the second portion in the N-type well region is 0.6 micrometers to 1 micrometer, and the angle between the sidewall of the second portion and the horizontal plane is 72 degrees to 83 degrees.

[0017] A PNP bipolar transistor fabrication process according to a second aspect of the present invention includes the following steps:

[0018] Step S1: Provide a P-type substrate, and form an N-type well region in the P-type substrate and form P-type well regions on both sides of the N-type well region, and deposit a silicon nitride layer and then a silicon oxide layer on the wafer surface.

[0019] Step S2: Define the location of the deep trench and etch to form the deep trench;

[0020] Step S3: Form a first oxide layer on the outside of the deep trench;

[0021] Step S4: Etch the upper part of the deep trench and the first oxide layer to form a deep trench structure and a gradient region. Control the etching depth by etching time so that the etching stops in the N-type well region.

[0022] Step S5: A second oxide layer is formed between the first oxide layer and the P-type substrate, between the first oxide layer and the N-type well region, and on the outer wall surface of the deep trench structure in the N-type well region that is not covered by the first oxide layer;

[0023] Step S6: Deposit boron-containing polycrystalline silicon within the deep trench structure;

[0024] Step S7: Remove excess material from the surface of the semiconductor substrate to form the emitter contact region, base contact region, and collector contact region.

[0025] According to some embodiments of the present invention, in step S6, the doping concentration of the boron-containing polycrystalline silicon is 1×10^19 atoms / cm³.

[0026] According to some embodiments of the present invention, in step S7, chemical mechanical polishing is used to remove excess polysilicon, oxide layer and silicon nitride outside the deep trench.

[0027] According to some embodiments of the present invention, in step S3, the first oxide layer is grown using a furnace tube process.

[0028] According to some embodiments of the present invention, in step S5, the second oxide layer is grown using a furnace tube process.

[0029] It has at least the following beneficial effects: This PNP bipolar transistor fabrication process has all the beneficial effects of the aforementioned PNP bipolar transistor, which will not be repeated here.

[0030] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0031] The present invention will be further described below with reference to the accompanying drawings and embodiments, wherein:

[0032] Figure 1 This is a schematic diagram of the structure after step S1 is completed in an embodiment of the present invention;

[0033] Figure 2 This is a schematic diagram of the structure after step S2 is completed in an embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of the structure after step S3 is completed in an embodiment of the present invention;

[0035] Figure 4 This is a schematic diagram of the structure after step S4 is completed in an embodiment of the present invention;

[0036] Figure 5 This is a schematic diagram of the structure after step S5 is completed in an embodiment of the present invention;

[0037] Figure 6 This is a schematic diagram of the structure after step S6 is completed in an embodiment of the present invention;

[0038] Figure 7 This is a schematic diagram of the structure after step S7 is completed in an embodiment of the present invention.

[0039] Icon labels:

[0040] P-type substrate 10, P+ contact region 11, silicon nitride layer 12, silicon oxide layer 13, N-type well region 20, N+ contact region 21, P-type well region 30, deep trench structure 40, first part 41, second part 42, first oxide layer 50, gradient region 51, emitter conductive layer 60, and second oxide layer 70. Detailed Implementation

[0041] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0042] In the description of this invention, the use of "first" and "second" is for the purpose of distinguishing technical features only, and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or the order of the technical features indicated.

[0043] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0044] Reference Figure 7 This invention discloses a PNP bipolar transistor comprising a P-type substrate 10, an N-type well region 20 formed within the P-type substrate 10, and P-type well regions 30 located on both sides of the N-type well region 20; a deep trench structure 40, the sidewalls of which are tapered and gradually narrow from top to bottom, and at least the portion within the N-type well region 20 has a sidewall inclination angle; a first oxide layer 50 covering the sidewalls and bottom of the deep trench structure 40, the first oxide layer 50 having a gradient region 51, the thickness of the gradient region 51 gradually increasing from bottom to top. The layer gradually thins; the emitter conductive layer 60 fills the interior of the deep trench structure 40 and serves as the emitter of the PNP bipolar junction transistor; the gradient region 51 serves as a tunneling oxide layer between the emitter and the base region; a portion of the second oxide layer 70 is located between the first oxide layer 50 and the P-type substrate 10, and a portion of the second oxide layer 70 is located between the first oxide layer 50 and the N-type well region 20; the second oxide layer 70 also covers the outer wall surface of the deep trench structure 40 in the N-type well region 20 that is not covered by the first oxide layer 50.

[0045] The device structure is constructed based on a P-type substrate 10. Within the P-type substrate 10, an N-type well region 20 and a P-type well region 30 are formed through an ion implantation process, with the P-type well region 30 located on both sides of the N-type well region 20. The N-type well region 20 serves as the base region of the PNP-type BJT, and the P-type well region 30 is used for subsequent formation of the collector contact.

[0046] A deep trench structure 40 is formed within the N-type trap region 20. The sidewalls of the deep trench structure 40 are not vertical, but tapered from top to bottom. At least the portion of the sidewall located within the N-type trap region 20 has a sidewall inclination angle, meaning that this portion of the sidewall forms an angle with the horizontal plane (or with the vertical direction), rather than being perpendicular.

[0047] The first oxide layer 50 covers the entire inner surface of the deep trench structure 40, including the sidewalls and the bottom. The first oxide layer 50 is provided with a gradient region 51, which is characterized in that its thickness gradually decreases from bottom to top, that is, the oxide layer near the bottom of the deep trench structure 40 is thicker and the oxide layer near the top is thinner.

[0048] The emitter conductive layer 60 fills the interior of the deep trench structure 40. In some embodiments of the present invention, the emitter conductive layer 60 is made of boron (B)-containing polycrystalline silicon, i.e., P-type heavily doped polycrystalline silicon, which serves as the emitter of the PNP bipolar junction transistor. Notably, the gradient region 51 acts as a tunneling oxide layer between the emitter and the base region (i.e., the N-type well region 20), through which charge carriers undergo quantum tunneling injection.

[0049] The second oxide layer 70 works in conjunction with the first oxide layer 50 to make the total thickness of the oxide layer on the sidewall of the deep trench structure 40 gradually transition from about 30 nm to about 2 nm from bottom to top.

[0050] By designing the sidewalls of the deep trench structure 40 as tapered, the emitter junction is transformed from a traditional planar contact to a three-dimensional sidewall contact, significantly increasing the effective area of ​​the emitter junction and providing a structural basis for improving the current amplification factor β (Beta). Simultaneously, the gradient region 51, acting as a tunneling oxide layer, allows carriers to be injected via a tunneling mechanism, rather than relying on direct injection through a traditional PN junction (the junction between a P-type and N-type semiconductor), effectively suppressing the reverse injection of electrons from the base region to the emitter and improving injection efficiency. The tapered sidewall structure ensures a uniform current distribution radially, reducing the current pooling effect.

[0051] Under normal operating bias conditions (emitter E connected to high potential, base B connected to medium potential, collector C connected to low potential), the energy bands on both sides of the ultrathin tunneling oxide layer (second oxide layer 70) with a thickness of about 2nm between the emitter (high concentration B-doped polycrystalline silicon, i.e., emitter conductive layer 60) and the base region (N-type well region 20) of the PNP type BJT of the present invention exhibit significant asymmetric bending.

[0052] Specifically, for holes on the emitter side, the high potential significantly raises the valence band top relative to the base region, transforming the originally rectangular valence band barrier into a triangular barrier with a drastically reduced effective thickness. Although the effective mass of a hole is greater than that of an electron, the quantum tunneling probability is exponentially negatively correlated with the barrier thickness. The sharp reduction in the effective barrier thickness causes the hole tunneling probability to increase exponentially, enabling a large number of holes to efficiently tunnel through the 2nm oxide layer into the base region, forming the emitter current.

[0053] Meanwhile, for electrons attempting to be injected back into the emitter from the base region (N-type well region 20), under this bias condition, the conduction band barrier is not effectively compressed by the electric field and its shape remains essentially a wide rectangle, with the effective tunneling thickness approaching the complete physical thickness of the oxide layer. Furthermore, the conduction band barrier height faced by the electron is significantly greater than the valence band barrier height faced by the hole. Therefore, the probability of electrons tunneling back is exponentially suppressed to an extremely low level, making it almost impossible for them to be injected from the base region into the emitter.

[0054] Based on the above mechanism, this invention achieves selective tunneling of charge carriers through an ultrathin oxide layer—that is, it allows only holes to be efficiently injected into the base region from the emitter, while effectively blocking electrons from being injected back into the emitter from the base region. This mechanism fundamentally overcomes the problem of electron reverse injection caused by the direct connection of the PN junction in traditional PNP BJTs, significantly improving the injection efficiency of the emitter junction, while avoiding Beta degradation caused by excessively high carrier concentration, providing a physical guarantee for the stable operation of the device under high current.

[0055] The working mechanism of the aforementioned 2nm tunneling oxide layer is the same as the carrier tunneling injection mechanism through the ultrathin oxide layer in one-time programmable (OTP) and multiple-time programmable (MTP) memories. It has been widely verified in semiconductor memory devices and has sufficient physical reliability.

[0056] Reference Figure 7 The deep trench structure 40 is divided into a first part 41 and a second part 42 along the vertical direction. The first part 41 is a vertical trench, and the second part 42 is above the first part 41. The second part 42 is a funnel-shaped trench that is wider at the top and narrower at the bottom. The second part 42 is located in the N-type well region 20. The first part 41 passes through the N-type well region 20 and extends into the P-type substrate 10. The portion of the first oxide layer 50 corresponding to the second part 42 is the gradient region 51.

[0057] The deep trench structure 40 is vertically divided into two parts: a first part 41 and a second part 42, with the second part 42 located above the first part 41. The first part 41 is a vertical trench, meaning its sidewalls are substantially perpendicular to the substrate surface, with a sidewall inclination angle close to 0 degrees (relative to the vertical direction). The first part 41 extends downward from the bottom of the N-type well region 20, passes through the N-type well region 20, and enters the P-type substrate 10. The second part 42 is located above the first part 41 and is entirely within the N-type well region 20. The second part 42 is a funnel-shaped trench (i.e., a frustum-shaped trench) that is wider at the top than at the bottom, with its sidewalls having an inclination angle relative to the vertical direction. Based on the above structure, the portion of the first oxide layer 50 corresponding to the second part 42 is designated as a gradient region 51. That is, the gradient region 51 is located on the upper sidewall of the deep trench structure 40, and this region is precisely where the oxide layer thickness gradually decreases from bottom to top.

[0058] The funnel-shaped (frustum-shaped) structure of the second part 42 further increases the emitter sidewall area, while the current is evenly distributed radially, further weakening the current pooling effect. The vertical trench of the first part 41 passes through the N-type well region 20 into the P-type substrate 10, providing a structural basis for subsequent grounding connections. Confining the gradient region 51 to the position corresponding to the second part 42 ensures that the tunneling oxide layer is located on the critical carrier transport path between the emitter and the base region (N-type well region 20).

[0059] Reference Figure 7 It also includes an N+ contact region 21 formed in the N-type well region 20, which serves as the base contact region; it also includes a P+ contact region 11 formed on the surface of the P-type substrate 10, which serves as the collector contact region; the emitter is electrically connected to a high potential, the base contact region is electrically connected to a medium potential, and the collector contact region is electrically connected to a low potential.

[0060] Within the N-type well region 20, an N+ contact region 21 is formed through high-concentration N-type ion implantation. This N+ contact region 21 serves as the base contact region, used to achieve electrical connection between the base (i.e., the N-type well region 20) and external circuitry. On the surface of the P-type substrate 10, a P+ contact region 11 is formed through high-concentration P-type ion implantation. This P+ contact region 11 serves as the collector contact region, used to achieve electrical connection between the collector (i.e., the P-type substrate 10 and the P-type well region 30) and external circuitry. In this embodiment, the contact regions form ohmic contacts through subsequently fabricated contact holes (CTs). Under normal operating conditions, the emitter (i.e., the emitter conductive layer 60) is connected to a high potential, the base contact region (i.e., the N+ contact region 21) is connected to a medium potential, and the collector contact region (i.e., the P+ contact region 11) is connected to a low potential. Under this bias condition, the emitter junction is forward biased, the collector junction is reverse biased, and the PNP type BJT is in amplification mode.

[0061] The N+ contact region 21 serves as the base contact region, and the P+ contact region 11 serves as the collector contact region. Together with the emitter conductive layer 60 within the deep trench structure 40, they form a complete three-terminal electrode structure for the PNP-type BJT. Under the aforementioned bias conditions, the potential difference between the emitter and base regions allows holes to efficiently tunnel through the gradient region 51 into the base region, thereby enabling device amplification.

[0062] It is worth noting that, in the embodiments of the present invention, the thickness of the first oxide layer 50 is 29nm-31nm, the thickness of the second oxide layer 70 is 1.5nm to 2.5nm, and the total thickness of the second oxide layer 70 and the first oxide layer 50 at the height region corresponding to the gradient region 51 gradually decreases from bottom to top.

[0063] The thickness of the first oxide layer 50 is 29 nm to 31 nm. Preferably, the thickness of the first oxide layer 50 is 30 nm. This first oxide layer 50 is formed by a furnace tube process (thermal oxidation) and covers the entire inner wall of the deep trench structure 40. The thickness of the second oxide layer 70 is 1.5 nm to 2.5 nm. Preferably, the thickness of the second oxide layer 70 is 2 nm. This second oxide layer 70 is also formed by a furnace tube process and covers the surface of the first oxide layer 50 and the exposed portion at the top of the deep trench structure 40.

[0064] The total thickness of the first oxide layer 50 and the second oxide layer 70 (i.e., the thickness after their superposition) gradually decreases from bottom to top. Specifically, in the bottom region of the deep trench structure 40, only the first oxide layer 50 exists (with a thickness of approximately 30 nm), and the second oxide layer 70 covers it, with a total thickness of approximately 32 nm. In the upper region of the deep trench structure 40 (gradient region 51), the thickness of the first oxide layer 50 gradually decreases from approximately 30 nm at the bottom to nearly 0 nm at the top, while the second oxide layer 70 (approximately 2 nm) covers the surface of the first oxide layer 50 or is grown directly on the silicon surface, so that the total thickness gradually transitions from approximately 30 nm at the bottom to approximately 2 nm at the top.

[0065] By specifying the thicknesses of the first oxide layer 50 and the second oxide layer 70, a gradient structure was achieved, transitioning from a thick oxide layer at the bottom (approximately 30 nm) to an ultrathin oxide layer at the top (approximately 2 nm). The thick oxide layer at the bottom provides sufficient insulation strength to prevent high-voltage breakdown; the ultrathin oxide layer at the top allows holes to be efficiently injected into the base region via quantum tunneling; and the continuous gradient transition region in the middle smooths the electric field distribution, suppresses the generation of spike electric fields, and improves the reliability of the device.

[0066] It is worth noting that, in the embodiments of the present invention, the width of the first part 41 is 1.34 micrometers to 1.66 micrometers, the height of the second part 42 in the N-type well region 20 is 0.6 micrometers to 1 micrometer, and the angle between the sidewall of the second part 42 and the horizontal plane is 72 degrees to 83 degrees.

[0067] The first part 41 is a vertical groove with a width of 1.34 micrometers to 1.66 micrometers. Preferably, the width of the first part 41 is 1.5 micrometers. Since the first part 41 is a vertical groove, its top width is substantially the same as its bottom width, so this width value is the typical width of the first part 41.

[0068] The second part 42, located within the N-type well region 20, has a height of 0.6 micrometers to 1 micrometer. Preferably, this height is 0.8 micrometers. This height determines the longitudinal extension range of the emitter junction and directly affects the size of the emitter junction sidewall area.

[0069] The angle between the sidewall of the second part 42 and the horizontal plane is 72 to 83 degrees. Preferably, the angle is 77 degrees. This angle determines the taper of the upper part of the deep trench structure 40. The smaller the angle, the larger the sidewall area, but too small an angle may lead to difficulties in process implementation.

[0070] The width of the first part 41 is preferably 1.5μm±0.16μm, the height of the second part 42 in the N-type well region 20 is preferably 0.8μm±0.2μm, and the angle between the sidewall of the second part 42 and the horizontal plane is preferably 77°±5°.

[0071] Reference Figures 1 to 7 A method for manufacturing a PNP bipolar transistor includes the following steps:

[0072] Step S1: Provide a P-type substrate 10, and form an N-type well region 20 in the P-type substrate 10 and form a P-type well region 30 on both sides of the N-type well region 20. Deposit a silicon nitride layer 12 on the wafer surface and then deposit a silicon oxide layer 13.

[0073] Step S2: Define the location of the deep trench and etch to form the deep trench;

[0074] Step S3: Form a first oxide layer 50 on the outside of the deep trench;

[0075] Step S4: Etch the upper part of the deep trench and the first oxide layer 50 to form the deep trench structure 40 and the gradient region 51. Control the etching depth by etching time so that the etching stops in the N-type well region 20.

[0076] Step S5: A second oxide layer 70 is formed between the first oxide layer 50 and the P-type substrate 10, between the first oxide layer 50 and the N-type well region 20, and on the outer wall surface of the deep trench structure 40 in the N-type well region 20 that is not covered by the first oxide layer 50.

[0077] Step S6: Deposit boron-containing polycrystalline silicon within the deep trench structure 40;

[0078] Step S7: Remove excess material from the surface of the semiconductor substrate to form the emitter contact region, base contact region, and collector contact region.

[0079] It is understood that in some embodiments of the present invention, step S1 involves providing a P-type substrate 10. An N-type well region 20 is formed within the P-type substrate 10 using an ion implantation process, and P-type well regions 30 are formed on both sides of the N-type well region 20. Subsequently, a silicon nitride layer 12 is deposited on the wafer surface as a stop layer for subsequent CMP (Chemical Mechanical Polishing), and a silicon oxide layer 13 is deposited as a hard mask layer for etching deep trenches.

[0080] Step S2: Define the formation location of the deep trench using photolithography, and then use anisotropic dry etching (such as reactive ion etching (RIE)) to etch and form the deep trench within the N-type well region 20. The sidewalls of the deep trench are tapered, and their tilt angle is preferably between 72 and 83 degrees.

[0081] Step S3: Using a furnace tube process, a first oxide layer 50 is formed on the inner wall (i.e., sidewall and bottom) of the deep trench through thermal oxidation. The thickness of the first oxide layer 50 is preferably 29 nm to 31 nm.

[0082] Step S4: Anisotropic dry etching is used to etch the upper part of the deep trench and the first oxide layer 50 covering it. Because anisotropic etching is directional, it primarily bombards the sidewalls of the upper part of the deep trench, thus selectively removing the first oxide layer 50 from the upper sidewalls while essentially preserving the first oxide layer 50 from the bottom and lower sidewalls. The etching depth is precisely controlled by the etching time, stopping the etching within the N-type well region 20. After this step, the first oxide layer 50 forms a gradient region 51 in the upper part of the deep trench, with its thickness gradually decreasing from bottom to top.

[0083] Step S5: Using the furnace tube process again, a second oxide layer 70 is formed by thermal oxidation between the first oxide layer 50 and the P-type substrate 10, between the first oxide layer 50 and the N-type well region 20, and on the outer surface of the deep trench structure 40 in the N-type well region 20 that is not covered by the first oxide layer 50. The thickness of the second oxide layer 70 is preferably 1.5 nm to 2.5 nm. Since the first oxide layer 50 on the upper sidewall of the deep trench has been partially or completely removed, the second oxide layer 70 is grown directly on the silicon surface, forming an ultrathin oxide layer; while the first oxide layer 50 on the lower sidewall of the deep trench is still retained, and the second oxide layer 70 covers the first oxide layer 50, so that the total oxide layer thickness gradually transitions from about 30 nm at the bottom to about 2 nm at the top.

[0084] Step S6: Deposit boron-containing polycrystalline silicon within the deep trench structure 40, filling the entire internal space of the deep trench structure 40. The doping concentration of the boron-containing polycrystalline silicon is preferably 1 × 10^19 atoms / cm³.

[0085] Step S7: CMP is used to remove excess material from the wafer surface, excluding the interior of the deep trench structure 40, including excess polysilicon, silicon oxide, and silicon nitride, to achieve wafer surface planarization. Subsequently, emitter contact regions, base contact regions, and collector contact regions are formed at the corresponding locations through photolithography and ion implantation processes, and contact holes (CTs) are fabricated to form ohmic contacts.

[0086] Furthermore, in some embodiments of the present invention, in step S6, the doping concentration of the boron-containing polycrystalline silicon is 1×10^19 atoms / cm³.

[0087] It is worth noting that the high concentration of boron doping results in an extremely high hole concentration on the emitter side, which is beneficial for generating a large number of holes for tunneling injection under forward bias conditions, thereby improving the current amplification factor β (Beta) of the device.

[0088] Furthermore, in some embodiments of the present invention, in step S7, CMP (Chemical Mechanical Polishing) is used to remove excess polysilicon, oxide layer, and silicon nitride outside the deep trench, achieving surface planarization. CMP technology is used to remove the aforementioned excess materials. CMP is a surface planarization technique combining chemical etching and mechanical polishing, capable of achieving global planarization and removing excess polysilicon, silicon oxide layer 13, and silicon nitride layer 12 outside the deep trench structure 40. Since silicon nitride layer 12 serves as a stop layer for CMP, the polishing rate significantly decreases when CMP reaches the surface of silicon nitride layer 12, effectively protecting the wafer surface from over-polishing and ensuring precise control of planarization.

[0089] Furthermore, in some embodiments of the present invention, in step S3, the first oxide layer 50 is grown using a furnace tube process.

[0090] By employing a furnace tube thermal oxidation process to form the first oxide layer 50, the uniform thickness of the oxide layer in all areas of the sidewalls and bottom of the deep trench structure 40 is ensured. The furnace tube process exhibits good process maturity and batch consistency, is compatible with the standard BCD process platform, and facilitates large-scale production.

[0091] Furthermore, in some embodiments of the present invention, in step S5, a furnace tube process is used to grow the second oxide layer 70.

[0092] By employing a furnace tube thermal oxidation process to form the second oxide layer 70, it is possible to re-grow an oxide layer on the surface of the etched deep trench sidewall. The second thermal oxidation, combined with the first thermal oxidation and intermediate selective etching steps, achieves a continuous gradient structure from ultrathin to thick oxide layers. This structure is the core technological guarantee for achieving tunneling injection and smooth electric field distribution in this invention. The furnace tube process is mature and controllable, enabling precise control of the thickness of the second oxide layer 70 down to the nanometer scale.

[0093] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] Of course, the present invention is not limited to the above-described embodiments. Those skilled in the art can make equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A PNP bipolar transistor, characterized in that, include: P-type substrate (10); An N-type well region (20) formed in the P-type substrate (10) and P-type well regions (30) located on both sides of the N-type well region (20); The deep trench structure (40) has a tapered sidewall that gradually narrows from top to bottom, and at least the portion located within the N-type trap region (20) has a sidewall inclination angle. A first oxide layer (50) covers the sidewalls and bottom of the deep trench structure (40), and the first oxide layer (50) is provided with a gradient region (51), the thickness of which gradually decreases from bottom to top; The emitter conductive layer (60) is filled inside the deep trench structure (40) and serves as the emitter of the PNP bipolar junction transistor. The gradient region (51) serves as the tunneling oxide layer between the emitter and the base region. The second oxide layer (70) is partially located between the first oxide layer (50) and the P-type substrate (10), and partially located between the first oxide layer (50) and the N-type well region (20). The second oxide layer (70) also covers the outer wall surface of the deep trench structure (40) in the N-type well region (20) that is not covered by the first oxide layer (50).

2. A PNP bipolar transistor according to claim 1, characterized in that, The deep trench structure (40) is divided into a first part (41) and a second part (42) in the vertical direction. The first part (41) is a vertical trench, and the second part (42) is above the first part (41). The second part (42) is a funnel-shaped trench that is wider at the top and narrower at the bottom. The second part (42) is located in the N-type well region (20). The first part (41) passes through the N-type well region (20) and extends into the P-type substrate (10). The portion of the first oxide layer (50) corresponding to the second part (42) is the gradient region (51).

3. A PNP bipolar transistor according to claim 1, characterized in that, It also includes an N+ contact region (21) formed within the N-type well region (20), the N+ contact region (21) serving as a base contact region; It also includes a P+ contact region (11) formed on the surface of the P-type substrate (10), the P+ contact region (11) serving as a collector contact region; The emitter is electrically connected to a high potential, the base contact area is electrically connected to a medium potential, and the collector contact area is electrically connected to a low potential.

4. A PNP bipolar transistor according to claim 1, characterized in that, The thickness of the first oxide layer (50) is 29nm-31nm, the thickness of the second oxide layer (70) is 1.5nm to 2.5nm, and the total thickness of the second oxide layer (70) and the first oxide layer (50) at the height region corresponding to the gradient region (51) gradually decreases from bottom to top.

5. A PNP bipolar transistor according to claim 2, characterized in that, The width of the first part (41) is 1.34 micrometers to 1.66 micrometers, the height of the second part (42) in the N-type well region (20) is 0.6 micrometers to 1 micrometer, and the angle between the sidewall of the second part (42) and the horizontal plane is 72 degrees to 83 degrees.

6. A method for manufacturing a PNP bipolar transistor as described in any one of claims 1 to 5, characterized in that, Includes the following steps: Step S1: Provide a P-type substrate (10), and form an N-type well region (20) in the P-type substrate (10) and form a P-type well region (30) on both sides of the N-type well region (20), and deposit a silicon nitride layer (12) on the wafer surface, and then deposit a silicon oxide layer (13). Step S2: Define the location of the deep trench and etch it to form the deep trench; Step S3: Form a first oxide layer (50) on the outside of the deep trench; Step S4: Etch the upper part of the deep trench and the first oxide layer (50) to form a deep trench structure (40) and a gradient region (51). Control the etching depth by etching time so that the etching stops in the N-type well region (20). Step S5: A second oxide layer (70) is formed between the first oxide layer (50) and the P-type substrate (10), between the first oxide layer (50) and the N-type well region (20), and on the outer wall surface of the deep trench structure (40) in the N-type well region (20) that is not covered by the first oxide layer (50). Step S6: Deposit boron-containing polycrystalline silicon within the deep trench structure (40); Step S7: Remove excess material from the surface of the semiconductor substrate to form the emitter contact region, base contact region, and collector contact region.

7. The method for manufacturing a PNP bipolar transistor according to claim 6, characterized in that, In step S6, the doping concentration of the boron-containing polycrystalline silicon is 1×10^19 atoms / cm³.

8. A method for manufacturing a PNP bipolar transistor according to claim 6, characterized in that, In step S7, chemical mechanical polishing is used to remove excess polysilicon, oxide layer and silicon nitride outside the deep trench.

9. A method for manufacturing a PNP bipolar transistor according to claim 6, characterized in that, In step S3, the first oxide layer (50) is grown using a furnace tube process.

10. A method for manufacturing a PNP bipolar transistor according to claim 6, characterized in that, In step S5, the second oxide layer (70) is grown using a furnace tube process.

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