Insulated gate bipolar transistor design and method

Abstract

The present disclosure relates to insulated gate bipolar transistor designs and methods. An insulated gate bipolar transistor includes a plurality of semiconductor layers, a plurality of mesas, a plurality of contact regions, and an electrically insulating layer. The semiconductor layers (i) include a well layer defining a semiconductor surface, and (ii) define a plurality of first type trenches and a plurality of second type trenches through the semiconductor surface and into at least the well layer. The mesas (i) separate the first type trenches and the second type trenches, and (ii) each include a sidewall facing a corresponding one of the second type trenches. The contact regions (i) are of a first doping type, and (ii) are formed in one or more of the sidewalls within each respective one of the plurality of second type trenches. The electrically insulating layer (i) is formed over the semiconductor surface, and (ii) defines a plurality of openings aligned with the contact regions.

Description

Background Technology

[0001] High-voltage insulated-gate bipolar transistors (IGBTs) are used in medium- to high-power electronic systems such as industrial drives, uninterruptible power supplies (UPS), renewable energy sources, electric vehicles, and traction motors. Advances in power density have been made by reducing on-state and switching losses, increasing current density, and lowering the maximum junction temperature. With the increasing popularity of wide-bandgap (WBG) semiconductors such as gallium nitride (GaN) and silicon carbide (SiC) in the power semiconductor market, IGBT designs are considered a potential competitor to WBG solutions.

[0002] Therefore, those skilled in the art continue to conduct research and development efforts in the field of silicon-based field-stop insulated gate bipolar transistors with narrow mesa. Summary of the Invention

[0003] This document provides an insulated gate bipolar transistor (IGBT). The IGBT includes multiple semiconductor layers, each semiconductor layer (i) including a well layer defining a semiconductor surface, and (ii) defining multiple first-type trenches and multiple second-type trenches extending through the semiconductor surface and into at least the well layer. The IGBT includes multiple mesas, each mesas (i) separating the first-type trenches and the second-type trenches, and (ii) each including a sidewall facing a corresponding second-type trench. Multiple contact regions of a first doping type are formed in one or more sidewalls within the sidewalls of each corresponding second-type trench. An electrically insulating layer (i) is formed above the semiconductor surface, and (ii) defines multiple openings aligned with the multiple contact regions.

[0004] The foregoing summary is not intended to represent every embodiment or aspect of this disclosure. Rather, it exemplifies certain novel aspects and features as set forth herein. The foregoing and other features and advantages of this disclosure will become apparent from the following detailed description of representative embodiments and models for carrying out this disclosure, taken in conjunction with the accompanying drawings and appended claims. Attached Figure Description

[0005] The accompanying drawings described herein are for illustrative purposes only, are schematic in nature, and are intended to be exemplary rather than limiting the scope of this disclosure.

[0006] Figure 1 This is a schematic cross-sectional view of an insulated gate bipolar transistor (IGBT) according to one or more exemplary embodiments.

[0007] Figure 2 This is a schematic plan view of another IGBT according to one or more exemplary embodiments.

[0008] Figure 3This is a circuit diagram of an IGBT according to one or more exemplary embodiments.

[0009] Figure 4 This is a schematic cross-sectional view of the starting semiconductor material for manufacturing an IGBT according to one or more exemplary embodiments.

[0010] Figure 5 This is a schematic cross-sectional view of a trench fabricated in an IGBT according to one or more exemplary embodiments.

[0011] Figure 6 This is a schematic cross-sectional view of the fabrication of an electrically insulating coating / layer and trench material in an IGBT according to one or more exemplary embodiments.

[0012] Figure 7 It is a schematic cross-sectional view of additional trenches formed in an IGBT according to one or more exemplary embodiments.

[0013] Figure 8 This is a schematic cross-sectional view of an interlayer dielectric cover fabricated in an IGBT according to one or more exemplary embodiments.

[0014] Figure 9 This is a schematic cross-sectional view of a contact element manufactured in an IGBT according to one or more exemplary embodiments.

[0015] Figure 10 This is a schematic cross-sectional view of fabricating an emitter conductive layer in an IGBT according to one or more exemplary embodiments.

[0016] This disclosure may be modified or embodied in alternative forms, with representative embodiments shown in the accompanying drawings and described in detail below. The inventive aspects of this disclosure are not limited to the disclosed embodiments. Rather, this disclosure is intended to cover alternatives that fall within the scope of this disclosure as defined by the appended claims. Detailed Implementation

[0017] Embodiments disclosed herein typically provide methods for designing and fabricating silicon-based field-stop (FS) insulated-gate bipolar transistors (IGBTs). These designs and / or methods reduce the distance between trenches (e.g., gate trenches and / or emitter trenches) formed into the semiconductor substrate. The reduced distance is comparable to the thickness of the inversion layer. The inversion layer can reside in a high-concentration n-type (n...) structure that also serves as a hole barrier. +In semiconductors, trenches are separated by very narrow mesa (e.g., spaced no wider than 0.5 micrometers (µm) apart). Contacts to these narrow mesa are provided across the trenches. Such mesa and contacts are achieved through dry etching with precise alignment. The resulting structure typically achieves high injection effects and high conduction modulation in the IGBT drift region. This structure also produces low forward voltage drops in IGBTs.

[0018] refer to Figure 1 This diagram illustrates a schematic cross-sectional view of an example specific embodiment of an insulated gate bipolar transistor (IGBT) 100 according to one or more exemplary embodiments. The IGBT 100 typically includes multiple semiconductor layers, including at least a first doped layer 102 (or simply "first layer"), a second doped layer 104 (or simply "second layer"), a third doped layer 106 (or simply "third layer"), and a fourth doped layer 108 (or simply "fourth layer"). Multiple conductive layers 110 and 114 are used to interconnect features of the IGBT 100.

[0019] In various embodiments, the first doped layer 102 may initially be fabricated as a lightly doped semiconductor layer or an intrinsic semiconductor layer. During subsequent fabrication steps, the first doped layer 102 may be lightly doped to p-type. - The layer may be doped into a p-layer. In some embodiments, the first doped layer 102 may form a p-well layer within the first doped layer 102.

[0020] The second doped layer 104 is lightly doped with n. - The second doped layer 104 provides a drift region for the IGBT 100. In various embodiments, the second doped layer 104 may be formed as an epitaxial layer on the third doped layer 106.

[0021] The third doped layer 106 is heavily doped with n. + The third doped layer 106 can initially be a semiconductor wafer. The wafer is typically a silicon wafer. The third doped layer 106 typically forms a buffer layer.

[0022] The fourth doped layer 108 is heavily doped p. + After the third doped layer 106 is thinned (e.g., wafer thinning), a fourth doped layer 108 is deposited or formed on the back side of the third doped layer 106. The fourth doped layer 108 can be generated by deposition or implantation. The fourth doped layer 108 realizes the collector layer of the IGBT 100.

[0023] The collector conductive layer 110 is formed to contact the fourth doped layer 108. The collector conductive layer 110 is typically a metal (e.g., aluminum, gold, or other conductive metal), a polysilicon layer, or other conductive material. The collector conductive layer 110 typically forms the collector node of the IGBT 100.

[0024] The emitter conductive layer 114 can be a metal (e.g., aluminum, gold, or other conductive metals), a polysilicon layer, or other conductive materials. The emitter conductive layer 114 forms the emitter node of the IGBT 100.

[0025] Multiple trenches 116 are formed to extend through the first doped layer 102 and into the second doped layer 104, thereby extending from the semiconductor surface 118 toward the third doped layer 106. Some of the trenches 116 form first-type trenches 120 for the gate of the IGBT 100. Other trenches 116 form second-type trenches 122 for the emitter of the IGBT 100. In various embodiments, the trenches 116 as illustrated may simply be first-type (e.g., gate) trenches 120.

[0026] Each trench 116 has an inner wall coated / layered with an electrically insulating coating / layer 124. The electrically insulating coating / layer (or insulating sidewall) 124 may be silicon dioxide (SiO2). The electrically insulating coating / layer 124 provides electrical isolation between the first type trench 120 and the second type trench 122 and the surrounding first doped layer 102 and second doped layer 104. Other electrically insulating materials may be used to meet the design criteria for specific applications.

[0027] Trench material 126 is disposed in each trench 116 and fills each trench. Trench material 126 may be an electrical conductor, a metal, a doped polycrystalline silicon material, etc.

[0028] Interlayer dielectric 128 (ILD) covers trench material 126 in each trench 120 and 122. Interlayer dielectric 128 provides electrical isolation between trench material 126 and emitter conductive layer 114. Other electrically insulating materials may be used to meet design criteria for specific applications.

[0029] Mesa 160 is formed between a combination of first-type trench 120 and second-type trench 122. In various embodiments, each mesa 160 may have a narrow width of no more than 0.5 μm. In various embodiments, the width may be approximately 0.16 μm. Because the emitter conductive layer 114 is deposited on the mesa 160 and extends over the second (e.g., emitter) type trench 122, each mesa 160 is in contact with the emitter conductive layer 114 (e.g., there is no "floating" mesa).

[0030] Well region 130 is formed in the first layer 102 within the mesas 160 between the emitter conductive layer 114 and the second layer 104. In various embodiments, well region 130 is lightly doped with p. - The layer may be doped into a p-layer.

[0031] Contact region 132 is formed in the sidewall of mesa 160 and extends into p-well 130. Contact region 132 is a heavily doped p+ region (e.g., a first doping type) to form a good direct ohmic contact between emitter conductive layer 114 and p-well 130. In various embodiments, contact region 132 is formed by ion implantation or diffusion.

[0032] Buffer 134 is formed in mesa 160 and adjacent to semiconductor surface 118. Buffer 134 is a heavily doped n-type layer that provides additional direct ohmic contact between emitter conductive layer 114 and p-well 130. + Region (e.g., second doping type). The second doping type of buffer 134 is typically the opposite of the first doping type of contact region 132, representing a charge carrier type. Buffer 134 can be referred to as the emitter of the insulated gate bipolar transistor 100 and supplies electrons to the drift region.

[0033] An optional electrical insulating layer 136 is deposited over the first layer 102. The electrical insulating layer 136 may be silicon dioxide (SiO2). Other electrical insulating materials may be used to meet the design criteria for specific applications.

[0034] An electrically insulating layer 136 is patterned to cover the semiconductor surface 118 and the interlayer dielectric 128 for protection and electrical isolation. Sidewall 162 ( Figure 9 The electrical insulating layer 136 on the surface is removed to expose the contact area 132 and the buffer zone 134 and to provide direct electrical contact between these contact areas and the emitter conductive layer 114.

[0035] Drift region 138 exists in a second doped layer 104 between the first type trench 120 and the second type trench 122. An electrically insulating coating / layer 124 adjacent to the first (e.g., gate) type trench 120 in the first doped layer 102 acts as gate oxide 140. When the gate is forward biased, an inversion layer is formed near the gate oxide 140 in the first doped layer 102. The inversion layer acts as a barrier for holes and enhances the conduction modulation of holes in drift region 138. Thus, the insulated gate bipolar transistor 100 is characterized by the absence of a hole storage region below the first doped well layer 102 in the mesa 160 (e.g., in the second doped layer 104 below the p-well 130). Holes are introduced into drift region 138 from collector conductive layer 110. During the transistor's on-state, the plasma concentration below trench 116 is typically higher for narrow mesa designs (e.g., < 0.5 μm) than for wider mesa designs (e.g., > 0.7 μm), which reduces conduction losses.

[0036] refer to Figure 2This diagram illustrates a schematic plan view of an example specific implementation of an IGBT 100a according to one or more exemplary embodiments. The IGBT 100a may be a variation of the IGBT 100. The diagram illustrates a design in which trenches alternate between first-type trenches 120 and second-type trenches 122. In other designs, the trench sequence may be first-type trench 120, second-type trench 122, second-type trench 122, first-type trench 120, second-type trench 122, etc. Other sequences and numbers of trenches can be implemented to meet the design criteria of a particular application.

[0037] The platform 160 may include a wide portion 170 and a narrow portion 172. The narrow portion 172 may be no wider than 0.5 μm. The wide portion 170 may be approximately 0.7 μm wide to 1.0 μm wide. Other dimensions of the wide portion 170 may be implemented to meet the design standards of specific applications.

[0038] An emitter conductive layer 114 is formed on each mesa 160 and extends into the second type trench 122. In various embodiments, the emitter conductive layer 114 may be doped with p-type materials. + For good contact. The width 174 of the emitter conductive layer 114 across the mesa 160 can be uniform. + Zone 176 can be limited to the width portion 170.

[0039] In various embodiments, the emitter conductive layer 114 does not overlap with the electrically insulating coating / layer 124. Therefore, n + Region 176 may exist in the wide portion 170 between the emitter conductive layer 114 and the electrically insulating coating / layer 124.

[0040] refer to Figure 3 This diagram illustrates a circuit schematic of an IGBT 100 according to one or more exemplary embodiments. A first (PNP) transistor 190 and a series resistor 192 (Ra) are formed by layers 102-108 between a collector conductive layer 110 and an emitter conductive layer 114. A second (NPN) transistor 194 and a ballast resistor 193 are formed between the base of the first transistor 190 and the emitter conductive layer 114 (the emitter node of the IGBT). The base of the second transistor 194 is connected to the collector of the first transistor 190. A third metal-oxide-semiconductor (MOS) transistor 196 is formed between the ballast resistor 193 and the base of the first transistor 190. The gate of the third transistor 196 is the gate node 115 of the IGBT 100.

[0041] refer to Figures 4 to 10A schematic cross-sectional view is shown of an example method for manufacturing an IGBT 100 according to one or more exemplary embodiments. The order of the steps is shown as a representative example. Other order of steps may be implemented to meet the standards of a particular application.

[0042] refer to Figure 4 A schematic cross-sectional view of the starting semiconductor material for manufacturing an IGBT 100 is shown according to one or more exemplary embodiments.

[0043] Doped layers 102, 104, and 106 are initially formed in a stacked / layered configuration, wherein an oxide mask layer 200 is coupled to the first doped layer 102 at the semiconductor surface 118. It should be noted that the first doped layer 102 may not be used as a p-layer. − Instead of starting with a semiconductor layer, it can be changed later during manufacturing to a lightly doped p-layer. − Or a p-doped semiconductor layer. The oxide mask layer 200 is then patterned to form vias 202 over trench 116 (see [link]). Figure 5 ).

[0044] In various embodiments, the first doped layer 102 may be formed after the trench 116 is formed in the second doped layer 104. In some embodiments, the third doped layer 106 may be formed before or after the front end.

[0045] refer to Figure 5 A schematic cross-sectional view of an IGBT 100 with grooves according to one or more exemplary embodiments is shown.

[0046] The trench 116 is formed by etching the semiconductor surface 118 and pattern into the first doped layer 102 via the oxide mask layer 200. Figure 4 Etching can be achieved through dry etching with precise alignment to produce narrow mesa surfaces.

[0047] refer to Figure 6 A schematic cross-sectional view of an IGBT 100 having an electrically insulating coating / layer and trench material according to one or more exemplary embodiments is shown.

[0048] The oxide mask layer 200 is then removed and an electrically insulating coating / layer 124 is grown. Subsequently, trench material 126 is deposited to fill trench 116.

[0049] refer to Figure 7 A schematic cross-sectional view of another trench formation according to one or more exemplary embodiments is shown.

[0050] For an implementation of an emitter trench, after excess trench material 126 has been removed, an additional trench 142 is formed to penetrate the semiconductor surface 118 into the first layer 102 and align with a second (e.g., emitter) type trench 122. The additional trench 142 may begin below the semiconductor surface 118 and extend to a trench depth 144 below the semiconductor surface 118 to expose the area where the contact region 132 will be formed. The trench depth 144 of each additional trench 142 is shallower than the well depth 150 of the second type trench 122.

[0051] In various embodiments, optional additional trenches 146 may be formed to extend through the semiconductor surface 118 into the first layer 102 and align with the first (e.g., gate) type trench 120. The additional trenches 146 may begin below the semiconductor surface 118 and extend to a further trench depth 148 below the semiconductor surface 118. The trench depth 148 of the additional trenches 146 is shallower than the well depth 150 of the first type trench 120.

[0052] A mask may be used to define additional trenches 142 and 146 aligned with the second type trench 122 and the first type trench 120. Dry etching may be used to remove some of the trench material 126 from the second type trench 122 and the first type trench 120. In some embodiments where optional additional trenches 146 are not implemented, the trench material 126 in the first type trench 120 may remain unchanged.

[0053] refer to Figure 8 A schematic cross-sectional view of an ILD cover according to one or more exemplary embodiments is shown. An interlayer dielectric 128 covers the trench material 126 in each trench 120 and 122. The interlayer dielectric 128 provides electrical isolation between the trench material 126 and the emitter conductive layer 114. Figure 10 ).

[0054] refer to Figure 9 A schematic cross-sectional view of a contact element according to one or more exemplary embodiments is shown. Figure 9 The overall example shows the p + Contact areas 132 and n +Specific implementations of buffer zone 134. In various embodiments, contact area 132 may be formed in two facing sidewalls 162 of a second (e.g., emitter) type trench 122a, as illustrated. In some embodiments, a single contact area 132 may be formed in a single sidewall 162 of a second type trench 122b. In various embodiments, buffer zone 134 may be formed in a pair of two mesa 160b surrounding the second type trench 122b. In other embodiments, a single buffer zone 134 may be formed in a single mesa in a pair of mesa 160a surrounding the second type trench 122a.

[0055] After forming the contact area 132 and buffer zone 134, an additional electrical insulating layer 136 can be used to cover and pattern the first type trench 120, the second type trench 122, and the remaining semiconductor surface 118. The electrical insulating layer 136 on the sidewall 162 is removed to provide electrical contact between the contact area 132 and buffer zone 134 and the emitter conductive layer 114. Figure 10 ).

[0056] refer to Figure 10 A schematic cross-sectional view of an emitter conductive layer according to one or more exemplary embodiments is shown.

[0057] An additional electrically insulating layer (not shown) is typically formed above the semiconductor surface 118. In some embodiments, the electrically insulating layer 136 is patterned to form an opening above the second type trench 122, thereby allowing full contact between the contact area 132 and the buffer zone 134 in the sidewall 162 of the mesa 160. Figure 9 An emitter conductive layer 114 is deposited over an electrically insulating layer 136 and extends into a second-type trench 122. In the second-type trench 122, the emitter conductive layer 114 forms an electrical connection with the contact area 132 and the buffer zone 134.

[0058] After wafer thinning of the third doped layer 106, a fourth doped layer 108 is disposed on the back side of the third doped layer 106. A collector conductive layer 110 is deposited on the back side of the fourth doped layer 108.

[0059] Those skilled in the art who have benefited from the foregoing disclosure will readily understand these and other benefits of this teaching. While several modes for carrying out many aspects of this teaching have been described in detail, those skilled in the art to which this teaching pertains will recognize various alternative aspects for practicing this teaching within the scope of the appended claims. The above description and figures are illustrative and exemplary of the entire range of alternative embodiments implied by the included content, structurally and / or functionally equivalent to the included content, or otherwise apparent based on the included content, and are not limited to those embodiments explicitly depicted and / or described. Furthermore, the concept explicitly includes combinations and sub-combinations of the described elements and features. The detailed description and figures are intended to support and describe this teaching, the scope of which is defined only by the claims.

Claims

1. An insulated-gate bipolar transistor, the insulated-gate bipolar transistor comprising: A plurality of semiconductor layers, the plurality of semiconductor layers (i) including a well layer defining a semiconductor surface, and (ii) defining a plurality of first-type trenches and a plurality of second-type trenches extending through the semiconductor surface and into at least the well layer; Multiple countertops, the multiple countertops (i) separating the multiple first type grooves and the multiple second type grooves, and (ii) each including a sidewall facing a corresponding second type groove among the multiple second type grooves; Multiple contact regions, wherein (i) are of a first doped type and (ii) are formed in one or more sidewalls of the sidewalls within each of the multiple second type trenches; and An electrically insulating layer (i) is formed above the semiconductor surface and (ii) defines a plurality of openings aligned with the plurality of contact areas.

2. The insulated gate bipolar transistor according to claim 1, further comprising: Multiple buffers of a second doping type, the multiple buffers being (i) formed in the multiple mesa and (ii) extending away from the semiconductor surface into the well layer, wherein the second doping type and the first doping type are opposite charge carrier types.

3. The insulated gate bipolar transistor according to claim 1, wherein: The plurality of semiconductor layers further define a plurality of additional trenches, which are formed to extend through the semiconductor surface into the well layer and are aligned with the plurality of second-type trenches.

4. The insulated gate bipolar transistor according to claim 3, wherein: The well layer has a well depth; The depth of each of the plurality of additional trenches is shallower than the depth of the well. and The plurality of additional grooves expose the contact areas in the plurality of countertops.

5. The insulated gate bipolar transistor according to claim 3, further comprising: A groove material disposed in the plurality of second-type grooves.

6. The insulated gate bipolar transistor according to claim 5, wherein: The electrical insulating layer covers the trench material.

7. The insulated gate bipolar transistor according to claim 5, wherein: The electrical insulating layer isolates the trench material from the plurality of semiconductor layers.

8. The insulated gate bipolar transistor according to claim 4, further comprising: An emitter conductive layer extends into and across each of the plurality of additional trenches.

9. The insulated gate bipolar transistor of claim 8, wherein the emitter conductive layer extends across each of the plurality of additional trenches.

10. The insulated gate bipolar transistor according to claim 1, wherein: The plurality of contact areas are formed in a single sidewall of each of the corresponding second type trenches.

11. The insulated gate bipolar transistor according to claim 1, wherein: The plurality of contact regions of the first doping type are formed in the two facing sidewalls of each corresponding second type trench.

12. The insulated gate bipolar transistor of claim 1, wherein the width of each of the plurality of mesa is not greater than 0.5 micrometers.

13. The insulated gate bipolar transistor of claim 1, wherein the insulated gate bipolar transistor is characterized in that there are no plurality of hole storage regions beneath the well layer in the plurality of mesa.

14. An insulated-gate bipolar transistor, the insulated-gate bipolar transistor comprising: A plurality of semiconductor layers, the plurality of semiconductor layers (i) including a well layer defining a semiconductor surface, and (ii) defining a plurality of first-type trenches and a plurality of second-type trenches extending through the semiconductor surface and into at least the well layer; A groove material, wherein the groove material is disposed in the plurality of second-type grooves; Multiple countertops, the multiple countertops (i) separating the multiple first type grooves and the multiple second type grooves, and (ii) each including a sidewall facing a corresponding second type groove among the multiple second type grooves; Multiple contact regions, wherein (i) are of a first doped type and (ii) are formed in one or more sidewalls of the sidewalls within each of the multiple second type trenches; An electrically insulating layer, (i) formed above the semiconductor surface, and (ii) defining a plurality of openings aligned with the plurality of contact areas; and An emitter conductive layer is formed above the electrical insulating layer, enters the plurality of second-type trenches, and directly contacts the plurality of contact areas through the plurality of openings.

15. The insulated-gate bipolar transistor of claim 14, further comprising: Multiple buffers of a second doping type, the multiple buffers being (i) formed in the multiple mesa and (ii) extending away from the semiconductor surface into the well layer, wherein the second doping type and the first doping type are opposite charge carrier types.

16. The insulated gate bipolar transistor according to claim 14, wherein: The plurality of semiconductor layers further define a plurality of additional trenches, which are formed to extend through the semiconductor surface into the well layer and are aligned with the plurality of second-type trenches.

17. The insulated gate bipolar transistor according to claim 14, wherein: The electrical insulating layer isolates the trench material from the plurality of semiconductor layers.

18. The insulated gate bipolar transistor of claim 14, wherein the width of each of the plurality of mesa is not greater than 0.5 micrometers.

19. The insulated gate bipolar transistor of claim 14, wherein the width of each of the plurality of mesa is approximately 0.16 micrometers.

20. A method for manufacturing an insulated-gate bipolar transistor, the method comprising: Multiple semiconductor layers are formed, the multiple semiconductor layers including a well layer defining a semiconductor surface; A plurality of first-type trenches and a plurality of second-type trenches are formed, the plurality of first-type trenches and the plurality of second-type trenches (i) extending through the semiconductor surface and into at least the well layer, and (ii) being separated by a plurality of mesa; The plurality of second-type trenches are filled using a trench material; Multiple contact regions are formed, wherein (i) the multiple contact regions are of a first doping type and (ii) are located in one or more sidewalls of a plurality of sidewalls within each of the multiple second type trenches; An electrically insulating layer is formed, the electrically insulating layer (i) being located above the semiconductor surface and (ii) defining a plurality of openings aligned with the plurality of contact areas; as well as An emitter conductive layer is formed, which is located above the electrical insulating layer, enters the plurality of second-type trenches, and directly contacts the plurality of contact areas through the plurality of openings.

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