A high-voltage planar gate RC-IGBT device with low diode forward voltage drop

Abstract

The application belongs to the technical field of power semiconductors, and particularly relates to a high-voltage planar gate RC-IGBT device with low diode forward voltage drop, which comprises a semiconductor substrate with an N-drift region, a cell region, a transition region and a termination region arranged in sequence along the lateral direction above the N-drift region, the cell region has a P body, and the termination region has a P ring on the side close to the transition region. The lateral width of the transition region is greater than the width of two cells and less than the width of three cells. An isolation belt is arranged in the transition region, the isolation belt is located between the P body on the outermost side of the cell region and the P ring, is composed of at least two P bodies arranged at intervals along the lateral direction, and is used for blocking the lateral diffusion of holes in the P body on the outermost side of the cell region to the P ring. The diode forward voltage drop VF is effectively reduced by widening the transition region and arranging the P body isolation belt.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor technology, and in particular to a high-voltage planar gate RC-IGBT device with low diode forward voltage drop. Background Technology

[0002] Insulated-gate bipolar transistors (IGBTs) typically operate in three modes: forward blocking, forward conduction, and reverse conduction. When an IGBT is in reverse conduction mode, its equivalent circuit is equivalent to two diodes connected in series back-to-back. The reverse current path is blocked, therefore an external freewheeling diode (FWD) is needed to conduct the reverse current. Reverse-conducting IGBTs (RC-IGBTs) integrate the IGBT and freewheeling diode onto the same chip, giving them high integration density and both forward and reverse conduction capabilities. This significantly reduces chip area and manufacturing costs.

[0003] Traditional high-voltage planar gate RC-IGBT devices replace the P+ portion with N+ on the collector side, with P+ and N+ alternating at the bottom of the device. The IGBT region is above P+, ​​and the FRD region is above N+. The P-body of the MOS structure serves as the anode of the FWD, and N+ serves as the cathode, forming the freewheeling diode (FWD). The outermost P-body of the unit cell region is connected to the innermost P-ring of the termination region.

[0004] To reduce the surface electric field at the terminal, a significant increase in the implantation dose of the P-ring is typically required. However, a highly doped P-ring forms a deep P-type potential well, where holes laterally diffused from the outermost P-body of the unit cell are locked inside the P-ring and cannot vertically enter the drift region to participate in conductance modulation. This weakens the conductance modulation effect in the drift region at the edge of the unit cell, leading to an increase in the diode's forward voltage drop (VF). This contradiction is particularly prominent in high-voltage planar gate RC-IGBT devices. Summary of the Invention

[0005] This invention proposes a high-voltage planar gate RC-IGBT device with low diode forward voltage drop, aiming to solve the technical problems existing in the prior art of high-voltage planar gate RC-IGBT devices, such as hole capture by highly doped P ring due to increased P ring injection dose, weakened conductance modulation in the drift region, and increased diode forward voltage drop VF.

[0006] This invention provides a high-voltage planar gate RC-IGBT device with low diode forward voltage drop, comprising a semiconductor substrate having an N-drift region, and a unit cell region, a transition region, and a termination region sequentially disposed in the transverse direction above the N-drift region. The unit cell region has a P-body, and the termination region has a P-ring on the side near the transition region. The lateral width of the transition region is greater than the width of two unit cells and less than the width of three unit cells; An isolation zone is provided in the transition region. The isolation zone is located between the outermost P body and the P ring of the protocell region. The isolation zone is composed of at least two P bodies arranged laterally at intervals. The isolation zone is used to block the lateral diffusion of cavities in the outermost P body of the protocell region to the P ring.

[0007] Furthermore, the lateral width of the transition region is 80μm to 300μm.

[0008] Furthermore, the distance between two adjacent P bodies in the isolation zone is the width of one unit cell.

[0009] Furthermore, the P ring is a highly doped P-type region, and the boron ion implantation dose of the P ring is 5 × 10⁻⁶. 14 cm -2 above.

[0010] Furthermore, an N+ collector and a P+ collector are disposed on the back side of the semiconductor substrate, wherein the N+ collector is disposed in the back side region corresponding to the unit cell region and the transition region.

[0011] Furthermore, the P+ collector is disposed in the back side region corresponding to the unit cell region and the terminal region, and the N+ collector and the P+ collector are arranged alternately in the lateral direction on the back side of the semiconductor substrate.

[0012] Furthermore, the lateral width of the N+ collector corresponding to the transition region is wider than the lateral width of the N+ collector corresponding to the unit cell region.

[0013] Furthermore, the boron ion implantation dose of the P body is 1×10⁻⁶. 13 cm -2 ~8×10 13 cm -2 .

[0014] Furthermore, the unit cell region includes multiple units cells, each unit cell further including a gate oxide layer, a gate polysilicon disposed above the gate oxide layer, and a source N+ disposed on the upper part of the P body.

[0015] Furthermore, the terminal region includes a plurality of P rings, which are arranged at lateral intervals.

[0016] The technical effects of the technical solution disclosed in this invention are: 1. By setting an isolation band composed of spaced P bodies in the transition region, the lateral diffusion path of holes in the P bodies at the edge of the unit cell region to the highly doped P ring is effectively blocked, and the holes are prevented from being trapped by the P ring potential well, thereby eliminating the adverse effect of the increase in the forward voltage drop VF of the diode caused by the high doping of the P ring.

[0017] By widening the total lateral width of the transition region to be greater than two unit cell widths but less than three unit cell widths (80μm~300μm), and in conjunction with the isolation band structure, holes in the P body at the edge of the unit cell region can be injected vertically downwards into the drift region instead of diffusing laterally to the P ring, thereby enhancing the conductivity modulation effect of the drift region and effectively reducing the forward voltage drop VF of the diode.

[0018] By widening the lateral width of the N+ collector corresponding to the transition region, the effective area of ​​the FRD is compensated, and the forward voltage drop VF of the diode is further reduced, thus achieving synergistic optimization of the device's forward conduction characteristics and reverse freewheeling characteristics. Attached Figure Description

[0019] Figure 1 This is a schematic cross-sectional view of a high-voltage planar gate RC-IGBT device with low diode forward voltage drop proposed in an embodiment of the present invention; Figure 2 This is a schematic cross-sectional view of the terminal P ring protection ring structure formed on the N-drift region according to an embodiment of the present invention; Figure 3 This is a schematic cross-sectional view of the gate oxide layer and gate polysilicon formed on the N-drift region according to an embodiment of the present invention; Figure 4 This is a cross-sectional schematic diagram of the P-body after formation according to an embodiment of the present invention, including the P-body in the unit cell region and the spaced P-body that constitutes the isolation zone in the transition region; Figure 5 This is a schematic cross-sectional view of the N+ source electrode as proposed in an embodiment of the present invention. Figure 6 This is a schematic cross-sectional view of the interlayer dielectric layer (ILD) after deposition, as proposed in an embodiment of the present invention. Figure 7 This is a schematic cross-sectional view of the ILD after etching and filling with metal to form the front emitter according to an embodiment of the present invention; Figure 8This is a schematic cross-sectional view of the wafer after flipping, back-side thinning, and forming an N+ collector according to an embodiment of the present invention. Figure 9 This is a schematic cross-sectional view of the P+ collector as proposed in an embodiment of the present invention.

[0020] Explanation of reference numerals in the attached figures: 1. N- Drift Region; 2. P Ring; 3. Gate Oxide; 4. Gate Polysilicon; 5. P Body; 6. Source N+; 7. Interlayer Dielectric Layer (ILD); 8. Emitter; 9. N+ Collector; 10. P+ Collector; 11. Collector. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] To address the technical problems mentioned in the background art regarding high-voltage planar gate RC-IGBT devices, such as hole trapping by highly doped P-rings due to increased P-ring injection dose, weakened drift region conductance modulation, and increased diode forward voltage drop (VF), this invention provides a high-voltage planar gate RC-IGBT device with low diode forward voltage drop. The device includes a semiconductor substrate having an N-drift region. The N-drift region is laterally divided into a primitive cell region, a transition region, and a termination region. The primitive cell region contains multiple primitive cells, each including a gate oxide layer, a gate polysilicon layer, a P-body, and a source N+. The boundary of the outermost gate polysilicon layer of the primitive cell region forms the boundary between the primitive cell region and the transition region.

[0023] The transition region includes a P-ring, which connects to the outermost P-body of the unit cell region. The boundary of the P-ring away from the unit cell region forms the boundary between the transition region and the terminal region. The terminal region contains multiple P-ring structures.

[0024] An isolation zone is provided in the transition region. The isolation zone is located on the side of the P body connected to the outermost P body of the protocell region, away from the protocell region. The isolation zone is composed of at least two P bodies arranged at intervals. This isolation zone is used to block the lateral diffusion of cavities in the P bodies at the edge of the protocell region to the P ring.

[0025] The total lateral width of the transition region is greater than the width of two unit cells but less than the width of three unit cells.

[0026] An N+ collector and a P+ collector are disposed on the back side of the semiconductor substrate, with the N+ collector disposed in the back side region corresponding to the unit cell region and the transition region.

[0027] The distance between two adjacent P-body in the isolation zone is the width of one unit cell. The total lateral width of the transition region is 80 μm to 300 μm.

[0028] The P-ring is a highly doped P-type region with a boron ion implantation dose of 5 × 10⁻⁶. 14 cm -2 The above. The boron ion implantation dose for the P body is 1×10⁻⁶. 13 cm -2 ~8×10 13 cm -2 .

[0029] Multiple P-ring structures in the terminal region are arranged laterally at intervals, with each P-ring being the first P-ring adjacent to the transition region in the terminal region. The N+ collector is disposed in the back-side region corresponding to the unit cell region and the transition region. The P+ collector is disposed in the back-side region corresponding to the unit cell region and the terminal region, with the N+ and P+ collectors arranged laterally alternately on the back side of the semiconductor substrate.

[0030] In this invention, the P-body constituting the isolation band not only serves as the channel region of the MOS structure in the unit cell region but also acts as an isolation layer in the transition region. This blocks the lateral diffusion of holes from the P-body at the edge of the unit cell region to the highly doped P-ring, preventing the hole trapping effect of the highly doped P-ring from increasing the voltage field (VF). Simultaneously, the widened transition region, combined with the width compensation of the N+ collector on the back side, allows holes in the P-body at the edge of the unit cell region to be injected vertically downwards into the N-drift region, recombine with electrons from the N+ collector, and form a high concentration of electron-hole pairs in the drift region, enhancing the conductivity modulation effect.

[0031] refer to Figures 1-9 As shown, the present invention provides a high-voltage planar gate RC-IGBT device with low diode forward voltage drop.

[0032] The device includes a semiconductor substrate. The semiconductor substrate has an N-drift region 1. The N-drift region 1 is a lightly doped N-type silicon region, and its doping concentration and thickness are determined according to the device's breakdown voltage level. A typical doping concentration for the N-drift region 1 is 1 × 10⁻⁶. 13 cm -3 ~1×10 14 cm -3 The thickness is typically 60μm to 520μm depending on the withstand voltage rating of 600V to 3300V.

[0033] The N-drift region 1 is divided horizontally from left to right into the primitive region, the transition region, and the terminal region.

[0034] The unit cell region contains multiple unit cells connected in parallel. Each unit cell includes a gate oxide layer 3, a gate polysilicon layer 4, a Pbody layer 5, and a source N+6. The gate oxide layer 3 is disposed on the upper surface of the N-drift region 1. The gate oxide layer 3 is made of silicon dioxide, and its thickness is typically 50 nm to 120 nm, formed by thermal oxidation growth. The gate polysilicon layer 4 is disposed on the upper surface of the gate oxide layer 3. The gate polysilicon layer 4 is doped polysilicon, and the doping concentration is typically 1 × 10⁻⁶. 20 cm -3 ~1×10 21 cm -3 The thickness is typically 500nm to 1000nm, formed by low-pressure chemical vapor deposition and patterned using photolithography and etching processes. Pbody5 is located on both sides of the upper part of the N-drift region 1, specifically on the surface layer of the N-drift region 1 below the gate oxide layer 3 and the gate polysilicon 4. Pbody5 is a P-type doped region, formed by boron ion implantation. The boron ion implantation dose of Pbody5 is 1×10⁻⁶. 13 cm -2 ~8×10 13 cm -2 The annealing temperature of P body 5 is 1100℃~1150℃, and the annealing time is 90min~150min. The typical junction depth of P body 5 is 3μm~6μm. The source N+6 is located on the upper part of each P body 5, that is, on the surface of P body 5 near the sidewall of the gate polysilicon 4. The source N+6 is an N-type heavily doped region, and its doping type is an N-type region formed by arsenic ion implantation. The arsenic ion implantation energy of the source N+6 is 90keV~150keV, and the dose is 2×10⁻⁶. 15 cm -2 ~6×10 15 cm -2 The annealing temperature for the source N+6 is 950℃, and the annealing time is 30 min. The typical junction depth of the source N+6 is 0.2 μm to 0.5 μm.

[0035] The boundary of the outermost gate polysilicon 4 in the unit cell region is the boundary between the unit cell region and the transition region. Specifically, the right boundary of the rightmost gate polysilicon 4 in the unit cell region is the dividing line between the unit cell region and the transition region.

[0036] The transition region is located between the primitive cell region and the terminal region. The terminal region has a Pring2 on the side closest to the transition region; this Pring2 is the first P-ring adjacent to the transition region in the terminal region. The transition region includes this Pring2, which is connected to the outermost P-body5 of the primitive cell. Pring2 is a P-type doped region, formed by boron ion implantation. The boron ion implantation dose of Pring2 is 1 × 10⁻⁶. 14 cm -2 ~8×10 14 cm -2 , of which 5×10 14 cm -2 The above represents high injection doses. The annealing temperature for P ring 2 is 1100℃~1150℃, and the annealing time is 200min~300min. The typical junction depth of P ring 2 is 8μm~15μm. The right boundary of P ring 2 is the boundary between the transition region and the terminal region.

[0037] An isolation band is provided in the transition region. The isolation band is located between the outermost P-body 5 and P-ring 2 of the unit cell region, specifically on the side of the P-body 5 connected to the outermost P-body 5 of the unit cell region that is furthest from the unit cell region, or on the side of the P-body 5 connected to P-ring 2 that is furthest from P-ring 2. The isolation band consists of at least two P-body 5s, which are spaced apart laterally. The spacing between two adjacent P-body 5s in the isolation band is the width of one unit cell. The width of a unit cell refers to the lateral dimension of a complete unit cell, typically ranging from 20 μm to 100 μm. The P-body 5s in the isolation band and the original P-body 5s in the transition region are structurally the same doped layer, meaning they are formed simultaneously through the same P-body photolithography and implantation process, and have the same doping concentration and junction depth.

[0038] The lateral width of the transition region is greater than the width of two unit cells but less than the width of three unit cells. Specifically, the lateral width of the transition region is 80 μm to 300 μm. The lateral width of the transition region refers to the lateral distance from the boundary of the outermost gate polysilicon 4 of the unit cell region to the right boundary of P ring 2.

[0039] The terminal region contains multiple P-ring2 structures. These P-ring2 structures are arranged laterally at intervals, with the spacing between adjacent P-rings typically ranging from 5 μm to 20 μm. The first P-ring adjacent to the transition region is the aforementioned P-ring2.

[0040] An N+ collector 9 and a P+ collector 10 are disposed on the back side of the semiconductor substrate. The N+ collector 9 is disposed in the back side region corresponding to the unit cell region and the transition region. The P+ collector 10 is disposed in the back side region corresponding to the unit cell region and the termination region. The N+ collector 9 and the P+ collector 10 are arranged alternately in the lateral direction on the back side of the semiconductor substrate. The phosphorus ion implantation energy of the N+ collector 9 is 40 keV to 80 keV, and the dose is 1 × 10⁻⁶. 14 cm -2 ~5×10 14 cm -2 The typical junction depth of N+ collector 9 is 0.5 μm to 1.5 μm. The boron ion implantation energy of P+ collector 10 is 30 keV to 60 keV, and the dose is 1 × 10⁻⁶. 13 cm -2 ~5×10 13 cm -2 The laser annealing energy is 1.8J to 2.2J. The typical junction depth of the P+ collector 10 is 0.3μm to 1.0μm.

[0041] Above the aforementioned layers, an interlayer dielectric layer 7 and an emitter 8 are also disposed. The interlayer dielectric layer 7 covers the gate polysilicon 4 and the N-drift region 1, and its material is borosilicate glass, phosphosilicate glass, or undoped silicon dioxide, with a thickness of 500 nm to 1500 nm. The emitter 8 is disposed above the interlayer dielectric layer 7, and achieves ohmic contact with the source N+6 and P body 5 through a contact hole penetrating the interlayer dielectric layer 7. The emitter 8 is made of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy, with a thickness of 4 μm to 5 μm.

[0042] In the device structure of this invention, P body 5 serves as the channel region of the MOS structure in the unit cell region, while at least two P bodies 5 arranged at intervals form an isolation band in the transition region, providing isolation. The isolation band blocks the lateral diffusion of holes in the outermost P body 5 of the unit cell region to the highly doped P ring 2, avoiding the hole trapping effect of the highly doped P ring 2 that leads to an increase in VF. Specifically, when the boron ion implantation dose of P ring 2 reaches 5 × 10⁻⁶, 14 cm -2 In the above scenario, P-ring2 forms a relatively deep P-type potential well. Without the barrier of the isolation bands, holes in the P-body5 at the edge of the unit cell region would diffuse laterally towards P-ring2 under the influence of the transverse electric field and be captured by the deep potential well of P-ring2, preventing them from entering the drift region to participate in conductivity modulation. However, in this invention, the spaced-apart isolation bands of P-body5 form a P-type doped barrier layer in the transverse direction. When holes reach the isolation band region, they are blocked by the doping barrier of P-body5 and cannot continue to diffuse laterally to P-ring2.

[0043] Simultaneously, the lateral width of the transition region is greater than the width of two unit cells but less than the width of three unit cells (i.e., 80 μm to 300 μm), providing sufficient longitudinal diffusion space for holes in the outermost P-body 5 of the unit cell region. With the widened transition region, holes in the outermost P-body 5 of the unit cell region are no longer forced to diffuse laterally, but can instead be injected vertically downwards into the N-drift region 1. These vertically injected holes recombine with electrons from the back-side N+ collector 9 in the N-drift region 1, forming high-concentration electron-hole pairs, significantly enhancing the conductivity modulation effect of the drift region, thereby reducing the forward voltage drop VF of the diode. Widening the lateral width of the back-side N+ collector 9 corresponding to the transition region ensures that there is also an N+ collector 9 below the transition region providing electron injection, further compensating for the effective area of ​​the FRD.

[0044] The following describes in detail the fabrication method of the low forward voltage drop high-voltage planar gate RC-IGBT device of the present invention.

[0045] Step S1: Perform terminal P-ring photolithography on the N-drift region 1. Specifically, firstly, photoresist is coated on the upper surface of the N-drift region 1, and then exposed and developed using a terminal P-ring mask to form the photolithographic pattern of the terminal P-ring. Then, boron ion implantation is performed at an energy of 50 keV–120 keV and a dose of 1 × 10⁻⁶. 14 cm -2 ~8×10 14 cm -2 After implantation, the photoresist is removed, and a high-temperature annealing process is performed at 1100℃~1150℃ for 200min~300min. Following these steps, a terminal P ring2 protection ring structure is formed, as shown... Figure 2 As shown, the terminal P-ring2 protection ring structure includes multiple P-type rings, with the innermost first P-ring being the aforementioned P-ring2 adjacent to the transition region. Its right boundary forms the boundary between the transition region and the terminal region. The junction depth of P-ring2 is controlled by the annealing temperature and time, with a typical junction depth of 8μm to 15μm.

[0046] Step S2: A gate oxide layer 3 is thermally grown on the N-drift region 1. Specifically, the wafer from step S1 is placed in a high-temperature oxidation furnace and thermally oxidized under an oxygen or water vapor atmosphere at a growth temperature of 900℃~1150℃ for 30min~120min, forming a silicon dioxide gate oxide layer 3 with a thickness of 50nm~120nm. Then, polysilicon is deposited on the gate oxide layer 3. Specifically, a layer of polysilicon is deposited on the upper surface of the gate oxide layer 3 using low-pressure chemical vapor deposition at a deposition temperature of 580℃~650℃, with a polysilicon thickness of 500nm~1000nm. The deposited polysilicon is doped (e.g., by phosphorus diffusion or ion implantation) to reduce its resistivity to the desired range; a typical doping concentration is 1×10⁻⁶. 20 cm -3 ~1×10 21 cm -3 Then, photolithography and etching processes are used to pattern the polysilicon layer to form the gate polysilicon 4, such as... Figure 3 As shown. The patterning of the gate polysilicon 4 determines the width and position of the unit cell region. The boundary of the outermost gate polysilicon 4 of the unit cell region is the boundary between the unit cell region and the transition region.

[0047] Step S3 involves P-body photolithography. Specifically, photoresist is coated on the upper surface of the N-drift region 1, and a P-body mask is used for exposure and development to form the P-body photolithographic pattern. The P-body photolithographic pattern covers the locations in the unit cell region where P-body 5 needs to be formed and the locations in the transition region where isolation bands need to be formed. Then, boron ion implantation is performed at an energy of 50 keV–120 keV and a dose of 1 × 10⁻⁶. 13 cm -2 ~8×10 13 cm -2 After implantation, the photoresist is removed, and high-temperature annealing is performed at 1100℃~1150℃ for 90min~150min to form P body 5. Figure 4 As shown. The junction depth of P body 5 is controlled by annealing temperature and time, with a typical junction depth of 3μm to 6μm. P body 5 serves as the channel region of the MOS structure in the unit cell region, while at least two P body 5s arranged at intervals form an isolation band in the transition region. The spacing between two adjacent P body 5s in the isolation band is the width of one unit cell.

[0048] Step S4: Perform source N+ photolithography. Specifically, photoresist is coated on the upper surface of the N-drift region 1, and a source N+ mask is used for exposure and development to form the source N+ photolithographic pattern. The source N+ photolithographic pattern covers the position on each P body 5 where the source N+6 needs to be formed, that is, the area on the surface of the P body 5 near the sidewall of the gate polysilicon 4. Then, arsenic ion implantation is performed with an arsenic ion implantation energy of 90keV to 150keV and a dose of 2×10⁻⁶. 15 cm -2 ~6×10 15 cm -2 After implantation, the photoresist is removed, and annealing is performed at 950℃ for 30 minutes to form the source N+6. Figure 5 As shown. The typical junction depth of source N+6 is 0.2 μm to 0.5 μm.

[0049] Step S5 involves depositing an interlayer dielectric (ILD). Specifically, an insulating dielectric layer is deposited on the upper surface of the wafer after the previous steps to form ILD7. The material of ILD7 can be borosilicate glass (BPSG), silicon phosphate glass (PSG), or undoped silicon dioxide. The deposition method can be atmospheric pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition. The typical thickness of ILD7 is 500 nm to 1500 nm. After deposition, a reflow process is performed to planarize the surface of ILD7. The reflow temperature is typically 850°C to 950°C. The structure after ILD7 formation is shown below. Figure 6 As shown.

[0050] Step S6: Etch the ILD and fill it with metal to form the front emitter 8. Specifically, using photolithography and etching processes, contact holes are etched in the ILD7, with the contact holes positioned above the source N+6 and P body 5. After the contact holes are etched, a metal layer is deposited inside the contact holes and on the upper surface of the ILD7. The metal layer material is aluminum, aluminum-silicon alloy, or aluminum-silicon-copper alloy. The deposition method can be magnetron sputtering or electron beam evaporation, and the typical thickness of the metal layer is 4μm to 5μm. Then, the metal layer is patterned using photolithography and etching processes to form the front emitter 8, as shown below. Figure 7 As shown. The front emitter 8 achieves ohmic contact with the source N+6 and P body 5 through the contact hole.

[0051] Step S7: Flip the IGBT wafer and perform back-side thinning. Specifically, flip the wafer after the front-side processing is completed so that its back side faces upwards. Thin the back side of the wafer using mechanical grinding and chemical mechanical polishing methods. The thickness of the thinned wafer is determined according to the device's voltage rating; for devices with a voltage rating of 600V to 3300V, the thinned thickness is typically 60μm to 520μm. After thinning, perform N+ collector photolithography. Specifically, coat the back side of the wafer with photoresist, and expose and develop using an N+ collector mask to form the N+ collector photolithographic pattern. The N+ collector photolithographic pattern covers the back-side area corresponding to the unit cell region and transition region. Then, perform phosphorus ion implantation at an energy of 40keV to 80keV and a dose of 1×10⁻⁶. 14 cm -2 ~5×10 14 cm -2 This forms an N+ collector 9, such as Figure 8 As shown. The typical junction depth of N+ collector 9 is 0.5 μm to 1.5 μm.

[0052] Step S8: Perform P+ collector implantation. Specifically, boron ion implantation is performed on the back side of the wafer at an energy of 30 keV to 60 keV and a dose of 1 × 10⁻⁶. 13 cm -2 ~5×10 13 cm -2 After injection, laser annealing is performed at an energy of 1.8 J to 2.2 J to form a P+ collector 10, as shown below. Figure 9 As shown. Laser annealing employs pulsed laser annealing, with typical laser wavelengths of 308 nm or 532 nm and pulse widths ranging from tens to hundreds of nanoseconds. Laser annealing enables rapid activation and limited diffusion of impurities, achieving a high doping activation rate while maintaining a shallow junction depth. The P+ collector 10 is located in the back-side region corresponding to the unit cell region and the terminal region. The typical junction depth of the P+ collector 10 is 0.3 μm to 1.0 μm.

[0053] Step S9: Evaporate the backside metal to form the collector 11. Specifically, a metal layer is evaporated on the backside of the wafer after step S8. The metal layer material is a titanium / nickel / silver stack or a titanium / nickel / gold stack, and the evaporation method can be electron beam evaporation. The typical total thickness of the metal layer is 200 nm to 1500 nm. After evaporation, an alloying process is performed. The typical alloying temperature is 300 °C to 450 °C, and the alloying time is 10 min to 60 min, so that the backside metal forms a good ohmic contact with the N+ collector 9 and the P+ collector 10, forming the collector 11, and finally obtaining the desired result. Figure 1 The device structure shown.

[0054] In the above preparation method, the boron ion implantation dose of P body5 in step S3 is 1×10⁻⁶. 13 cm -2 ~8×10 13 cm -2 The annealing temperature is 1100℃~1150℃, and the annealing time is 90min~150min. These process conditions ensure that Pbody5 has an appropriate doping concentration and junction depth, meeting both the electrical performance requirements of the cell region channel and forming an effective isolation band in the transition region. In step S1, the boron ion implantation dose of P ring2 is 1×10⁻⁶. 14 cm -2 ~8×10 14 cm -2 , of which 5×10 14 cm -2 The above is for high injection dose, annealing temperature of 1100℃~1150℃, annealing time of 200min~300min. These process conditions enable P ring2 to form a deep P-type potential well, effectively reducing the electric field on the terminal surface. At the same time, in conjunction with the isolation band structure in the transition region, holes are prevented from being captured by P ring2.

[0055] In the aforementioned device structure and fabrication method, the lateral width of the transition region is greater than the width of two unit cells but less than the width of three unit cells, specifically ranging from 80 μm to 300 μm. This width range was obtained through extensive experimental optimization. When the transition region width is less than the width of two unit cells, the space of the isolation band is insufficient to effectively block the lateral diffusion of holes, and some holes can still bypass the isolation band to reach P ring 2. When the transition region width is greater than the width of three unit cells, although the isolation effect is better, it leads to an excessive increase in chip area. Therefore, limiting the transition region width to a range greater than the width of two unit cells but less than the width of three unit cells, i.e., 80 μm to 300 μm, can ensure the isolation effect while also considering chip area and VF optimization.

[0056] During device operation, holes in the outermost P-body 5 of the unit cell region cannot diffuse laterally to P-ring 2 due to the obstruction of the isolation band. Specifically, when the device is in reverse conduction, the FRD region is turned on, and holes are injected from P-body 5 into the N-drift region 1. In conventional structures, these holes drift towards P-ring 2 under the influence of the lateral electric field and are captured by the deep potential well of the highly doped P-ring 2. However, in this invention, the P-body 5s arranged at intervals in the isolation band form a P-type doped barrier region laterally. When holes reach the isolation band region, they are blocked by the doping barrier of P-body 5 and cannot continue to diffuse laterally. At the same time, the widened transition region increases the longitudinal diffusion path of holes, and when holes cannot diffuse laterally, they are injected vertically downward into the N-drift region 1. These vertically injected holes recombine with electrons from the N+ collector 9 on the back side in the N-drift region 1, forming high-concentration electron-hole pairs, which significantly enhances the conductivity modulation effect of the drift region, thereby reducing the forward voltage drop VF of the diode. The lateral width of the N+ collector 9 on the back side corresponding to the widened transition region is increased to ensure that there is also an N+ collector 9 below the transition region to provide electron injection, further compensating for the effective area of ​​the FRD and further optimizing the VF characteristics.

[0057] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A high-voltage planar gate RC-IGBT device with low diode forward voltage drop, characterized in that: The semiconductor substrate includes an N-drift region (1), and a unit cell region, a transition region and a terminal region are sequentially arranged in the transverse direction above the N-drift region (1). The unit cell region has a P body (5), and the terminal region has a P ring (2) on the side near the transition region. The lateral width of the transition region is greater than the width of two unit cells and less than the width of three unit cells; An isolation zone is provided in the transition region. The isolation zone is located between the outermost P body (5) of the protocell region and the P ring (2). The isolation zone is composed of at least two P bodies (5) arranged laterally. The isolation zone is used to block the lateral diffusion of cavities in the outermost P body (5) of the protocell region to the P ring (2).

2. The high-voltage planar gate RC-IGBT device with low diode forward voltage drop according to claim 1, characterized in that, The lateral width of the transition region is 80μm to 300μm.

3. The high-voltage planar gate RC-IGBT device with low diode forward voltage drop according to claim 1, characterized in that, The distance between two adjacent P bodies (5) in the isolation zone is the width of one unit cell.

4. The high-voltage planar gate RC-IGBT device with low diode forward voltage drop according to claim 1, characterized in that, The P ring (2) is a highly doped P-type region, and the boron ion implantation dose of the P ring (2) is 5 × 10⁻⁶. 14 cm -2 above.

5. The high-voltage planar gate RC-IGBT device with low diode forward voltage drop according to claim 1, characterized in that, The back side of the semiconductor substrate is provided with an N+ collector (9) and a P+ collector (10), and the N+ collector (9) is disposed in the back side region corresponding to the unit cell region and the transition region.

6. The high-voltage planar gate RC-IGBT device with low diode forward voltage drop according to claim 5, characterized in that, The P+ collector (10) is disposed in the unit cell region and the back surface region corresponding to the terminal region, and the N+ collector (9) and the P+ collector (10) are arranged alternately in the lateral direction on the back surface of the semiconductor substrate.

7. The high-voltage planar gate RC-IGBT device with low diode forward voltage drop according to claim 5, characterized in that, The lateral width of the N+ collector (9) corresponding to the transition region is wider than the lateral width of the N+ collector (9) corresponding to the unit cell region.

8. The high-voltage planar gate RC-IGBT device with low diode forward voltage drop according to claim 1, characterized in that, The boron ion implantation dose of the P body (5) is 1×10⁻⁶. 13 cm -2 ~8×10 13 cm -2 .

9. The high-voltage planar gate RC-IGBT device with low diode forward voltage drop according to claim 1, characterized in that, The unit cell region includes multiple units cells, each of which further includes a gate oxide layer (3), a gate polysilicon (4) disposed above the gate oxide layer (3), and a source N+ (6) disposed on the upper part of the P body (5).

10. The high-voltage planar gate RC-IGBT device with low diode forward voltage drop according to claim 1, characterized in that, The terminal area includes a plurality of P rings (2), which are arranged at horizontal intervals.

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