Semiconductor discharge tube and method of manufacturing the same

Abstract

The application discloses a semiconductor discharge tube and a manufacturing method thereof. The semiconductor discharge tube comprises an N-type substrate and P-type regions located on both sides of the N-type substrate; the P-type regions located on both sides of the N-type substrate each comprise P-regions, P+ regions and P++ regions with different doping concentrations, and the P-regions, the P+ regions and the P++ regions have different junction depths in the N-type substrate; the P-regions, the P+ regions and the P++ regions are arranged adjacent to the N-type substrate, the P+ regions are arranged in intervals with the P++ regions, the P-regions are located between adjacent P++ regions and between adjacent P+ regions and P++ regions, and the P-regions surround the P+ regions and the P++ regions; wherein the doping concentration of the P-regions is less than the doping concentration of the P+ regions, and the doping concentration of the P+ regions is less than the doping concentration of the P++ regions. The application can effectively transfer the breakdown position of the semiconductor discharge tube from the surface to the inside, and improve the reliability of the semiconductor discharge tube.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor discharge tube and a method for manufacturing the same. Background Technology

[0002] Thyristor surge suppressors (TSS), also known as semiconductor discharge tubes, are PNPN junction four-layer structure devices manufactured using semiconductor technology. Their current-voltage characteristics exhibit typical switching characteristics. TSSs are typically used in parallel in circuits. Under normal operation, they are in the off state. When an abnormal overvoltage occurs in the circuit due to induced lightning strikes, operational overvoltages, or other reasons, the discharge tube quickly conducts and discharges the surge current, protecting sensitive downstream equipment from damage. After the abnormal overvoltage disappears, the discharge tube automatically returns to the off state. It has advantages such as fast response speed, strong repeated surge immunity, low leakage current, and stable performance.

[0003] Traditional high-voltage semiconductor discharge tube (TSS) chips typically employ a vertically stacked structure of two PNPN four-layer triple-junction structures, integrated in reverse parallel on the same silicon wafer, or achieving bidirectional symmetrical current-voltage characteristics through a special symmetrical doping design. Their manufacturing process primarily relies on traditional thermal diffusion and ion implantation, with glass or silicon dioxide passivation layers protecting the PN junction edges on the chip surface. However, since these PN junctions are located on the silicon wafer surface, precisely in the region of strongest electric field, the long-term reliability of the chip largely depends on the quality of the passivation process and the stability of the passivation material. If the passivation layer has defects or is affected by factors such as moisture or ion contamination, the surface PN junction is highly susceptible to premature breakdown, leading to device failure. Summary of the Invention

[0004] This invention provides a semiconductor discharge tube and its manufacturing method, which effectively transfers the breakdown location of the semiconductor discharge tube from the body surface to the body, thereby improving the reliability of the semiconductor discharge tube.

[0005] In a first aspect, embodiments of the present invention provide a semiconductor discharge tube, the semiconductor discharge tube comprising an N-type substrate and P-type regions located on both sides of the N-type substrate; The P-type regions located on both sides of the N-type substrate each include P-, P+, and P++ regions with different doping concentrations, and the junction depths of the P-, P+, and P++ regions in the N-type substrate are all different. The P- region, the P+ region, and the P++ region are all disposed adjacent to the N-type substrate. The P+ region and the P++ region are disposed at an interval. The P- region is located between adjacent P++ regions and between adjacent P+ regions and P++ regions, and the P- region surrounds the P+ region and the P++ region. The doping concentration of the P- region is less than that of the P+ region, and the doping concentration of the P+ region is less than that of the P++ region.

[0006] Optionally, in the P-type region on the same side of the N-type substrate, the P+ region and the P++ region are located on opposite sides of the side of the N-type substrate. The P++ region includes multiple spaced-apart third P sub-regions, which are uniformly distributed on one side of the N-type substrate.

[0007] Optionally, in the P-type region on the same side of the N-type substrate, the contact area between the P- region and the N-type substrate accounts for 60% to 70% of the surface area of ​​the N-type substrate, the contact area between the P+ region and the N-type substrate accounts for 20% to 35% of the surface area of ​​the N-type substrate, and the contact area between the P++ region and the N-type substrate accounts for 10% to 25% of the surface area of ​​the N-type substrate.

[0008] Optionally, the shape of the vertical projection of the third P sub-region onto the N-type substrate includes a rectangle, a circle, a triangle, or a star shape.

[0009] Optionally, the junction depth of the P+ region is greater than the junction depth of the P- region, and the junction depth of the P- region is greater than the junction depth of the P++ region; Optionally, the junction depth of the P- region includes 30um to 40um, the junction depth of the P+ region includes 60um to 80um, and the junction depth of the P++ region includes 25um to 35um.

[0010] Optionally, a plurality of uniformly distributed N+ regions are provided on the side of the P++ region away from the N-type substrate, and the doping concentration of the N+ regions is greater than that of the N-type substrate; The vertical projection of the N+ region onto the N-type substrate occupies 40% to 50% of the surface area of ​​the N-type substrate, and the junction depth of the N+ region in the P++ region is 10 μm to 15 μm.

[0011] Optionally, the N+ region is provided with a short-circuit hole that penetrates the N+ region, and the P++ region is filled in the short-circuit hole, the diameter of the short-circuit hole being 50um-120um.

[0012] Secondly, embodiments of the present invention also provide a method for manufacturing a semiconductor discharge tube, the method being used to form the semiconductor discharge tube described in any embodiment of the present invention, comprising: The corresponding regions of the P+ region are etched on the surfaces on both sides of the N-type substrate, and the P+ region is deposited to form the P+ region. The corresponding regions of the P-regions are etched on the surfaces on both sides of the N-type substrate, and the P-regions are deposited to form them. The corresponding regions of the P++ region are etched on the surfaces on both sides of the N-type substrate, and the P++ region is deposited to form the P++ region; wherein the junction depths of the P- region, the P+ region and the P++ region in the N-type substrate are different, the doping concentration of the P- region is less than the doping concentration of the P+ region, and the doping concentration of the P+ region is less than the doping concentration of the P++ region.

[0013] Furthermore, after forming the P++ region, the process also includes: Multiple uniformly distributed N+ regions are etched and deposited on the side of the P++ region away from the N-type substrate, and the doping concentration of the N+ regions is greater than that of the N-type substrate.

[0014] This invention provides a semiconductor discharge tube and its fabrication method. The semiconductor discharge tube includes an N-type substrate and P-type regions located on both sides of the N-type substrate. Each P-type region on both sides of the N-type substrate includes P-, P+, and P++ regions with different doping concentrations, and the junction depths of the P-, P+, and P++ regions in the N-type substrate are different. The P-, P+, and P++ regions are all adjacent to the N-type substrate, with the P+ region and P++ region spaced apart. The P- region is located between adjacent P++ regions and between adjacent P+ and P++ regions. By setting multiple P-type regions with different concentrations and junction depths on both sides of the N-type substrate, and by surrounding the high-doped P+ and P++ regions with the low-doped P- regions (i.e., the P- regions are closer together), compared to the traditional structure, when a reverse voltage is applied, the semiconductor discharge tube of this invention will preferentially break down at the bulk P++N junction rather than at the weakest surface PN junction. This achieves an effective transfer of the breakdown location of the high-voltage semiconductor discharge tube from the surface to the bulk, improving the reliability of the semiconductor discharge tube. Attached Figure Description

[0015] Figure 1 A schematic cross-sectional view of a semiconductor discharge tube provided in an embodiment of the present invention; Figure 2 This is a top view schematic diagram of a semiconductor discharge tube provided in an embodiment of the present invention; Figure 3 A cross-sectional schematic diagram of another mesa-structured semiconductor discharge tube provided in an embodiment of the present invention, after passivation and appearance shaping. Figure 4 A schematic cross-sectional view of a planar semiconductor discharge tube provided in an embodiment of the present invention; Figure 5 A top view of the planar semiconductor discharge tube provided in an embodiment of the present invention; Figure 6 A flowchart illustrating a method for fabricating a semiconductor discharge tube according to an embodiment of the present invention; Figure 7 A flowchart illustrating another method for fabricating a semiconductor discharge tube according to an embodiment of the present invention. Detailed Implementation

[0016] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0017] In related technologies, the TSS (Transient Voltage Spectrometer) chip structure typically employs a vertically stacked design of two PNPN four-layer triple junctions, integrated in reverse parallel on the same silicon wafer, or through a special symmetrical doping design to form bidirectional symmetrical current-voltage characteristics. The manufacturing process involves traditional diffusion and ion implantation, and passivation generally involves using a glass passivation or silicon dioxide passivation layer to protect the PN junction edges on the chip surface. Since this PN junction is located on the silicon wafer surface and at the point of strongest electric field, the chip's reliability largely depends on the passivation process or passivation material.

[0018] Figure 1 This is a schematic cross-sectional view of a semiconductor discharge tube provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the semiconductor discharge tube includes an N-type substrate 110 and P-type regions 120 located on both sides of the N-type substrate 110.

[0019] The P-type regions 120 located on both sides of the N-type substrate 110 each include P-region 121, P+region 122 and P++region 123 with different doping concentrations. The junction depths of P-region 121, P+region 122 and P++region 123 in the N-type substrate 110 are all different.

[0020] In this design, the N-type substrate 110 serves as the base material for the semiconductor discharge tube. P-regions 121, P+regions 122, and P++regions 123 are disposed on both sides of the N-type substrate 110, i.e., the upper and lower surfaces of the N-type substrate 110, and can be arranged in a centrally symmetrical manner. The resistivity of the N-type substrate 110 corresponds to the chip breakdown voltage of the semiconductor discharge tube, for example, it can cover 0.5–50 Ω·cm, corresponding to the V0 of the semiconductor discharge tube. DRMWithin a voltage range of 100–1000V, the thickness of the N-type substrate 110 can be 200–260 μm. The resistivity of the N-type substrate 110 is matched with its thickness. By adjusting the resistivity and thickness of the N-type substrate, it can be flexibly adapted to various voltage levels from 100 to 1000V. The P-region 121, P+region 122, and P++region 123 can all be formed by diffusion of P-type acceptor trivalent elements, such as boron (B), aluminum (Al), and gallium (Ga) impurities. Preferably, boron can be used as the diffusion source, and the desired doping concentration and junction depth can be obtained by controlling the pre-deposition and redistribution processes.

[0021] P-region 121, P+region 122, and P++region 123 are all disposed adjacent to the N-type substrate 110. P+region 122 and P++region 123 are disposed alternately. P-region 121 is located between adjacent P++region 123 and between adjacent P+region 122 and P++region 123, and P-region 121 surrounds P+region 122 and P++region 123. The doping concentration of P-region 121 is less than that of P+region 122, and the doping concentration of P+region 122 is less than that of P++region 123.

[0022] Specifically, the doping concentration of P- region 121 is less than that of P+ region 122, which is less than that of P++ region 123. P- region 121 is lightly doped, P+ region 122 is heavily doped, and P++ region 123 is extremely heavily doped. P+ region 122 and P++ region 123 are spaced apart and do not contact each other on the N-type substrate 110, maintaining a certain distance. P- region 121 fills all the gaps, including the area between P+ region 122 and P++ region 123 and the area between adjacent P++ region 123. That is, the high-concentration P+ region and P++ region are surrounded and wrapped by the low-concentration P- region.

[0023] Due to its lower doping concentration, P-region 121 exhibits a wider lateral expansion of the depletion layer when a reverse bias voltage is applied. This distributes the voltage at the termination of the surface PN junction over a larger lateral distance, significantly reducing the peak surface electric field and keeping it below the critical breakdown electric field of the semiconductor material. P++region 123, with its extremely high doping concentration, pushes the depletion layer almost entirely into the N-type substrate 110. A highly concentrated electric field is formed on the longitudinal bulk portion of the P++N junction near the N-type substrate 110, where the peak electric field is higher than the surface electric field suppressed by the P-region. Therefore, the P++N junction within the semiconductor discharge tube reaches the critical breakdown electric field first, resulting in avalanche breakdown. The PN junction on the semiconductor discharge tube surface, however, does not break down due to insufficient electric field. Consequently, when a reverse voltage is applied to the high-voltage semiconductor discharge tube, breakdown preferentially occurs at the bulk P++N junction, rather than at the weakest surface PN junction, thus effectively shifting the breakdown location of the high-voltage semiconductor discharge tube from the surface to the bulk. In traditional semiconductor discharge tubes, the region where the PN junction terminates on the silicon wafer surface suffers from high electric field concentration and susceptibility to external environmental corrosion due to factors such as junction curvature effect, passivation layer interface, fixed charge, and mobile ion contamination, making it a weak point in device reliability. The embodiments of this invention can avoid the influence of unstable factors on the semiconductor discharge tube surface. For example, it eliminates the decisive influence of the passivation layer quality on breakdown behavior, extending the device's surge life and minimizing parameter drift after high-temperature aging. This avoids the surface weakness in traditional structures that relies on passivation process quality, shifting the breakdown point to the interior of the silicon mass without requiring additional passivation steps, significantly improving the long-term operational reliability of the semiconductor discharge tube.

[0024] This invention provides a semiconductor discharge tube, relating to a power semiconductor overvoltage protection discharge tube chip structure. The semiconductor discharge tube has an N-type substrate with multiple P-type regions of different concentrations and junction depths on both sides. The P+ and P++ regions are surrounded by the P- region, so that the high and low concentration P-type regions are arranged alternately. When a reverse voltage is applied, breakdown occurs preferentially at the P++N junction inside the semiconductor discharge tube, rather than at the PN junction on the surface where the semiconductor discharge tube's reliability is weakest. This realizes the transfer of high-voltage series discharge tube chip breakdown from the surface to the core, thereby improving the chip's reliability.

[0025] Figure 2 This is a top view schematic diagram of a semiconductor discharge tube provided in an embodiment of the present invention, as shown below. Figure 1 and Figure 2 As shown, in the P-type region 120 on the same side of the N-type substrate 110, the P+ region 122 and the P++ region 123 are located on both sides of the side of the N-type substrate 110.

[0026] The P++ region 123 includes a plurality of spaced third P sub-regions 1231, which are uniformly distributed on one side of the N-type substrate 110.

[0027] like Figure 1 As shown, P+ region 122 and P++ region 123 are located on opposite sides of the N-type substrate 110. In the cross-section of the semiconductor discharge tube, on one side of the N-type substrate 110, P- region 121, P++ region 123, P- region 121, P++ region 123, P- region 121, P+ region 122, and P- region 121 are arranged sequentially on the side of the N-type substrate 110. On the other side of the N-type substrate 110, P- region 121, P+ region 122, P- region 121, P++ region 123, P- region 121, P++ region 123, and P- region 121 are arranged sequentially on the other side of the N-type substrate 110. Figure 2 As shown, P+ region 122 and P++ region 123 are located on opposite sides of the N-type substrate 110. P- region 121 surrounds P++ region 123 and P+ region 122, respectively. P++ region 123 is composed of multiple small third P sub-regions 1231, and P- region 121 also surrounds multiple third P sub-regions 1231. By dispersing the P++ regions 123, the edge effect of the large-size P++ region 123 can be eliminated, and the electric field distribution of P++ region 123 is optimized. An electric field concentration point is formed at the bulk P++N junction directly below each third P sub-region 1231. Multiple sub-regions make the bulk electric field concentration points uniformly distributed in an array. When an abnormal overvoltage occurs, multiple third P sub-regions 1231 simultaneously conduct to discharge surge current. The current density of each sub-region is significantly reduced, effectively avoiding the hot spot effect caused by current concentration. The surge resistance and repetitive lifetime of the device are significantly improved. When a reverse voltage is applied, the bulk P++N junctions directly below the third P subregion 1231 almost simultaneously reach the critical breakdown electric field and avalanche occurs. The breakdown points are evenly distributed inside the chip, avoiding local overheating caused by the concentration of breakdown points.

[0028] P+ region 122 and P++ region 123 are located on opposite sides of the N-type substrate 110. P- region 121 can also act as a buffer layer to isolate P++ region 123 from P+ region 122, avoiding boundary electric field distortion caused by direct proximity of high concentration differences, resulting in a more uniform and smooth electric field distribution. Furthermore, the spatial separation of P+ region 122 and P++ region 123 allows P- region 121, P+ region 122, and P++ region 123 to be formed separately through independent photolithography masks and diffusion processes. Junction depth and doping concentration are independently controllable, making the process simple and reliable.

[0029] In some embodiments of the present invention, in the P-type region 120 on the same side of the N-type substrate 110, the contact area between the P- region 121 and the N-type substrate 110 accounts for 60% to 70% of the surface area of ​​the N-type substrate 110, the contact area between the P+ region 122 and the N-type substrate 110 accounts for 20% to 35% of the surface area of ​​the N-type substrate 110, and the contact area between the P++ region 123 and the N-type substrate 110 accounts for 10% to 25% of the surface area of ​​the N-type substrate 110.

[0030] Specifically, the surface area of ​​the N-type substrate is also the chip area of ​​the semiconductor discharge tube. That is, the contact area between the P- region 121 and the N-type substrate 110 accounts for 60% to 70% of the chip area of ​​the semiconductor discharge tube, the contact area between the P+ region 122 and the N-type substrate 110 accounts for 20% to 35% of the chip area of ​​the semiconductor discharge tube, and the contact area between the P++ region 123 and the N-type substrate 110 accounts for 10% to 25% of the chip area of ​​the semiconductor discharge tube.

[0031] In some embodiments of the present invention, the shape of the third P sub-region 1231 is not limited to... Figure 2 The rectangle shown, the shape of the third P sub-region 1231 projected vertically onto the N-type substrate 110 includes rectangles, circles, triangles, star shapes, or other irregular patterns.

[0032] In some embodiments of the present invention, reference is made to Figure 1 The junction depth of P+ region 122 is greater than that of P- region 121, and the junction depth of P- region 121 is greater than that of P++ region 123.

[0033] Specifically, the junction depth of P+ region 122 > junction depth of P- region 121 > junction depth of P++ region 123, which, together with the setting of doping concentration of P- region 121 < doping concentration of P+ region 122 < doping concentration of P++ region 123, has a synergistic effect, jointly achieving the precise transfer of the breakdown point from the bulk surface to the bulk. Since the junction depth of P++ 123 is the shallowest, the depletion layer is almost entirely pushed into one side of the N-type substrate 110, forming an extremely high vertical electric field peak at the P++ N junction, which will preferentially break down within the semiconductor discharge tube.

[0034] Optionally, the junction depth of P- region 121 includes 30um to 40um, the junction depth of P+ region 122 includes 60um to 80um, and the junction depth of P++ region 123 includes 25um to 35um.

[0035] Specifically, P- region 121 contains diffused P-type acceptor trivalent elements such as boron, aluminum, and gallium, with a pre-deposited sheet resistance of 15–25 ohms / sq, a junction depth of 30–40 μm, and an area accounting for 60%–70% of the total chip area of ​​the semiconductor discharge tube. P+ region 122 contains diffused P-type acceptor trivalent elements such as boron, aluminum, and gallium, with a pre-deposited sheet resistance of 4–10 ohms / sq, a junction depth of 60–80 μm, and an area accounting for 20%–35% of the total chip area of ​​the semiconductor discharge tube. P++ region 123 contains diffused P-type acceptor trivalent elements such as boron, aluminum, and gallium, with a pre-deposited sheet resistance of 8–15 ohms / sq, a junction depth of 25–35 μm, and an area accounting for 10%–25% of the total chip area. P+ region 122 and P++ region 123 are located on opposite sides of the same side of the N-type substrate 110. After the acceptor impurities in P-region 121, P+region 122, and P++region 123 undergo high-temperature redistribution, the leading-edge impurity concentrations of P-region 121, P+region 122, and P++region 123 are arranged in descending order as follows: P++region 123 > P+region 122 > P-region 121. The leading-edge impurity concentration is the impurity concentration in the region of P-region 121, P+region 122, and P++region 123 closest to the N-type substrate 110. Therefore, in this embodiment of the invention, the doping concentrations of P-region 121, P+region 122, and P++region 123 are specifically the leading-edge impurity concentrations of P-region 121, P+region 122, and P++region 123, i.e., the doping concentration of P++region 123 > the doping concentration of P+region 122 > the doping concentration of P-region 121.

[0036] It's important to note that doping in semiconductor materials is used to create N-type or P-type semiconductor regions to form various device structures. The basic idea of ​​doping is to introduce a certain concentration of trivalent or pentavalent elements into a semiconductor substrate using certain techniques, thereby replacing some atoms of the raw material with impurity atoms. Doping methods are divided into thermal diffusion and ion implantation. Thermal diffusion is the earliest and simplest doping process. It utilizes the diffusion motion of atoms at high temperatures to allow impurity atoms to diffuse from a high-concentration impurity source into the silicon and form a certain distribution. Thermal diffusion typically involves two steps: pre-deposition and main diffusion. Pre-deposition involves diffusing impurity sources such as boron or phosphorus onto the doping windows on the silicon wafer at high temperatures, forming a thin but highly concentrated impurity layer at the window. Main diffusion uses the surface impurity layer formed by pre-deposition as an impurity source, diffusing this impurity layer into the silicon mass at high temperatures. This process usually takes a relatively long time.

[0037] In this embodiment of the invention, due to the different junction depths of P-region 121, P+region 122, and P++region 123, the impurity concentration decreases progressively from the surface of the semiconductor discharge tube towards the junction depth of P-region 121, P+region 122, and P++region 123 (the direction from the surface of P-region 121, P+region 122, and P++region 123 towards the N-type substrate 110). P+region 122 has the deepest junction depth, at 60–80 μm, while P++region 123 has a relatively shallow junction depth of only 25–35 μm. Although the pre-deposition sheet resistance of P++region 123 is 8–15 ohms / sq, which is greater than that of P-region 121 (4–10 ohms / sq), the impurity concentration decreases accordingly. The smaller the pre-deposited sheet resistance (ohm / sq), the higher the impurity concentration. After acceptor impurity redistribution, since the junction depth of P++ region 123 is relatively shallow and the junction depth of P+ region 122 is relatively deep, the impurity concentration in the deepest part of P+ region 122, i.e., the region of P+ region 122 near the N-type substrate 110, will be smaller than the impurity concentration on the surface of P+ region 122 far from the N-type substrate 110. Therefore, after acceptor impurity redistribution, the leading impurity concentration of P+ region 122 will still be smaller than the leading impurity concentration of P++ region 123, ensuring that the leading impurity concentrations of P- region 121, P+ region 122, and P++ region 123 are arranged from high to low as follows: P++ region 123 > P+ region 122 > P- region 121.

[0038] Optionally, a plurality of uniformly distributed N+ regions 130 are provided on the side of the P++ region 123 away from the N-type substrate 110, and the doping concentration of the N+ regions 130 is greater than that of the N-type substrate 110. The vertical projection of the N+ regions 130 onto the N-type substrate 110 occupies 40% to 50% of the surface area of ​​the N-type substrate, and the junction depth of the N+ regions 130 in the P++ region 123 is 10 μm to 15 μm.

[0039] Specifically, on the same side of the N-type substrate 110, the N+ region 130 is located on the same side as the P++ region 123. The vertical projection of the N+ region 130 onto the N-type substrate 110 overlaps with the vertical projection of the P++ region 123 onto the N-type substrate 110. The pre-deposited sheet resistance of the N+ region 130 is 1–5 ohms / sq, and the junction depth is 10–15 μm. The N+ region 130 occupies 40%–50% of the total chip area of ​​the semiconductor discharge tube. The N+ region 130, together with the P++ region 123 and the bottom of the N-type substrate 110, forms an NPN structure, i.e., the N+ region 130 and the P++ region 123 form another PN junction. The N+ region 130 is a heavily doped region and also an electrode contact region, with extremely low ohmic contact resistance, providing a heavily doped contact layer for the subsequent short-circuit via 131.

[0040] Optionally, the N+ region 130 is provided with a short-circuit hole 131 that penetrates the N+ region 130, and the diameter of the short-circuit hole 131 is 50um-120um.

[0041] Specifically, the short-circuit hole 131 penetrates the N+ region 130, and the P++ region 123 is filled in the short-circuit hole 131. Since the PN junction formed by the N+ region 130 and the P++ region 123 has a withstand voltage when the semiconductor discharge tube is initially turned on, the current cannot pass through. Setting the P++ region 123 to fill the short-circuit hole 131 can provide a current path when the semiconductor discharge tube is initially turned on.

[0042] In addition, the surfaces of P- region 121, P+ region 122, P++ region 123 and N+ region 130 are provided with glass 140 or passivation layer 150 and covered with metal electrode 160, which is not limited to being formed by chemical plating, evaporation, deposition and other processes.

[0043] The semiconductor discharge tube in this embodiment of the invention may include unidirectional or bidirectional structures, or mesa or planar structures.

[0044] P-region 121, P+region 122, P++region 123, and N+region 130 can be formed through the following steps: pre-deposition and redistribution of PN junctions at various levels and in various patterns. Specifically, this may include: 1.1 The N-type substrate 110 silicon wafer is chemically polished to thin it, and the silicon wafer surface is etched to form unit cells; according to V DRM Select the range and the corresponding resistivity.

[0045] 1.2. Perform ultrasonic cleaning and SC1+SC2 cleaning on the N-type substrate 110 silicon wafer.

[0046] 1.3. A silicon dioxide layer with a thickness of 111 used for masking is grown by high-temperature oxidation.

[0047] 1.4. Using photolithography, P+ regions 122 are etched on both sides of an N-type substrate 110 silicon wafer.

[0048] 1.5. Acceptor element pre-deposition and redistribution are carried out in P+ region 122.

[0049] 1.6. Using photolithography, P-region 121 is etched on both sides of the N-type substrate 110 silicon wafer.

[0050] 1.7. Acceptor element pre-deposition and redistribution are performed in P-region 121.

[0051] 1.8. Using photolithography, P++ region 123 is etched on both sides of an N-type substrate 110 silicon wafer.

[0052] 1.9 Perform acceptor element pre-deposition and redistribution in P++ region 123.

[0053] 1.10. Using photolithography, N+ regions 130 are etched on both sides of an N-type substrate 110 silicon wafer.

[0054] 1.11. Donor element pre-deposition and redistribution are performed in the N+ region 130.

[0055] In addition, the surfaces of the semiconductor discharge tube, namely the P- region 121, P+ region 122, and P++ region 123, which are away from the N-type substrate 110, also need to undergo passivation and shape treatment. Figure 1 Specifically, it refers to the cross-sectional structure of a mesa-shaped semiconductor discharge tube after passivation and aesthetic design. Figure 3 This is a cross-sectional schematic diagram of another mesa-structured semiconductor discharge tube provided in an embodiment of the present invention, after passivation and appearance shaping. Figure 3 A thin film is also grown at 140 locations on the glass, and the passivation and appearance are specifically included as follows: 2.1 For discharge transistor chips with glass passivated mesa structures, refer to... Figure 1 and Figure 3 As shown, following step 1.11: 2.1.1. Double-sided trench lines are etched on an N-type substrate 110 silicon wafer using photolithography.

[0056] 2.1.2. Grooves are etched on both sides of the wafer using wet etching.

[0057] 2.1.3 Clean the N-type substrate 110 silicon wafer after trench etching is completed.

[0058] 2.1.4. Glass paste is filled into the double-sided trenches of the N-type substrate 110 silicon wafer, and the glass 140 is crystallized by high-temperature sintering.

[0059] 2.2 For thin-film passivated mesa structure discharge tube chips, following step 2.1.3, 2.2.1. An SIPOS thin film is grown on an N-type substrate 110 silicon wafer by low-pressure vapor deposition.

[0060] 2.2.2. SIN thin films are grown on N-type substrate 110 silicon wafers by low-pressure vapor deposition.

[0061] 2.2.3. LTO thin films are grown on N-type substrate 110 silicon wafers by low-pressure vapor deposition.

[0062] 2.3. For planar semiconductor discharge tube chips, Figure 4 This is a schematic cross-sectional view of a planar semiconductor discharge tube provided in an embodiment of the present invention. Figure 5 This is a top view of a planar semiconductor discharge tube provided in an embodiment of the present invention, as shown in the figure. Figure 4 and Figure 5 As shown, following step 1.11: 2.3.1 Remove all silicon dioxide layers on the surface by wet etching 111.

[0063] 2.3.2 Clean the N-type substrate 110 silicon wafer after the oxide layer has been removed.

[0064] 2.3.3. A passivation layer 150 is regrown on the chip surface. This passivation layer can be silicon dioxide, or a multilayer composite insulating passivation layer 150 such as SIPOS, SIN, or LTO.

[0065] 3. Metal electrode 160 formation: 3.1. Using photolithography, wire hole patterns are etched on both sides of the passivated N-type substrate 110 silicon wafer.

[0066] 3.2 Use BOE or mixed acid to remove the silicon dioxide layer 111 or the multilayer composite insulating passivation layer 150 in the lead hole pattern.

[0067] 3.3 Clean the N-type silicon wafer 111 after the lead hole etching is completed.

[0068] 3.4. The cleaned N-type silicon wafer 111 is then fitted with double-sided metal electrodes 160.

[0069] This invention provides a semiconductor discharge tube, relating to a power semiconductor overvoltage protection discharge tube chip structure. The semiconductor discharge tube has an N-type substrate with multiple P-type regions of different concentrations and junction depths on both sides. The P+ and P++ regions are surrounded by the P- region, so that the high and low concentration P-type regions are arranged alternately. When a reverse voltage is applied, breakdown occurs preferentially at the P++N junction inside the semiconductor discharge tube, rather than at the PN junction on the surface where the semiconductor discharge tube's reliability is weakest. This realizes the transfer of high-voltage series discharge tube chip breakdown from the surface to the core, thereby improving the chip's reliability.

[0070] This invention also provides a method for fabricating a semiconductor discharge tube, which is used to form the semiconductor discharge tube in any embodiment of this invention. Figure 6 A flowchart illustrating a method for fabricating a semiconductor discharge tube according to an embodiment of the present invention is shown below. Figure 6 As shown, the method for manufacturing a semiconductor discharge tube includes: S110. Etch the corresponding regions of the P+ region on both sides of the N-type substrate and deposit to form the P+ region.

[0071] Specifically, the N-type substrate 110 silicon wafer undergoes chemical polishing to thin it, and the silicon wafer surface is etched to form unit cells; according to V DRMSelect the corresponding resistivity range, such as 100~1000V, corresponding to a resistivity of 0.5~50Ω·cm. Perform ultrasonic cleaning for 20 min, followed by SC1+SC2 cleaning for 10 min each, and then spin dry. Then, grow a silicon dioxide layer 111 with a thickness of 13000±2000Å using high-temperature oxidation. That is, the N-type substrate 110 has undergone the treatment described in steps 1.1-1.3 above. Next, deposit the P+ region 122. Specifically, the P+ region 122 can be formed using photolithography. Coat both sides of the N-type substrate 110 silicon wafer with photoresist, and etch the P+ region 122 using exposure, development, and wet etching. Its area accounts for 20%~35% of the entire chip area. Then, acceptor element pre-deposition is performed in the P+ region 122 at a temperature of 1050–1150℃ for 30–90 min, forming acceptor pre-deposition layers on both sides of the semiconductor discharge tube chip. Taking boron as an example, its sheet resistance is 4–10 ohm / sq. After pre-deposition, the borosilicate glass on the silicon wafer surface is rinsed with BOE acid, and steps 1.2 are repeated. The N-type substrate 110 silicon wafer with completed acceptor element pre-deposition is then subjected to high-temperature redistribution of the P+ region 122 at 1270℃ for 25–40 h, forming P+N junctions on both sides of the N-type substrate 110 silicon wafer, with a junction depth of 60–80 μm. Simultaneously, a silicon dioxide layer 111 with a thickness of 12000 ± 2000 Å is grown on the chip surface through high-temperature oxidation via hydrogen-oxygen synthesis.

[0072] S120: Etch the corresponding regions of the P-regions on both sides of the N-type substrate and deposit to form P-regions.

[0073] Among them, P-region 121 is a diffused P-type acceptor trivalent element, such as boron, aluminum, gallium and other impurities. The pre-deposited sheet resistance is 15 to 25 ohm / sq, the junction depth is 30 to 40 μm, and the area accounts for 60% to 70% of the chip area of ​​the entire semiconductor discharge tube.

[0074] Specifically, photolithography can be used to etch P-regions 121 on both sides of an N-type substrate 110 silicon wafer, followed by acceptor pre-deposition and redistribution in P-regions 121. This involves: applying photoresist to both sides of the N-type substrate 110 silicon wafer using photolithography; etching P-regions 121, covering 60%–70% of the entire chip area, through exposure, development, and wet etching. Step 1.2 is repeated. Then, acceptor pre-deposition is performed in P-regions 121 at a temperature of 900–1050℃ for 30–90 minutes, forming acceptor pre-deposition layers on both sides of the chip. For example, boron has a sheet resistance of 15–25 ohms / sq. After pre-deposition, the borosilicate glass on the silicon wafer surface is rinsed with BOE acid, and step 1.2 is repeated. The N-type substrate 110 silicon wafer, after acceptor element pre-deposition, undergoes high-temperature redistribution of the P-region 121 at 1270℃ for 20–30 hours, forming PN junctions on both sides of the chip. The depth of the P-region 121 junction is 30–40 μm. Simultaneously, a silicon dioxide layer 111 with a thickness of 12000 ± 2000 Å is grown on the chip surface through high-temperature oxidation via hydrogen-oxygen synthesis.

[0075] S130. Etch the corresponding regions of the P++ region on both sides of the N-type substrate and deposit the P++ region. The junction depths of the P-, P+ and P++ regions in the N-type substrate are different. The doping concentration of the P- region is less than that of the P+ region, and the doping concentration of the P+ region is less than that of the P++ region.

[0076] Among them, the P++ region 123 is a diffused P-type acceptor trivalent element, such as boron, aluminum, gallium and other impurities. The pre-deposited sheet resistance is 8 to 15 ohm / sq, the junction depth is 25 to 35 μm, and the area accounts for 10% to 25% of the total chip area. The P+ region 122 and the P++ region 123 are located on both sides of the same side of the N-type substrate 110.

[0077] Specifically, by employing photolithography, P++ regions 123 can be etched on both sides of an N-type substrate 110 silicon wafer, and acceptor element pre-deposition and redistribution can be performed in P++ regions 123. This includes: applying photoresist to both sides of the N-type substrate 110 silicon wafer using photolithography; etching the P++ regions 123, covering 10%–25% of the total chip area, through exposure, development, and wet etching. Step 1.2 is repeated. Acceptor element pre-deposition is performed in P++ regions 123 at a temperature of 1000–1100℃ for 30–90 minutes; acceptor pre-deposition layers are formed on both sides of the chip; taking boron as an example, its sheet resistance is 8–15 ohms / sq. After pre-deposition, the borosilicate glass on the silicon wafer surface is rinsed with BOE acid, and step 1.2 is repeated. The N-type substrate 110 silicon wafer, after acceptor element pre-deposition, undergoes high-temperature redistribution of the P++ region 123 at 1250℃ for 10–20 hours, forming PN junctions on both sides of the chip. The depth of the P++ region 123 junction is 25–35 μm. Simultaneously, a silicon dioxide layer 111 with a thickness of 12000 ± 1000 Å is grown on the chip surface through high-temperature oxidation via hydrogen-oxygen synthesis.

[0078] The P-type regions 120 located on both sides of the N-type substrate 110 each include P-region 121, P+region 122, and P++region 123 with different doping concentrations. The junction depths of P-region 121, P+region 122, and P++region 123 in the N-type substrate 110 are all different. P-region 121, P+region 122, and P++region 123 are all adjacent to the N-type substrate 110. P+region 122 and P++region 123 are spaced apart. P-region 121 is located between adjacent P++region 123 and between adjacent P+region 122 and P++region 123. P-region 121 surrounds P+region 122 and P++region 123. When a reverse voltage is applied to the high-voltage semiconductor discharge tube, breakdown will preferentially occur at the location of the bulk P++N junction, rather than at the surface PN junction where reliability is weakest. This effectively transfers the breakdown location of the high-voltage semiconductor discharge tube from the surface to the bulk, improving the reliability of the semiconductor discharge tube.

[0079] Figure 7 A flowchart illustrating another method for fabricating a semiconductor discharge tube according to an embodiment of the present invention is shown below. Figure 7 As shown, the method for manufacturing a semiconductor discharge tube includes: S210. Etch the corresponding regions of the P+ region on both sides of the N-type substrate and deposit to form the P+ region.

[0080] S220: Etch the corresponding regions of the P-regions on both sides of the N-type substrate and deposit to form the P-regions.

[0081] S230. Etch the corresponding regions of the P++ region on both sides of the N-type substrate and deposit the P++ region. The junction depths of the P-, P+ and P++ regions in the N-type substrate are different. The doping concentration of the P- region is less than that of the P+ region, and the doping concentration of the P+ region is less than that of the P++ region.

[0082] S240. Multiple uniformly distributed N+ regions are etched and deposited on the side of the P++ region away from the N-type substrate. The doping concentration of the N+ regions is greater than that of the N-type substrate.

[0083] The N+ region 130, when projected vertically onto the N-type substrate 110, occupies 40% to 50% of the surface area of ​​the N-type substrate. The junction depth of the N+ region 130 in the P++ region 123 is 10 μm to 15 μm. A short-circuit via 131, with a diameter of 50 μm to 120 μm, is provided in the N+ region 130.

[0084] Specifically, N+ regions 130 are etched on both sides of an N-type substrate 110 silicon wafer using photolithography. Donor element pre-deposition and redistribution are performed in N+ regions 130. Specifically, photoresist is coated on both sides of an N-type substrate 110 silicon wafer using photolithography, and N+ regions 130 are etched by exposure, development, and wet etching, with the area accounting for 40% to 50% of the entire chip area. Step 1.2 is repeated. Donor element pre-deposition is performed in N+ regions (5): the temperature is 1000 to 1100°C, and the time is 30 to 90 minutes. Donor pre-deposition layers are formed on both sides of the chip. Taking phosphorus as an example, its sheet resistance is 1 to 5 ohms / sq. After pre-deposition, the phosphorus-silicon glass on the surface of the silicon wafer is rinsed with BOE acid, and step 1.2 is repeated. The N-type substrate 110 silicon wafer, after donor element pre-deposition, undergoes high-temperature redistribution of the N+ region 130 at 1150–1200 °C for 150–400 min, forming PN junctions on both sides of the chip. The junction depth of the N+ region is 10–15 μm. Simultaneously, a silicon dioxide layer 111 with a thickness of 5000 ± 1000 Å is grown on the chip surface through high-temperature oxidation via hydrogen-oxygen synthesis.

[0085] After forming the N+ region 130, passivation and surface shaping steps are required, specifically including: 2.1 For discharge transistor chips with glass passivated mesa structures, such as Figure 1 and Figure 3 As shown, following step S240 above: 2.1.1 Photoresist is coated on both sides of an N-type substrate 110. Trench lines are etched on both sides by exposure, development, and wet etching. The line width is 200-300um.

[0086] 2.1.2 Trenches were etched on both sides of the wafer using wet etching; the temperature was 0–10℃, and the etching time was 300–500 seconds. The trench depth was 50–70 μm.

[0087] 2.1.3 The N-type substrate 110 after trench etching was ultrasonically cleaned for 20 min and SC1+SC2 cleaned for 10 min each, and then spun dry.

[0088] 2.1.4 Fill the double-sided trenches of the N-type substrate 110 with glass slurry and bake on a hot plate at 130-140℃. Then perform high-temperature sintering to crystallize the glass 140 at a temperature of 800-820℃ for 15-25 minutes.

[0089] 2.1.5 Repeat step 2.14 to make the glass 140 in the groove reach the required thickness of 30±10um.

[0090] 2.2 For thin-film passivated mesa structure discharge transistor chips, refer to Figure 3 Following step 2.1.3, 2.2.1 SIPOS thin films were grown on N-type substrate 110 silicon wafers by low-pressure vapor deposition.

[0091] 2.2.2 SIN thin films were grown on N-type substrate 110 silicon wafers by low-pressure vapor deposition.

[0092] 2.2.3 LTO thin films were grown on N-type substrate 110 silicon wafers by low-pressure vapor deposition.

[0093] 2.3 For planar discharge tube chips, such as Figure 4 As shown, following step S240: 2.3.1 All silica layers on the surface were removed by wet etching 111.

[0094] 2.3.2 The N-type substrate 110 after the oxide layer was removed was ultrasonically cleaned for 20 min, and then cleaned with SC1+SC2 for 10 min each, and then spun dry.

[0095] 2.3.3 A passivation layer 150 is regrown on the chip surface. This passivation layer may be silicon dioxide, or a multilayer composite insulating passivation layer 150 such as SIPOS, SIN, or LTO.

[0096] 3. Metal electrode 160 formation: 3.1 Using photolithography, lead hole patterns are etched on both sides of the passivated N-type substrate 110 silicon wafer: for mesa-structured semiconductor discharge tube chips, the distance from the lead hole boundary to the trench edge is 30-50 μm; for planar structured semiconductor discharge tube chips, the distance from the lead hole boundary to the surface P-N+ junction is 50-70 μm.

[0097] 3.2 Use BOE or mixed acid to remove the silicon dioxide layer 111 or the multilayer composite insulating passivation film 140 in the lead hole pattern.

[0098] 3.3 Perform ultrasonic cleaning for 20 min and SC1+SC2 cleaning for 10 min each on the N-type substrate 110 silicon wafer after the lead hole etching is completed, and then spin dry.

[0099] 3.4 The cleaned N-type substrate 110 silicon wafer is fitted with double-sided metal electrodes 160, which can be completed by chemical plating, or by evaporation and deposition processes.

[0100] This invention provides a method for fabricating a semiconductor discharge tube, relating to a power semiconductor overvoltage protection discharge tube chip structure. By setting multiple P-type regions of different concentrations and junction depths on both sides of the N-type substrate of the semiconductor discharge tube, with the P+ and P++ regions surrounded by the P- region, the high and low concentration P-type regions are arranged alternately. When a reverse voltage is applied, breakdown preferentially occurs at the P++N junction within the semiconductor discharge tube, rather than at the PN junction on the surface where the semiconductor discharge tube's reliability is weakest. This achieves the transfer of high-voltage series discharge tube chip breakdown from the surface to the core, thereby improving the chip's reliability.

[0101] The embodiments described above are merely examples of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, such as the shape and size of the P++ region in the present invention; these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

[0102] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A semiconductor discharge tube, characterized in that, The semiconductor discharge tube includes an N-type substrate and P-type regions located on both sides of the N-type substrate; The P-type regions located on both sides of the N-type substrate each include P-, P+, and P++ regions with different doping concentrations, and the junction depths of the P-, P+, and P++ regions in the N-type substrate are all different. The P- region, the P+ region, and the P++ region are all disposed adjacent to the N-type substrate. The P+ region and the P++ region are disposed at a distance. The P- region is located between adjacent P++ regions and between adjacent P+ regions and P++ regions, and the P- region surrounds the P+ region and the P++ region. The doping concentration of the P- region is less than that of the P+ region, and the doping concentration of the P+ region is less than that of the P++ region.

2. The semiconductor discharge tube according to claim 1, characterized in that, In the P-type region on the same side of the N-type substrate, the P+ region and the P++ region are located on opposite sides of the side of the N-type substrate, respectively. The P++ region includes multiple spaced-apart third P sub-regions, which are uniformly distributed on one side of the N-type substrate.

3. The semiconductor discharge tube according to claim 2, characterized in that, In the P-type region on the same side of the N-type substrate, the contact area between the P- region and the N-type substrate accounts for 60% to 70% of the surface area of ​​the N-type substrate, the contact area between the P+ region and the N-type substrate accounts for 20% to 35% of the surface area of ​​the N-type substrate, and the contact area between the P++ region and the N-type substrate accounts for 10% to 25% of the surface area of ​​the N-type substrate.

4. The semiconductor discharge tube according to claim 2, characterized in that, The shape of the vertical projection of the third P subregion onto the N-type substrate includes a rectangle, a circle, a triangle, or a star shape.

5. The semiconductor discharge tube according to any one of claims 1, characterized in that, The junction depth of the P+ region is greater than that of the P- region, and the junction depth of the P- region is greater than that of the P++ region.

6. The semiconductor discharge tube according to claim 5, characterized in that, The junction depth of the P- region is 30um to 40um, the junction depth of the P+ region is 60um to 80um, and the junction depth of the P++ region is 25um to 35um.

7. The semiconductor discharge tube according to claim 1, characterized in that, The P++ region has multiple uniformly distributed N+ regions on the side away from the N-type substrate, and the doping concentration of the N+ regions is greater than that of the N-type substrate. The vertical projection of the N+ region onto the N-type substrate occupies 40% to 50% of the surface area of ​​the N-type substrate, and the junction depth of the N+ region in the P++ region is 10 μm to 15 μm.

8. The semiconductor discharge tube according to claim 7, characterized in that, The N+ region is provided with a short-circuit hole that penetrates the N+ region, and the P++ region is filled in the short-circuit hole. The diameter of the short-circuit hole is 50um-120um.

9. A method for manufacturing a semiconductor discharge tube, characterized in that, The method for manufacturing the semiconductor discharge tube is used to form the semiconductor discharge tube according to any one of claims 1-8, comprising: The corresponding regions of the P+ region are etched on the surfaces on both sides of the N-type substrate, and the P+ region is deposited to form the P+ region. The corresponding regions of the P-regions are etched on the surfaces on both sides of the N-type substrate, and the P-regions are deposited to form them. The corresponding regions of the P++ region are etched on the surfaces on both sides of the N-type substrate, and the P++ region is deposited to form the P++ region; wherein the junction depths of the P- region, the P+ region and the P++ region in the N-type substrate are different, the doping concentration of the P- region is less than the doping concentration of the P+ region, and the doping concentration of the P+ region is less than the doping concentration of the P++ region.

10. The method for manufacturing a semiconductor discharge tube according to claim 8, characterized in that, After forming the P++ region, the following is also included: Multiple uniformly distributed N+ regions are etched and deposited on the side of the P++ region away from the N-type substrate, and the doping concentration of the N+ regions is greater than that of the N-type substrate.

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