Metal gate FDSOI device and method of fabrication

Abstract

The application provides a metal gate FDSOI device and a manufacturing method. The metal gate structure and the HiR layer are connected in parallel, the characteristics of resistance parallel connection are used to reduce the gate resistance, the improvement degree of the reduced channel length on the maximum oscillation frequency of the device is improved, and the RF performance is improved. In addition, the size of the HiR layer is expanded, the HiR resistance is reduced, the parallel resistance is further reduced, and the device performance is improved. Moreover, no new mask is added, and the existing process is compatible.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a metal gate FDSOI device and its fabrication method. Background Technology

[0002] FDSOI (Fully Depletion Silicon On Insulator) devices use a very thin semiconductor film to create the transistor channel on the buried oxide layer. Because the channel is so thin, there is no need to perform a doping process on the channel. The depletion layer fills the entire channel region, which is a fully depletion transistor.

[0003] The buried oxide layer in FDSOI devices reduces parasitic capacitance between the source and drain and effectively suppresses electron flow from the source to the drain, thus significantly reducing leakage current that leads to performance degradation. Furthermore, FDSOI devices possess many other unique advantages, such as back-bias capability, excellent transistor matching characteristics, the ability to operate at near-threshold low supply voltages, ultra-low sensitivity to radiation, and very high intrinsic transistor operating speeds. These advantages enable them to operate in millimeter-wave applications. For RF performance, parameters such as cutoff frequency (Ft) and maximum oscillation frequency (Fmax) are typically important, and many factors influence these parameters, including device transconductance, inversion layer capacitance, and gate resistance. To achieve higher transconductance and lower inversion layer capacitance, a smaller gate length is usually designed, which can improve Ft. Additionally, since the gate in RF devices is used as a low-resistance conductor, reducing the gate resistance is desirable to increase Fmax.

[0004] like Figure 1 The diagram shows a single-ended metal gate. The metal gate 01 has a source region 02 and a drain region 03 on either side, and a metal layer 04 is connected to one end of the metal gate 01. Figure 2 The diagram shows a schematic of a metal gate with leads at both ends. Leading out the two ends of metal layer 04 and metal gate 01 reduces gate resistance. Taking four metal gates as an example, the resistance of the metal gate with leads at both ends can be reduced to 1 / 4 of the original resistance. Combined with the reduction in gate length, this improves Fmax. Please refer to [reference needed]. Figure 3 The graph shows the relationship between Ft and Fmax and the device channel length in an N-type device with a metal gate connected at both ends. Ft and Fmax increase as the device channel length (gate length) decreases, but the increase in Fmax is slower. Although connecting the two ends of the metal gate can reduce resistance, and the reduced gate length further lowers resistance and can increase Fmax, the increase in Fmax is limited and cannot meet the requirements of high-performance RF. Increasing the gate thickness can further reduce resistance, but this leads to an increase in the gate coupling capacitance, which is detrimental to improving Fmax. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a metal gate FDSOI device and its fabrication method to solve the problem that the Fmax increase is limited in the prior art and cannot meet the high RT performance requirements.

[0006] To achieve the above and other related objectives, the present invention provides a metal gate FDSOI device, comprising:

[0007] SOI substrate, the SOI substrate comprising a bottom substrate layer, a middle buried insulating layer and a top semiconductor layer;

[0008] A metal gate structure is located on the SOI substrate, wherein the top semiconductor layer covered by the metal gate structure forms a channel region, and the two sides of the channel region are the source region and the drain region, respectively;

[0009] An insulating layer is located above the SOI substrate, and the insulating layer covers the metal gate structure;

[0010] The HiR layer, located above the insulating layer, has a length less than the length of the metal gate structure in a direction perpendicular to the source region and pointing towards the drain region.

[0011] A dielectric layer, located above the insulating layer and covering the HiR layer, has a shared contact hole at both ends of the HiR layer in a direction perpendicular to the source region and pointing to the drain region. The shared contact hole exposes the ends of the HiR layer and the metal gate structure.

[0012] A conductive interconnect structure is located in the shared contact hole, which connects the HiR layer and the metal gate structure in parallel.

[0013] Optionally, it also includes:

[0014] A source contact hole penetrates the dielectric layer and the insulating layer, and a source metal layer fills the source contact hole and is electrically connected to the source region.

[0015] A drain contact hole penetrates the dielectric layer and the insulating layer, and a drain metal layer fills the drain contact hole and is electrically connected to the drain region.

[0016] Optionally, a source lifting layer is formed between the source region and the insulating layer, and the source metal layer is electrically connected to the source region through the source lifting layer;

[0017] A drain lifting layer is formed between the drain region and the insulating layer, and the drain metal layer is electrically connected to the drain region through the drain lifting layer.

[0018] Optionally, the width of the HiR layer is greater than the width of the metal gate structure in the direction from the source region to the drain region.

[0019] Optionally, the HiR layer is a TiN layer.

[0020] This invention also provides a method for fabricating a metal gate FDSOI device, comprising the following steps:

[0021] An SOI substrate is provided, the SOI substrate comprising a bottom substrate layer, a middle buried insulating layer, and a top semiconductor layer;

[0022] A metal gate structure is formed on the SOI substrate, wherein the top semiconductor layer covered by the metal gate structure forms a channel region, and the two sides of the channel region are the source region and the drain region, respectively.

[0023] An insulating layer is formed on the SOI substrate, the insulating layer covering the metal gate structure;

[0024] A HiR layer is formed on the insulating layer, and the length of the HiR layer is less than the length of the metal gate structure in the direction perpendicular to the source region to the drain region.

[0025] A dielectric layer covering the HiR layer is formed on the insulating layer. In a direction perpendicular to the source region and pointing to the drain region, a shared contact hole is formed at both ends of the HiR layer. The shared contact hole exposes the ends of the HiR layer and exposes the metal gate structure.

[0026] A conductive layer is filled into the shared contact hole to form a conductive interconnect structure, which connects the HiR layer and the metal gate structure in parallel.

[0027] Optionally, it further includes forming a source metal layer and a drain metal layer, wherein the source metal layer penetrates the dielectric layer and the insulating layer to be electrically connected to the source region, and the drain metal layer penetrates the dielectric layer and the insulating layer to be electrically connected to the drain region.

[0028] Optionally, before forming the insulating layer, the method further includes forming a source lift layer and a drain lift layer, wherein the source lift layer is located above the source region and the drain lift layer is located above the drain region, wherein the source metal layer is electrically connected to the source region through the source lift layer and the drain metal layer is electrically connected to the drain region through the drain lift layer.

[0029] Optionally, the width of the HiR layer is greater than the width of the metal gate structure in the direction from the source region to the drain region.

[0030] Optionally, the HiR layer is a TiN layer.

[0031] As described above, in the metal gate FDSOI device and fabrication method of the present invention, the metal gate structure and the HiR layer are connected in parallel. The gate resistance is reduced by utilizing the characteristics of parallel resistance, thereby improving the degree of improvement of the maximum oscillation frequency of the device by reducing the channel length and improving RF performance. In addition, by increasing the size of the HiR layer, the HiR resistance can be reduced, further reducing the parallel resistance and improving device performance. Moreover, no new mask is added, and it is compatible with existing processes. Attached Figure Description

[0032] Figure 1 The diagram shows a single-ended metal gate.

[0033] Figure 2 The diagram shows a metal gate with leads at both ends.

[0034] Figure 3 The graph shows the relationship between Ft and Fmax and the device channel length in a device (N-type) with a metal gate led out at both ends.

[0035] Figure 4 The image shown is a top view of the metal gate FDSOI device in Embodiment 1 of the present invention.

[0036] Figure 5 Displayed as Figure 4 Enlarged view of the dashed area.

[0037] Figure 6 Displayed as Figure 5 A cross-sectional view along the AA' direction.

[0038] Figure 7 Displayed as Figure 5 A cross-sectional view along the BB' direction.

[0039] Figure 8 The diagram shows the relationship between the width of the HiR layer and the sheet resistance in Embodiment 1 of the present invention.

[0040] Figure 9 This diagram illustrates how a source lift-up layer and a drain lift-up layer are set to expand the width of the HiR layer in Embodiment 1 of the present invention.

[0041] Figure 10 The diagram shown is a comparative example without source and drain lift layers.

[0042] Figure 11 The diagram shows a flowchart of the fabrication method of the metal gate FDSOI device in Embodiment 2 of the present invention.

[0043] Component designation explanation

[0044] 01 Metal gate

[0045] 02 Source Region

[0046] 03 Leakage Area

[0047] 04. Lead out the metal layer

[0048] 1 SOI substrate

[0049] 100 Bottom Substrate

[0050] 101 Middle Insulation Buried Layer

[0051] 102 Top Semiconductor Layer

[0052] 2. Metal grid structure

[0053] 3. Ditch area

[0054] 4 source regions

[0055] 5. Leakage Area

[0056] 6 Insulation layer

[0057] 7 HiR layers

[0058] 8. Dielectric layer

[0059] 9. Conductive interconnect structure

[0060] 10 Source Metal Layer

[0061] 11 Drain metal layer

[0062] 12 Source Uplift Layer

[0063] 13 Drain Lift Layer

[0064] 14. Lead out the metal layer

[0065] Steps S1 to S6 Detailed Implementation

[0066] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0067] Please see Figures 4 to 11It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0068] Example 1

[0069] This embodiment provides a metal gate FDSOI device. Please refer to [link / reference]. Figures 4 to 7 The metal-gate FDSOI device includes an SOI substrate 1, a metal gate structure 2, an insulating layer 6, a HiR layer 7, a dielectric layer 8, and a conductive interconnect structure 9. The SOI substrate 1 includes a bottom substrate layer 100, a middle buried insulating layer 101, and a top semiconductor layer 102. The metal gate structure 2 is located on the SOI substrate 1, and the top semiconductor layer 102, covered by the metal gate structure 2, forms a channel region 3. The two sides of the channel region 3 are a source region 4 and a drain region 5, respectively. The insulating layer 6 is located above the SOI substrate 1 and covers the metal gate structure 2. The HiR layer 9... Layer 7 is located above the insulating layer 6. In the direction perpendicular to the source region 4 and pointing to the drain region 5, the length of the HiR layer 7 is less than the length of the metal gate structure 2. The dielectric layer 8 is located above the insulating layer 6 and covers the HiR layer 7. In the direction perpendicular to the source region 4 and pointing to the drain region 5, both ends of the HiR layer 7 are provided with shared contact holes. The shared contact holes expose the ends of the HiR layer 7 and the metal gate structure 2. The conductive interconnect structure 9 is located in the shared contact holes and connects the HiR layer 7 and the metal gate structure 2 in parallel.

[0070] As an example, in the SOI substrate 1, the bottom substrate layer 100 is a silicon layer, the middle insulating buried layer 101 is a silicon oxide layer (BOX), and the top semiconductor layer 102 is a silicon layer.

[0071] As an example, the metal gate structure 2 includes a stacked gate dielectric layer and a gate metal layer, wherein the gate dielectric layer may be a high-k dielectric layer such as an HfO2 layer, and the gate metal layer may be an Al layer.

[0072] As an example, the insulating layer 6 is used to insulate and isolate the metal gate structure 2 and the HiR layer 7. In this embodiment, the insulating layer 6 is a silicon oxide layer.

[0073] As an example, the HiR layer 7 is a high resistance layer. In this embodiment, the HiR layer 7 is a TiN layer.

[0074] As an example, the dielectric layer 8 is an interlayer dielectric layer. In this embodiment, the dielectric layer 8 is a silicon oxide layer.

[0075] As an example, in a direction perpendicular to the source region 4 and pointing to the drain region 5, the shared contact hole is disposed at both ends of the HiR layer 7. The shared contact hole penetrates the dielectric layer 8 and the insulating layer 6. The shared contact hole exposes the end of the HiR layer 7 and the metal gate structure 2. A metal layer is filled in the shared contact hole to form the conductive interconnect structure 9. The conductive interconnect structure 9 connects the HiR layer 7 and the metal gate structure 2 in parallel.

[0076] As an example, by connecting the HiR layer 7 and the metal gate structure 2 in parallel, the gate resistance is reduced by utilizing the characteristics of parallel resistance.

[0077] For example, please refer to Figure 8 The width of the HiR layer 7 is inversely proportional to the unit sheet resistance. In this embodiment, the width of the HiR layer 7 is greater than the width of the metal gate structure 2 in the direction from the source region 4 to the drain region 5. By increasing the width of the HiR layer 7, the resistance is reduced, thereby reducing the parallel resistance.

[0078] As an example, it also includes a source contact hole and a drain contact hole, wherein the source contact hole penetrates the dielectric layer 8 and the insulating layer 6, and the source metal layer 10 is filled into the source contact hole and electrically connected to the source region 4; the drain contact hole penetrates the dielectric layer 8 and the insulating layer 6, and the drain metal layer 11 is filled into the drain contact hole and electrically connected to the drain region 5.

[0079] As an example, a source lifting layer 12 is formed between the source region 4 and the insulating layer 6, and the source metal layer 10 is electrically connected to the source region 4 through the source lifting layer 12; a drain lifting layer 13 is formed between the drain region 5 and the insulating layer 6, and the drain metal layer 11 is electrically connected to the drain region 5 through the drain lifting layer 13, wherein the source lifting layer 12 and the drain lifting layer 13 have the same doping type as the source region 4 and the drain region 5.

[0080] As an example, by providing the source lift layer 12 and the drain lift layer 13, the contact resistance between the source and drain can be reduced. Since the top semiconductor layer 102 in the SOI substrate 1 is very thin, it is impossible to form a low-resistance, insoluble silicide. By providing the source lift layer 12 and the drain lift layer 13, the thickness is increased, allowing the formation of a low-resistance, insoluble silicide layer, thus reducing the contact resistance between the source and drain. Furthermore, by providing the source lift layer 12 and the drain lift layer 13, the width of the HiR layer 7 can be further increased. Please refer to [link to relevant documentation]. Figure 9 andFigure 10 At the same bottom of the contact hole (a=a'), when the source elevation layer 12 and the drain elevation layer 13 are provided, the height of the contact hole can be reduced (h'<h), thereby increasing the distance between the contact holes (b'>b). In the case of maintaining the same distance from the contact hole to the HiR layer 7 (s=s'), the width of the HiR layer 7 can be increased (c'>c), further reducing the parallel resistance.

[0081] As an example, the semiconductor device further includes an extraction metal layer 14, which is connected to both ends of the metal gate structure 2. By leading out the metal gate structure 2 from both ends, the gate resistance is reduced.

[0082] As an example, please refer to Table 1 below. When the channel length of the device is reduced, the transconductance (Gm) increases, and the inversion layer capacitance (Cinv) decreases. When there is no parallel HiR layer, the gate resistance (Rgate) is reduced to a small extent, and the cutoff frequency (Ft) and maximum oscillation frequency (Fmax) increase to a limited extent; when the HiR layer is connected in parallel, the gate resistance (Rgate) is further reduced, that is, the reduction degree of Rgate is increased, and Ft and Fmax can be improved to a relatively large extent, meeting high-performance requirements.

[0083] Table 1:

[0084] Class Length Gm Cinv Rgate Ft Fmax Gate un-parallel HiR layer Down Up Down Down Up Up Gate parallel HiR layer Down Up Down Down+ Up+ Up+

[0085] As an example, please refer to Table 2 below, taking an N-type device as an example. When no HiR layer is connected in parallel, the resistance value of the metal gate (MG) with a width of 0.1μm and an effective resistance length of 2μm is 2000 ohm, and the resistance value of the metal gate with a width of 0.02μm and an effective resistance length of 2μm is 812 ohm; when the HiR layer is connected in parallel, the estimated resistance value after parallel connection of the metal gate with a width of 0.1μm and an effective resistance length of 2μm and the HiR layer with a width of 0.1μm and an effective resistance length of 2μm is 1729 ohm, the resistance value is reduced by about 13%, the estimated resistance value after parallel connection of the metal gate with a width of 0.02μm and an effective resistance length of 2μm and the HiR layer with a width of 0.1μm and an effective resistance length of 2μm is 760 ohm, the resistance value is reduced by about 6%, that is, the metal gate and the HiR resistor are connected in parallel, the gate resistance after parallel connection is reduced, which can improve the RF performance of the device.

[0086] Table 2:

[0087]

[0088] As described above, in the metal gate FDSOI device of this embodiment, the metal gate structure and the HiR layer are connected in parallel. The gate resistance is reduced by utilizing the characteristics of parallel resistance, thereby improving the degree of improvement of the maximum oscillation frequency of the device by reducing the channel length and improving RF performance. In addition, by increasing the size of the HiR layer, the HiR resistance can be reduced, further reducing the parallel resistance and improving device performance.

[0089] Example 2

[0090] This embodiment provides a method for fabricating a metal gate FDSOI device. Please refer to [link to relevant documentation]. Figure 11 This includes the following steps:

[0091] S1: Provide an SOI substrate, the SOI substrate comprising a bottom substrate layer, a middle buried insulating layer and a top semiconductor layer;

[0092] S2: A metal gate structure is formed on the SOI substrate, wherein the top semiconductor layer covered by the metal gate structure forms a channel region, and the two sides of the channel region are the source region and the drain region, respectively;

[0093] S3: An insulating layer is formed on the SOI substrate, the insulating layer covering the metal gate structure;

[0094] S4: A HiR layer is formed on the insulating layer, wherein the length of the HiR layer is less than the length of the metal gate structure in the direction perpendicular to the source region and pointing to the drain region;

[0095] S5: A dielectric layer covering the HiR layer is formed on the insulating layer. In a direction perpendicular to the source region and pointing to the drain region, a shared contact hole is formed at both ends of the HiR layer. The shared contact hole exposes the end of the HiR layer and exposes the metal gate structure.

[0096] S6: Fill the shared contact hole with a conductive layer to form a conductive interconnect structure, wherein the conductive interconnect structure connects the HiR layer and the metal gate structure in parallel.

[0097] As an example, the method further includes forming a source metal layer and a drain metal layer, the source metal layer penetrating the dielectric layer and the insulating layer to be electrically connected to the source region, and the drain metal layer penetrating the dielectric layer and the insulating layer to be electrically connected to the drain region.

[0098] As an example, in the direction from the source region to the drain region, the width of the HiR layer is greater than the width of the metal gate structure.

[0099] As an example, before forming the insulating layer, the method further includes forming a source lift layer and a drain lift layer, wherein the source lift layer is located above the source region and the drain lift layer is located above the drain region, wherein the source metal layer is electrically connected to the source region through the source lift layer and the drain metal layer is electrically connected to the drain region through the drain lift layer.

[0100] As an example, the HiR layer is a TiN layer.

[0101] As an example, the method for fabricating the metal gate FDSOI device in this embodiment is used to fabricate the metal gate FDSOI device described in Embodiment 1. The content of Embodiment 1 can be quoted in its entirety here, and will not be repeated below.

[0102] In summary, the metal-gate FDSOI device and fabrication method of the present invention connects the metal gate structure and the HiR layer in parallel, utilizing the characteristics of parallel resistance to reduce the gate resistance, thereby enhancing the improvement of the maximum oscillation frequency of the device by reducing the channel length and improving RF performance. Furthermore, increasing the size of the HiR layer reduces the HiR resistance, further reducing the parallel resistance and improving device performance. Moreover, no additional mask is required, ensuring compatibility with existing processes. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0103] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A metal gate FDSOI device, characterized in that, include: SOI substrate, the SOI substrate comprising a bottom substrate layer, a middle buried insulating layer and a top semiconductor layer; A metal gate structure is located on the SOI substrate, wherein the top semiconductor layer covered by the metal gate structure forms a channel region, and the two sides of the channel region are the source region and the drain region, respectively; An insulating layer is located above the SOI substrate, and the insulating layer covers the metal gate structure; The HiR layer, located above the insulating layer, has a length less than the length of the metal gate structure in a direction perpendicular to the source region and pointing towards the drain region. A dielectric layer, located above the insulating layer and covering the HiR layer, has a shared contact hole at both ends of the HiR layer in a direction perpendicular to the source region and pointing to the drain region. The shared contact hole exposes the ends of the HiR layer and the metal gate structure. A conductive interconnect structure is located in the shared contact hole, which connects the HiR layer and the metal gate structure in parallel.

2. The metal gate FDSOI device according to claim 1, characterized in that, Also includes: A source contact hole penetrates the dielectric layer and the insulating layer, and a source metal layer fills the source contact hole and is electrically connected to the source region. A drain contact hole penetrates the dielectric layer and the insulating layer, and a drain metal layer fills the drain contact hole and is electrically connected to the drain region.

3. The metal gate FDSOI device according to claim 2, characterized in that: A source electrode lifting layer is formed between the source region and the insulating layer, and the source electrode metal layer is electrically connected to the source region through the source electrode lifting layer; A drain lifting layer is formed between the drain region and the insulating layer, and the drain metal layer is electrically connected to the drain region through the drain lifting layer.

4. The metal gate FDSOI device according to claim 1, characterized in that: In the direction from the source region to the drain region, the width of the HiR layer is greater than the width of the metal gate structure.

5. The metal gate FDSOI device according to claim 1, characterized in that: The HiR layer is a TiN layer.

6. A method for fabricating a metal gate FDSOI device, characterized in that, Includes the following steps: An SOI substrate is provided, the SOI substrate comprising a bottom substrate layer, a middle buried insulating layer, and a top semiconductor layer; A metal gate structure is formed on the SOI substrate, wherein the top semiconductor layer covered by the metal gate structure forms a channel region, and the two sides of the channel region are the source region and the drain region, respectively. An insulating layer is formed on the SOI substrate, the insulating layer covering the metal gate structure; A HiR layer is formed on the insulating layer, and the length of the HiR layer is less than the length of the metal gate structure in the direction perpendicular to the source region to the drain region. A dielectric layer covering the HiR layer is formed on the insulating layer. In a direction perpendicular to the source region and pointing to the drain region, a shared contact hole is formed at both ends of the HiR layer. The shared contact hole exposes the ends of the HiR layer and exposes the metal gate structure. A conductive layer is filled into the shared contact hole to form a conductive interconnect structure, which connects the HiR layer and the metal gate structure in parallel.

7. The method for fabricating a metal gate FDSOI device according to claim 6, characterized in that: It also includes forming a source metal layer and a drain metal layer, wherein the source metal layer penetrates the dielectric layer and the insulating layer to be electrically connected to the source region, and the drain metal layer penetrates the dielectric layer and the insulating layer to be electrically connected to the drain region.

8. The method for fabricating a metal gate FDSOI device according to claim 7, characterized in that: Before forming the insulating layer, the process further includes forming a source lift layer and a drain lift layer, wherein the source lift layer is located above the source region and the drain lift layer is located above the drain region, wherein the source metal layer is electrically connected to the source region through the source lift layer and the drain metal layer is electrically connected to the drain region through the drain lift layer.

9. The method for fabricating a metal gate FDSOI device according to claim 6, characterized in that: In the direction from the source region to the drain region, the width of the HiR layer is greater than the width of the metal gate structure.

10. The method for fabricating a metal gate FDSOI device according to claim 6, characterized in that: The HiR layer is a TiN layer.

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