Methods of fabricating jfets using a series of self-aligned processing techniques

Abstract

The present disclosure relates to methods of fabricating JFETs using a series of self-aligned processing techniques. Embodiments disclose a method for fabricating a junction field effect transistor (JFET). The method includes forming a source region adjacent a surface of a semiconductor substrate; forming a spacer from a spacer material over the surface of the semiconductor substrate; and forming a gate region, wherein the gate region is masked by the spacer to define a boundary of a channel region extending vertically from the source region toward a drift region. The method further includes increasing a spacer width of the spacer; etching through the source region and to the gate region using the spacer as a mask; and forming a gate contact region in the gate region.

Description

Technical Field

[0001] This disclosure relates in general to junction field-effect transistors (JFETs), and more particularly to methods for manufacturing JFETs using self-aligned processing techniques. Background Technology

[0002] Power electronics facilitate the conversion and distribution of electricity from power sources to electronic devices and motors. Power conversion circuits are typically located at the core of every electronic power system and can be configured to convert power from its raw, unregulated form and quantity, such as that generated by a power source, into the appropriate regulated form and quantity required by machines, engines, and / or other electronic equipment.

[0003] JFETs can be used in power electronic devices such as switching power converters and inverters. In some applications, JFETs can be formed as discrete components included in an integrated circuit package. A key parameter of a JFET used in power electronics is its on-state resistance (RON). For example, a lower on-state resistance provides a smaller voltage drop for a given current load. Therefore, a lower on-state resistance provides less conduction loss in a system implementing a JFET.

[0004] The inventors of the embodiments of this disclosure have recognized that increasing the number of active cells in a JFET can reduce on-state resistance, but typically at the cost of a larger chip area and higher cost. The inventors of the embodiments of this disclosure have also recognized that typical techniques for improving the area utilization of a JFET are limited by the minimum feature sizes (e.g., for lines, pitch, overlap, etc.) of the lithography processes used to manufacture the JFET. The embodiments of this disclosure can address one or more of these challenges. Attached Figure Description

[0005] A more complete understanding of this embodiment can be obtained by referring to the following description taken in conjunction with the accompanying drawings, in which similar reference numerals indicate similar features.

[0006] Figure 1 A cross-sectional view of a vertical channel JFET according to an embodiment of the present disclosure is illustrated.

[0007] Figures 2A to 2P A series of cross-sectional views are illustrated during the manufacture of a JFET according to an embodiment of the present disclosure.

[0008] Figure 3 An example method for manufacturing a JFET according to an embodiment of this disclosure is illustrated.

[0009] Figure 4 An example method for manufacturing a JFET according to an embodiment of this disclosure is illustrated. Detailed Implementation

[0010] Details of one or more embodiments are set forth in the following description and accompanying drawings. Other features will be apparent from the description, the drawings, and the claims. The disclosed embodiments should not be construed as or otherwise used to limit the scope of this disclosure, including the claims. Furthermore, those skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is intended to be an example of that embodiment and is not intended to imply that the scope of this disclosure, including the claims, is limited to that embodiment.

[0011] Various terms are used to refer to specific system components. Different companies may use different names to refer to a component, and this disclosure is not intended to distinguish between components with different names but the same form and function. In the following discussion and in the claims, the terms "comprising" and "including" are used in an open form, and therefore, these terms should be interpreted as meaning "including but not limited to". Additionally, the term "coupled" is intended to indicate either an indirect connection or a direct connection. Thus, if a first device is coupled to or is coupled to a second device, the connection between the first device and the second device can be achieved through a direct connection or through an indirect connection via other devices and connectors.

[0012] Furthermore, although terms such as “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. Terms such as “first” and “second” may be used only to distinguish one element from another. For example, a first element may be named a second element, and similarly, a second element may be named a first element, without departing from the scope of this disclosure. Moreover, the identification of a “first” element does not necessarily require the presence of a “second” element. As used herein, the term “and / or” includes any and all combinations of one or more of the associated entries listed.

[0013] Figure 1 A cross-sectional view of a JFET 100 according to an embodiment of the present disclosure is illustrated. The JFET 100 may be a planar vertical JFET. For example, as... Figure 1 As shown, the JFET 100 may include a channel region 40 extending vertically between a source region 31 and a drift region 41. The source region 31 may be disposed in a mesa between two dielectric spacers 60. Furthermore, the source region 31 may be coupled to a source contact 30 on a first surface of the semiconductor substrate. The JFET 100 may also include a gate region 22 disposed on the opposite side of the channel region 40. Figure 1As shown, the gate region 22 may include different portions on opposite sides of the channel region. For the purposes of this disclosure, the different portions of the gate region 22 may be collectively referred to as gate region 22. The JFET 100 may also include a gate contact region 21 disposed within the gate region 22 and coupled to the gate contact portion 20. Furthermore, the JFET 100 may include a drift region 41 coupled to the drain contact portion 50 on a second surface of the semiconductor substrate opposite to the first surface on which the source contact portion 30 is formed.

[0014] In some embodiments, each of the source region 31, channel region 40, and drift region 41 may be formed to have a first conductivity type, while the gate contact region 21 and gate region 22 may be formed to have a second conductivity type opposite to the first conductivity type. For example, in an embodiment where JFET 100 is an n-channel JFET, the source region 31, channel region 40, and drift region 41 are n-type regions, while the gate contact region 21 and gate region 22 are p-type regions. And in an embodiment where JFET 100 is a p-channel JFET, the source region 31, channel region 40, and drift region 41 are p-type regions, while the gate contact region 21 and gate region 22 are n-type regions.

[0015] As described in further detail below, a channel region 40 may be formed in the upper portion of the drift region 41. In some embodiments, the channel region 40 may have the same doping type and doping concentration as the drift region 41. In other embodiments, the channel region 40 may have the same doping type as the drift region 41, but with a different doping concentration. For example, the channel region 40 may be more heavily doped than the drift region 41. Furthermore, although Figure 1 The example shows that the depth of the channel region 40 is approximately equal to the depth of the gate region 22, but the depth of the channel region 40 may be greater than or less than the depth of the gate region 22.

[0016] like Figure 1 As shown, the channel region 40 can extend vertically between the portions of the gate region 22. Therefore, the voltage applied to the gate contact region 21 and the gate region 22 relative to the source contact 30 and the source region 31 can be used to modulate the conductivity characteristics of the channel region 40, thereby changing the conductivity of the JFET 100 from the drain to the source. Although Figure 1 Not shown, but in some embodiments, JFET 100 may include an additional current spreading layer below the channel region 40 and gate region 22 and above the drift region 41. Such an additional current spreading layer may be of the same first conductivity type as the channel region 40 and drift region 41, and may have any suitable doping level to extend current carriers to the upper part of the drift region 41.

[0017] In some embodiments, JFET 100 may be a silicon carbide JFET. For example, in some embodiments, each of the gate contact region 21, gate region 22, source region 31, channel region 40, and drift region 41 may be formed in an epitaxial growth layer of silicon carbide. In other embodiments, the lower portion of drift region 41 may further include a low-resistivity substrate region on which the aforementioned epitaxially grown semiconductor material is formed. JFET 100 may also be formed of any other suitable semiconductor material, including but not limited to silicon (Si), gallium nitride (GaN), diamond, and gallium oxide (Ga2O3).

[0018] Gate contact 20 and source contact 30 may be formed of metal or silicide, including, for example, nickel silicide, or any other silicide, metal, metal alloy, or combination thereof, adapted to make ohmic contact with the corresponding gate contact region 21 and source region 31 below gate contact 20 and source contact 30. Furthermore, drain contact 50 may be made of metal or silicide, including, for example, nickel silicide, or any other silicide, metal, metal alloy, or combination thereof, adapted to make ohmic contact with drift region 41. In some embodiments, gate contact 20, source contact 30, and / or drain contact 50 may comprise the same metal, silicide, or combination thereof. In other embodiments, gate contact 20 and source contact 30 may be formed of different metals, silicides, or combinations thereof compared to drain contact 50. Although Figure 1 Although not shown, JFET 100 may include additional metal or metal alloy layers patterned within the interlayer dielectric to couple source contact 30 to the source terminal of JFET 100, gate contact 20 to the gate terminal of JFET 100, and drain contact 50 to the drain terminal of JFET 100, respectively.

[0019] JFET 100 may include multiple JFET cells. These multiple JFET cells may be coupled in parallel with each other and may be relative to each other. Figure 1 The sectional view extends linearly into the page to form a striped layout pattern. For illustrative purposes, Figure 1 A cross-sectional view of three cells of JFET 100 is shown. However, JFET 100 may include any suitable number of cells arranged in parallel with each other. For example, JFET 100 may include 10, 100, 1000, 10000 or more JFET cells arranged in parallel with each other. A larger number of JFET cells increases the number of channel regions 40 through which current can flow, thereby reducing the on-state resistance of JFET 100.

[0020] See below for reference Figures 2A to 2P , Figure 3 and Figure 4As described in detail, the JFET 100 can be formed using a range of self-alignment techniques, thereby providing a more compact size compared to dimensions achievable during semiconductor manufacturing processes using photolithography. In some embodiments, and due to the self-alignment techniques described herein, the JFET 100 may have a channel width 45 of 1 μm or less. For example, the channel region 40 may have a channel width 45 ranging from 0.2 μm to 1 μm. In some examples, the channel region 40 may have a channel width 45 ranging from 0.2 μm to 0.5 μm. Furthermore, in some embodiments, and due to the self-alignment techniques described herein, the JFET 100 may have a cell pitch 70 of 2 μm or less. For example, the JFET 100 may have a cell pitch ranging from 1 μm to 2 μm. By providing, for example, a cell pitch 70 of 2 μm or less, the JFET 100 can include a larger number of cells for a given semiconductor area, thereby providing a lower on-state resistance for a given chip area.

[0021] In addition, please refer to the following: Figure 2H In further detail, the semiconductor substrate can be etched to form a mesa, within which the source region 31 is disposed. Due to the self-alignment technique described herein, the JFET 100 may have a mesa width 75 of 1 μm or less. For example, the JFET 100 may have a mesa width 75 ranging from 0.5 μm to 1 μm. Furthermore, in some embodiments, the JFET 100 may have a mesa depth 76 of 0.3 μm or less. For example, the JFET 100 may have a mesa depth 76 ranging from 0.1 μm to 0.3 μm.

[0022] Furthermore, despite Figure 1Not shown, but JFET 100 may also include termination regions surrounding a plurality of JFET cells forming JFET 100. For example, the termination region may be located on the outer edge of the active region of JFET 100. The termination region may define the outer periphery of the active region in which the plurality of JFET cells are formed. In some embodiments, the termination region may include one or more doped regions (e.g., formed by diffusion or implantation) and / or one or more trench structures to reduce the electric field gradient at geometrically sharp points associated with operation of the JFET device at high voltages. Thus, the termination region may help maintain the breakdown voltage (BV) of the JFET cells close to the maximum BV limited by material properties. For example, the termination region may prevent breakdown below the blocking capability of the plurality of JFET cells, for example, by terminating or gradually reducing the high electric field around the device during off-state operation of JFET 100. The termination region or portions thereof may have a second conductivity type opposite to the first conductivity type. For example, in embodiments where source region 31, channel region 40, and drift region 41 are n-type regions, the termination region may be a p-type region. Furthermore, in an implementation where the source region 31, channel region 40, and drift region 41 are p-type regions, the termination region can be an n-type region.

[0023] Figures 2A to 2P A series of cross-sectional views are illustrated during the manufacture of JFET 100 according to an embodiment of the present disclosure.

[0024] like Figure 2A As shown, a semiconductor substrate including a drift region 41 can be provided. In some embodiments, the upper portion of the drift region 41 forming the channel region 40 can be formed by epitaxial growth on a substrate forming the lower portion of the drift region 41. In such embodiments, the channel region 40 can be doped in situ during epitaxial growth, or the channel region can be doped by subsequent doping after the formation of the channel region 40.

[0025] In some embodiments, further doping of the same conductivity type as drift region 41 and channel region 40 may be added to the upper surface of the semiconductor substrate to form source region 31 adjacent to the upper surface of the semiconductor substrate. Source region 31 may have a higher doping concentration than channel region 40.

[0026] like Figure 2A As shown, a patterned mask 202 can be formed over a semiconductor substrate. For example, the patterned mask 202 can be formed on the upper surface of the semiconductor substrate above the source region 31. The patterned mask 202 may include a mask material such as polysilicon, oxide nitride, or an oxide such as silicon dioxide. In some embodiments, photolithography can be used to form the patterned mask 202.

[0027] Next move to Figure 2B and Figure 2CSpacers 206 can be formed above the upper surface of the semiconductor substrate. For example, such as Figure 2B As shown, spacer material 204 can be conformally deposited over patterned mask 202 and semiconductor substrate. Spacer material 204 can include any suitable material for use as a mask in subsequent processing steps. For example, spacer material 204 can include one or more of polysilicon, oxide nitride, or oxides such as silicon dioxide. In some embodiments, spacer material 204 can be a different material from patterned mask 202, such that patterned mask 202 and spacer material 204 can be individually targeted by subsequent etching processes.

[0028] like Figure 2C As shown, isotropic etching (also known as directional etching) can be applied to remove portions of the spacer material 204. Isotropic etching can be achieved by chemical etching, plasma etching, a combination of chemical and plasma etching, or any other etching process suitable for acting on the spacer material 204. For example, isotropic etching can be configured to act vertically on the spacer material 204 to remove the upper and lower portions of the spacer material 204 that extend horizontally and parallel to the surface of the semiconductor substrate. Isotropic etching of the spacer material 204 can leave spacers 206 vertically oriented relative to the surface of the semiconductor substrate. Figure 2C As shown, spacer 206 may have a first spacer width 207.

[0029] move Figure 2D Another etching process can be applied to remove the patterned mask 202. For example, etching can be performed by chemical etching, plasma etching, a combination of chemical and plasma etching, or any other etching process suitable for acting on and removing the patterned mask 202. In some embodiments, the etching can be configured to have an etching rate for the patterned mask 202 that is, for example, 4, 9, 19, or more times faster than the etching rate for the spacer 206. Therefore, by means of... Figures 2C to 2D The etch shown in the transformation removes the patterned mask 202 while keeping the spacer 206 largely intact at the first spacer width 207.

[0030] Next move to Figure 2E A gate region 22 can be formed in a semiconductor substrate. The gate region 22 can be formed by doping portions of the semiconductor substrate with a conductivity type opposite to that of the drift region 41, channel region 40, and source region 31. Doping of the gate region 22 can be applied by diffusion, ion implantation, or any other suitable doping technique. Figure 2E As shown, the formation of the gate region 22 can be masked by the spacer 206 to define the boundary of the channel region 40, whereby the channel region 40 extends vertically from the source region 31 toward the drift region 41. For example, in situations such as Figure 2EIn the embodiment shown where there is no separate current spread layer between the channel region 40 and the drift region 41, the channel region 40 may extend vertically from the source region 31 to the drift region 41.

[0031] like Figure 2E As shown, the channel region 40 may have a channel width 45 based on the width 207 of the first spacer 206. Therefore, the channel width 45 of the channel region 40 may be 1 μm or less. For example, the channel region 40 may have a channel width 45 in the range of 0.2 μm to 1 μm. In some examples, the channel region 40 may have a channel width 45 in the range of 0.2 μm to 0.5 μm.

[0032] Furthermore, corresponding portions of gate region 22 may be formed at a distance from each other to provide a cell pitch of 2 μm or less. For example, corresponding portions of gate region 22 may be formed at a distance from each other to provide a cell pitch in the range of 1 μm to 2 μm. By providing, for example, a cell pitch of 2 μm or less 70 ( Figure 1 As shown in the diagram, a JFET may include a larger number of cells for a given semiconductor area, thereby providing a lower on-state resistance for a given chip area.

[0033] Next move to Figure 2F and Figure 2G The width of the spacer 206 can be increased. For example, the width of the spacer 206 can be increased or widened from the first spacer width 207 to a second spacer width 217 that is greater than the first spacer width 207. Figure 2F As shown, a second spacer layer 210 can be conformally deposited over spacer material 204 and semiconductor substrate. The second spacer layer 210 may comprise any suitable material to serve as a mask for subsequent processing steps. For example, the second spacer layer 210 may comprise one or more of polysilicon, oxide nitride, or oxides such as silicon dioxide. In some embodiments, the second spacer layer 210 may be formed of the same material as spacer material 204 or a combination of materials.

[0034] like Figure 2GAs shown, isotropic etching can be applied to remove portions of the second spacer layer 210. Isotropic etching can be achieved by chemical etching, plasma etching, a combination of chemical etching and plasma etching, or any other etching process suitable for acting on the second spacer layer 210. For example, isotropic etching can be configured to act vertically on the material of the second spacer layer 210 to remove the upper and lower portions of the second spacer layer 210, which extends horizontally and parallel to the surface of the semiconductor substrate. Isotropic etching of the second spacer layer 210 can leave a portion of the second spacer layer 210 on the sidewalls of the spacer material 204, thereby reducing the spacer width of the spacer 206 from the first spacer width 207 ( Figure 2D and Figure 2E (As shown) Increased to the width of the second spacer 217 ( Figure 2G (As shown).

[0035] Next move to Figure 2H The spacer 206 can be used as a mask to etch the semiconductor substrate. For example, etching can be achieved by chemical etching, plasma etching, a combination of chemical and plasma etching, or any other suitable etching process for etching into the semiconductor substrate. For example, as... Figure 2H As shown, a trench can be formed by using spacer 206 (with a second spacer width 217) as a mask to etch through the source region 31 and reach the gate region 22. In some embodiments, using spacer 206 as a mask to etch through the source region 31 to reach the gate region 22 can form a mesa with a mesa depth 76 of 0.3 μm or less (the remaining portion of the source region 31 is disposed within this mesa). For example, the mesa may have a mesa depth 76 ranging from 0.1 μm to 0.3 μm. The mesa may also have a mesa width 75 of 1 μm or less. For example, the mesa may have a mesa width 75 ranging from 0.5 μm to 1 μm.

[0036] Next move to Figure 2I and Figure 2J The width of the spacer 206 can be further increased or widened. For example, the width of the spacer 206 can be increased or widened from the second spacer width 217 to a third spacer width 227 that is greater than the second spacer width 217. Figure 2I As shown, an additional spacer layer 220 can be conformally deposited over spacer material 204, second spacer layer 210, and semiconductor substrate. The additional spacer layer 220 may comprise any suitable material to serve as a mask for subsequent processing steps. For example, the additional spacer layer 220 may comprise one or more of polysilicon, oxide nitride, or oxides such as silicon dioxide. In some embodiments, the additional spacer layer 220 may be formed of the same material or a combination of materials as spacer material 204 and / or second spacer layer 210.

[0037] like Figure 2J As shown, isotropic etching can be applied to remove portions of the additional spacer layer 220. Isotropic etching can be achieved by chemical etching, plasma etching, a combination of chemical etching and plasma etching, or any other etching process suitable for acting on the additional spacer layer 220. For example, isotropic etching can be configured to act vertically on the material of the additional spacer layer 220 to remove the upper and lower portions of the additional spacer layer 220, which extends horizontally and parallel to the surface of the semiconductor substrate. Isotropic etching of the additional spacer layer 220 can leave a portion of the additional spacer layer 220 on the sidewall of the second spacer layer 210, thereby reducing the spacer width of the spacer 206 from the second spacer width 217 ( Figure 2G and Figure 2H (As shown) Increased to the width of the third spacer 227 ( Figure 2J (As shown).

[0038] Next move to Figure 2K The spacer 206 can be used as a mask to form the gate contact region 21 in the gate region 22. The gate contact region 21 can be formed by doping portions of the gate region 22 with a higher doping concentration of the same conductivity type as the gate region 22. Doping of the gate contact region 21 can be applied by diffusion, ion implantation, or any other suitable doping technique. In some embodiments, a higher doping concentration of the gate contact region 21 can help facilitate the formation of a low-resistance gate contact portion 20 coupled to the gate contact region 21, as described below. Figure 2O and Figure 2P Further detailed description.

[0039] like Figure 2K As shown, the formation of the gate contact region 21 can be masked by the spacer 206. An additional spacer layer 220 of the spacer 206 protects the source region 31 from doping used to form the gate contact region 21. In some embodiments, the doping concentration of the source region 31 (of a first conductivity type) can be significantly higher than the doping concentration of the gate contact region 21 (of a second conductivity type). In such embodiments, the higher doping concentration of the first conductivity type for the source region 31 can dominate even when exposed to doping of the second conductivity type for the gate contact region 21. Therefore, in such embodiments, the doping concentration of the gate contact region 21 can optionally be omitted. Figure 2I and Figure 2J The illustrated processing steps involve adding an additional spacer layer 220.

[0040] Next move to Figure 2LThe spacer 206 can be removed. For example, spacer material 204, a second spacer layer 210, and / or an additional spacer layer 220 can be applied as etching targets to remove the spacer 206 from the upper surface of the semiconductor substrate. After the spacer 206 is removed, the device can be added. Figure 2L Other features not shown. For example, a termination region may be formed on the outer periphery of the active region in which multiple JFET cells may be formed. Figure 2L (Not shown in the image). In some embodiments, the termination region may include one or more doped regions (e.g., formed by diffusion or implantation) and / or one or more trench structures to reduce the electric field gradient at geometrically sharp points associated with the operation of the JFET device at high voltages. Furthermore, high-temperature activation (HTA) and / or driven diffusion may be performed to activate the implanted impurities, including dopants applied to form the termination region directly described above, and / or implanted impurities applied to form the gate region 22 and the gate contact region 21, as referenced above. Figure 2E and Figure 2K As described.

[0041] Next move to Figure 2M and Figure 2N A dielectric spacer 60 can be formed on the sidewall of the source region 31. For example... Figure 2M As shown, dielectric layer 230 may be conformally deposited over a semiconductor substrate, including gate contact region 21, gate region 22, and a mesa in which source region 31 is disposed. Dielectric layer 230 may include any suitable dielectric material to electrically insulate source region 31 from subsequently added metal wiring that couples gate contact region 21 to the gate terminal of JFET 100. For example, dielectric layer 230 may include silicon dioxide or any other suitable dielectric material.

[0042] like Figure 2N As shown, isotropic etching can be applied to remove portions of the dielectric layer 230. Isotropic etching can be achieved by chemical etching, plasma etching, a combination of chemical etching and plasma etching, or any other etching process suitable for acting on the dielectric layer 230. For example, isotropic etching can be configured to act vertically on the material of the dielectric layer 230 to remove the upper and lower portions of the dielectric layer 230, which extends horizontally and parallel to the surface of the semiconductor substrate. Isotropic etching of the dielectric layer 230 can leave vertically oriented portions of the dielectric layer 230 to form dielectric spacers 60 on the sidewalls of the source region 31.

[0043] Next move to Figure 2OThe metal layer 240 may be conformally deposited over the semiconductor substrate, including the source region 31, the dielectric spacer 60, and the gate contact region 21. Any suitable metal or metal alloy may be used to form the metal layer 240. As an example, the metal layer 240 may include nickel (N) or an alloy thereof. After depositing the metal layer 240, annealing may be performed. For example, a low-temperature rapid thermal annealing (RTA) may be performed to react portions of the metal layer 240 with the regions beneath the source region 31 and the gate contact region 21. The reaction of the metal with the underlying semiconductor regions may form silicide (e.g., nickel silicide) regions.

[0044] Next move to Figure 2P Unreacted portions of the metal layer 240 can be removed, including the unreacted portions of the metal layer 240 above the dielectric spacer 60. Reacted portions of the metal layer 240 can be retained. For example, as... Figure 2P As shown, the gate contact 20 and source contact 30 can be formed from the remaining regions of a silicide (e.g., nickel silicide), wherein the metal layer 240 reacts with the regions below the source region 31 and the gate contact region 21. This can then be compared to the above reference. Figure 2O The first rapid thermal annealing (RTA) described herein is performed at a higher temperature to perform a second RTA to further anneal the gate contact 20 and the source contact 30, thereby further reducing the contact resistance of the gate contact 20 and the source contact 30.

[0045] After forming the gate contact 20 and the source contact 30, further processing steps can be used to couple the gate region 22, the source region 31, and the drift region 41 to the corresponding gate terminal, source terminal, and drain terminal of the JFET device. For example, a silicide can be formed on the back side of the semiconductor substrate to form the drain contact, such as... Figure 1 The drain contact 50 is illustrated in the figure. In addition, one or more metal layers (separated by one or more interlayer dielectrics and / or passivation layers) may be patterned and formed to provide wiring from the gate contact 20 to the gate pad on the pad metal layer, and to provide wiring from the source contact 30 to the source pad on the pad metal layer.

[0046] Figure 3 A method 300 for manufacturing a JFET device according to an embodiment of the present disclosure is illustrated. In some embodiments, the steps of method 300 can be compared with... Figure 3 The method is performed using fewer or more steps as shown. For simplicity, additional fabrication steps, such as the formation of the source region, gate region, and termination region, and the backside metallization for forming the drain contact, are omitted from the steps of method 300. Furthermore, in some embodiments, certain steps of method 300 may be omitted, repeated, performed in parallel, or combined with... Figure 3The execution order shown may differ from the execution sequence, or it may be executed recursively. As an example, step 312 may be omitted in some implementations.

[0047] Step 302 may include forming a source region adjacent to the surface of the semiconductor substrate. For example, as referenced above. Figure 2A As described, a dopant with a higher concentration and the same conductivity type than the drift region 41 and the channel region 40 can be added to the upper surface of the semiconductor substrate to form a source region 31 adjacent to the upper surface of the semiconductor substrate.

[0048] Step 304 may include forming a spacer above the surface of the semiconductor substrate using a spacer material. For example, as referenced above. Figures 2B to 2D As described, spacers 206 can be formed on the upper surface of the semiconductor substrate using spacer material 204. In some embodiments, forming spacers 206 on the surface of the semiconductor substrate may include: forming a patterned mask 202 over the semiconductor substrate; depositing spacer material 204 over the patterned mask 202 and the semiconductor substrate; performing isotropic etching on the spacer material 204; and removing the patterned mask 202.

[0049] Step 306 may include forming a gate region, wherein the gate region is masked by the spacer to define a boundary of a channel region extending vertically from the source region toward the drift region. For example, as referenced above. Figure 2E As described, the gate region 22 can be formed by doping portions of the semiconductor substrate with a conductivity type opposite to that of the drift region 41, the channel region 40, and the source region 31. Figure 2E As shown, the formation of the gate region 22 can be masked by the spacer 206 to define the boundary of the channel region 40, whereby the channel region 40 extends vertically from the source region 31 toward the drift region 41.

[0050] Step 308 may include increasing the spacer width. In some embodiments, increasing the spacer width may include: depositing a second spacer layer over the spacer material and the semiconductor substrate; and performing isotropic etching on the second spacer layer. For example, as referenced above... Figure 2F and Figure 2G As described, the width of spacer 206 can be increased or widened from the first spacer width 207 to a second spacer width 217 greater than the first spacer width 207. For example... Figure 2F As shown, a second spacer layer 210 can be conformally deposited over spacer material 204 and semiconductor substrate. Then, as... Figure 2GAs shown, isotropic etching can be applied to remove portions of the second spacer layer 210. Isotropic etching of the second spacer layer 210 can leave a portion of the second spacer layer 210 on the sidewall of the spacer material 204, thereby reducing the spacer width of the spacer 206 from the first spacer width 207. Figure 2D and Figure 2E (As shown) Increased to the width of the second spacer 217 ( Figure 2G (As shown).

[0051] Step 310 may include using the spacer as a mask to etch through the source region and reach the gate region. For example, as referenced above. Figure 2H As described, a trench can be formed by using spacer 206 (the second spacer width 217 of spacer 206) as a mask to etch through the source region 31 and reach the gate region 22. In some embodiments, using spacer 206 as a mask to etch through the source region 31 to reach the gate region 22 can form a mesa, within which the remaining portion of the source region 31 is disposed.

[0052] Step 312 may include further increasing the spacer width before forming the gate contact region. In some embodiments, further increasing the spacer width may include: depositing an additional spacer layer over the spacer and the semiconductor substrate; and performing isotropic etching against the additional spacer layer. For example, as referenced above. Figure 2I and Figure 2J As described, the width of spacer 206 can be increased or widened from the second spacer width 217 to a third spacer width 227 that is greater than the second spacer width 217. For example... Figure 2I As shown, an additional spacer layer 220 can be conformally deposited over spacer material 204, second spacer layer 210, and semiconductor substrate. Subsequently, as Figure 2J As shown, isotropic etching can be applied to remove portions of the additional spacer layer 220. The isotropic etching of the additional spacer layer 220 can leave a portion of the additional spacer layer 220 on the sidewall of the second spacer layer 210, thereby reducing the spacer width of the spacer 206 from the second spacer width 217. Figure 2G and Figure 2H (As shown) Increased to the width of the third spacer 227 ( Figure 2J (As shown).

[0053] like Figure 2KAs shown, the additional spacer layer 220 of spacer 206 protects the source region 31 from doping used to form the gate contact region 21. In some embodiments, the doping concentration of the source region 31 (of a first conductivity type) can be significantly higher than the doping concentration of the gate contact region 21 (of a second conductivity type). In such embodiments, the higher doping concentration of the first conductivity type for the source region 31 can dominate even when exposed to doping of the second conductivity type for the gate contact region 21. Therefore, in such embodiments, the doping layer 220 can optionally be omitted. Figure 2I and Figure 2J The illustrated processing steps add an additional spacer layer 220. For such embodiments, method 300 may optionally omit step 312 and may proceed directly from step 310 to step 314.

[0054] Step 314 may include forming a gate contact region in the gate region. For example, as referenced above. Figure 2K As described, the spacer 206 can be used as a mask to form the gate contact region 21 in the gate region 22. The gate contact region 21 can be formed by doping portions of the gate region 22 with a higher doping concentration of the same conductivity type as the gate region 22. In some embodiments, the higher doping concentration of the gate contact region 21 can help facilitate the formation of low-resistance gate contacts 20 coupled to the gate contact region 21 in a later processing step.

[0055] Step 316 may include removing the spacer. For example, as referenced above. Figure 2L As described, spacer material 204, second spacer layer 210 and / or additional spacer layer 220, which are used as etching targets, can be applied to remove spacer 206 from the upper surface of the semiconductor substrate.

[0056] As mentioned above (see reference) Figure 2L As described, other features of the device, such as termination regions, can be added after the spacer 206 is removed. For example, termination regions can be formed on the outer periphery of the active region in which multiple JFET cells are formed. In some embodiments, the termination regions may include one or more doped regions (e.g., formed by diffusion or implantation) and / or one or more trench structures to reduce the electric field gradient at geometrically sharp points associated with operation of the JFET device at high voltages. High-temperature activation (HTA) and / or driven diffusion can be performed to activate the implanted impurities, including dopants applied to form the termination regions directly described above, and / or implanted impurities applied to form the gate region 22 and the gate contact region 21, as referenced above. Figure 2E and Figure 2K As described.

[0057] Step 318 may include forming a dielectric spacer on the sidewall of the source region. For example, as referenced above. Figure 2M and Figure 2N As described, a dielectric spacer 60 can be formed on the sidewall of the source region 31. For example... Figure 2M As shown, the dielectric layer 230 is conformally deposited over the semiconductor substrate, including the gate contact region 21, the gate region 22, and the mesas where the source region 31 is disposed. Subsequently, as Figure 2N As shown, isotropic etching can be applied to remove the upper and lower portions of the dielectric layer 230 that extend horizontally and parallel to the surface of the semiconductor substrate. The isotropic etching of the dielectric layer 230 can leave a vertically oriented portion of the dielectric layer 230 to form a dielectric spacer 60 on the sidewall of the source region 31.

[0058] Step 320 may include depositing a metal layer. For example, as referenced above. Figure 2O As described, the metal layer 240 may be conformally deposited over the semiconductor substrate, including over the source region 31, the dielectric spacer 60, and the gate contact region 21. The metal layer 240 may be formed of any suitable metal or metal alloy, such as nickel (N) or alloys thereof.

[0059] Step 322 may include performing annealing to cause portions of the metal layer to react with the regions beneath the source region and the gate contact region. For example, as referenced above... Figure 2O As described, a low-temperature rapid thermal annealing (RTA) can be performed to react portions of the metal layer 240 with the regions beneath the source region 31 and the gate contact region 21. The reaction of the metal with the underlying semiconductor regions can form silicide (e.g., nickel silicide) regions.

[0060] Step 324 may include removing unreacted portions of the metal layer above the dielectric spacer. For example, as referenced above. Figure 2P As described, unreacted portions of the removable metal layer 240 include those above the dielectric spacer 60. Reacted portions of the metal layer 240 can be retained. For example, as Figure 2P As shown, the gate contact 20 and the source contact 30 may be formed from the remaining regions of silicide (e.g., nickel silicide), wherein the metal layer 240 reacts with the regions below the source region 31 and the gate contact region 21.

[0061] Figure 4 A method 400 for manufacturing a JFET device according to an embodiment of the present disclosure is illustrated. In some embodiments, the steps of method 400 can be compared with... Figure 4 The method is performed using fewer or more steps as shown. For simplicity, additional fabrication steps, such as the formation of the source region, gate region, and termination region, and the backside metallization for forming the drain contact, are omitted from the steps of method 400. Furthermore, in some embodiments, certain steps of method 400 may be omitted, repeated, performed in parallel, or combined with... Figure 4 The execution order shown may differ from the execution sequence, or it may be executed recursively. As an example, step 410 may be omitted in some implementations.

[0062] Step 402 may include forming a spacer having a first spacing width on the surface of the semiconductor substrate. For example, as referenced above. Figures 2B to 2D As described, spacers 206 having a first spacer width 207 can be formed on the upper surface of the semiconductor substrate using spacer material 204. In some embodiments, forming spacers 206 above the surface of the semiconductor substrate may include: forming a patterned mask 202 above the semiconductor substrate; depositing spacer material 204 over the patterned mask 202 and the semiconductor substrate; performing isotropic etching on the spacer material 204; and removing the patterned mask 202.

[0063] Step 404 may include using the spacer having the width of the first spacer as a first mask to form a gate region on opposite sides of a channel region extending vertically from the source region to the drift region. For example, as referenced above. Figure 2E As described, the gate region 22 can be formed by doping portions of the semiconductor substrate with a conductivity type opposite to that of the drift region 41, the channel region 40, and the source region 31. Figure 2E As shown, the formation of the gate region 22 can be masked by the spacer 206 (and in particular the first spacer width 207 of the spacer 206) to define the boundary of the channel region 40, whereby the channel region 40 extends vertically from the source region 31 toward the drift region 41.

[0064] Step 406 may include widening the spacer to a second spacer width greater than the width of the first spacer. In some embodiments, widening the spacer to a second spacer width greater than the width of the first spacer may include: depositing a second spacer layer over the spacer material and the semiconductor substrate; and performing isotropic etching on the second spacer layer. For example, as referenced above. Figure 2F and Figure 2G As described, the width of spacer 206 can be increased or widened from the first spacer width 207 to a second spacer width 217 greater than the first spacer width 207. For example... Figure 2F As shown, a second spacer layer 210 can be conformally deposited over spacer material 204 and semiconductor substrate. Then, as... Figure 2G As shown, isotropic etching can be applied to remove portions of the second spacer layer 210. Isotropic etching of the second spacer layer 210 can leave a portion of the second spacer layer 210 on the sidewall of the spacer material 204, thereby reducing the spacer width of the spacer 206 from the first spacer width 207. Figure 2D and Figure 2E(As shown) Increased to the width of the second spacer 217 ( Figure 2G (As shown).

[0065] Step 408 may include using the spacer having the width of the second spacer as a second mask to form a trench extending through the source region and into the gate region. For example, as referenced above. Figure 2H As described, a trench can be formed by using spacer 206 (the second spacer width 217 of spacer 206) as a mask to etch through the source region 31 and reach the gate region 22. In some embodiments, using spacer 206 as a mask to etch through the source region 31 to reach the gate region 22 can form a mesa, within which the remaining portion of the source region 31 is disposed.

[0066] Step 410 may include further widening the spacer to a third spacer width greater than the width of the second spacer before forming the gate contact region. In some embodiments, further widening the spacer to a third spacer width greater than the width of the second spacer may include: depositing an additional spacer layer over the spacer and the semiconductor substrate; and performing isotropic etching against the additional spacer layer. For example, as referenced above. Figure 2I and Figure 2J As described, the width of spacer 206 can be increased or widened from the second spacer width 217 to a third spacer width 227 that is greater than the second spacer width 217. For example... Figure 2I As shown, an additional spacer layer 220 can be conformally deposited over spacer material 204, second spacer layer 210, and semiconductor substrate. Subsequently, as Figure 2J As shown, isotropic etching can be applied to remove portions of the additional spacer layer 220. The isotropic etching of the additional spacer layer 220 can leave a portion of the additional spacer layer 220 on the sidewall of the second spacer layer 210, thereby reducing the spacer width of the spacer 206 from the second spacer width 217. Figure 2G and Figure 2H (As shown) Increased to the width of the third spacer 227 ( Figure 2J (As shown).

[0067] like Figure 2K As shown, the additional spacer layer 220 of spacer 206 protects the source region 31 from doping used to form the gate contact region 21. In some embodiments, the doping concentration of the source region 31 (of a first conductivity type) can be significantly higher than the doping concentration of the gate contact region 21 (of a second conductivity type). In such embodiments, the higher doping concentration of the first conductivity type for the source region 31 can dominate even when exposed to doping of the second conductivity type for the gate contact region 21. Therefore, in such embodiments, the doping layer 220 can optionally be omitted. Figure 2I and Figure 2J The illustrated processing steps add an additional spacer layer 220. For such embodiments, method 400 may optionally omit step 410 and may proceed directly from step 408 to step 412.

[0068] Step 412 may include forming a gate contact region in the gate region. For example, as referenced above. Figure 2K As described, the spacer 206 can be used as a mask to form the gate contact region 21 in the gate region 22. The gate contact region 21 can be formed by doping portions of the gate region 22 with a higher doping concentration of the same conductivity type as the gate region 22. In some embodiments, the higher doping concentration of the gate contact region 21 can help facilitate the formation of low-resistance gate contacts 20 coupled to the gate contact region 21 in a later processing step.

[0069] Step 414 may include removing the spacer. For example, as referenced above. Figure 2L As described, spacer material 204, second spacer layer 210 and / or additional spacer layer 220, which are used as etching targets, can be applied to remove spacer 206 from the upper surface of semiconductor substrate.

[0070] Step 416 may include forming a dielectric spacer on the sidewall of the source region. For example, as referenced above. Figure 2M and Figure 2N As described, a dielectric spacer 60 can be formed on the sidewall of the source region 31. For example... Figure 2M As shown, the dielectric layer 230 is conformally deposited over the semiconductor substrate, including the gate contact region 21, the gate region 22, and the mesas where the source region 31 is disposed. Subsequently, as Figure 2N As shown, isotropic etching can be applied to remove the upper and lower portions of the dielectric layer 230 that extend horizontally and parallel to the surface of the semiconductor substrate. The isotropic etching of the dielectric layer 230 can leave a vertically oriented portion of the dielectric layer 230 to form a dielectric spacer 60 on the sidewall of the source region 31.

[0071] Step 418 may include depositing a metal layer. For example, as referenced above. Figure 2O As described, the metal layer 240 may be conformally deposited over the semiconductor substrate, including over the source region 31, the dielectric spacer 60, and the gate contact region 21. The metal layer 240 may be formed of any suitable metal or metal alloy, such as nickel (N) or alloys thereof.

[0072] Step 420 may include performing annealing to cause portions of the metal layer to react with the regions beneath the source region and the gate contact region. For example, as referenced above... Figure 2OAs described, a low-temperature rapid thermal annealing (RTA) can be performed to react portions of the metal layer 240 with the regions beneath the source region 31 and the gate contact region 21. The reaction of the metal with the underlying semiconductor regions can form silicide (e.g., nickel silicide) regions.

[0073] Step 422 may include removing unreacted portions of the metal layer above the dielectric spacer. For example, as referenced above. Figure 2P As described, unreacted portions of the removable metal layer 240 include those above the dielectric spacer 60. Reacted portions of the metal layer 240 can be retained. For example, as Figure 2P As shown, the gate contact 20 and the source contact 30 may be formed from the remaining regions of silicide (e.g., nickel silicide), wherein the metal layer 240 reacts with the regions below the source region 31 and the gate contact region 21.

[0074] Although examples have been described above, other modifications and variations can be made from this disclosure without departing from the spirit and scope of these examples. The description of the various embodiments above exemplifies the principles of the invention. Based on the above disclosure, many variations and modifications will become apparent to those skilled in the art. The following claims are intended to encompass all such variations and modifications.

Claims

1. A method for manufacturing a junction field-effect transistor (JFET), the method comprising: Forming a source region adjacent to the surface of the semiconductor substrate; A spacer is formed above the surface of the semiconductor substrate using a spacer material; A gate region is formed, wherein the gate region is masked by the spacer to define the boundary of a channel region that extends vertically from the source region toward the drift region; Increase the width of the spacer; The spacer is used as a mask to etch through the source region and reach the gate region; as well as A gate contact region is formed in the gate region.

2. The method according to claim 1, further comprising: Remove the spacer; A dielectric spacer is formed on the sidewall of the source region; Deposited metal layer; Annealing is performed to cause portions of the metal layer to react with the regions beneath the source region and the gate contact region; as well as Remove the unreacted portion of the metal layer above the dielectric spacer.

3. The method of claim 1, wherein forming the spacer above the surface of the semiconductor substrate comprises: A patterned mask is formed over the semiconductor substrate; The spacer material is deposited over the patterned mask and the semiconductor substrate; Perform isotropic etching on the spacer material; as well as Remove the patterned mask.

4. The method of claim 1, wherein increasing the width of the spacer comprises: A second spacer layer is deposited over the spacer material and the semiconductor substrate; as well as Perform isotropic etching on the second spacer layer.

5. The method according to claim 1, further comprising: The width of the spacer is further increased before the gate contact region is formed.

6. The method of claim 5, wherein further increasing the width of the spacer comprises: An additional spacer layer is deposited over the spacer and the semiconductor substrate; as well as Perform isotropic etching on the additional spacer layer.

7. The method according to claim 1, wherein the channel region is formed having a channel width in the range of 0.2 μm to 1 μm.

8. The method of claim 1, wherein the spacer is used as the mask to etch through the source region and reach the gate region to form a mesa, the mesa having a mesa depth in the range of 0.1 μm to 0.3 μm and a mesa width in the range of 0.5 μm to 1.0 μm.

9. The method of claim 1, wherein the respective portions of the gate regions are formed at a distance from each other to provide a cell spacing in the range of 1 μm to 2 μm.

10. The method according to claim 1, wherein the semiconductor substrate is a silicon carbide (SiC) substrate.

11. The method according to claim 1, wherein: The source region, the channel region, and the drift region are n-type regions; and The gate region and the gate contact region are p-type regions.

12. A method for manufacturing a junction field-effect transistor (JFET), the method comprising: A spacer having a first spacer width is formed on the surface of a semiconductor substrate; The spacer having the width of the first spacer is used as a first mask to form a gate region on the opposite side of the channel region extending vertically from the source region to the drift region; The spacer is widened to a second spacer width that is greater than the width of the first spacer; The spacer having the width of the second spacer is used as a second mask to form a trench that extends through the source region and into the gate region; as well as A gate contact region is formed in the gate region.

13. The method according to claim 12, further comprising: Remove the spacer; A dielectric spacer is formed on the sidewall of the source region; Deposited metal layer; Annealing is performed to cause portions of the metal layer to react with the regions beneath the source region and the gate contact region; as well as Remove the unreacted portion of the metal layer above the dielectric spacer.

14. The method of claim 12, wherein widening the spacer to a width greater than the width of the first spacer comprises: A second spacer layer is deposited over the spacer and the semiconductor substrate; as well as Perform isotropic etching on the second spacer layer.

15. The method according to claim 12, further comprising: Before forming the gate contact region, the spacer is further widened to a third spacer width greater than the width of the second spacer, wherein the spacer having the third spacer width is used as a third mask to form the gate contact region.

16. The method of claim 15, wherein further widening the spacer comprises: An additional spacer layer is deposited over the spacer and the semiconductor substrate; as well as Perform isotropic etching on the additional spacer layer.

17. A junction field-effect transistor (JFET), the JFET comprising: A source region is disposed in a mesa between two dielectric spacers and coupled to a source contact on a first surface of a semiconductor substrate. A drift region, the drift region being coupled to a drain contact on a second surface of the semiconductor substrate opposite to the first surface; A channel region that extends vertically between the source region and the drift region; A gate region is disposed on the opposite side of the channel region; and A gate contact region, wherein the gate contact region is disposed within the gate region and coupled to the gate contact portion; and The JFET described therein has a cell pitch in the range of 1 μm to 2 μm.

18. The JFET of claim 17, wherein the channel region has a channel width in the range of 0.2 μm to 1 μm.

19. The JFET of claim 17, wherein the mesa has a mesa width in the range of 0.5 μm to 1.0 μm and a mesa depth in the range of 0.1 μm to 0.3 μm.

20. The JFET of claim 17, wherein the JFET is a silicon carbide JFET.

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