Semiconductor device and method of manufacturing the same

Abstract

The semiconductor device and the manufacturing method thereof are disclosed. The semiconductor device is characterized in that, when forming the source opening and / or the drain opening, the barrier layer in the region where the opening is located is etched completely, and a thin dielectric layer is deposited. The ohmic contact of the drain and / or the source is formed by annealing. The over-reaction of the ohmic metal and the barrier layer is prevented by the thin dielectric layer, so as to ensure the stable composition and the appearance of the ohmic metal, improve the yield of the device and the reliability of the device. The ohmic contact of the drain and / or the source is formed by the tunneling effect of the two-dimensional electron gas and the ohmic metal, so as to reduce the annealing temperature.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] As market demands for smaller size and higher energy efficiency in power devices increase, wide-bandgap GaN devices, due to their lower power loss and faster switching capabilities, have been widely used in high-frequency power conversion systems. Compared to silicon metal-oxide-semiconductor field-effect transistors (MOSFETs), GaN high electron mobility transistors (HEMTs) offer better quality factors and more promising performance in high-power and high-frequency applications.

[0003] To further improve the performance of GaN transistors, reducing the device's on-resistance is an effective method, among which reducing the resistance of ohmic contacts (source and drain) is crucial. Conventional ohmic contacts, such as (Ti / Al / Ni / Au stacks), require high-temperature annealing (>800 degrees Celsius), and the high thermal budget required for this process limits the implementation of semiconductor integration processes. Summary of the Invention

[0004] In view of this, the present invention proposes a method for manufacturing a semiconductor device to reduce the annealing temperature of the ohmic contact and reduce the resistance of the ohmic contact between the drain and the source.

[0005] In a first aspect, embodiments of the present invention provide a method for manufacturing a semiconductor device, comprising: forming a substrate layer; forming a channel layer on the substrate layer; forming a barrier layer on the channel layer; forming a drain opening and / or a source opening, wherein the drain opening and / or source opening terminates at the upper surface of the channel layer or extends into the channel layer; forming a thin dielectric layer at least on the inner surface of the drain opening and / or source opening; and depositing metal in the drain opening and / or source opening including the thin dielectric layer.

[0006] Preferably, the thin dielectric layer comprises an oxide or a nitride.

[0007] Preferably, the oxide comprises SiO2.

[0008] Preferably, the nitride comprises SiN or AlN.

[0009] Preferably, the thickness of the thin dielectric layer is no greater than 4 nm.

[0010] Preferably, the thin dielectric layer is formed by chemical deposition.

[0011] Preferably, the drain opening and / or the source opening are trapezoidal in shape, wider at the top and narrower at the bottom, and include two inclined sides.

[0012] Preferably, the angle between the side surface and the upper surface of the channel layer is no greater than 80°.

[0013] Preferably, the metal comprises a single-layer structure or a multilayer structure formed of at least one material selected from Ti, Al, Ni, TiN, and Ta.

[0014] Preferably, the method further includes: forming ohmic contacts of the drain and / or source by annealing, wherein the annealing temperature is less than 650°.

[0015] Preferably, the method further includes: forming a gate structure above the barrier layer after the barrier layer; and forming a first dielectric layer covering the gate structure.

[0016] Preferably, the drain opening and / or the source opening are formed by etching the first dielectric layer and the barrier layer.

[0017] Preferably, the drain opening and / or the source opening are formed by etching the first dielectric layer, the barrier layer and a portion of the channel layer.

[0018] Preferably, the thin dielectric layer also covers the top of the gate structure.

[0019] Secondly, embodiments of the present invention also provide a semiconductor device, comprising: a channel layer; a barrier layer located on the channel layer; wherein a two-dimensional electron gas is formed at the interface between the channel layer and the barrier layer; a drain opening and / or a source opening, the bottom of which terminates on the upper surface of the channel layer or extends into the channel layer; a thin dielectric layer located at least on the inner surface of the drain opening and / or the source opening; a drain metal and / or a source metal, wherein the drain metal fills the drain opening including the thin dielectric layer, and the source metal fills the source opening including the thin dielectric layer.

[0020] Preferably, the annealing temperature for forming the ohmic contacts of the drain and / or source is below 650 degrees Celsius.

[0021] Preferably, the thin dielectric layer comprises an oxide or a nitride.

[0022] Preferably, the oxide comprises SiO2.

[0023] Preferably, the nitride comprises SiN or AlN.

[0024] Preferably, the thickness of the thin dielectric layer is no greater than 4 nm.

[0025] Preferably, the drain opening and / or the source opening are trapezoidal in shape, wider at the top and narrower at the bottom, and include two inclined sides.

[0026] Preferably, the angle between the side surface and the upper surface of the channel layer is no greater than 80°.

[0027] Preferably, the semiconductor device further includes: a substrate layer; a buffer layer located between the substrate layer and the channel layer; a gate structure located on the barrier layer; and a first dielectric layer covering the gate structure.

[0028] Preferably, the thin dielectric layer covers not only the drain opening and / or the source opening, but also the gate structure.

[0029] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0030] In the semiconductor device of the present invention, when forming the source opening and / or drain opening, the barrier layer in the region where the source opening and / or drain opening is located is fully etched and a thin dielectric layer is deposited. Metal is deposited on top of the thin dielectric layer above the drain opening and / or source opening, and ohmic contacts of the drain and / or source are formed by annealing. The present invention prevents over-reaction between the ohmic metal and the barrier layer through the thin dielectric layer, ensuring stable composition and morphology of the ohmic metal, improving the uniformity of the ohmic contacts of the drain and source, thereby improving the device yield and reliability. Furthermore, the ohmic contacts of the drain and source are formed through the tunneling effect of the two-dimensional electron gas and the ohmic metal, reducing the annealing temperature. The side of the drain opening and / or source opening is tilted, increasing the contact area between the two-dimensional electron gas and the drain metal and / or source metal during ohmic contact formation, thus further reducing the resistance of the drain and source ohmic contacts. Simultaneously, the material of the thin dielectric layer is set to be the same as that of the adjacent dielectric layer, reducing the influence of the thin dielectric layer on the device. Attached Figure Description

[0031] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0032] Figure 1 This is a cross-sectional view of the semiconductor device according to the first embodiment of this application;

[0033] Figure 2 This is a flowchart illustrating a method for manufacturing a semiconductor device according to the first embodiment of this application;

[0034] Figures 3 to 9 These are cross-sectional views of each stage of the semiconductor device manufacturing method according to the first embodiment of this application;

[0035] Figure 10 This is a cross-sectional view of the semiconductor device according to the second embodiment of this application. Detailed Implementation

[0036] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0037] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0038] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0039] Those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

[0040] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0041] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0042] In the semiconductor field (especially for GaN HEMT devices), the channel layer or buffer layer has an extremely low doping content (typically ≤10¹). 5 ~10¹ 6 The "near-intrinsic" state (cm⁻³) of the channel is characterized by conductivity primarily driven by thermally excited carriers, closely resembling that of a pure, undoped intrinsic semiconductor. This design aims to generate a 2DEG using the polarization effect while minimizing impurity scattering, ensuring high electron mobility, and maintaining high resistivity in the channel region to suppress leakage current.

[0043] This application provides a semiconductor device with low ohmic contact resistance. Exemplary examples include power transistors, such as GaN HEMTs (high electron mobility transistors).

[0044] Figure 1This is a cross-sectional view of a semiconductor device according to an embodiment of this application. The semiconductor device includes: a bottom layer structure, a source structure, a drain structure, and a gate structure.

[0045] The underlying structure includes a substrate layer 100, a buffer layer 110, a channel layer 120, and a barrier layer 130. The substrate layer 100 is, for example, a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, or a sapphire substrate. The channel layer 120 includes a group III-V nitride, such as a gallium nitride (GaN) layer, and the barrier layer 130 includes a group III-V nitride, such as an AlGaN layer, an InGaN layer, or a combination of AlN and AlGaN layers. The bandgap of the barrier layer 130 is greater than that of the channel layer 120 to form a heterojunction between them. A high content of two-dimensional electron gas (2DEG) is induced at the interface between the two layers through a polarization effect. The 2DEG serves as the conductive channel for the semiconductor device. The content of the 2DEG can be controlled by adjusting the gate voltage, thereby changing the conductivity. As an example, the thickness of the channel layer 120 is greater than the thickness of the barrier layer 130. The substrate layer 100 and the channel layer 120 have different lattice constants, and the buffer layer 110 serves as a transition layer between the substrate layer 100 and the channel layer 120.

[0046] As an example, the buffer layer 110 may include a buffer layer of multiple materials. Any composition and number of layers that can serve as a buffer layer between the substrate layer 100 and the channel layer 120 are acceptable and are not limited here.

[0047] like Figure 1 As shown, the gate structure includes a P-type gate 151 and a gate metal 152, which is located between the source structure and the gate structure. A gate material layer is formed above the barrier layer 130, and a gate metal layer is formed above the gate material layer. The gate metal layer can be formed, for example, by sputtering deposition, and the material of the gate metal layer is, for example, TiN, Ti, AlCu, TaN, etc. The gate material layer and the gate metal layer are patterned to form the P-type gate 151 and the gate metal 152, respectively.

[0048] like Figure 1 As shown, the semiconductor device further includes a first dielectric layer 140, which is located on the upper surface of the underlying structure. Specifically, the first dielectric layer 140 is located above the barrier layer 130. The first dielectric layer 140 covers the gate structure and the barrier layer 130. The material of the first dielectric layer 140 can be, for example, SiO2, Si3N4, Al2O3, etc.

[0049] like Figure 1As shown, as an example, the source and drain openings penetrate the first dielectric layer 140 and the barrier layer 130. The bottoms of the source and drain openings terminate at the upper surface of the channel layer 120. Alternatively, in other examples, the bottoms of the source and drain openings may extend into the channel layer 120, located inside the channel layer 120. The source and drain openings have a trapezoidal shape, wider at the top and narrower at the bottom, and include two inclined sides. The inclination angle θ of both sides is no greater than 80°, meaning the angle θ between the two sides and the horizontal plane of the underlying structure is no greater than 80°, and the angle θ between the two sides and the upper surface of the channel layer 120 is no greater than 80°. The lower surfaces of the source and drain openings are horizontal and terminate at the upper surface of the channel layer or inside the channel layer. The smaller the angle θ, the larger the contact area between the two sides and the barrier layer, resulting in a smaller resistance in the formed drain and / or source ohmic contact.

[0050] like Figure 1 As shown, the semiconductor device further includes a thin dielectric layer 170, which is located on the inner surface of the openings of the source and drain electrodes and covers the first dielectric layer 140. Specifically, the thin dielectric layer 170 may include one of an oxide or a nitride. When the thin dielectric layer 170 is an oxide, it may be SiO2; when the thin dielectric layer 170 is a nitride, it may be one of SiN or AlN.

[0051] More specifically, the thickness of the thin dielectric layer 170 is no greater than 4 nm.

[0052] like Figure 1 As shown, the drain and source structures of the semiconductor device include drain metal 153 and source metal 154. The drain metal 153 and source metal 154 form an ohmic contact between the drain and source through annealing, wherein the annealing temperature is less than 650°C. The semiconductor device also includes a second dielectric layer 160 covering the drain structure, the source structure, and the thin dielectric layer 170.

[0053] It should be noted that the thin dielectric layer 170 formed above the drain and source openings is to prevent the drain and source metals from reacting excessively with the barrier layer 130, thus preventing damage to the shape and composition of the ohmic metal. This ensures the stability of the ohmic metal's shape and composition, improves the uniformity of the ohmic contact between the drain and source, and consequently improves the device yield and reliability. Simultaneously, extending the bottoms of the source and drain openings at least to the upper surface of the channel layer, and tilting the sides of the source and drain openings, is to increase the uniformity of the ohmic contact. During the formation process, the contact area between the two-dimensional electron gas and the drain and source metals is increased, thereby forming a lower ohmic contact between the drain and source through the tunneling effect of the two-dimensional electron gas and the ohmic metal. Furthermore, because this application forms a low-impedance ohmic contact between the drain and source through the tunneling effect of the two-dimensional electron gas and the ohmic metal, the required annealing temperature is lower, which reduces the annealing temperature to less than the high-temperature annealing temperature in the prior art. In this embodiment, the annealing temperature for forming the ohmic contact can be less than 650°, which is much lower than the 800° high temperature required for high-temperature annealing in the prior art.

[0054] In addition, since the presence of the thin dielectric layer 170 affects the tunneling effect between the two-dimensional electron gas and the ohmic metal, the influence of the thin dielectric layer 170 on the tunneling effect between the two-dimensional electron gas and the ohmic metal is reduced by setting the thickness of the thin dielectric layer 170 to no more than 4 nm.

[0055] In this embodiment, the purpose of providing the thin dielectric layer 170 is to prevent the ohmic metal from directly contacting the barrier layer 130, which would cause the ohmic metal to react with the barrier layer 130 and damage the shape and composition of the ohmic metal. Therefore, the thin dielectric layer 170 only needs to be provided between the drain metal and the source metal and the barrier layer 130, or only needs to be provided on the inner surface above the opening of the drain and the source. The thin dielectric layer 170 may not be provided above the first dielectric layer 140 or part of the first dielectric layer 140. On the other hand, if the thin dielectric layer 170 is formed only on the inner surface of the openings of the drain and source, additional process steps are required to remove the thin dielectric layer 170 other than the inner surface of the openings of the drain and source. Therefore, in this embodiment, the material of the thin dielectric layer 170 is set to oxide or nitride, and the material of the thin dielectric layer 170 is set to be the same as or similar to the material of the first dielectric layer 140 and / or the second dielectric layer 160, thereby reducing the impact of the thin dielectric layer 170 on the semiconductor device and eliminating the process steps that require the removal of part of the thin dielectric layer 170.

[0056] This application also provides a method for manufacturing a semiconductor device. This method can be used to manufacture the semiconductor devices described in the above embodiments. Figure 2 The manufacturing method includes:

[0057] S1: Forms the underlying structure;

[0058] The formation of the underlying structure includes: forming a substrate layer; forming a channel layer on the substrate layer; and forming a barrier layer on the channel layer.

[0059] Specifically, forming the underlying structure includes: forming a substrate; forming a channel layer on the substrate; forming a barrier layer on the channel layer; wherein a two-dimensional electron gas is formed at the interface between the channel layer and the barrier layer.

[0060] S2: Forming a drain opening and / or a source opening; wherein the drain opening and / or source opening terminates at the upper surface of the channel layer or extends into the channel layer.

[0061] S3: A thin dielectric layer is formed on at least the inner surface of the drain opening and / or the source opening;

[0062] S4: Deposit metal in the drain opening and / or source opening, which includes a thin dielectric layer, and form ohmic contacts for the drain and / or source by annealing.

[0063] The metal deposited in the drain opening and / or source opening includes a single-layer structure or a multilayer structure formed of at least one of Ti, Al, Ni, TiN, and Ta.

[0064] The following is based on Figure 1 Taking the semiconductor device shown as an example, the manufacturing process steps of the semiconductor device will be explained in detail.

[0065] like Figure 3 As shown, a bottom layer structure is formed; wherein, the steps of forming the bottom layer structure include: first forming a substrate layer 100; then, epitaxially forming a buffer layer 110 above the substrate layer 100; then epitaxially forming a channel layer 120 above the buffer layer 110; then, epitaxially forming a barrier layer 130 above the channel layer 120.

[0066] A two-dimensional electron gas is formed on the side of the interface between the channel layer and the barrier layer, closer to the barrier layer.

[0067] The substrate layer 100 may include a Si substrate, a SiC substrate, a GaN substrate, sapphire, etc. The buffer layer 110 epitaxially formed on the substrate layer 100 may include a first buffer dielectric layer above the substrate layer 100 and a second buffer dielectric layer above the first buffer dielectric layer. There are no restrictions on the number of buffer layers or their material; any number and composition of buffer layers capable of achieving a buffering effect between the substrate layer 100 and the channel layer 120 is acceptable.

[0068] like Figure 4 As shown, a gate structure 150 is formed on the underlying structure.

[0069] As an example, the gate structure 150 includes a P-type gate 151 and a gate metal 152. A P-type gate material layer is epitaxially formed on the barrier layer 140, and the gate metal layer is deposited, for example, by sputtering. The P-type gate material layer can be a Mg-doped GaN layer or an AlGaN layer. The gate metal layer is formed on the P-type gate material layer. The P-type gate material layer and the gate metal layer are patterned to form the P-type gate 151 and the gate metal 152, respectively, resulting in a cross-sectional view of the device as shown. Figure 4 As shown. The material of the gate metal 142 is, for example, TiN, Ti, AlCu, TaN, etc.

[0070] like Figure 5 As shown, a first dielectric layer 140 is formed on the barrier layer 130 and the gate structure 150, wherein the first dielectric layer 140 serves as a passivation layer on the epitaxial layer.

[0071] like Figure 6 As shown, the first dielectric layer 140 and the underlying structure are etched to form a drain opening 153-1 and a source opening 154-1, with the bottom of the drain opening 153-1 and the source opening 154-1 stopping at the upper surface of the channel layer or extending into the channel layer. Specifically, during the formation of the drain and source openings, the etching of the underlying structure stops at the upper surface of the channel layer by etching the first dielectric layer 140 and the barrier layer 130, or by etching the first dielectric layer 140, the barrier layer 130, and a portion of the thickness of the channel layer 120, thereby stopping the etching of the underlying structure inside the channel layer 120. Both the source and drain openings have a trapezoidal shape, wider at the top and narrower at the bottom, and include two inclined sides. The inclination angle θ of each side is no greater than 80°, meaning the angle θ between the two sides and the horizontal plane of the underlying structure is no greater than 80°, and the angle θ between the two sides and the upper surface of the channel layer is no greater than 80°. The smaller the included angle θ, the larger the contact area between the two sides and the barrier layer, resulting in a smaller resistance of the drain and / or source ohmic contacts.

[0072] It should be noted that in this embodiment, when forming the drain opening 153-1 and the source opening 154-1, it is only necessary to ensure that the barrier layer 130 is completely etched away. It does not necessarily have to stop exactly on the upper surface of the channel layer 120; a portion of the channel layer 120 thickness can also be etched away. In this embodiment, completely etching away the barrier layer 130 ensures that the contact area between the two sides of the source and drain openings and the barrier layer is maximized, thereby reducing the resistance of the ohmic contact between the drain and source. In this embodiment, when forming the drain and source openings, the barrier layer 130 below the openings is completely etched, and no two-dimensional electron gas is formed directly below the openings. However, during the annealing process, the two-dimensional electron gas on the sides of the drain and source openings can pass through the barrier layer 130 and the thin dielectric layer 170 to form a tunneling effect with the drain metal and the source metal, thereby reducing the ohmic contact resistance between the drain and the source. Furthermore, the smaller the tilt angle θ of the side of the opening is, the larger the contact area between the two-dimensional electron gas and the metal layer in the opening, which is more conducive to reducing the ohmic contact resistance between the drain and the source.

[0073] As an example, photoresist serves as the etching mask for the first dielectric layer 161, covering the area except for the drain and source openings. The underlying structure is then etched to completely remove the barrier layer. Dry etching is used to form the drain opening 153-1 and the source opening 154-1, which penetrate the first dielectric layer 140 and the barrier layer 130. The bottom of the drain opening 153-1 and the source opening 154-1 is located on the upper surface of the channel layer 120 or extends into the channel.

[0074] As an example, forming the drain opening 153-1 and the source opening 154-1 may specifically include the following steps: For example... Figure 5 The structure undergoes surface cleaning; photoresist is spin-coated, exposed, reverse-baked, and then alkaline developed to form a photoresist mask; the first dielectric layer and barrier layer are etched using inductively coupled plasma dry etching process. By adjusting the etching chamber pressure, etching power, and etching gas composition, the lateral chemical action of the etching is enhanced, resulting in a trapezoidal source and drain opening that is wider at the top and narrower at the bottom; the sides of the openings are inclined outwards, and the angle between the sides and the horizontal plane of the underlying structure is no greater than 80°. The steps for forming the drain opening 153-1 and the source opening 154-1 are only described here as examples, but should not be considered as limitations.

[0075] like Figure 7 As shown, a thin dielectric layer 170 is formed on at least the inner surfaces of the drain opening 153-1 and the source opening 154-1; specifically, the thin dielectric layer 170 is formed by chemical deposition, and the thickness of the thin dielectric layer 170 is no greater than 4 nm.

[0076] like Figure 7 As described above, when forming the thin dielectric layer 170, a thin dielectric layer is formed not only above the drain opening 153-1 and the source opening 154-1, but also above the first dielectric layer 140. Furthermore, the material of the thin dielectric layer 170 can be the same as or similar to the material of the first dielectric layer 140 and / or the second dielectric layer 160. The thin dielectric layer 170 does not affect the device performance, thus eliminating the need to remove the thin dielectric layer 170 except for the areas above the source and drain openings, saving the process step of removing part of the thin dielectric layer 170.

[0077] like Figure 8 As shown, metals are deposited layer by layer above the thin dielectric layer 170 in the drain opening 153-1 and the source opening 154-1 to form drain metal and source metal, respectively. As an example, the deposited multilayer metal stack can be a stack of metal materials such as Ti / Al / Ni / TiN / Ta from bottom to top, with Ti as the bottom metal. Then, an annealing process is used to generate N vacancies to form an n-type interface, which significantly reduces the Schottky barrier layer and achieves tunneling ohmic contact.

[0078] In this embodiment, the side surfaces of the drain and source openings are tilted to increase the contact area between the two-dimensional electron gas and the drain and source metals during the formation of the ohmic metal. This results in a lower drain and source ohmic contact resistance through the tunneling effect of the two-dimensional electron gas and the ohmic metal. Unlike traditional high-temperature ohmic contacts, which require partial chemical reactions between the ohmic metal and the barrier / channel layer to form a low-resistance ohmic contact, in this application, the two-dimensional electron gas on the side surfaces of the drain and source openings can pass through the barrier layer and the thin dielectric layer 170 during the annealing process to form a tunneling effect with the drain and source metals. This tunneling effect between the two-dimensional electron gas and the ohmic metal forms the drain and source ohmic contact, requiring a lower annealing temperature. The annealing temperature for forming the ohmic contact in this application can be less than 650°C, which is much lower than the 800°C high temperature required for high-temperature annealing in the prior art.

[0079] like Figure 9 As shown, a second dielectric layer 160 is formed, which covers the drain metal 153 and the source metal 154, as well as the thin dielectric layer 170.

[0080] It should be noted that this embodiment proposes a method for forming ohmic contacts by fully etching the barrier layer and combining it with an inserted thin dielectric layer. Low-resistance ohmic contacts are formed through the tunneling effect between the GaN two-dimensional electron gas (2DEG) channel and the ohmic metal, without the need for high-temperature annealing. A thin dielectric layer is inserted between the ohmic metal and the barrier layer to prevent over-reaction between the drain metal and / or source metal and the barrier layer, ensuring stable composition and morphology of the drain metal and / or source metal. The above embodiment uses an enhancement-mode transistor as an example, but it is not limited to this; it can also be a depletion-mode transistor.

[0081] like Figure 10 The diagram shown is a cross-sectional view of a semiconductor device according to another embodiment of the present invention. This semiconductor device includes: a bottom layer structure, a gate dielectric layer 180, a source structure, a drain structure, and a gate structure. The bottom layer structure includes: a substrate layer 100, a buffer layer 110, a channel layer 120, and a barrier layer 130. A gate dielectric layer 180 covering the bottom layer structure is formed on top of the bottom layer structure. The gate structure of this semiconductor device includes a gate metal 152. ， The gate structure is located between the source structure and the gate structure. The semiconductor device also includes a first dielectric layer 140, which is located above the gate dielectric layer 180. Specifically, the first dielectric layer 140 covers the gate metal 152. ， and gate dielectric layer 180.

[0082] like Figure 10 As shown, the source and drain openings penetrate the first dielectric layer 140, the gate dielectric layer 180, and the barrier layer 130. The bottoms of the source and drain openings terminate at the upper surface of the channel layer 120. Alternatively, in other examples, the bottoms of the source and drain openings may extend into the channel layer 120, located inside the channel layer 120. The source and drain openings have a trapezoidal shape, wider at the top and narrower at the bottom, and include two inclined sides. The inclination angle θ of both sides is no greater than 80°, meaning the angle θ between the two sides and the horizontal plane of the underlying structure is no greater than 80°. The lower surfaces of the source and drain openings are horizontal and terminate at the upper surface of the channel layer 120 or inside the channel layer 120. The smaller the angle θ, the larger the contact area between the two sides and the barrier layer, resulting in a smaller resistance in the ohmic contact between the drain and source.

[0083] like Figure 10As shown, the semiconductor device further includes a thin dielectric layer 170, which is located on the inner surface of the openings of the source and drain electrodes and covers the first dielectric layer 140. The thin dielectric layer 170 is provided to prevent the drain and source metals from over-reacting with the barrier layer 130, thus preventing damage to the shape and composition of the ohmic metal, thereby ensuring the stability of the shape and composition of the ohmic metal, improving the uniformity of the ohmic contact between the drain and source electrodes, and thus improving the device yield and reliability. Specifically, the thin dielectric layer 170 may include one of an oxide or a nitride. When the thin dielectric layer 170 is an oxide, it may be SiO2; when the thin dielectric layer 170 is a nitride, it may be one of SiN or AlN. More specifically, the thickness of the thin dielectric layer 170 is no greater than 4 nm. In other examples, the thin dielectric layer 170 may be disposed only between the drain metal and source metal and the barrier layer 130, or only on the inner surface above the openings of the drain and source. The thin dielectric layer 170 may not be disposed above the first dielectric layer 140 or a portion of the first dielectric layer 140. As an example, the material of the thin dielectric layer 170 may be set to be the same as or similar to the material of the first dielectric layer 140 and / or the second dielectric layer 160, thereby reducing the impact of the thin dielectric layer 170 on the semiconductor device and eliminating the need for a process step that requires the removal of a portion of the thin dielectric layer 170. Furthermore, since the presence of the thin dielectric layer 170 affects the tunneling effect between the two-dimensional electron gas and the ohmic metal, the influence of the thin dielectric layer 170 on the tunneling effect between the two-dimensional electron gas and the ohmic metal can be reduced by setting the thickness of the thin dielectric layer 170 to no more than 4 nm.

[0084] like Figure 10 As shown, the drain and source structures of the semiconductor device include drain metal 153 and source metal 154, and ohmic contacts for the drain and / or source are formed by annealing, wherein the annealing temperature is less than 650°. The semiconductor device also includes a second dielectric layer 160 covering the drain structure, the source structure, and the thin dielectric layer 170.

[0085] The bottom of the source and drain openings extends at least to the upper surface of the channel layer, and the sides of the source and drain openings are inclined to increase the contact area between the two-dimensional electron gas and the drain and source metals during the formation of the ohmic contact. This allows for the formation of a lower ohmic contact between the drain and source through the tunneling effect of the two-dimensional electron gas and the ohmic metal. Furthermore, because this application forms a low-impedance ohmic contact between the drain and source through the tunneling effect of the two-dimensional electron gas and the ohmic metal, the required annealing temperature is lower, which is less than the high-temperature annealing temperature in the prior art. In this embodiment, the annealing temperature for forming the ohmic contact can be less than 650°, which is much lower than the 800° high temperature required for high-temperature annealing in the prior art.

[0086] and Figure 1The difference between the Chinese and other embodiments is that... Figure 10 The embodiment is a depletion-type transistor. This semiconductor device has a gate dielectric layer 180 formed on top of the underlying structure. The gate structure of this semiconductor device does not include a P-type gate 151, but only a gate metal 152. ， The first dielectric layer 140 is formed on the gate metal 152. ， Above the gate dielectric layer 180. With Figure 1 Similar to the previous embodiment, the drain and source openings in this embodiment can stop at the upper surface of the channel layer or extend into the channel layer. Figure 10 The example used is where the drain and source openings stop at the upper surface of the channel layer. Figure 1 The difference in this embodiment is that, in forming the drain and source openings, it is necessary to etch the first dielectric layer 140, the gate dielectric layer 180, and the barrier layer 130 to form the drain and source openings, compared to... Figure 1 The embodiment requires etching an additional gate dielectric layer 180.

[0087] As an example, the gate dielectric layer 180 can be Al2O3 or SiN, and can be formed by deposition. The gate dielectric layer 180 can be made of gate metal 152. ， It is isolated from the barrier layer, reducing the risk of gate leakage, while passivating surface traps of the barrier layer 130.

[0088] Figure 10 The underlying structure of the embodiment, the shape of the drain and source openings, the drain and source metals, and the arrangement of the thin dielectric layer are all consistent with... Figure 1 Similarly, the steps and processes for forming the drain opening and source opening, as well as the ohmic contact between the drain opening and source, are also the same, and will not be repeated here.

[0089] It should be noted that, Figures 1-10 The examples illustrate that the drain and source openings stop at the upper surface of the channel layer. In other examples, the drain and / or source openings can extend deep into the channel layer, i.e., compared to... Figures 1-10 In the example above, when forming the drain and source openings, a portion of the channel layer also needs to be etched. Furthermore, the ohmic contacts for both the drain and source are explained in the example above; however, depending on the actual application requirements, this can be applied only to the drain or only to the source.

[0090] In summary, the present invention discloses a semiconductor device and its manufacturing method. When forming source and / or drain openings, the barrier layer in the region where the opening is located is fully etched and a thin dielectric layer is deposited. Metal is deposited on the thin dielectric layer above the drain opening and / or source opening, and ohmic contacts of the drain and / or source are formed by annealing. This invention prevents over-reaction between the ohmic metal and the barrier layer by using a thin dielectric layer, ensuring stable composition and morphology of the ohmic metal, and improving the uniformity of the ohmic contact between the drain and source, thereby improving device yield and reliability. Furthermore, the ohmic contact between the drain and source is formed through the tunneling effect of the two-dimensional electron gas and the ohmic metal, reducing the annealing temperature. The drain and / or source openings are designed as trapezoids, wider at the top and narrower at the bottom, with the sides of the openings angled, increasing the contact area between the two-dimensional electron gas and the drain and / or source metals during ohmic contact formation, thus further reducing the resistance of the drain and source ohmic contact. Simultaneously, the thin dielectric layer is made of the same material as the adjacent dielectric layer, reducing the impact of the thin dielectric layer on the device and eliminating the need for its removal.

[0091] As used herein, descriptions of numerical values ​​or angles are appropriate for terms such as “approximately,” “generally,” “roughly,” and “about,” which are used to describe and explain small variations. When used in conjunction with an event or situation, the term may refer to an example of an event or situation occurring precisely or an example of an event or situation occurring very approximately. For example, when used in conjunction with a numerical value, the term may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" or "approximately" the same.

[0092] Although the embodiments or implementations are described and explained separately above, some common technologies are involved. Those skilled in the art can replace and integrate them among the embodiments or implementations. If any content is not explicitly described in one embodiment or implementation, reference can be made to another embodiment that is described.

[0093] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: Forming a substrate layer; A channel layer is formed on the substrate layer; A barrier layer is formed on the channel layer; A drain opening and / or a source opening are formed, wherein the drain opening and / or the source opening terminates at the upper surface of the channel layer or extends into the channel layer; A thin dielectric layer is formed on at least the inner surface of the drain opening and / or source opening; Metal is deposited in the drain opening and / or source opening, which includes the thin dielectric layer.

2. The semiconductor device manufacturing method according to claim 1, characterized in that: The thin dielectric layer comprises oxides or nitrides.

3. The semiconductor device manufacturing method according to claim 2, characterized in that: The oxide includes SiO2.

4. The semiconductor device manufacturing method according to claim 2, characterized in that: The nitrides include SiN or AlN.

5. The semiconductor device manufacturing method according to claim 1, characterized in that: The thickness of the thin dielectric layer is no greater than 4 nm.

6. The semiconductor device manufacturing method according to claim 1, characterized in that: The thin dielectric layer is formed by chemical deposition.

7. The semiconductor device manufacturing method according to claim 2, characterized in that: The drain opening and / or the source opening are trapezoidal in shape, wider at the top and narrower at the bottom, and include two inclined sides.

8. The semiconductor device manufacturing method according to claim 7, characterized in that: The angle between the side surface and the upper surface of the channel layer is no greater than 80°.

9. The semiconductor device manufacturing method according to claim 1, characterized in that: The metal includes a single-layer structure or a multilayer structure formed from at least one of Ti, Al, Ni, TiN, and Ta.

10. The semiconductor device manufacturing method according to claim 2, characterized in that, The method further includes: Ohmic contacts for the drain and / or source are formed by annealing, wherein the annealing temperature is less than 650°.

11. The semiconductor device manufacturing method according to claim 1, characterized in that, The method further includes: A gate structure is formed after the barrier layer and above the barrier layer; A first dielectric layer is formed to cover the gate structure.

12. The semiconductor device manufacturing method according to claim 11, characterized in that: The drain opening and / or the source opening are formed by etching the first dielectric layer and the barrier layer.

13. The semiconductor device manufacturing method according to claim 11, characterized in that: The drain opening and / or the source opening are formed by etching the first dielectric layer, the barrier layer and a portion of the channel layer.

14. The semiconductor device manufacturing method according to claim 11, characterized in that: The thin dielectric layer also covers the top of the gate structure.

15. A semiconductor device, characterized in that, include: Channel layer; A barrier layer is located on the channel layer; wherein a two-dimensional electron gas is formed at the interface between the barrier layer and the channel layer. Drain opening and / or source opening, the bottom of which stops at the upper surface of the channel layer or extends into the channel layer; A thin dielectric layer located at least on the inner surface of the drain opening and / or source opening; Drain metal and / or source metal, the drain metal filling the drain opening including the thin dielectric layer, and the source metal filling the source opening including the thin dielectric layer.

16. The semiconductor device according to claim 15, characterized in that: The annealing temperature for forming the ohmic contacts of the drain and / or source is below 650 degrees Celsius.

17. The semiconductor device according to claim 15, characterized in that: The thin dielectric layer comprises oxides or nitrides.

18. The semiconductor device according to claim 17, characterized in that: The oxide includes SiO2.

19. The semiconductor device according to claim 17, characterized in that: The nitrides include SiN or AlN.

20. The semiconductor device according to claim 15, characterized in that: The thickness of the thin dielectric layer is no greater than 4 nm.

21. The semiconductor device according to claim 15, characterized in that: The drain opening and / or the source opening are trapezoidal in shape, wider at the top and narrower at the bottom, and include two inclined sides.

22. The semiconductor device according to claim 21, characterized in that: The angle between the side surface and the upper surface of the channel layer is no greater than 80°.

23. The semiconductor device according to claim 15, characterized in that, The semiconductor device further includes: Substrate layer; A buffer layer located between the substrate layer and the channel layer; Gate structure located on the barrier layer; A first dielectric layer covering the gate structure.

24. The semiconductor device according to claim 23, characterized in that: The thin dielectric layer covers not only the drain opening and / or source opening, but also the gate structure.

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