Alignment mark structure for SGT semiconductor device and preparation method of SGT semiconductor chip

Abstract

The application discloses a kind of alignment mark structure for SGT semiconductor device and the preparation method of SGT semiconductor chip, the alignment mark structure for SGT semiconductor device includes: alignment sub-mark and anti-static polysilicon;The alignment sub-mark is formed on substrate and epitaxial layer, and the material of the alignment sub-mark is silicon oxide, and the material of epitaxial layer is silicon;The anti-static polysilicon is formed on substrate and epitaxial layer, and the anti-static polysilicon is used to quickly guide the static electricity ESD of alignment sub-mark area to substrate.The application has the advantages of improving alignment accuracy and reducing electrostatic damage to alignment sub-mark.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to alignment marking of semiconductor devices, and more particularly to an alignment marking structure for SGT semiconductor devices and a method for fabricating SGT semiconductor chips. Background Technology

[0002] like Figure 1-4 As shown, the existing methods for fabricating SGT semiconductor devices are as follows: S1: Provide a substrate 100; S2: Form an epitaxial layer 102 (drift region) on the substrate 100; Perform exposure, development, etching, and other processes on the epitaxial layer 102 to form a trench 104; S3: Form a polysilicon material layer 105 covering the surface of the epitaxial layer 102, and the polysilicon material layer 105 fills the trench 104; S4: The thickness of the polysilicon material layer 105 is approximately 8000 Å to 10000 Å, therefore... Figure 3 The polysilicon material layer 105 is subjected to CMP chemical mechanical polishing; then alignment marks 106 are formed; S5: the fabrication of the SGT semiconductor device is completed; S6: after the SGT semiconductor device is formed, the substrate 100 needs to be thinned, and then a metal film layer 108 is formed on the back side of the substrate 100. The alignment marks 106 are used to form the gate polysilicon, the channel layer, and the source doped layer.

[0003] However, in this preparation method, the alignment marker 106 is made of polycrystalline silicon, which has a reflectivity close to that of the epitaxial layer 102, resulting in low contrast and reduced alignment accuracy. In existing alignment techniques, infrared irradiation of the 106 region is used; however, due to the similar reflectivity of 106 and 102, the alignment equipment faces increased difficulty in identification. Furthermore, the CMP process causes issues with the alignment marker 106, such as… Figure 4 The sharp corner at 106a, where 106a is a concave shape with a lower center and higher ends, is susceptible to ESD discharge during the manufacturing process. This discharge can cause the alignment mark 106 to burn or become damaged, reducing alignment accuracy or preventing proper alignment. Consequently, this lowers the yield of semiconductor device fabrication. Furthermore, during the polishing process, the epitaxial layer 102 may wear down or crack at 106b. When ESD occurs on or near the alignment mark 106, 102 is easily burned or damaged at 106b, making it impossible to grasp the edge of 106 during alignment and hindering proper focusing. This leads to alignment failure or poor alignment accuracy, further reducing the yield of semiconductor device fabrication. To improve alignment accuracy, an alignment mark structure for SGT semiconductor devices and a method for fabricating SGT semiconductor chips are proposed. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art.

[0005] Therefore, this invention proposes an alignment marking structure for SGT semiconductor devices and a method for fabricating SGT semiconductor chips. The alignment marking structure for SGT semiconductor devices has the advantages of improving alignment accuracy and reducing electrostatic damage to alignment markings.

[0006] The alignment mark structure for an SGT semiconductor device according to an embodiment of the present invention includes: an alignment mark and an antistatic polysilicon; the alignment mark is formed on a substrate and an epitaxial layer, the alignment mark is made of silicon oxide, and the epitaxial layer is made of silicon; the antistatic polysilicon is formed on the substrate and the epitaxial layer, and the antistatic polysilicon is used to quickly guide the electrostatic ESD of the alignment mark region to the substrate.

[0007] Silicon oxide is used as the material for the alignment marker to distinguish the reflectivity of the alignment marker from that of the epitaxial layer to infrared light, so as to accurately identify the edge region of the alignment marker. In addition, since the antistatic polysilicon is extended into the substrate, the low resistance of the antistatic polysilicon and the substrate can quickly guide the electrostatic ESD of the alignment marker region to the substrate, reducing damage to the alignment marker.

[0008] According to one embodiment of the present invention, the number of alignment sub-marks is multiple, and the multiple alignment sub-marks are set at intervals.

[0009] By employing multiple alignment sub-markers, multi-point positioning is achieved, further improving the accuracy of alignment.

[0010] According to one embodiment of the present invention, the number of antistatic polysilicon is multiple, and the multiple antistatic polysilicon and multiple alignment markers are interspersed.

[0011] A method for fabricating an SGT semiconductor chip, comprising the following steps: Step S1. Providing a substrate; heavily doping the substrate to serve as the drain doped layer of the SGT semiconductor device; aligning the substrate with the alignment mark x of the exposure machine, and forming a plurality of first grooves on the substrate through an exposure, development and etching process. Step S2. An epitaxial layer is formed covering the upper surface of the substrate through epitaxial and doping processes, and the epitaxial layer fills the first groove; Step S3. Form a second groove and a third groove from the upper surface of the epitaxial layer. The sidewall of the second groove is flush with the sidewall of the first groove. The number of second grooves is the same as the number of first grooves and they correspond one-to-one. The corresponding second grooves and the first grooves form a complete groove. The multiple grooves are anti-static grooves and alignment grooves, respectively. The third groove is an SGT device groove. Step S4. A gate dielectric layer is formed on the inner wall of the SGT device recess, and a shielding gate polysilicon is formed within the gate dielectric layer; an antistatic polysilicon is formed within the antistatic recess. Step S5. An isolation layer is formed above the shielding gate polysilicon in the gate dielectric layer, and an alignment groove is filled to form an alignment sub-marker. The isolation layer and the alignment sub-marker are both made of silicon oxide. Step S6. Form a gate polysilicon layer above the isolation layer in the gate dielectric layer, and form a channel layer on the epitaxial layer, so that the channel layer is adjacent to the gate dielectric layer.

[0012] According to one embodiment of the present invention, it further includes: Step S71. Thin the substrate from the back side to expose the bottom end face of the antistatic polycrystalline silicon and the alignment mark. Then, thin the substrate by dry etching so that the bottom of the alignment mark protrudes 100-500 nanometers from the lower surface of the substrate. Step S72. A back metal material layer is formed by PVD; at this time, the antistatic polysilicon and the alignment marker, as well as the gap between the antistatic polysilicon and the alignment marker, form the alignment marker region; Step S73. The AOI equipment establishes a coordinate system with the alignment mark area and detects defects in the back metal material layer; Step S74. Align the back metal material layer mask with the alignment sub-marks in the alignment mark area, and pattern the back metal material layer by removing the back metal material layer at the substrate edge and the dicing area to form metal.

[0013] By protruding the antistatic polysilicon and alignment marks from the substrate, alignment marking can be performed based on the antistatic polysilicon and alignment marks during subsequent production processes, meeting the user's self-etching needs and ensuring etching accuracy.

[0014] According to one embodiment of the present invention, in step S3, the alignment mark on the mask of the second groove is aligned with the alignment mark x on the exposure machine stage, and the second groove and the third groove are formed by processes such as exposure, development and etching.

[0015] According to one embodiment of the present invention, in step S4, an atomic layer deposition process is used to form a gate dielectric material layer covering the antistatic groove, the alignment groove, and the sidewall of the SGT device groove. The mask of the gate dielectric material layer is aligned with the alignment mark x on the exposure machine. The gate dielectric material layer in the antistatic groove and the alignment groove is removed by processes such as exposure, development, and etching, leaving only the gate dielectric layer covering the SGT device groove.

[0016] According to an embodiment of the present invention, in step S4, a first polysilicon material layer covering the epitaxial layer is formed by chemical vapor deposition. The first polysilicon material layer fills the antistatic groove, the alignment groove, and the SGT device groove. Then, the first polysilicon material layer is subjected to a chemical mechanical polishing (CMP) process, and the remaining first polysilicon material layer fills the antistatic groove, the alignment groove, and the SGT device groove. Next, the alignment mark on the mask of the first polysilicon material layer is aligned with the alignment mark x on the exposure machine. The first polysilicon material layer in the antistatic groove, the alignment groove, and the SGT device groove is subjected to an exposure, development, and etching process to remove the first polysilicon material layer in the alignment groove and part of the first polysilicon material layer in the SGT device groove, forming a shielding gate polysilicon layer filling the SGT device groove and an antistatic polysilicon layer filling the antistatic groove.

[0017] According to one embodiment of the present invention, step S5 includes: Step S51. A dielectric material layer is formed by chemical vapor deposition, which covers the surface of the epitaxial layer and fills the alignment groove and SGT device groove.

[0018] Step S52. Remove the dielectric material layer on the surface of the epitaxial layer by dry etching process; Step S53. Align the mask of the dielectric material layer with the alignment mark x of the exposure machine, and form an isolation layer that fills the groove of the SGT device and an alignment sub-mark in the alignment groove through processes such as exposure, development and etching.

[0019] According to one embodiment of the present invention, step S6 includes: Step S61. A second polysilicon material layer covering the surface of the epitaxial layer is formed by chemical vapor deposition. The mask of the second polysilicon material layer is aligned with the alignment marker, and then the second polysilicon material is subjected to exposure, development and etching processes to form a gate polysilicon layer that fills the groove of the SGT device. Step S62. Align the channel layer mask with the alignment marker, and form a channel layer that is located on both sides of the gate polysilicon layer and in contact with the gate dielectric layer through a doping process.

[0020] Step S63. An epitaxial material layer is formed on the epitaxial layer through epitaxial and doping processes. The epitaxial material layer mask is aligned with the alignment marker. The epitaxial material layer is formed into a source doped layer electrically connected to the channel layer through processes such as exposure, development and etching.

[0021] The beneficial effects of this invention are that it uses silicon oxide as the material for the alignment marker to distinguish the reflectivity of the alignment marker from that of the epitaxial layer to infrared light, so as to accurately identify the edge region of the alignment marker; in addition, since the antistatic polycrystalline silicon is extended into the substrate, the electrostatic ESD of the alignment marker region can be quickly guided to the substrate by utilizing the low resistance of the antistatic polycrystalline silicon and the substrate resistance, thereby reducing damage to the alignment marker.

[0022] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention.

[0023] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0024] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a top view of the alignment marks on an existing chip; Figure 2 This is a schematic diagram of the groove position at section A-A1 in step S2 of the existing preparation method; Figure 3 This is a schematic diagram of the groove position at section A-A1 in step S3 of the existing preparation method; Figure 4 This is a schematic diagram showing the defect location of the alignment marker in the existing preparation method; Figure 5 This is a cross-sectional schematic diagram of step S1 of the present invention; Figure 6 This is a cross-sectional schematic diagram of step S2 of the present invention; Figure 7 This is a cross-sectional schematic diagram of step S3 of the present invention; Figure 8 This is a cross-sectional schematic diagram of step S4 of the present invention; Figure 9 This is a cross-sectional schematic diagram of step S5 of the present invention; Figure 10 This is a cross-sectional schematic diagram of step S7 of the present invention; Figure 11 This is a cross-sectional schematic diagram of step S6 of the present invention; Figure 12 This is a bottom view of the alignment marking area of ​​the present invention; Figure 13 This is a schematic diagram of the present invention showing that the upper surface of the position marker is lower than the upper surface of the epitaxial layer.

[0025] Figure label: 1. First trench; 200. Substrate; 201. Epitaxial layer; 202. SGT device trench; 204. Antistatic trench; 206. Alignment trench; 208. Gate dielectric layer; 210. Shielding gate polysilicon; 212. Antistatic polysilicon; 214. Alignment marker; 216. Isolation layer; 218. Gate polysilicon; 220. Channel layer; 222. Source doped layer; 224. Metal; 500. Alignment marker region. Detailed Implementation

[0026] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0027] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, features defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0028] The following is a reference appendix. Figure 1-13 The specific description includes the alignment mark structure for SGT semiconductor devices and the fabrication method of SGT semiconductor chips according to embodiments of the present invention.

[0029] Example 1: The alignment mark structure for SGT semiconductor devices includes: alignment mark 214 and antistatic polysilicon 212; alignment mark 214 is formed on substrate 200 and epitaxial layer 201, alignment mark 214 is made of silicon oxide, and epitaxial layer 201 is made of silicon; antistatic polysilicon 212 is formed on substrate 200 and epitaxial layer 201, and antistatic polysilicon 212 is used to quickly guide electrostatic ESD in the alignment mark 214 region to substrate 200.

[0030] Silicon oxide is used as the material for the alignment marker 214 to differentiate its infrared reflectivity from that of the epitaxial layer 201, facilitating precise identification of the edge region of the alignment marker 214. Furthermore, since the antistatic polysilicon 212 extends into the substrate 200, the low resistance of both the antistatic polysilicon 212 and the substrate 200 allows for rapid conduction of ESD from the alignment marker 214 region to the substrate 200, reducing damage to the alignment marker 214. Additionally, since both the alignment marker 214 and the antistatic polysilicon 212 extend into the substrate 200, they continue to play a crucial role in precise positioning during the subsequent fabrication of the lower surface metal 224 of the substrate 200, improving yield. Moreover, the electrical connection between the antistatic polysilicon 212 and the metal 224 allows for the release of static electricity between the epitaxial layer 201 and the metal 224.

[0031] Example 2: The difference from Embodiment 1 is that: there are multiple alignment marks 214, and the multiple alignment marks 214 are spaced apart, with an antistatic polysilicon 212 between each pair of adjacent alignment marks 214; and there is a gap between the alignment marks 214 and the antistatic polysilicon 212.

[0032] By employing multiple alignment sub-markers 214 and multiple anti-static polycrystalline silicon 212, multi-point positioning is achieved, further improving the accuracy of alignment.

[0033] A method for fabricating an SGT semiconductor chip, used to fabricate any alignment mark structure and an SGT semiconductor chip for an SGT semiconductor device, includes the following steps: Step S1. Provide a substrate 200; heavily dope the substrate 200 to serve as the drain doping layer for the SGT semiconductor device; align the substrate mask with the alignment mark x of the exposure machine, and form multiple first grooves 1 on the substrate 200 through exposure, development, and etching processes.

[0034] Step S2. An epitaxial layer 201 is formed covering the upper surface of the substrate 200 through epitaxial and doping processes, and the epitaxial layer 201 fills the first groove 1.

[0035] Step S3. A second groove and a third groove are formed on the upper surface of the epitaxial layer 201. The sidewall of the second groove is flush with the sidewall of the first groove 1. The number of second grooves is the same as that of the first groove 1 and they correspond one-to-one. The corresponding second grooves and the first groove 1 form a complete groove. The multiple grooves are anti-static grooves 204 and alignment grooves 206, and the third groove is an SGT device groove 202.

[0036] Specifically, the alignment mark on the mask of the second groove is aligned with the alignment mark x on the exposure machine, and the second groove and the third groove are formed through processes such as exposure, development and etching.

[0037] Step S4. A gate dielectric layer 208 is formed on the inner wall of the SGT device recess 202, and a shielding gate polysilicon 210 is formed in the gate dielectric layer 208; an antistatic polysilicon 212 is formed in the antistatic recess 204.

[0038] Specifically, an atomic layer deposition process is used to form a gate dielectric material layer covering the sidewalls of the antistatic groove 204, the alignment groove 206, and the SGT device groove 202. The mask of the gate dielectric material layer is aligned with the alignment mark x on the exposure machine. Through processes such as exposure, development, and etching, the gate dielectric material layer in the antistatic groove 204 and the alignment groove 206 is removed, leaving only the gate dielectric layer 208 covering the SGT device groove 202.

[0039] A first polysilicon material layer covering the epitaxial layer 201 is formed using a chemical vapor deposition (CVD) process. This first polysilicon material layer fills the antistatic trench 204, alignment trench 206, and SGT device trench 202. Then, the first polysilicon material layer undergoes a chemical mechanical polishing (CMP) process, leaving the remaining first polysilicon material layer filling the antistatic trench 204, alignment trench 206, and SGT device trench 202. Next, the alignment marks on the mask of the first polysilicon material layer are aligned with the alignment mark x on the exposure machine. An exposure, development, and etching process is then performed on the first polysilicon material layer within the antistatic trench 204, alignment trench 206, and SGT device trench 202 to remove a portion of the first polysilicon material layer within the alignment trench 206 and the SGT device trench 202, forming a shielding gate polysilicon 210 filling the SGT device trench 202 and an antistatic polysilicon 212 filling the antistatic trench 204.

[0040] Step S5. An isolation layer 216 is formed above the shielding gate polysilicon 210 in the gate dielectric layer 208, and an alignment groove 206 is filled to form an alignment sub-mark 214. The isolation layer 216 and the alignment sub-mark 214 are both made of silicon oxide.

[0041] Specifically, in step S51, a dielectric material layer is formed by chemical vapor deposition, which covers the surface of the epitaxial layer 201 and fills the alignment groove 206 and the SGT device groove 202.

[0042] Step S52. Remove the dielectric material layer on the surface of the epitaxial layer 201 by dry etching process; Step S53. The photomask of the dielectric material layer is aligned with the alignment mark x of the exposure machine. Through processes such as exposure, development, and etching, an isolation layer 216 is formed to fill the SGT device groove 202, and an alignment sub-mark 214 is formed in the alignment groove 206. The upper surface of the alignment sub-mark 214 is flush with the upper surface of the epitaxial layer 201, serving as an alignment mark for subsequent film layers, which can improve the alignment effect. That is, infrared light is used to irradiate the epitaxial layer 201 and the alignment sub-mark 214. Since the reflectivity of the epitaxial layer 201 and the alignment sub-mark 214 to infrared light is significantly different, the accuracy of the alignment equipment in identifying the entire alignment mark area 500 is improved, thereby improving the manufacturing yield.

[0043] like Figure 13 As shown, a dry etching process can also be used to form alignment marker 214, and the upper surface of alignment marker 214 is lower than the upper surface of epitaxial layer 201, with a height difference of 100 nanometers to 500 nanometers, so that natural light can be used for alignment through the step or infrared light can be used for alignment.

[0044] Step S6. A gate polysilicon 218 is formed above the isolation layer 216 in the gate dielectric layer 208, and a channel layer 220 is formed on the epitaxial layer 201, such that the channel layer 220 is adjacent to the gate dielectric layer 208.

[0045] Specifically, in step S61, a second polysilicon material layer is formed covering the surface of the epitaxial layer 201 by chemical vapor deposition. The mask of the second polysilicon material layer is aligned with the alignment mark 214, and then the second polysilicon material is subjected to exposure, development and etching processes to form a gate polysilicon layer 218 that fills the groove 202 of the SGT device.

[0046] Step S62. Align the channel layer mask with the alignment mark 214, and form the channel layer 220 on both sides of the gate polysilicon layer 218 and in contact with the gate dielectric layer 208 through a doping process.

[0047] Step S63. An epitaxial material layer is formed on the epitaxial layer 201 through epitaxial and doping processes. The epitaxial material layer mask is aligned with the alignment marker 214. The epitaxial material layer is formed into a source doped layer 222 electrically connected to the channel layer 220 through processes such as exposure, development and etching.

[0048] The isolation layer 216 is used to electrically isolate and shield the gate polysilicon 210 and the gate polysilicon layer 218. Subsequently, a source metal layer electrically connected to the source doped layer 222 is formed, which can be done by referring to existing process technology.

[0049] Step S71. Thin the substrate 200 from the back side to expose the bottom end face of the antistatic polysilicon 212 and the alignment mark 214. Then, thin the substrate 200 by dry etching so that the bottom of the alignment mark 214 protrudes 100 nm to 500 nm from the lower surface of the substrate 200.

[0050] Step S72. A back metal material layer is formed by PVD; at this time, the antistatic polysilicon 212 and the alignment mark 214 and the spacing between the antistatic polysilicon 212 and the alignment mark 214 form an alignment mark region 500.

[0051] Step S73. The AOI equipment establishes a coordinate system with the alignment mark area 500 and detects defects in the back metal material layer.

[0052] Step S74. The back metal material layer mask is aligned with the alignment sub-marks 214 in the alignment mark area 500. The back metal material layer is patterned by removing the back metal material layer at the edge of the substrate 200 and in the dicing area to form metal 224. During alignment, the accuracy of the alignment marks on the mask is determined by the distance from both sides of the alignment marks to both sides of the alignment sub-marks 214, or by the distance from both sides of the alignment marks to the epitaxial layers 201 on both sides of the alignment sub-marks 214. In other words, the accuracy of the alignment is determined by whether the marks are centered.

[0053] In existing fabrication methods, the metal 108 formed on the back side of the substrate 100 is a single piece of metal, which has the following problems: 1. It can easily cause substrate 100 to warp. After warping, the cracks in the film layer on substrate 100, especially at the dicing location and the edge of substrate 100, will expand and reduce reliability.

[0054] 2. Since there are no alignment marks on the back side of the substrate 100, the defects of the metal 108 formed by PVD process cannot be detected by optical inspection equipment such as AOI.

[0055] When different users subsequently use photolithography to etch metal 108 according to their needs, metal 108 has no alignment marks, making it inconvenient for users to etch.

[0056] By protruding the antistatic polysilicon 212 and the alignment mark 214 from the substrate 200, alignment marking can be performed according to the antistatic polysilicon 212 and the alignment mark 214 in the subsequent production process, which meets the user's self-etching needs and ensures the accuracy of etching.

[0057] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0058] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A alignment mark structure for SGT semiconductor devices, characterized in that, include: Alignment marker (214), the alignment marker (214) is formed on substrate (200) and epitaxial layer (201), the alignment marker (214) is made of silicon oxide and the epitaxial layer (201) is made of silicon; Antistatic polysilicon (212) is formed on a substrate (200) and an epitaxial layer (201) for rapidly guiding electrostatic ESD of the alignment marker (214) region to the substrate (200).

2. The alignment mark structure for SGT semiconductor devices according to claim 1, characterized in that, The number of the alignment sub-marks (214) is multiple, and the multiple alignment sub-marks (214) are spaced apart.

3. The alignment mark structure for SGT semiconductor devices according to claim 2, characterized in that, The number of antistatic polysilicon (212) is multiple, and multiple antistatic polysilicon (212) and multiple alignment marks (214) are interspersed.

4. A method for fabricating an SGT semiconductor chip, used to fabricate an alignment mark structure for an SGT semiconductor device as described in any one of claims 1-3, characterized in that, Includes the following steps: Step S1. Provide a substrate (200); heavily dope the substrate (200) to serve as the drain doping layer of the SGT semiconductor device; align the substrate mask with the alignment mark x of the exposure machine, and form multiple first grooves (1) on the substrate (200) through exposure, development and etching processes. Step S2. An epitaxial layer (201) is formed covering the upper surface of the substrate (200) through epitaxial process and doping process, and the epitaxial layer (201) fills the first groove (1). Step S3. A second groove and a third groove are formed on the upper surface of the epitaxial layer (201). The sidewall of the second groove is flush with the sidewall of the first groove (1). The number of second grooves and first grooves (1) are the same and correspond one-to-one. The corresponding second grooves and first grooves (1) form a complete groove. The multiple grooves are antistatic grooves (204) and alignment grooves (206), respectively. The third groove is an SGT device groove (202). Step S4. A gate dielectric layer (208) is formed on the inner wall of the SGT device recess (202), and a shielding gate polysilicon (210) is formed in the gate dielectric layer (208); an antistatic polysilicon (212) is formed in the antistatic recess (204). Step S5. An isolation layer (216) is formed above the shielding gate polysilicon (210) in the gate dielectric layer (208), and an alignment groove (206) is filled to form an alignment sub-mark (214). The isolation layer (216) and the alignment sub-mark (214) are both made of silicon oxide. Step S6. A gate polysilicon (218) is formed above the isolation layer (216) in the gate dielectric layer (208), and a channel layer (220) is formed on the epitaxial layer (201) so that the channel layer (220) is adjacent to the gate dielectric layer (208).

5. The method for fabricating an SGT semiconductor chip according to claim 4, characterized in that, Also includes: Step S71. Thin the substrate (200) from the back side of the substrate (200) to expose the bottom end face of the antistatic polycrystalline silicon (212) and the alignment mark (214). Then, thin the substrate (200) by dry etching process so that the bottom of the alignment mark (214) protrudes 100 nm to 500 nm from the lower surface of the substrate (200). Step S72. A back metal material layer is formed by PVD; at this time, the antistatic polysilicon (212) and the alignment sub-marker (214) and the interval between the antistatic polysilicon (212) and the alignment sub-marker (214) form an alignment mark region (500). Step S73. The AOI equipment establishes a coordinate system with the alignment mark area (500) and detects defects in the back metal material layer; Step S74. Align the back metal material layer mask with the alignment sub-mark (214) in the alignment mark area (500) to pattern the back metal material layer and form metal (224).

6. The method for fabricating an SGT semiconductor chip according to claim 4, characterized in that, In step S3, the alignment mark on the mask of the second groove is aligned with the alignment mark x on the exposure machine stage, and the second groove and the third groove are formed by processes such as exposure, development and etching.

7. The method for fabricating an SGT semiconductor chip according to claim 4, characterized in that, In step S4, an atomic layer deposition process is used to form a gate dielectric material layer covering the sidewalls of the antistatic groove (204), the alignment groove (206), and the SGT device groove (202). The mask of the gate dielectric material layer is aligned with the alignment mark x on the exposure machine. The gate dielectric material layer in the antistatic groove (204) and the alignment groove (206) is removed by exposure, development, etching and other processes, leaving only the gate dielectric layer (208) covering the SGT device groove (202).

8. The method for fabricating an SGT semiconductor chip according to claim 4, characterized in that, In step S4, a first polysilicon material layer covering the epitaxial layer (201) is formed by chemical vapor deposition. The first polysilicon material layer is filled with antistatic grooves (204), alignment grooves (206), and SGT device grooves (202). Then, the first polysilicon material layer is subjected to CMP chemical mechanical polishing. The remaining first polysilicon material layer is filled with antistatic grooves (204), alignment grooves (206), and SGT device grooves (202). Next, the alignment marks on the mask of the first polysilicon material layer are... Align with the alignment mark x on the exposure machine, and perform exposure, development and etching processes on the first polysilicon material layer in the antistatic groove (204), alignment groove (206) and SGT device groove (202) to remove the first polysilicon material layer in the alignment groove (206) and part of the first polysilicon material layer in the SGT device groove (202) to form a shielding gate polysilicon (210) filling the SGT device groove (202) and an antistatic polysilicon layer (212) filling the antistatic groove (204).

9. The method for fabricating an SGT semiconductor chip according to claim 4, characterized in that, Step S5 includes: Step S51. A dielectric material layer is formed by chemical vapor deposition process, which covers the surface of the epitaxial layer (201) and fills the alignment groove (206) and SGT device groove (202). Step S52. Remove the dielectric material layer on the surface of the epitaxial layer (201) by dry etching process; Step S53. Align the mask of the dielectric material layer with the alignment mark x of the exposure machine, and form an isolation layer (216) in the groove (202) of the SGT device and an alignment sub-mark (214) in the alignment groove (206) through processes such as exposure, development and etching.

10. The method for fabricating an SGT semiconductor chip according to claim 4, characterized in that, Step S6 includes: Step S61. A second polysilicon material layer covering the surface of the epitaxial layer (201) is formed by chemical vapor deposition. The mask of the second polysilicon material layer is aligned with the alignment mark (214), and then the second polysilicon material is exposed, developed and etched to form a gate polysilicon layer (218) filling the groove (202) of the SGT device. Step S62. Align the channel layer mask with the alignment mark (214) and form a channel layer (220) that is in contact with the gate dielectric layer (208) on both sides of the gate polysilicon layer (218) through a doping process. Step S63. Through epitaxial process and doping process, an epitaxial material layer is formed on the epitaxial layer (201). The epitaxial material layer mask is aligned with the alignment marker (214). Through exposure, development and etching processes, a source doped layer (222) electrically connected to the channel layer (220) is formed on the epitaxial material layer.

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