A semiconductor device and a method of fabricating the same

Abstract

The application relates to a semiconductor device and a preparation method thereof. The semiconductor device comprises a III-V compound epitaxial body, a gate stack structure, a multi-step continuous field plate structure, and a drain and a source, wherein the III-V compound epitaxial body comprises a channel layer and a barrier layer; the gate stack structure comprises a gate control layer and a gate electrode located above the gate control layer, and the gate electrode and the gate control layer form steps on a source side and a drain side respectively; the steps comprise a first dielectric layer covering a gate electrode sidewall, and a second dielectric layer covers the first dielectric layer sidewall and the gate control layer sidewall; the multi-step continuous field plate structure is located in a gate-drain region of the epitaxial body; and the distance between the source and the gate electrode is the dielectric layer thickness of the gate electrode sidewall. The application improves the breakdown voltage of the device by smoothing the electric field in the device, reduces the parasitic resistance of the device, and further improves the device performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] III-V group semiconductor materials (such as gallium nitride, GaN) are widely used in high-frequency, high-power electronic devices due to their advantages such as wide bandgap, high breakdown electric field, fast electron saturation drift velocity, and high temperature resistance. A typical example is the high electron mobility transistor (HEMT) device. Because HEMT devices are prone to generating strong local electric fields in the gate-drain region under high voltage operation, which can lead to premature breakdown, current collapse, and decreased reliability, a field plate structure is usually incorporated into the device. The field plate can modulate the electric field distribution on the device surface, reducing local electric field peaks and thus improving the device's breakdown voltage, stability, and reliability. Depending on the connection method, field plates can include gate field plates, source field plates, and floating field plates. Different types of field plates have different characteristics in terms of electric field modulation effect, parasitic capacitance, and high-frequency performance, thus becoming an important electric field modulation structure in HEMT devices.

[0003] Furthermore, since the source-gate region of a HEMT device does not bear the device breakdown voltage, and significant parasitic resistance is generated when the source-gate pitch is large, HEMT devices typically need to minimize the source-gate pitch. However, due to the limitations of lithography machine precision, the source-gate pitch becomes difficult to further reduce after reaching a certain distance. Summary of the Invention

[0004] In view of the technical problems existing in the prior art, the present invention proposes a semiconductor device and its fabrication method, which can improve the breakdown voltage of the device and reduce the parasitic resistance of the device by smoothing the electric field in the device.

[0005] To address the aforementioned technical problems, according to one aspect of the present invention, a semiconductor device is provided, comprising: A III-V compound epitaxial body, comprising a channel layer and a barrier layer, wherein a heterojunction is formed between the channel layer and the barrier layer, and a two-dimensional carrier gas is formed at the interface of the heterojunction. A gate stack structure includes a gate control layer located above the barrier layer in the gate region of an epitaxial body and a gate located above the gate control layer, wherein the gate and the gate control layer form steps on the source side and the drain side, respectively; the steps include a first dielectric layer covering the sidewall of the gate, and a second dielectric layer covering the sidewall of the first dielectric layer and the sidewall of the gate control layer. A multi-stage continuous field plate structure located in the gate drain region of the epitaxial body; The drain and source are formed in the drain region and source region of the epitaxial body, respectively, and are electrically connected to the two-dimensional carrier gas. The distance between the source and the gate is the dielectric thickness of the gate sidewall.

[0006] According to another aspect of the present invention, the present invention also provides a method for fabricating a semiconductor device, comprising: Provide a III-V compound epitaxial body, including a channel layer and a barrier layer thereon, wherein a heterojunction is formed between the channel layer and the barrier layer, and a two-dimensional carrier gas is formed at the interface of the heterojunction. A gate stack structure is formed in the gate region defined above the epitaxial body, including a gate control layer above the barrier layer in the gate region of the epitaxial body and a gate above the gate control layer. The gate and the gate control layer form steps on the source side and the drain side, respectively. The steps include a first dielectric layer covering the sidewall of the gate, and a second dielectric layer covers the sidewall of the first dielectric layer and the sidewall of the gate control layer. A multi-stage continuous field plate structure is provided in the gate drain region of the epitaxial body; The drain region and source region of the epitaxial body form the drain and source, respectively, and the drain and source are electrically connected to the two-dimensional carrier gas. The distance between the source and the gate is the total thickness of the first dielectric layer and the second dielectric layer of the gate sidewall.

[0007] This invention achieves a smooth transition of the internal electric field of the device through a series of multi-level field plates, thereby effectively improving the breakdown voltage of the device. This invention utilizes a mask on the sidewall of the gate stack for self-aligned source ohmic contact etching, achieving stable control of the source-gate distance, reducing the difficulty of photolithography and the parasitic resistance caused by the source-gate distance. Attached Figure Description

[0008] The preferred embodiments of the present invention will now be described in further detail with reference to the accompanying drawings, wherein: Figure 1 This is a schematic diagram of the structure of a semiconductor device according to Embodiment 1 of the present invention; Figure 2 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention; Figure 3 This is a flowchart of a method for fabricating a semiconductor device according to Embodiment 1 of the present invention; Figure 4 It corresponds to Figure 3 A schematic diagram of the device structure corresponding to steps S101 to S108 in the semiconductor device fabrication process; Figure 5 It corresponds to Figure 3 A schematic diagram of the device structure corresponding to steps S109 to S112 in the semiconductor device fabrication process; Figure 6 This is a schematic diagram of some steps in the semiconductor device fabrication method according to Embodiment 2 of the present invention and the corresponding device structure. Figure 7 This is a schematic diagram of some steps in the semiconductor device fabrication method according to Embodiment 3 of the present invention and the corresponding device structure. Figure 8 This is a schematic diagram of the structural principle of a semiconductor device according to Embodiment 4 of the present invention; Figure 9 This is a schematic diagram of the structural principle of a semiconductor device according to Embodiment 5 of the present invention; Figure 10 This is a schematic diagram illustrating the structural principle of another semiconductor device according to Embodiment 5 of the present invention; Figure 11 This is a schematic diagram of the device structure corresponding to some steps in the semiconductor device fabrication method according to Embodiment Six of the present invention; Figure 12 This is a schematic diagram of the device structure corresponding to some steps in the semiconductor device fabrication method according to Embodiment 7 of the present invention; Figure 13 This is a schematic diagram of the structure of a semiconductor device according to Embodiment 8 of the present invention; Figure 14 This is a schematic diagram of the structure of another semiconductor device according to Embodiment 8 of the present invention; Figure 15 This is a schematic diagram of the device structure corresponding to some steps in the semiconductor device fabrication method according to Embodiment 9 of the present invention; Figure 16 This is a schematic diagram of the structure of another semiconductor device according to Embodiment 9 of the present invention; Figure 17 This is a schematic diagram of the structure of a semiconductor device according to Embodiment 10 of the present invention; Figure 18 A schematic diagram of the partial projection of the electrodes of the semiconductor device according to Embodiment Eleven of the present invention in the xy plane; Figure 19 It is along Figure 18 A schematic diagram of the side structure of one embodiment after being cut along line AA; Figure 20 It is along Figure 18 A schematic diagram of the side structure after the BB line is cut open; Figure 21 This is a schematic diagram of the structure of the field plate electrode and the source metal connected according to another embodiment of the present invention; Figure 22 This is a schematic diagram of the structure of a semiconductor device according to Embodiment Twelve of the present invention; Figure 23This is a partial structural schematic diagram of the overall structure of the semiconductor device according to Embodiment Thirteen of the present invention. Detailed Implementation

[0009] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0010] In the following detailed description, reference can be made to the accompanying drawings, which form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to implement the technical solutions of the present application. It should be understood that other embodiments may also be utilized, or structural, logical, or electrical changes may be made to the embodiments of the present application.

[0011] Whether it's an Emode (normally off) or Dmode (normally on) III-V semiconductor device, a field plate structure is typically required to control the electric field distribution on the device surface. One type of field plate structure is a multi-level discontinuous field plate structure. In fabricating this structure, a first-level field plate electrode metal layer is typically grown on the surface of an epitaxial layer, then etched to obtain the first-level field plate electrode. A dielectric layer and a second-level field plate electrode metal layer are then grown, followed by etching, and so on, resulting in multiple levels of field plate electrodes separated by dielectrics. However, due to the discontinuity of the field plate electrodes, while the surface electric field can be adjusted, the potential abrupt changes between the electrodes create a stepped electric field distribution, preventing the device from achieving the desired breakdown voltage. Furthermore, the fabrication process involves a multi-step field plate electrode etching process. Since the field plate electrode etching process can cause some over-etching of the underlying dielectric, the thickness of the field plate dielectric is difficult to control.

[0012] This invention provides a semiconductor device with a multi-stage continuous field plate structure. Through the continuous step structure, a smooth transition of field plate potential and electric field can be achieved, thereby improving the breakdown voltage of the device.

[0013] Example 1 See Figure 1 , Figure 1This is a schematic diagram of the structure of a semiconductor device according to Embodiment 1 of the present invention. In this embodiment, the semiconductor device includes a III-V compound epitaxial body 20, a gate stack structure 30, a multi-stage continuous field plate structure 40, and a source 32 and a drain 33. The III-V compound epitaxial body 20 is a multilayer structure epitaxially grown on a substrate 10, which includes at least a channel layer 210 and a barrier layer 220. A heterojunction is formed between the channel layer 210 and the barrier layer 220, and a two-dimensional carrier gas is formed at the interface of the heterojunction. The two-dimensional carrier gas can be a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG). The two-dimensional carrier gas shown in the figure is 2DEG. The gate stack structure 30 includes a gate control layer 300 located above the barrier layer 220 in the gate region of the epitaxial body 20, a gate 31 above the gate control layer 300, a first dielectric layer 310, and a second dielectric layer 320. The width of the gate 31 is smaller than the width of the gate control layer 300. Near the source 32 and drain 33, the gate 31 and the gate control layer 300 form a stepped structure. A first dielectric layer 310 is formed on the gate sidewall near the source 32 and drain 33 and on the upper surface of the gate control layer 300 of the lower stepped structure. In this embodiment, the second dielectric layer 320 covers the top of the gate sidewall, the sidewall of the first dielectric layer 310, and the sidewall of the gate control layer 300, extending into the non-gate region. The region corresponding to the gate stack structure 30 is the gate region. The regions where the source 32 and drain 33 are formed are the source region and drain region, respectively. The region between the drain 33 and the gate stack structure 30 is the gate-drain region. The gate-drain region is the region that carries high voltage. The gate-drain region is deposited with multi-level field plate dielectric steps 41. In this embodiment, it includes two levels of field plate dielectric steps. Each level of field plate dielectric step includes a first surface 411 parallel to the surface of the gate-drain region and a second surface 412 extending from the edge of the first surface to the surface of the gate-drain region. The first surface of the lower level field plate dielectric step connects to the second surface of the upper level field plate dielectric step. The first surface of the multi-level field plate dielectric steps 41 increases progressively from the gate to the drain. The first surface 411 and the second surface 412 of each level of field plate dielectric step form a continuous surface on which a continuous field plate electrode 42 is grown. The first surface of the multi-level field plate dielectric steps 41 is the surface of the second dielectric layer 320 covering the barrier layer 220 of the gate-drain region. In one embodiment, the height of the upper surface of the second dielectric layer 320 above the barrier layer 220 of the gate-drain region from the two-dimensional carriers is lower than or equivalent to the height of the upper surface of the gate control layer 300 from the two-dimensional carriers. In other words, the lowest point of the continuous field plate electrode 42 is lower than or equal to the height of the gate control layer 300 and close to the edge of the gate control layer 300, thereby further reducing the electric field strength at the edge of the gate semiconductor layer 310 and improving the device's withstand voltage capability.

[0014] In this embodiment, the continuous field plate electrode 42 extends from the surface of the gate-drain region to the sidewall of the gate stack structure 30, and further to a portion of the top of the gate stack structure 30. The upper surface of the continuous field plate electrode 42 is covered with a fourth dielectric layer 50. The source electrode 32 and the drain electrode 33 are formed in the drain region and source region of the epitaxial body 20, respectively, and are electrically connected to the two-dimensional carrier gas.

[0015] See Figure 2 , Figure 2 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention, the method comprising: Step S1, providing a III-V compound epitaxial body, including a channel layer and a barrier layer above it, wherein a heterojunction is formed between the channel layer and the barrier layer, and a two-dimensional carrier gas is formed at the interface of the heterojunction. Step S2: A gate stack structure is formed in the gate region defined above the epitaxial body, including a gate control layer above the barrier layer in the gate region of the epitaxial body and a gate above the gate control layer. The gate and the gate control layer form steps on the source side and the drain side, respectively. The steps include a first dielectric layer covering the sidewall of the gate, and a second dielectric layer covers the sidewall of the first dielectric layer and the sidewall of the gate control layer. Step S3: Provide a multi-stage continuous field plate structure in the gate-drain region of the epitaxial body; In step S4, the drain region and source region of the epitaxial body are respectively formed into a drain and a source. The drain and source are electrically connected to the two-dimensional carrier gas. The distance between the source and the gate is the total thickness of the first dielectric layer and the second dielectric layer of the gate sidewall.

[0016] This invention, through its multi-stage continuous field plate structure, effectively achieves a smooth transition between field plate potential and electric field, thereby improving the device's breakdown voltage. Since the field plate structure in this invention includes only one continuous field plate electrode, damage to the dielectric layer from metal etching is reduced, making it easier to control the field plate dielectric thickness. During source fabrication, this invention utilizes the dielectric of the gate stack structure sidewalls for self-alignment, reducing the precision requirements of photolithography. Furthermore, the gate-source spacing can be controlled by adjusting the dielectric thickness of the gate stack structure sidewalls, thereby reducing parasitic resistance between the gate and source and improving device performance.

[0017] Figure 3 This is a flowchart of a semiconductor device fabrication method according to Embodiment 1 of the present invention. Figure 4 It corresponds to Figure 3 The schematic diagram of the device structure from step S101 to step S108 in the semiconductor device fabrication process. Figure 5 It corresponds to Figure 3 The schematic diagram of the device structure from step S109 to step S1112 in the semiconductor device fabrication process is shown. (Combined with...) Figure 3 , Figure 4 and Figure 5 The method for fabricating semiconductor devices includes the following steps: Step S101: Provide a III-V compound epitaxial body 20. Specifically, a III-V compound epitaxial body 20 is provided on a substrate 10 through an epitaxial process. The substrate 10 can be made of various materials, such as III-V compounds, like GaN. Al2O3 (sapphire single crystal), crystalline silicon (Si), and silicon carbide (SiC) can also be used as substrates. When the substrate 10 is GaN, the upper surface of the substrate 10 is the (0001) plane or the (000-1) plane of GaN; when the substrate 10 is Si, the upper surface of the substrate 10 is the (111) plane of Si; when the substrate is sapphire, the upper surface of the substrate 10 is the (0001) plane of sapphire; when the substrate is SiC, the upper surface of the substrate 10 is the (0001) plane or the (000-1) plane of SiC. The substrate materials shown in the figure are only examples. In a preferred embodiment, sapphire is selected as the substrate. Then, a channel layer 210 and a first barrier layer 220 are sequentially epitaxially grown on the substrate 10. A heterojunction is formed between the channel layer 210 and the first barrier layer 220, and a two-dimensional carrier gas, such as a two-dimensional electron gas or a two-dimensional hole gas, is formed at the heterojunction interface.

[0018] The channel layer 210 can be an undoped or unintentionally doped gallium nitride (GaN) layer, or a gallium nitride (GaN) layer doped with one or more impurities. The first barrier layer 220 is made of one or more of the following materials: unintentionally doped aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum nitride (AlN), and aluminum indium gallium nitride (AlInGaN).

[0019] In step S102, a gate semiconductor layer 301 and a gate metal layer 31' are sequentially provided above the epitaxial body 20 from the first barrier layer 220 upwards. The gate semiconductor layer 301 serves as a gate control layer, and its type is adapted to the first barrier layer 220 and the channel layer 210. For example, when the first barrier layer 220 is AlGaN and the channel layer 210 is GaN, the gate semiconductor layer 301 is P-type GaN (or P-type AlGaN, AlN, InGaN, and a stacked structure composed of the above materials). The gate metal layer 31' is, for example, a titanium nitride (TiN) layer prepared by physical vapor deposition (PVD) or chemical vapor deposition (CVD), or a metal alloy composed of Ti, Al, W, Mo, Ni, Au, Zr, etc.

[0020] Step S103: Etch away the gate metal layer 31' in the non-gate region to obtain the gate 31 in the gate region above the gate semiconductor layer 301. In one embodiment, dry etching of the gate metal layer 31' (such as a TiN layer) is used to form a steep TiN sidewall morphology. The etching of the TiN layer can stop at the P-GaN layer or partially etch the P-GaN layer. In another embodiment, wet etching of the gate metal layer 31' can also be used, such as using solutions like H2O2, SPM, or SCl to etch the TiN layer. Of course, a combination of dry and wet etching can also be used to etch the gate metal layer 31', for example, dry etching of a portion of the TiN followed by wet etching to remove the remaining portion. The aforementioned pure H2O2 etching of TiN can also achieve a steep sidewall morphology >87deg, but dry etching has better etching anisotropy than wet etching, while wet etching has better etching selectivity.

[0021] Step S104: A first dielectric layer 310 is provided above the current structure. The first dielectric layer 310 covers the top, sidewalls, and upper surface of the first barrier layer 220 in the non-gate region of the gate 31. The first dielectric layer 310 is, for example, silicon dioxide (SiO2) or silicon nitride (SiN). x )wait.

[0022] Step S105: Etch away the first dielectric layer 310 and the underlying gate semiconductor layer 301 in the non-gate region to obtain the gate stack structure 30. The gate stack structure 30 can be obtained using dry etching, wet etching, or a combination of both. In this embodiment, after etching the first dielectric layer 310 in the non-gate region, etching continues using the first dielectric layer 310 as a mask to remove the gate semiconductor layer 301 in the non-gate region, forming a gate stack with a ledge structure. The distance between the sidewall of the gate 31 and the sidewall of the gate semiconductor layer 301 in the gate stack structure 30 is determined by the thickness of the first dielectric layer 310 on the sidewall of the gate 31. This embodiment also removes the first dielectric layer 310 on the upper surface of the gate 31; however, the first dielectric layer 310 on the upper surface of the gate 31 can also be retained.

[0023] In step S106, a second dielectric layer 320 and a field plate dielectric layer 410 are sequentially provided above the current structure. The second dielectric layer 320 covers the top, sidewalls, and upper surface of the first barrier layer 220 in the non-gate region of the gate stack structure 30. The second dielectric layer 320 and the field plate dielectric layer 410 are, for example, silicon dioxide (SiO2) and silicon nitride (SiN). x Silicon oxynitride (SiON) or aluminum oxide (Al2O3), etc. In one embodiment, the second dielectric layer 320 and the field plate dielectric layer 410 are different dielectric materials.

[0024] Step S107: Etch the field plate dielectric layer 410 to obtain multi-level field plate dielectric steps 41. For example, multi-level continuous field plate dielectric steps 41 are obtained by selecting the etching range and etching depth. In this embodiment, only the continuous field plate dielectric steps 41 of the gate-drain region are retained, and the field plate dielectric layer 410 of the source region, drain region, and the top and sidewalls of the gate stack structure 30 are etched away. Each level of field plate dielectric step includes a first surface 411 parallel to the surface of the gate-drain region and a second surface 412 extending from the edge of the first surface 411 to the surface of the gate-drain region. The first surface 411 of the lower level field plate dielectric step is connected to the second surface 412 of the upper level field plate dielectric step to form a continuous multi-level field plate dielectric step. The first surface of the multi-level field plate dielectric step increases progressively from the gate to the drain. The first surface 411 and the second surface 412 of each field plate dielectric step constitute a continuous step surface.

[0025] Step S108: Provide a field plate metal layer 421 on top of the current structure.

[0026] Step S109: Etch the field plate metal layer 421 to obtain a continuous field plate electrode 42. Specifically, the field plate metal layer 421 is etched away from the source region, drain region, sidewalls of the gate stack structure 30 near the source, and part of the top of the gate stack structure 30. Part of the top of the gate stack structure 30, sidewalls near the drain, the surface of the second dielectric layer 320 connecting the gate stack structure 30 and the gate-drain region of the multi-level field plate dielectric steps 41, and the surface of the continuous steps of the multi-level field plate dielectric steps 41 are retained to obtain the continuous field plate electrode 42.

[0027] In step S110, a fourth dielectric layer 50 is provided above the current structure, and the source and drain regions are etched to obtain drain contact openings and source contact openings. When etching the drain contact openings in the source region, the fourth dielectric layer 50 covering the gate stack structure 30 is used as a mask, and the dielectric material on the sidewalls of the gate stack structure 30 near the source region is etched according to a preset gate-source spacing. As shown in the figure, in this embodiment, all dielectric layers on the sidewalls of the gate stack structure 30 are retained during etching. However, it can be understood that a certain thickness of dielectric material can be etched as needed to meet the preset gate-source spacing.

[0028] Step S111: Provide an ohmic metal layer 32' on top of the current structure. The ohmic metal layer 32' can be a material such as Ti, Al, TiAl alloy, TiN, Ni, Au, Ta, Hf, or a stacked material composed of the above materials.

[0029] Step S112: Etch the ohmic metal layer 32' to obtain the source 32 and drain 33.

[0030] Example 2 See Figure 6 , Figure 6This is a schematic diagram of some steps and corresponding device structures in the semiconductor device fabrication method according to Embodiment 2 of the present invention. The difference between Embodiment 2 and Embodiment 1 lies in the deposition and etching of the field plate dielectric; therefore, this embodiment omits the same fabrication steps as Embodiment 1. After etching away the first dielectric layer 310 and the underlying gate semiconductor layer 301 in step S105 to obtain the gate stack structure 30, the following method is performed: Step S206 involves providing a second dielectric layer 320, a first stop layer 4101, a first field plate dielectric layer 4102, a second stop layer 4103, and a second field plate dielectric layer 4104. The stop layers are spaced apart from the field plate dielectric layers. The thickness of each field plate dielectric layer can be the same or different, and the deposition thickness can be precisely controlled according to design requirements. The stop layer may be, for example, Al2O3, AlN (or P-type AlN), AlGaN (or P-type AlGaN), etc., a dielectric layer that produces an etching selectivity or corrosion selectivity with the field plate dielectric such as SiO2 or SiN. The stop layer can be relatively thin, sufficient to achieve the etching stopping effect, for example, 1 nm to 10 nm.

[0031] Step S207 involves etching downwards from the top of the field plate dielectric layer according to preset dielectric step positions to remove the dielectric material of the corresponding field plate dielectric layer and the corresponding lower stop layer, thereby obtaining a multi-level field plate dielectric step 41. Since the field plate dielectric layer and the stop layer have a high etching selectivity, etching almost stops when reaching the stop layer from the field plate dielectric layer downwards, and then the stop layer is removed using a wet etching process. This allows for the obtaining of steps with precisely preset heights. Correspondingly, the step heights of each level of the continuous field plate electrode 42 grown on the continuous step surface are controllable, thereby achieving controllable electric field adjustment.

[0032] The other steps are the same as in Example 1, and will not be repeated here.

[0033] Example 3 See Figure 7 , Figure 7 This is a schematic diagram of some steps and corresponding device structures in the semiconductor device fabrication method according to Embodiment 3 of the present invention. The difference between Embodiment 3 and Embodiment 1 lies in the deposition and etching of the field plate dielectric; therefore, this embodiment omits the same fabrication steps as Embodiment 1. After etching away the first dielectric layer 310 of the non-gate region and the underlying gate semiconductor layer 301 in step S105 to obtain the gate stack structure 30, the following method is performed: In step S306, two field plate dielectric layers 4105 and 4106 are sequentially provided in the gate-drain region of the epitaxial body. The thickness of each field plate dielectric layer may be the same or different, and each field plate dielectric layer may have a different etching selectivity or corrosion selectivity. For example, the field plate dielectric layer 4105 may be SiO2 or SiN, and the field plate dielectric layer 4106 may be Al2O3 or AlN.

[0034] Step S307: Starting from the top of the field plate dielectric layer, etching is performed sequentially downwards according to the preset dielectric step positions to remove the dielectric of the corresponding layer, thereby obtaining a multi-level field plate dielectric step 41. Since each field plate dielectric layer has a different etching selectivity or corrosion selectivity, the etching can be precisely stopped at the surface of the lower dielectric layer, thus achieving precise control of the field plate step height.

[0035] The other steps are the same as in Example 1, and will not be repeated here.

[0036] Example 4 See Figure 8 , Figure 8 This is a schematic diagram of the structural principle of a semiconductor device according to Embodiment 4 of the present invention. In this embodiment, when etching the dielectric steps of the field plate, the etching angle is controlled to be 30-90 degrees, so that the included angle between the first surface 411 and the second surface 412 of the dielectric steps of the field plate is 90-150 degrees. Therefore, the continuous field plate electrode 42 forms a corresponding included angle of 90-150 degrees when covering the first surface 411 and the second surface 412 of the dielectric steps of the field plate 41, which improves the smoothness of the rise of the multi-level continuous field plate electrode 42 and can better transition the electric field to avoid electric field spikes.

[0037] Example 5 See Figure 9 , Figure 9 This is a schematic diagram illustrating the structural principle of a semiconductor device according to Embodiment 5 of the present invention. (Reference) Figure 3 and Figure 4 The first embodiment is shown. In this embodiment, the ohmic metal layer 32' is etched in step S112 of the first embodiment, and the second field plate electrode 43 is obtained by controlling the etching range. See also Figure 9 When etching the ohmic metal layer 32', a separate drain 33 is obtained, and the source 32 and the second field plate electrode 43 are connected together.

[0038] See Figure 10 , Figure 10 This is a schematic diagram of the structural principle of another semiconductor device according to Embodiment 5 of the present invention. Etching the ohmic metal layer 32' yields a separate drain 33, source 32, and second field plate electrode 43.

[0039] Example 6 See Figure 11 , Figure 11This is a schematic diagram of the device structure corresponding to some steps in the semiconductor device fabrication method according to Embodiment Six of the present invention. Most of the fabrication process in Embodiment Six is ​​the same as in Embodiment One; only the different fabrication processes are described below, omitting fabrication steps identical to those in Embodiment One. After providing the field plate dielectric layer 410 according to the same fabrication steps as in Embodiment One, in this embodiment, in step S407, while etching the field plate dielectric layer 410, the second dielectric layer 320 on top of the gate stack structure 30 is also etched until the gate 31 is exposed. In step S408, a field plate metal layer 421 is grown on the current structure. Then, in step S409, during the etching of the field plate metal layer 421, the source region, drain region, sidewalls of the gate stack structure 30 near the source, and part of the top of the field plate metal layer 421 are etched away. The inner surface of part of the top opening 3201 of the gate stack structure 30, the sidewalls near the drain, the surface of the second dielectric layer 320 connecting the gate stack structure 30 and the gate-drain region surface of the multi-level field plate dielectric steps 41, and the field plate metal layer on the continuous step surface of the multi-level field plate dielectric steps 41 are retained to obtain the continuous field plate electrode 42. In this embodiment, the continuous field plate electrode 42 is electrically connected to the gate 31. This effectively adjusts the height and number of electric field spikes at the gate edge, thereby improving the device's withstand voltage capability.

[0040] Example 7 See Figure 12 , Figure 12 This is a schematic diagram of the device structure corresponding to some steps in the semiconductor device fabrication method according to Embodiment 7 of the present invention. In this embodiment, some fabrication steps are the same as in Embodiment 1, therefore, the description of the steps that are the same as in Embodiment 1 is omitted in this embodiment, and only the differences are described below.

[0041] In step S502, a gate semiconductor layer 301, a gate metal layer 31', and a third dielectric layer 330 are sequentially provided above the epitaxial body 20 from the barrier layer 220 upwards.

[0042] Step S503: Etch away the third dielectric layer 330 and the gate metal layer 31' in the non-gate region to obtain the gate 31 in the gate region above the gate semiconductor layer 301 and the third dielectric layer 330 above it.

[0043] Step S504: A first dielectric layer 310 is provided above the current structure. The first dielectric layer 310 covers the top and sidewalls of the third dielectric layer 330 and the upper surface of the first barrier layer 220 in the non-gate region. The first dielectric layer 310 is, for example, silicon dioxide (SiO2) or silicon nitride (SiN). x )wait.

[0044] Step S505: Etch away the first dielectric layer 310 and the underlying gate semiconductor layer 301 in the non-gate region to obtain the gate stack structure 30.

[0045] Step S506: Extend a second barrier layer 221 above the current structure.

[0046] The subsequent fabrication process is the same as in Example 1 and will not be repeated here. In this embodiment, a second barrier layer 221 is provided above the barrier layer 220, which can increase the two-dimensional carrier gas concentration at the heterojunction interface, reduce the on-resistance of the device, and increase the adjustment range of the threshold voltage. In one embodiment, when the material of the barrier layer 220 is unintentionally doped aluminum gallium nitride (AlGaN), the material of the second barrier layer 221 is also unintentionally doped AlGaN, and the percentage content of the Al component in the second barrier layer 221 is greater than or equal to the percentage content of the Al component in the first barrier layer 220. For example, when the percentage content of the Al component in the first barrier layer 220 is 15%~35%, the percentage content of the aluminum (Al) component in the second barrier layer 221 is between 15% and 100%. In this embodiment, the upper surface of the gate 31 in the gate stack structure 30 also includes a third dielectric layer 330. On the one hand, since chlorine-based gases are typically used when etching the P-GaN layer, and these gases can etch gate metals such as TiN, the third dielectric layer 330 above the gate 31 and the first dielectric layer 310 on the sidewall of this embodiment cover the gate 31, which acts as a hard mask for etching the P-GaN layer, thereby preventing the gate 31 from being etched during the etching of the P-GaN layer. On the other hand, the third dielectric layer 330 and the first dielectric layer 310 in the gate stack structure 30 cover the gate 31, which can prevent the semiconductor barrier layer of the secondary epitaxy from contacting the gate 31 (such as TiN). In addition, this structure also prevents the gate 31 from being exposed to the high-temperature growth environment of the MOCVD machine during the secondary epitaxial growth process.

[0047] The second barrier layer 221 on the sidewalls and top of the gate stack structure 30 can be removed or retained during subsequent etching. In this embodiment, the second barrier layer 221 on the sidewalls and top of the gate stack structure 30, as well as the second dielectric layer 320, are retained.

[0048] After obtaining the second barrier layer 221 through epitaxy, a passivation layer (not shown in the figure), such as SiN, is deposited in situ above the second barrier layer 221. x Alternatively, an AlN material can be used; or a passivation layer can be deposited off-site above the second barrier layer 40. The off-site deposited passivation layer 550 can be, for example, SiN, AlN, Al2O3, SiO2, SiON, HfO2, etc. The passivation layer serves to regulate surface defects, adjust stress, and increase the underlying carrier concentration. Optionally, in the foregoing embodiments, a passivation layer can be used instead of the second barrier layer 221.

[0049] Example 8 The sidewalls of the gate stack structure in this invention can also be covered by one or more field plate dielectric layers, or by a second barrier layer 221 obtained through secondary epitaxy. See also Figure 13 , Figure 13 This is a schematic diagram of the semiconductor device according to Embodiment 8 of the present invention. In this embodiment, the sidewalls of the gate stack structure 30 near the source and drain electrodes retain the second barrier layer 221, the second dielectric layer 320, the field plate dielectric layer, and the stop layer below them, obtained by secondary epitaxy, as shown in the figure: the first stop layer 4101, the first field plate dielectric layer 4102, the second stop layer 4103, the second field plate dielectric layer 4104, and the fourth dielectric layer 50. When etching the field plate dielectric, the field plate dielectric layer above the second dielectric layer 320 at the top of the gate stack structure 30 and the stop layer below it are etched away, while all dielectric layers on the sidewalls are retained. In this embodiment, the dielectrics of the first field plate dielectric layer 4102 and the second field plate dielectric layer 4104 are different, while the dielectrics of the first stop layer 4101 and the second stop layer 4103 are the same.

[0050] See Figure 14 , Figure 14 This is a schematic diagram of the structure of another semiconductor device according to Embodiment 8 of the present invention. In this invention, the gate-source spacing can be adjusted by the dielectric thickness of the gate stack structure 30 near the source sidewall. Therefore, when forming the source and etching the source contact area, a precise gate-source spacing is obtained by adjusting the photolithography precision to etch away a certain thickness of the sidewall dielectric. Figure 14 As shown, the fourth dielectric layer 50 and the field plate dielectric are etched away, leaving only the second barrier layer 221 and part of the second dielectric layer 320 during the secondary epitaxy.

[0051] It can be understood that the second barrier layer 221 and various dielectric layers at the top of the gate stack structure 30 can be retained or removed. The dielectric layers near the drain sidewall of the gate stack structure 30 can be fully retained or only partially retained.

[0052] Example 9 Figure 15This is a schematic diagram of the device structure corresponding to some steps in the fabrication method of the semiconductor device according to Embodiment 9 of the present invention. The semiconductor device in this embodiment is a Dmode device, wherein the gate control layer is a gate dielectric layer, such as silicon oxide (SiO2). The fabrication process of the gate stack structure 30 and the continuous field plate step in this embodiment is the same as that in the previous embodiment, and will not be repeated here. After obtaining the gate stack structure 30 and the continuous field plate step 41 in step S604, in step S605, the drain region and the source region are etched to obtain the drain contact opening and the source contact opening. Then, in step S606, an ohmic metal layer 32' is provided above the current structure. The ohmic metal layer 32' covers the drain contact opening of the drain region of the epitaxial body, the multi-level continuous field plate dielectric step 41, the gate stack structure 30, and the source contact opening of the source region. In step S607, the ohmic metal layer 32' in the middle region between the drain contact opening and the continuous field plate dielectric step is etched away to disconnect the metal at the drain contact opening from the metal layer on the surface of the continuous field plate dielectric step, thereby obtaining the drain 33. In this embodiment, the ohmic metal layer 32' of the source contact opening constitutes the source 32, and the ohmic metal layer 32' of the surface of the continuous field plate dielectric step constitutes the multi-level continuous field plate electrode 41, and the two are electrically connected together.

[0053] See Figure 16 , Figure 16 This is a schematic diagram of the structure of another semiconductor device according to Embodiment Nine of the present invention. The process for fabricating the semiconductor device in this embodiment is similar to... Figure 15 The process is similar, except that in step S607, when etching the ohmic metal layer 32', a portion of the ohmic metal layer 32' at the top of the gate stack structure is also etched away. This reduces the overlap area between the ohmic metal layer and the gate 31 in the vertical projection direction, thereby reducing the parasitic capacitance generated due to the overlap between the ohmic metal layer and the gate 31 in the vertical projection direction and reducing the impact on device performance.

[0054] This embodiment uses ohmic metal to form the field plate electrode, which reduces the number of metal depositions, photolithography steps, and photomasks, simplifying the fabrication process, reducing the complexity of fabrication, and saving costs.

[0055] Example 10 Figure 17This is a schematic diagram of the structure of a semiconductor device according to Embodiment 10 of the present invention. In this embodiment, after obtaining the drain contact opening and the source contact opening through self-aligned etching, a high-concentration doped semiconductor layer is obtained through a secondary epitaxial process, as shown in the figure, the source high-concentration doped region 222-1 and the drain high-concentration doped region 222-2. For example, when the dielectric layer in the device is, for example, SiN or SiO2, and the field electrode is a TiN electrode, since both the dielectric layer and the field electrode can withstand relatively high temperatures, after etching the drain contact opening and the source contact opening, highly doped n-type GaN, InGaN, AlGaN and other materials can be grown at high temperatures (above 700 degrees Celsius) using MBE or MOCVD. If the structure in the device is not resistant to high temperatures, highly doped n-type GaN, InGaN, AlGaN and other materials can be grown at low temperatures using PVD, PECVD, PLD and other methods. The doping amount is, for example, 1E18~2E20, and the doping elements are, for example, silicon (Si), germanium (Ge), oxygen (O) ions or sulfur (S), etc.

[0056] Alternatively, after providing the III-V compound epitaxial body 20, ion implantation can be performed on the drain contact region and source contact region of the epitaxial body to obtain highly doped source and drain regions. For example, n-type dopant can be implanted into the barrier layer 220 of the drain and source contact regions, or n-type dopant can be implanted into the barrier layer 13 and at least part of the channel layer 210 of the drain and source contact regions. Then, during self-alignment etching, the highly doped drain and source regions are etched to obtain drain and source contact openings, followed by subsequent processes, which will not be elaborated here. The source 32 and drain 33 can be in contact with the surface of the ion implantation region or extend into the ion implantation region, thereby enhancing the ohmic contact between the source 32, drain 33 and the two-dimensional carrier gas.

[0057] In this embodiment, the high-concentration doped region reduces the ohmic contact between the source and drain electrodes and the two-dimensional carrier gas, effectively lowering the on-resistance of the enhancement-mode semiconductor device. Furthermore, the interface of the high-concentration doped region formed by secondary epitaxy or ion implantation is smoother, more uniform, and chemically more stable than the interface of metal compounds formed by alloying, resulting in better current distribution and heat dissipation, and reducing the risk of localized overheating. Moreover, the step of adding a high-concentration doped region can be naturally integrated into the device fabrication process without significant changes to the process flow, significantly improving the performance of the enhancement-mode semiconductor device without increasing process complexity.

[0058] Example 11 The III-V compound epitaxial body of the semiconductor device described in this invention includes multiple gate regions, multiple drain regions, and multiple source regions. The drain regions and source regions are separated by gate regions, and the region between the gate and drain is the gate-drain region. A multi-level continuous field plate structure is formed on the gate-drain region. Figure 18 As shown, Figure 18 This is a partial projection schematic diagram of the electrodes of a semiconductor device according to Embodiment Eleven of the present invention in the xy plane. To fully utilize the epitaxial material, the drain and source regions in this embodiment are arranged in a strip-like, parallel, spaced-apart configuration. The source region has a source electrode 32, and the drain region has a drain electrode 33. A gate stack structure 30 is located above the gate region. The strip-shaped drain and source regions are surrounded by the gate stack structure of the gate region. In this embodiment, the region between the gate stack structure 30 and the drain electrode 33 is the gate-drain region. The gate-drain region is provided with a continuous field plate electrode 42. In this embodiment, the continuous field plate electrode 42 extends from the gate-drain region to the sidewall and part of the top of the gate stack structure 30, thus overlapping in the projection portion in the xy plane, as shown in the figure. The dashed line below the continuous field plate electrode 42 in the figure represents the edge of the sidewall of the gate stack structure 30. At least one connecting segment 422 of the continuous field plate electrode 42 in the gate-drain region between the strip-shaped drain region and the adjacent gate stack structure extends through the gate stack structure 30 and electrically connects the source electrode 33 in the adjacent strip-shaped source region. While etching the dielectric steps of the field plate, the second dielectric layer 320 deposited in the source region is also etched, thereby exposing the barrier layer 220. In one embodiment, during the deposition and etching of the field plate metal layer, see [reference needed]. Figure 19 , Figure 19 It is along Figure 18 The schematic diagram shown is a side view of an embodiment after being cut along line AA. In the Y direction, the field plate metal layer is retained from the field plate dielectric step in the gate-drain region, the gate stack structure, the source region, the adjacent gate stack structure, to the field plate dielectric step in the adjacent gate-drain region, thus obtaining the following... Figure 18 In section 422, only the field plate metal layer is retained in other areas, from the field plate dielectric step in the gate drain region to the top portion of the gate stack structure. See also Figure 20 , Figure 20 It is along Figure 18 The diagram shows the side structure after the BB line is cut open.

[0059] In this embodiment, the field plate electrode is connected to the source 33-ohm metal at a certain location across the gate stack structure along the y-direction. The field plate electrode has a shorter length in the y-direction and a longer length in the x-direction. Therefore, connecting the field plate electrode to the ohm metal at certain intervals can effectively reduce the resistance of the field plate, thereby reducing switching losses.

[0060] In another embodiment, see Figure 21 , Figure 21This is a schematic diagram of the structure in which the field plate electrode and the source metal are connected according to another embodiment of the present invention. In this embodiment, the field plate electrode extends from the field plate dielectric step in the gate drain region to the top of the gate stack structure. When performing self-aligned etching on the source region, the dielectric layer above the field plate electrode on the side of the gate stack structure near the source is opened; thereby, the ohmic metal of the source 32 is directly connected to the field plate electrode.

[0061] In the structures of the aforementioned embodiments one to eleven, the field plate electrode can extend from the gate-drain region to the sidewall of the gate stack structure 30 near the drain, and continue to extend upward to a portion of the top region, thereby covering the top edge of the gate stack structure 30 near the drain. This achieves isolation between the gate and the drain, reduces gate-drain parasitic capacitance, and improves the electric field distribution at the gate edge.

[0062] Example 12 Figure 22 This is a schematic diagram of the structure of a semiconductor device according to Embodiment Twelve of the present invention. The semiconductor device in this embodiment is a bidirectional device, including a substrate 10, an epitaxial layer 20, a first electrode 611, a second electrode 612, a gate stack structure 30, and a continuous field plate structure. The gate stack structure 30 has a symmetrical arrangement of the first electrode 611 and the second electrode 612 on both sides. The region between the gate stack structure 30 and the first electrode 611 is a first withstand voltage region 601, and the region between the gate stack structure 30 and the second electrode 612 is a second withstand voltage region 602. The continuous field plate structure includes continuous field plate dielectric steps and continuous field plate electrodes 42. The continuous field plate dielectric steps include a first continuous field plate dielectric step 621 and a second continuous field plate dielectric step 622 located above the first withstand voltage region 601 and the second withstand voltage region 602, respectively. The continuous field plate electrodes 42 cover the continuous surface formed by the first continuous field plate dielectric step 621, the gate stack structure 30, and the second continuous field plate dielectric step 622. In this embodiment, the gate stack structure 30 includes a gate control layer 300, a gate 31, a third dielectric layer 330, a second barrier layer 221, and a second dielectric layer 320 arranged sequentially upwards along the z-direction. The width of the gate 31 is smaller than the width of the gate control layer 300. Near the first electrode 611 and the second electrode 612, the gate 31 and the gate control layer 300 form a step. A first dielectric layer 310 is formed on the gate sidewalls near the first electrode 611 and the second electrode 612 and on the upper surface of the gate control layer 300 of the lower step. The second barrier layer 221 covers the barrier layer 220, the sidewalls of the gate control layer 300, the first dielectric layer 310, and the top third dielectric layer 330. The second dielectric layer 320 covers the outer surface of the second barrier layer 221. A fourth dielectric layer 50 is deposited on the continuous field plate electrode 42.

[0063] The structure and preparation method of the second continuous field plate dielectric step 622 of the first continuous field plate dielectric step 621 are the same as those in the foregoing embodiments. As described in Embodiment 1, a field plate dielectric layer is deposited, and when etching the field plate dielectric layer, the etching range and etching depth are selected to obtain multi-level continuous field plate dielectric steps. As described in Embodiment 2, multiple field plate dielectric layers and corresponding stop layers are deposited, and steps with a precisely preset height are obtained through the deposited stop layers. As described in Embodiment 3, multiple field plate dielectric layers with different etching selectivity ratios or corrosion selectivity ratios are deposited, which can also obtain steps with a precisely preset height. As described in Embodiment 4, when etching the continuous field plate dielectric steps, the etching angle is controlled to be 30-90 degrees, so that the included angle between the first surface 411 and the second surface 412 of the field plate dielectric step is 90-150 degrees.

[0064] Alternatively, in the withstand voltage region, a second field plate electrode is also included above the continuous field plate electrode 42. As shown in Embodiment 5, a second field plate electrode 43 is obtained by etching the ohmic metal layer 32' used to form the first electrode 611 and the second electrode 612, and controlling the etching range. The second field plate electrode 43 can be a separate electrode or can be electrically connected to the first electrode 611 or the second electrode 612.

[0065] Alternatively, as described in Embodiment Six, the continuous field plate electrode 42 may be electrically connected to the gate 31 in the gate stack structure 30.

[0066] The structure and fabrication of the substrate, epitaxial body, gate stack structure 30, first electrode 611 and second electrode 612 of the bidirectional device in this embodiment are the same as those in the aforementioned embodiments one to ten, and will not be repeated here.

[0067] Example 13 Figure 23 This is a partial structural schematic diagram of the overall structure of a semiconductor device according to Embodiment Thirteen of the present invention. The semiconductor device in this embodiment is a bidirectional device, comprising a substrate, an epitaxial layer, and multiple functional units. Each functional unit includes a first electrode 611, a second electrode 612, and a gate stack structure 30. Adjacent functional units share one electrode. The first electrode 611 and the second electrode 612 are symmetrically distributed on both sides of the gate stack structure 30. The distance between the gate stack structure 30 and the electrodes on both sides is determined by the sidewall thickness of the gate stack structure 30. The gate stack structure 30 in this embodiment is any one of the aforementioned Embodiments One to Eleven. As a specific embodiment, Figure 23The gate stack structure 30 includes a gate control layer 300 above the barrier layer 220, a gate 31 above the gate control layer 300, a first dielectric layer 310, a second dielectric layer 320, and a third dielectric layer 330 above the second dielectric layer 320. A passivation layer 223 is also included on the side of the first dielectric layer 310. In this embodiment, when defining the source contact region, self-aligned etching can be performed using the gate stack structure 30, reducing the photolithography precision requirements. Furthermore, the thickness of the sidewalls of the gate stack structure 30 can be controlled to satisfy the distance between the electrodes (first electrode 611 and second electrode 612) and the gate 31, thereby achieving the purpose of controlling parasitic resistance.

[0068] In this embodiment, a passivation layer is grown directly on the surface of the barrier layer, which reduces the defect state density on the barrier layer surface and suppresses current collapse. Additionally, in the bidirectional devices of embodiments 12 and 13, a heavily doped semiconductor layer can be fabricated in the region where the first electrode 611 and the second electrode 621 are located to reduce the ohmic contact resistance of the electrodes and further improve the switching characteristics and power efficiency of the device. The structure and fabrication of the substrate, epitaxial body, gate stack structure 30, first electrode 611, and second electrode 612 in this embodiment are the same as those in embodiments 1 to 10, and will not be repeated here.

[0069] The semiconductor devices in the above embodiments also include other conventional structures and corresponding fabrication processes, such as dielectric deposition, drilling, metal interconnection, surface grinding, and deposition and patterning of pad metal layers to obtain various electrode pads after obtaining the source and drain electrodes. Since these are conventional structures and fabrication processes in the art, they will not be described in detail in this invention.

[0070] The above embodiments are for illustrative purposes only and are not intended to limit the invention. Those skilled in the art can make various changes and modifications without departing from the scope of the invention. Therefore, all equivalent technical solutions should also fall within the scope of the invention.

Claims

1. A semiconductor device, characterized in that, include: A III-V compound epitaxial body, comprising a channel layer and a barrier layer, wherein a heterojunction is formed between the channel layer and the barrier layer, and a two-dimensional carrier gas is formed at the interface of the heterojunction. A gate stack structure includes a gate control layer located above the barrier layer in the gate region of an epitaxial body and a gate located above the gate control layer, wherein the gate and the gate control layer form steps on the source side and the drain side, respectively; the steps include a first dielectric layer covering the sidewall of the gate, and a second dielectric layer covering the sidewall of the first dielectric layer and the sidewall of the gate control layer. A multi-stage continuous field plate structure located in the gate drain region of the epitaxial body; The drain and source are formed in the drain region and source region of the epitaxial body, respectively, and are electrically connected to the two-dimensional carrier gas. The distance between the source and the gate is the dielectric thickness of the gate sidewall.

2. The semiconductor device according to claim 1, characterized in that, Multi-stage continuous field plate structures include: A multi-level field plate dielectric step, each level of the field plate dielectric step includes a first surface parallel to the surface of the gate-drain region and a second surface extending from the edge of the first surface to the surface of the gate-drain region. The first surface of the lower level field plate dielectric step is connected to the second surface of the upper level field plate dielectric step. The first surface of the multi-level field plate dielectric step increases stepwise from the gate to the drain. A continuous field plate electrode, wherein the continuous field plate electrode at least covers the continuous surface formed by the first surface and the second surface of each stage of the field plate dielectric step.

3. The semiconductor device according to claim 2, characterized in that, The included angle between the first and second surfaces of the field plate dielectric step is greater than 90 degrees. Correspondingly, the field plate electrode forms an included angle greater than 90 degrees when covering the first and second surfaces of the field plate dielectric step.

4. The semiconductor device according to claim 2, characterized in that, The continuous field plate electrode extends from the gate-drain region at least to the sidewall of the gate stack structure to cover the gate edge near the drain.

5. The semiconductor device according to claim 1, characterized in that, The continuous field plate electrode is electrically connected to the gate, or the continuous field plate electrode is electrically connected to the source, or the continuous field plate electrode is floating.

6. The semiconductor device according to claim 2, characterized in that, The continuous field plate electrode is the same ohmic metal layer as the source / drain electrode.

7. The semiconductor device according to claim 6, characterized in that, The continuous field plate electrode extends to the top of the gate stack structure, and the source electrode extends to the top of the gate stack structure. The continuous field plate electrode is separated from the source electrode at the top of the gate stack structure to reduce the overlap area between the ohmic metal layer and the gate in the vertical projection direction.

8. The semiconductor device according to claim 2, characterized in that, It also includes a second field plate electrode, which is separated from the continuous field plate electrode by a dielectric layer.

9. The semiconductor device according to claim 8, characterized in that, The second field plate electrode is the same ohmic metal layer as the source / drain electrode.

10. The semiconductor device according to claim 9, characterized in that, The second field plate electrode extends to the top of the gate stack structure and is integrally connected to the source electrode.

11. The semiconductor device according to claim 2, characterized in that, The multi-level field plate dielectric steps are dielectric steps obtained by etching a single dielectric layer; or, two adjacent steps correspond to different field plate dielectric layers; or, the field plate dielectric layers corresponding to two adjacent steps include an etching stop dielectric layer.

12. The semiconductor device according to claim 1, characterized in that, The gate stack structure further includes a third dielectric layer formed above the gate, wherein the first dielectric layer extends upward from the gate sidewall and covers the sidewall of the third dielectric layer.

13. The semiconductor device according to claim 1 or 12, characterized in that, The sidewalls of the second dielectric layer are also covered by one or more field plate dielectric layers.

14. The semiconductor device according to claim 1, characterized in that, The gate control layer is a gate dielectric layer or a gate semiconductor layer.

15. The semiconductor device according to claim 12 or 14, characterized in that, At least a second barrier layer or passivation layer is also included above the barrier layer in the gate drain region of the epitaxial body.

16. The semiconductor device according to claim 4, characterized in that, The drain region forming the drain and / or the source region forming the source are highly doped regions that have undergone ion implantation or secondary epitaxy, in order to enhance the ohmic contact between the drain and the drain region and / or the ohmic contact between the source and the source region.

17. The semiconductor device according to claim 2, characterized in that, The III-V compound epitaxial material includes multiple gate regions, multiple drain regions, and multiple source regions. The gate-drain region between each drain region and the adjacent gate region includes a multi-level continuous field plate structure.

18. The semiconductor device according to claim 17, characterized in that, The drain and source regions are arranged in a strip-shaped, parallel arrangement, and the strip-shaped drain and source regions are surrounded by a gate stack structure of the gate region. The continuous field plate electrode in the gate-drain region between each strip-shaped drain region and the adjacent gate stack structure has at least one section extending through the gate stack structure and the source electrical connection in the adjacent strip-shaped source region.

19. A method for fabricating a semiconductor device, characterized in that, include: Provide a III-V compound epitaxial body, including a channel layer and a barrier layer thereon, wherein a heterojunction is formed between the channel layer and the barrier layer, and a two-dimensional carrier gas is formed at the interface of the heterojunction. A gate stack structure is formed in the gate region defined above the epitaxial body, including a gate control layer above the barrier layer in the gate region of the epitaxial body and a gate above the gate control layer. The gate and the gate control layer form steps on the source side and the drain side, respectively. The steps include a first dielectric layer covering the sidewall of the gate, and a second dielectric layer covers the sidewall of the first dielectric layer and the sidewall of the gate control layer. A multi-stage continuous field plate structure is provided in the gate drain region of the epitaxial body; The drain region and source region of the epitaxial body form the drain and source, respectively, and the drain and source are electrically connected to the two-dimensional carrier gas. The distance between the source and the gate is the total thickness of the first dielectric layer and the second dielectric layer of the gate sidewall.

20. The method according to claim 19, characterized in that, The steps for providing a multi-stage continuous field plate structure in the gate drain region of the epitaxial body include: Multi-level field plate dielectric steps are formed in the gate-drain region of the epitaxial material. Each level of the field plate dielectric step includes a first surface parallel to the surface of the gate-drain region and a second surface extending from the edge of the first surface to the surface of the gate-drain region. The first surface of a lower level field plate dielectric step connects to the second surface of an upper level field plate dielectric step. The first surfaces of the multi-level field plate dielectric steps gradually increase from the gate to the drain. A field plate metal layer is provided on at least the continuous step surface formed by the first and second surfaces of each stage field plate dielectric step to obtain a continuous field plate electrode.

21. The method according to claim 20, characterized in that, The steps for forming multi-level field plate dielectric steps in the gate drain region of the epitaxial body include: A dielectric layer of first thickness is provided in the gate-drain region of the epitaxial body; The dielectric layer of the first thickness is continuously etched downwards from the top according to the preset dielectric step position and thickness to obtain a multi-level field plate dielectric step. The etching position of each dielectric step approaches the gate from the drain in sequence, and the total thickness of all dielectric steps is the first thickness. Alternatively, the steps of forming multi-level field plate dielectric steps in the gate-drain region of the epitaxial body include: Multiple dielectric layers of second thickness are sequentially provided in the gate-drain region of the epitaxial body; The dielectric layer is etched downwards sequentially from the top of the dielectric layer according to the preset dielectric step position to remove the dielectric of the corresponding layer to obtain a multi-level field plate dielectric step. The second thickness of each dielectric layer is the same or different, and each dielectric layer has a different etching selectivity or corrosion selectivity. Alternatively, the steps of forming multi-level field plate dielectric steps in the gate-drain region of the epitaxial body include: A stop layer and a dielectric layer of a third thickness are sequentially provided in the gate drain region of the epitaxial body, wherein the first stop layer is provided on the surface of the gate drain region of the epitaxial body; The dielectric layer is etched sequentially downwards from the top of the dielectric layer according to the preset dielectric step position to remove the dielectric of the corresponding layer and the corresponding lower stop layer to obtain a multi-level field plate dielectric step. The third thickness of each dielectric layer is the same or different, and each dielectric layer and its corresponding lower stop layer have different etching selectivity or corrosion selectivity.

22. The method according to claim 21, characterized in that, When a dielectric layer of a first, second, or third thickness is provided in the gate drain region of the epitaxial body, the dielectric layer is provided on the gate stack structure surface in the gate region. During the etching of the dielectric layer to obtain multi-level field plate dielectric steps, the dielectric layer on the top and / or sidewalls of the gate stack structure in the gate region is etched to remove or retain one or more dielectric layers on the top and / or sidewalls of the gate stack structure.

23. The method according to any one of claims 20-22, characterized in that, When the field plate metal layer covers the continuous surface of the multi-level field plate dielectric steps in the gate drain region of the epitaxial body and the top and sidewalls of the gate stack structure in the gate region, the field plate metal layer on part or all of the top of the gate stack structure is etched to obtain a continuous field plate electrode extending from the continuous surface of the multi-level field plate dielectric steps to the sidewalls or top of the gate stack structure.

24. The method according to any one of claims 20-23, characterized in that, After obtaining the continuous field plate electrode, a dielectric layer is provided at least above the continuous field plate electrode.

25. The method according to claim 24, characterized in that, The steps of forming the drain and source in the drain and source regions of the epitaxial body, respectively, include: The drain and source regions of the epitaxial material are etched separately to obtain the drain contact opening and the source contact opening; It provides a continuous ohmic metal layer covering the drain contact opening of the epitaxial body, a dielectric layer above the continuous field plate electrode, a gate stack structure, and a source contact opening; The continuous ohmic metal layer is etched to retain at least the drain contact opening and the source contact opening to obtain the drain of the drain region and the source of the source region.

26. The method according to claim 25, characterized in that, When a dielectric layer is provided above the continuous field plate electrode, the dielectric layer covers the continuous field plate electrode, the gate stack structure, and the drain and source regions of the epitaxial body; Correspondingly, the step of forming a drain and a source in the drain region and source region of the epitaxial body respectively further includes: etching the dielectric layer to remove the dielectric layer in the drain region and source region, wherein a portion of the dielectric on the source sidewall of the gate stack structure is removed according to a preset source-gate distance.

27. The method according to claim 26, characterized in that, The steps of forming the drain and source regions of the epitaxial material further include: etching the dielectric layer above the continuous field plate electrode to expose a portion of the continuous field plate electrode; correspondingly, when providing a continuous ohmic metal layer covering the drain contact opening of the epitaxial material, the dielectric layer above the continuous field plate electrode, the gate stack structure, and the source contact opening, the continuous ohmic metal layer is electrically connected to the exposed portion of the continuous field plate electrode; when etching the continuous ohmic metal layer to at least retain the ohmic metal layer of the drain contact opening and the source contact opening to obtain the drain region of the drain region and the source region of the source region, the source region is retained to the ohmic metal layer electrically connected to the portion of the continuous field plate electrode.

28. The method according to claim 26, characterized in that, When etching the continuous ohmic metal layer to retain at least the ohmic metal layer of the drain contact opening and the source contact opening to obtain the drain region and the source region, the ohmic metal layer above the continuous field plate electrode is retained to obtain the second field plate electrode; wherein, the ohmic metal of the second field plate electrode is separated from the ohmic metal of the drain; the ohmic metal of the second field plate electrode is electrically connected to the ohmic metal of the source electrode or the ohmic metal of the second field plate electrode is separated from the ohmic metal of the source electrode at the top of the gate stack structure to reduce the overlap area of ​​the ohmic metal layer and the gate in the vertical projection direction.

29. The method according to claim 25, characterized in that, After obtaining the drain contact opening and the source contact opening, a high-concentration doped semiconductor layer is epitaxially stretched at the drain contact opening and the source contact opening to obtain a high-concentration doped region. Alternatively, after providing a III-V compound epitaxial layer, ion implantation can be performed on the drain contact region and source contact region of the epitaxial layer to obtain a highly doped region. The high-concentration doped region of the drain and the high-concentration doped region of the source are etched separately to obtain the drain contact opening and the source contact opening.

30. The method according to claim 19, characterized in that, The steps of forming a gate stack structure in the gate region defined above the epitaxial body include: A gate control layer and a gate metal layer are sequentially provided upwards above the III-V compound epitaxial layer; The gate metal layer in the non-gate region is etched away to obtain the gate; A first dielectric layer is provided, the first dielectric layer covering the gate top and sidewalls and the gate control layer of the non-gate region; The first dielectric layer is etched to remove at least the first dielectric layer outside the gate sidewall; The gate control layer in the non-gate region is etched away, wherein the gate and the underlying gate control layer form steps on the source and drain sides, respectively; the steps include a first dielectric layer covering the gate sidewalls; and A second dielectric layer is provided to at least cover the current gate top, the first dielectric layer of the gate sidewall, and the gate control layer sidewall.

31. The method according to claim 30, characterized in that, A second barrier layer or passivation layer is provided before the second dielectric layer, the second barrier layer or passivation layer at least covering the barrier layer of the gate drain region.

32. The method according to claim 30 or 31, characterized in that, After a gate control layer and a gate metal layer are sequentially provided upwards above a III-V compound epitaxial layer, a third dielectric layer is provided above the gate metal layer; correspondingly, the third dielectric layer is etched downwards from the third dielectric layer to remove the third dielectric layer outside the gate region and the gate metal layer below it to obtain the gate and the third dielectric layer above it.

33. The method according to claim 19, characterized in that, When providing a multi-level continuous field plate structure in the gate drain region of the epitaxial body, a multi-level continuous field plate dielectric step is provided; The steps of forming the drain and source in the drain and source regions of the epitaxial body, respectively, include: It provides a drain region covering the epitaxial layer, a multi-level continuous field plate dielectric step, a gate stacking structure, and a continuous ohmic metal layer for the source region; The continuous ohmic metal layer is etched to at least retain the drain region, the source region, and the ohmic metal layer on the surface of the multi-level continuous field plate dielectric step to obtain the drain of the drain region, the source of the source region, and the multi-level continuous field plate electrode on the surface of the multi-level continuous field plate dielectric step; wherein the multi-level continuous field plate electrode is electrically connected to the source of the source region, or the two are separated at the top of the gate stack structure to reduce the overlap area between the ohmic metal layer and the gate in the vertical projection direction.

34. The method according to claim 19 or 33, characterized in that, Further includes: Multiple gate regions, multiple drain regions, and multiple source regions are defined on the epitaxial body, with the drain and source regions separated by the gate and gate-drain regions.

35. The method for fabricating a normally-off semiconductor device according to claim 34, characterized in that, When multiple gate regions, multiple drain regions, and multiple source regions are defined on the epitaxial body, drain regions and source regions are defined in parallel and spaced apart, and gate regions are defined to surround the strip drain regions and strip source regions respectively. The region between the gate regions and the drain regions is the gate-drain region. Correspondingly, the gate regions defined above the epitaxial body form a gate stack structure, which includes the strip drain regions and strip source regions respectively. When a multi-level continuous field plate structure is provided in the gate-drain region of the epitaxial body, the continuous field plate electrode in each strip gate-drain region has at least one section extending through the gate stack structure and the source electrical connection in the adjacent strip source region.

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