Half-bridge power module and method of manufacturing and use thereof

Abstract

The application discloses a kind of half-bridge power module and preparation method and application thereof.The half-bridge power module includes first power switching device, second power switching device, drive module and capacitor, and the first surface of first power switching device is distributed with non-electric connection area and the electric connection area of drain, source and gate;The third surface of second power switching device is distributed with source, drain and gate terminal, and is also provided with electrically conductive channel that is connected with fourth surface and source terminal or drain terminal, and is attached to drain or source electric connection area through fourth surface;Drive module is attached to non-electric connection area and is connected with gate terminal or gate electric connection area capacitor is attached to source or drain electric connection area.The application is integrated by vertical laminated interconnection and functional division, and the parasitic inductance of power commutation, drive and decoupling circuit is systematically reduced, and the power density is improved.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device packaging technology, and more specifically, relates to a half-bridge power module, its preparation method and application. Background Technology

[0002] In the application of wide-bandgap semiconductor power devices such as gallium nitride (GaN), the half-bridge topology is the core unit of power electronic converters. For GaN devices, as the switching frequency increases to the megahertz (MHz) level, the parasitic inductance of the power commutation circuit, the parasitic parameters of the gate drive circuit, and the parasitic inductance of the decoupling capacitor circuit become key bottlenecks restricting device performance. Specifically, firstly, the long interconnect path from the source of the upper transistor to the drain of the lower transistor results in a large parasitic inductance, restricting the efficient operation of GaN devices at MHz-level switching frequencies; secondly, the high-side gate drive chip is far from the upper transistor, resulting in large parasitic parameters in the drive circuit, leading to waveform distortion and the risk of false turn-on; thirdly, the input decoupling capacitor is located far from the printed circuit board surface, resulting in poor high-frequency bypass performance; and fourthly, traditional packages have large areas and low power densities. How to simultaneously reduce the parasitic parameters of these three key circuits and reduce the package area is of great significance for fully unleashing the MHz-level switching potential of GaN devices.

[0003] In the prior art, patent US9,640,471 B2 discloses a GaN half-bridge co-package scheme, in which the upper and lower transistors are arranged horizontally side by side, and the switching nodes are interconnected by wire bonding; although patent US20220084978 A1 proposes an integrated half-bridge scheme, its core interconnection still relies on wire bonding or copper clips. The interconnection paths of the above-mentioned existing schemes are relatively long, resulting in parasitic inductances in the power circuit typically ranging from 1 to 5 nH, which is difficult to meet the requirements of high-frequency applications. At the same time, the high-side driver chip and decoupling capacitor are usually placed far away from the power transistors, resulting in large parasitic parameters in the driver circuit and decoupling circuit, which can easily lead to false turn-on and voltage overshoot problems. In addition, the traditional planar layout package area is large, limiting power density.

[0004] Furthermore, through-silicon via (TSV) technology on the back of GaN chips (such as research by Intel) proposes integrating high-voltage metal-insulator-metal (MIM) capacitors on the back of GaN-based wafers, connecting them to GaN devices on the front side via the TSV. However, this technology focuses on heterogeneous integration of the front and back sides within a single GaN chip. The TSV's function is to connect the back-side capacitors to the front-side circuitry, rather than bringing power terminals (source or drain) to the back side for multi-chip stack-up interconnection, thus failing to solve the aforementioned problems. Therefore, there is an urgent need for a half-bridge power module that can systematically reduce multi-loop parasitic parameters and improve power density from the chip level to the package level. Summary of the Invention

[0005] The main objective of this invention is to provide a half-bridge power module, its fabrication method, and its application, in order to overcome the shortcomings of the prior art.

[0006] To achieve the above-mentioned objectives, the present invention adopts the following technical solution: The first aspect of the present invention provides a half-bridge power module, including a first power switching device, a second power switching device, a driving module, and a capacitor: the first power switching device has a first surface and a second surface disposed opposite to each other in a set direction, the first surface having a drain electrical connection region, a source electrical connection region, a gate electrical connection region, and a non-electrical connection region distributed therein; the second power switching device has a third surface and a fourth surface disposed opposite to each other in the set direction, the third surface having a source terminal, a drain terminal, and a gate terminal distributed therein, and the fourth surface having an electrical connection region distributed therein; the driving module is attached to the non-electrical connection region; the driving module is connected to the gate terminal; the second power switching device also includes A conductive channel is provided, which passes through the second power switch device in a predetermined direction and connects the electrical connection area of ​​the fourth surface and the source terminal. The second power switch device is attached to the drain electrical connection area through the fourth surface, and the capacitor is attached to the source electrical connection area. Alternatively, the driving module is connected to the gate electrical connection area. The second power switch device also has a conductive channel, which passes through the second power switch device in a predetermined direction and connects the electrical connection area of ​​the fourth surface and the drain terminal. The second power switch device is attached to the source electrical connection area through the fourth surface, and the capacitor is attached to the drain electrical connection area.

[0007] Preferably, for the structure of the driving module connected to the gate terminal: the drain terminal is connected to the other end of the capacitor and is used to connect to the positive terminal of the DC bus; the source electrical connection region is grounded, and the gate electrical connection region is used to connect to the external driving circuit; for the structure of the driving module connected to the gate electrical connection region: the drain electrical connection region is connected to the other end of the capacitor and is used to connect to the positive terminal of the DC bus; the source terminal is grounded, and the gate terminal is used to connect to the external driving circuit.

[0008] Preferably, the conductive channel is a vertical conductive channel.

[0009] Preferably, the conductive channel includes: an array of through holes penetrating the second power switching device along a direction perpendicular to the third surface, a first insulating layer disposed on the inner wall of the through holes, a diffusion barrier layer disposed on the surface of the first insulating layer, and a conductive material filling the through holes.

[0010] Preferably, the diameter of the through hole is 5~100μm.

[0011] Preferably, the spacing between through holes is 1.5 to 5 times the diameter of the through hole.

[0012] Preferably, the thickness of the first insulating layer is 100 nm to 1 μm.

[0013] Preferably, the thickness of the diffusion barrier layer is 5~50nm.

[0014] Preferably, for the structure where the driving module is connected to the gate terminal: the third surface is provided with an independent Kelvin source sensing pad, which is led out through a through-silicon via or a trace to provide an independent source reference potential for the driving module; for the structure where the driving module is connected to the gate electrical connection region: the first surface is provided with an independent Kelvin source sensing pad, which is led out through a through-silicon via or a trace to provide an independent source reference potential for the driving module.

[0015] Preferably, the first surface is fixed to the device substrate by a thermally conductive adhesive medium or a conductive adhesive medium, wherein the device substrate includes a packaging substrate, a lead frame, or a heat dissipation substrate.

[0016] Preferably, the ratio between the area of ​​the electrical connection region on the fourth surface and the area of ​​the fourth surface is not less than 60%.

[0017] Preferably, for the structure in which the driving module is connected to the gate terminal, the substrate thickness of the second power switching device is 50~200μm; for the structure in which the driving module is connected to the gate electrical connection region, the substrate thickness of the first power switching device is 50~200μm.

[0018] Preferably, a conductive interconnect layer is further provided between the first power switching device and the second power switching device, and the thickness of the conductive interconnect layer is 5~50μm.

[0019] Preferably, the drive module is further provided with a second insulating layer on one side of the non-electrical connection area, the second insulating layer being located between the drive module and the non-electrical connection area, and the thickness of the second insulating layer being 5~50μm.

[0020] Preferably, for the structure of the driving module connecting to the gate terminal: the ratio of the area of ​​the drain electrical connection region to the area of ​​the first surface is 30%~50%, the ratio of the area of ​​the source electrical connection region to the area of ​​the first surface is 20%~40%, and the ratio of the area of ​​the non-electrical connection region to the area of ​​the first surface is 10%~30%; for the structure of the driving module connecting to the gate electrical connection region: the ratio of the area of ​​the source electrical connection region to the area of ​​the first surface is 30%~50%, the ratio of the area of ​​the drain electrical connection region to the area of ​​the first surface is 20%~40%, and the ratio of the area of ​​the non-electrical connection region to the area of ​​the first surface is 10%~30%.

[0021] A second aspect of the present invention provides a method for fabricating a half-bridge power module, comprising: fabricating a first power switching device, the first power switching device having a first surface and a second surface disposed opposite to each other in a predetermined direction, the first surface having a drain electrical connection region, a source electrical connection region, a gate electrical connection region, and a non-electrical connection region distributed thereon; fabricating a second power switching device, the second power switching device having a third surface and a fourth surface disposed opposite to each other in a predetermined direction, the third surface having a source terminal, a drain terminal, and a gate terminal distributed thereon; fabricating a conductive channel in the second power switching device, the conductive channel passing through the second power switching device along the predetermined direction and connecting the source terminal and the fourth surface, fabricating a multilayer composite metal conductive electrode layer electrically connected to the conductive channel on the fourth surface; attaching the second power switching device to the drain electrical connection region, with the fourth surface in contact with the drain electrical connection region; attaching a capacitor to the source electrical connection region, and attaching a driving module to the non-electrical connection region; connecting the driving module to the gate terminal, connecting one end of the capacitor not in contact with the source electrical connection region and the drain terminal to the positive terminal of a DC bus, and grounding the source electrical connection region.

[0022] A third aspect of the present invention provides a method for fabricating a half-bridge power module, comprising: fabricating a first power switching device, the first power switching device having a first surface and a second surface disposed opposite to each other in a predetermined direction, the first surface having a drain electrical connection region, a source electrical connection region, a gate electrical connection region, and a non-electrical connection region distributed thereon; fabricating a second power switching device, the second power switching device having a third surface and a fourth surface disposed opposite to each other in a predetermined direction, the third surface having a source terminal, a drain terminal, and a gate terminal distributed thereon; and fabricating a conductive channel within the second power switching device, the conductive channel passing through the predetermined direction. A second power switching device is provided, connecting the drain terminal and the fourth surface. A multilayer composite metal conductive electrode layer electrically connected to the conductive channel is prepared on the fourth surface. The second power switching device is attached to the source electrical connection region, and the fourth surface is in contact with the source electrical connection region. The capacitor is attached to the drain electrical connection region, and the driving module is attached to the non-electrical connection region. The driving module is connected to the gate electrical connection region. The end of the capacitor that is not in contact with the source electrical connection region and the drain electrical connection region are connected to the positive terminal of the DC bus. The source terminal is grounded.

[0023] A fourth aspect of the present invention provides a power conversion device, including the half-bridge power module as described above.

[0024] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention provides a half-bridge power module and its preparation method and application. By functionally partitioning the surface of the first power switching device and vertically stacking the second power switching device, capacitor and driving module, combined with the conductive channel design inside the second power switching device, the interconnection path of the power commutation circuit is compressed from the millimeter level to the micrometer level, so that the parasitic inductance of the power circuit can be reduced to the sub-Anahen level, effectively suppressing high-frequency switching voltage overshoot. At the same time, the close integration of the driving module and capacitor significantly reduces the parasitic parameters of the driving circuit and decoupling circuit, improving the high-frequency stability of the system. In addition, the three-dimensional stacked structure makes full use of vertical space, so that the module projection area is close to the area of ​​a single power chip, which greatly improves the power density. The heat dissipation path is optimized by vertical conductive channels and large-area metallization layer, taking into account both electrical performance and thermal management requirements. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1This is the circuit diagram of a half-bridge power module.

[0027] Figure 2 This is a top view schematic diagram of the packaging structure of the half-bridge power module provided in the first embodiment of the present invention.

[0028] Figure 3 This is a schematic diagram of the packaging of a half-bridge power module provided in the first embodiment of the present invention.

[0029] Figure 4 This is a cross-sectional schematic diagram of the second power switching device in the half-bridge power module provided in the first embodiment of the present invention.

[0030] Figure 5 This is a top view schematic diagram of the packaging structure of the half-bridge power module provided in the second embodiment of the present invention. Detailed Implementation

[0031] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate this technical solution, its implementation process, and its principles.

[0032] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0033] Furthermore, in the description of this invention, it should be understood that the terms "upper," "lower," "inner," "outer," "horizontal," "vertical," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0034] In the description of this specification, the references to terms such as "an embodiment," "a particular embodiment," or "the embodiment" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0035] See Figure 1 The circuit structure of the power half-bridge module is shown, including the upper transistor Q1, the lower transistor Q2, the driver module, and the capacitor. The source of Q1 is connected to the drain of Q2, and the drain of Q1 is connected to V. DC Q2's source is grounded (GND). Figure 1 In the middle, V DC For DC bus input, Q1 is the high-side transistor, and Q2 is the low-side transistor. Q1 and Q2 form a half-bridge topology. The connection point between the two transistors is the switching node SW. Q1 is equipped with a gate drive circuit (i.e., a drive module), and a capacitor is connected in parallel to V. DC It serves as an input decoupling capacitor between GND and GND.

[0036] The half-bridge power module provided in this embodiment of the invention includes a first power switching device, a second power switching device, a driving module, and a capacitor. The first power switching device has a first surface and a second surface disposed opposite to each other in a set direction. The first surface has a drain electrical connection region, a source electrical connection region, a gate electrical connection region, and a non-electrical connection region distributed therein. The second power switching device has a third surface and a fourth surface disposed opposite to each other in the set direction. The third surface has a source terminal, a drain terminal, and a gate terminal distributed therein. The fourth surface has an electrical connection region distributed therein. The driving module is attached to the non-electrical connection region.

[0037] A topology (such as) Figure 2 In the diagram shown, the driving module is connected to the gate terminal. A conductive channel is also formed within the second power switch device. This conductive channel passes through the second power switch device along a predetermined direction and connects the electrical connection area of ​​the fourth surface to the source terminal. The second power switch device is attached to the drain electrical connection area via the fourth surface, and the capacitor is attached to the source electrical connection area. In this topology, the first power switch device is a low-side switch, and the second power switch device is a high-side switch. The package schematic is shown below. Figure 3 As shown.

[0038] Another topology (such as) Figure 5 As shown, the driving module is connected to the gate electrical connection region. A conductive channel is also formed within the second power switch device. This conductive channel passes through the second power switch device along a predetermined direction and connects the electrical connection region of the fourth surface and the drain terminal. The second power switch device is attached to the source electrical connection region via the fourth surface, and the capacitor is attached to the drain electrical connection region. In this topology, the first power switch device is a high-side switch, and the second power switch device is a low-side switch.

[0039] The first and second power switching devices are, for example, GaN high electron mobility transistors (HEMTs), SiC HEMTs, SiGe HEMTs, etc. The drain electrical connection region, source electrical connection region, gate electrical connection region, and non-electrical connection region correspond, for example, to the drain pad region, source pad region, gate pad region, and no-pad region (or small-signal region), respectively. Figure 2 The structure shown has a gate electrical connection region located at the chip edge for easy introduction of external signals. The capacitor is, for example, a Si capacitor; preferably, the capacitance density per unit area of ​​the Si capacitor is not less than 100 nF / mm². 2 Ensure sufficient decoupling capacity.

[0040] In this embodiment, the first power switching device serves as the base layer of a stacked package. Its first surface (i.e., the front side) is divided into multiple functional regions, which serve not only for its own electrical connections but also as a platform for supporting other components. The non-electrical connection area refers to the region on the first surface without high-power pads. Directly attaching the drive module to this area allows the drive module to be physically adjacent to the high-side switching transistor, significantly shortening the trace length of the gate drive circuit and reducing the parasitic inductance of the drive circuit. It should be understood that although a specific partition layout is shown in the figure, in other embodiments, the shape and relative position of each region can be adjusted according to the actual chip layout, as long as the isolation and interconnection requirements of the functional partitions are met.

[0041] for Figure 2 In the topology shown, the drain terminal is connected to the other end of the capacitor and is used to connect to the positive terminal of the DC bus; the source electrical connection region is grounded, and the gate electrical connection region is used to connect to the external drive circuit. For Figure 5 In the topology, the drain terminal is connected to the other end of the capacitor and is used to connect to the positive terminal of the DC bus; the source terminal is grounded, and the gate terminal is used to connect to the external drive circuit.

[0042] Through the two parallel technical solutions described above, this embodiment constructs a highly integrated three-dimensional power module. Regardless of the topology used, the drive module is always attached to the non-electrical connection area of ​​the first power switching device. This allows the drive signal to be transmitted to the gate of the high-side switching transistor with the shortest possible distance, effectively suppressing gate oscillation and the risk of false turn-on caused by long traces. Simultaneously, the common substrate integration of capacitors and power devices compresses the parasitic inductance of the decoupling loop to the sub-Anahen level, significantly improving the high-frequency bypass effect. More importantly, the vertical interconnection achieved through conductive channels replaces traditional wire bonding, fundamentally eliminating the parasitic inductance bottleneck caused by millimeter-level horizontal interconnections. This enables the half-bridge power module to maintain low voltage overshoot and high efficiency operation at MHz-level switching frequencies.

[0043] In one implementation, the conductive channel is a vertical conductive channel. This vertical orientation design allows current to pass through the substrate of the second power switching device via the shortest path. Compared to conventional horizontal wire bonding or side leads, the vertical channel greatly reduces the area enclosed by the current loop, thereby reducing parasitic inductance from a physical structural perspective.

[0044] In one embodiment, the conductive channel includes: an array of through holes penetrating the second power switching device along a direction perpendicular to the third surface, a first insulating layer disposed on the inner wall of the through holes, a diffusion barrier layer disposed on the surface of the first insulating layer, and a conductive material filling the through holes.

[0045] The via array is, for example, a silicon via array. The first insulating layer is made of materials such as SiO2, Si3N4, or other high-insulation-strength dielectrics. The conductive material filling the vias is, for example, copper, tungsten, polysilicon, or other low-resistivity conductive materials. The depth of the vias is determined based on the thickness of the second power switch substrate after thinning (typically 50~200 μm).

[0046] by Figure 2 Taking the illustrated topology as an example, the structure of the conductive channel in the second power switching device is as follows: Figure 4 As shown, this conductive channel exhibits a typical three-layer composite structure of "insulation-blocking-conductivity". The core function of the first insulating layer is to achieve electrical isolation between the conductive material and the semiconductor substrate, preventing leakage current or short-circuit failure. The diffusion blocking layer, located between the first insulating layer and the conductive material, prevents conductive metal atoms (especially copper atoms) from diffusing into the substrate or epitaxial layer during high-temperature processes or long-term operation, avoiding device performance degradation or reliability issues. The conductive material fills the center of the via, providing a low-impedance current path.

[0047] As one implementation, the via diameter is 5–100 μm. Examples of via diameters include 5 μm, 20 μm, 40 μm, 60 μm, 80 μm, or 100 μm. The via diameter affects the single-hole resistance and density. Within this range, the via has a sufficient cross-sectional area to carry power currents in the tens of amperes and reduce on-resistance, without excessively weakening the substrate's mechanical strength or occupying too much active area due to excessively large apertures.

[0048] In one implementation, the via spacing is 1.5 to 5 times the via diameter. Examples of via spacing include 1.5, 2.5, 3.5, 4.5, and 5 times the via diameter. The via spacing affects array density and mechanical strength. If the spacing is too small, the silicon pillars between adjacent vias are too thin, making them prone to cracking due to thermal mismatch stress during thermal cycling. If the spacing is too large, the via density is too low, leading to increased lateral current spreading resistance between the back metallization layer and the front pads, which is detrimental to current sharing and heat dissipation under high current conditions.

[0049] In one implementation, the thickness of the first insulating layer is 100 nm to 1 μm. Examples of thicknesses for the first insulating layer include 100 nm, 300 nm, 500 nm, 700 nm, 900 nm, and 1 μm. The first insulating layer provides electrical isolation, preventing short circuits between the silicon via and the substrate. This thickness is sufficient to withstand voltage requirements of several hundred volts and provide reliable interface passivation, while avoiding the filling void problem caused by a sharp increase in the via aspect ratio due to excessive film thickness.

[0050] In one implementation, the thickness of the diffusion barrier layer is 5–50 nm. Examples of thicknesses for the diffusion barrier layer are 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, and 50 nm. The diffusion barrier layer prevents conductive materials (e.g., copper) within the via from diffusing into the silicon substrate. At this thickness, the barrier layer forms a continuous, dense film to effectively block metal diffusion without significantly increasing the overall series resistance of the via.

[0051] As one implementation method, for Figure 2 The structure shown depicts the connection of the driving module to the gate terminal, and the substrate thickness of the second power switching device is 50~200μm; for Figure 5 The structure shown depicts the drive module connecting to the gate electrical connection region. The substrate thickness of the first power switching device is 50~200μm. The substrate thickness directly determines the longitudinal length of the conductive channel, thus affecting the total parasitic inductance of the power circuit. Reducing the substrate thickness to the range of 50~200μm can reduce the inductance of the vertical interconnect path to the sub-Anahen level, while retaining sufficient silicon bulk thickness to maintain mechanical integrity during wafer-level processing, preventing warpage or breakage.

[0052] In one implementation, a conductive interconnect layer with a thickness of 5–50 μm is further disposed between the first power switching device and the second power switching device. This conductive interconnect layer affects the resistance and inductance of the SW node. The thickness range of 5–50 μm ensures that the bonding interface has low contact resistance and thermal resistance, while providing sufficient flexibility to absorb height tolerances and thermal expansion coefficient mismatches during the stacking assembly process.

[0053] In one implementation, a second insulating layer is provided on the side of the drive module attached to the non-electrical connection area. The second insulating layer is located between the drive module and the non-electrical connection area to prevent short circuits between the drive chip and the surface of the first power switching device. The thickness of the second insulating layer is 5~50μm. Since there may still be active circuits or wiring below the non-electrical connection area, the second insulating layer can prevent electrical short circuits between the bottom of the drive module and the surface of the first power switching device.

[0054] As one implementation method, for Figure 2 The structure of the driver module connected to the gate terminal shown: An independent Kelvin source sensing pad is provided on the third surface. This Kelvin source sensing pad is led out through a through-silicon via (TSV) or a trace to provide an independent source reference potential for the driver module; for Figure 5 The structure of the drive module connected to the gate electrical connection area shown is as follows: The first surface is provided with an independent Kelvin source sensing pad, which is led out through a through-silicon via or a trace to provide an independent source reference potential for the drive module.

[0055] The Kelvin source sensor pads can be led out via either through-silicon vias (TSVs) or surface-mount traces. Using TSVs enables three-dimensional vertical interconnects, further shortening signal paths and saving chip surface area. Surface-mount traces offer a simpler process and are suitable for cost-sensitive applications or those that don't require extreme compactness. Through this independent Kelvin connection design, this embodiment effectively improves the driving stability and anti-interference capability of the half-bridge power module at MHz-level switching frequencies, providing crucial signal integrity assurance for fully leveraging the high-speed performance of gallium nitride devices.

[0056] In one implementation, the first surface is fixed to the device substrate using a thermally conductive or electrically conductive adhesive medium. The device substrate includes a packaging substrate, a lead frame, or a heat dissipation substrate. Since the first power switching device acts as the supporting substrate for the entire three-dimensional stacked structure, its second surface (i.e., the back surface) is not only the mechanical support surface of the module but also the main heat dissipation channel. Different adhesive media and different device substrates can be selected for different application scenarios, allowing the half-bridge power module to flexibly adapt to the heat dissipation and installation requirements of different fields.

[0057] As one implementation method, for Figure 2 The structure of the driving module connected to the gate terminal shown is as follows: the ratio of the area of ​​the drain electrical connection region to the area of ​​the first surface is 30%~50%, the ratio of the area of ​​the source electrical connection region to the area of ​​the first surface is 20%~40%, and the ratio of the area of ​​the non-electrical connection region to the area of ​​the first surface is 10%~30%. For Figure 5 The structure of the drive module connecting the gate electrical connection region is shown below: the ratio of the area of ​​the source electrical connection region to the area of ​​the first surface is 30%~50%, the ratio of the area of ​​the drain electrical connection region to the area of ​​the first surface is 20%~40%, and the ratio of the area of ​​the non-electrical connection region to the area of ​​the first surface is 10%~30%. Through this refined area control, this embodiment achieves high-density three-dimensional integration of power switching devices, passive components, and control chips without increasing the total chip area. It is understood that the sum of the areas of the drain electrical connection region, the source electrical connection region, the gate electrical connection region, and the non-electrical connection region is not greater than the area of ​​the first surface.

[0058] In one implementation, the ratio between the area of ​​the electrical connection region on the fourth surface and the area of ​​the fourth surface is not less than 60%. For example, a large-area continuous multilayer metallization layer (Ti / Cu / Ni / Au or Ti / Cu / Ag) is formed on the fourth surface through processes such as sputtering or electroplating, covering more than 60% of the back surface area of ​​the second power switching device, and electrically connected to all through-silicon vias to form a low-impedance source back terminal or drain back terminal.

[0059] From an electrical performance perspective, a large-area metallization layer can effectively collect the current from the internal via array and distribute it evenly across the entire bonding interface, avoiding local overheating or electromigration failure caused by current congestion. From a thermal management perspective, the heat generated by the second power switching device is mainly conducted to the back side through the vias, and then enters the first power switching device or substrate via the interconnect layer. If the back metal coverage is too low, the heat flow will face huge lateral thermal resistance when leaving the chip, which can easily form hot spots under the vias and affect the device life.

[0060] for Figure 2 In the structure shown, the second power switch device has only a drain pad on its front side (occupying the main area of ​​the front side, used for V). DC Input connection) and gate pad (located at the front edge). For Figure 5 The structure shown has only a source pad (occupying the main area of ​​the front side and used for grounding) and a gate pad (located at the edge of the front side) on the front side of the second power switch device.

[0061] by Figures 2-4 Taking the structure shown as an example, the three-dimensional stacked packaging architecture of the half-bridge power module provided in this embodiment of the invention is illustrated. The packaging form can be plastic encapsulation or open-cavity packaging. The three-dimensional stacked packaging structure includes the following layers from bottom to top: First layer / base layer: The lower transistor chip (Q2) is mounted on the back side of a heat sink substrate, with the front side facing upwards. Second layer / stacked layer: Above the front side of the lower transistor, the upper transistor chip (Q1), silicon-based integrated capacitor chip (which can also be replaced with deep trench capacitors or MIM capacitors), and upper transistor gate driver chip are stacked in separate areas.

[0062] The upper transistor chip (Q1) is stacked on the drain connection area of ​​the lower transistor: the upper transistor chip is stacked with its front side facing up and its back side facing down. The source metallization layer on the back of the upper transistor (leading out through silicon vias) is directly bonded to the drain connection area of ​​the lower transistor through conductive interconnect materials (solder bump array, sintered silver layer, sintered copper layer, anisotropic conductive film or conductive adhesive), forming a half-bridge switching node. This interconnect achieves the shortest vertical current path from the source of the upper transistor to the drain of the lower transistor—the current flows vertically from the source metallization layer on the front of the upper transistor through the silicon via array, passes vertically through the substrate to the back metallization layer, and then vertically across the interconnect material layer to the drain pad of the lower transistor. The total path length is equal to the thickness of the substrate of the upper transistor plus the thickness of the interconnect material (total 50~250μm), and the parasitic inductance can be less than 0.5nH, with a theoretical limit of sub-Anahen.

[0063] Silicon-based integrated capacitor chips are stacked in the source-electrical connection area of ​​the lower transistor: The silicon-based integrated capacitor chips are manufactured using deep trench capacitor or MIM capacitor technology, with a capacitance density of not less than 100nF / mm². 2One end of the capacitor chip is electrically connected to the source pad of the lower transistor via a back or front pad (i.e., connected to GND), and the other end is connected to the drain pad of the upper transistor or V-type transistor via a redistribution layer or wire bonding. DC The input terminals are electrically connected to form an input decoupling capacitor located adjacent to the power transistor. The distance between this capacitor and the power commutation circuit is reduced to the chip-level scale (hundreds of micrometers to several millimeters), and the parasitic inductance of the decoupling circuit can be reduced to 0.2~0.8nH.

[0064] The upper transistor's gate driver chip is stacked on the non-electrically connected area of ​​the lower transistor: the silicon-based gate driver chip is stacked on the area on the front side of the lower transistor where no power pads are located, and an insulating layer is provided at the bottom to prevent electrical short circuits with the surface of the lower transistor. The driver chip is electrically connected to the gate pads and Kelvin source reference pads on the front side of the upper transistor chip via short-distance wire bonding or copper pillar bumps. Because the driver chip is adjacent to the upper transistor, the physical area and path length of the gate drive circuit are significantly shortened, and the parasitic inductance of the drive circuit can be controlled below 0.5nH.

[0065] Furthermore, V DC The DC bus positive terminal is connected to the drain pad on the front side of the upper MOSFET, and is also connected to one end of the silicon-based capacitor via a redistribution trace or external connection. The switching node / half-bridge midpoint is formed by direct bonding between the source metallization layer on the back side of the upper MOSFET and the drain pad of the lower MOSFET. GND (ground / DC bus negative terminal) is connected to the source pad of the lower MOSFET, and is also connected to the other end of the silicon-based capacitor. The gate pad on the front side of the upper MOSFET is connected to the output terminal of the upper MOSFET driver chip via a short-distance interconnect. The Kelvin source reference pad of the upper MOSFET is connected to the reference ground terminal of the driver chip via an independent through-silicon via or a front pad, forming a drive circuit reference independent of the power circuit. The gate pad on the front edge of the lower MOSFET is connected to the external lower MOSFET driver circuit via wire bonding or other methods. In this structure, the total parasitic inductance of the power commutation circuit is <0.5nH, suppressing switching voltage overshoot; the parasitic inductance of the drive circuit is <0.5nH, ensuring drive waveform quality; and the parasitic inductance of the decoupling circuit is <0.8nH, ensuring high-frequency bypass effect.

[0066] Based on the same inventive concept, embodiments of the present invention also provide a method for fabricating a half-bridge power module, used to fabricate such a module. Figure 2 The method for the half-bridge power module shown includes the following steps S100-S600.

[0067] Step S100: Prepare a first power switching device. The first power switching device has a first surface and a second surface disposed opposite to each other in a set direction. The first surface is distributed with a drain electrical connection region, a source electrical connection region, a gate electrical connection region and a non-electrical connection region.

[0068] Step S200: Prepare a second power switching device. The second power switching device has a third surface and a fourth surface disposed opposite to each other in a set direction. The third surface is provided with an active terminal, a drain terminal and a gate terminal.

[0069] In step S300, a conductive channel is fabricated in the second power switching device. The conductive channel passes through the second power switching device along a set direction and connects the source end and the fourth surface. A multilayer composite metal conductive electrode layer electrically connected to the conductive channel is fabricated on the fourth surface.

[0070] In step S400, the second power switching device is attached to the drain connection region, and the fourth surface is in contact with the drain connection region.

[0071] In step S500, the capacitor is attached to the source electrical connection area, and the drive module is attached to the non-electrical connection area.

[0072] Step S600: Connect the drive module to the gate terminal, connect the end of the capacitor that is not in contact with the source electrical connection area and the drain terminal to the positive terminal of the DC bus, and ground the source electrical connection area.

[0073] Based on the same inventive concept, embodiments of the present invention also provide a method for fabricating a half-bridge power module, used to fabricate such a module. Figure 5 The half-bridge power module shown includes the following steps S100'-S600'.

[0074] Step S100': Prepare a first power switching device. The first power switching device has a first surface and a second surface disposed opposite to each other in a set direction. The first surface is distributed with a drain electrical connection region, a source electrical connection region, a gate electrical connection region, and a non-electrical connection region.

[0075] Step S200': Prepare a second power switching device. The second power switching device has a third surface and a fourth surface disposed opposite to each other in a set direction. The third surface is provided with an active terminal, a drain terminal and a gate terminal.

[0076] In step S300', a conductive channel is fabricated in the second power switching device. The conductive channel passes through the second power switching device along a set direction and connects the drain terminal and the fourth surface. A multilayer composite metal conductive electrode layer electrically connected to the conductive channel is prepared on the fourth surface.

[0077] In step S400', the second power switching device is attached to the source electrical connection region, and the fourth surface is in contact with the source electrical connection region.

[0078] Step S500': Attach the capacitor to the drain electrical connection area and attach the drive module to the non-electrical connection area.

[0079] Step S600': Connect the drive module to the gate electrical connection area, connect the end of the capacitor that is not in contact with the source electrical connection area and the drain electrical connection area to the positive terminal of the DC bus, and ground the source terminal.

[0080] Based on the same inventive concept, embodiments of the present invention also provide a power conversion device, including the half-bridge power module in the embodiments described above.

[0081] The half-bridge power module, its fabrication method, and applications provided in this invention can be used in the following fields: high-frequency DC-DC buck / boost converters (for server power supplies, AI accelerator card power supplies, laptop adapters, etc.); half-bridge / full-bridge inverters (for motor drives, solar inverters, etc.); totem-pole bridgeless power factor correction circuits (for high-efficiency switching power supply front-end stages, etc.); LLC resonant converters (for data center power supplies, etc.); power integrated circuit modules (for consumer electronics fast charging adapters, wireless charging transmitters, etc.); electric vehicle on-board chargers and DC-DC converters.

[0082] In high-frequency buck applications from a 48V bus to a 12V load in a data center, extremely low power loop inductance is required to support low voltage overshoot at a 1MHz switching frequency, while also necessitating a compact drive circuit and on-chip decoupling. This example uses... Figure 2 The structure shown is used as an example in a high-frequency DC-DC buck converter application (48V→12V, switching frequency 1MHz) to illustrate the half-bridge power module and its fabrication method.

[0083] The parameters are set as follows: the substrate thickness after thinning is 100μm; the via diameter is 30μm, the via spacing is 60μm (twice the via diameter), and the array covers the source region; the first insulating layer SiO2 is 500nm thick, the diffusion barrier layer TaN is 20nm thick, and the filler metal is electroplated copper; the back-side source metallization layer is Ti (50nm) / Cu (5μm) / Ni (2μm) / Au (0.5μm) with a coverage of 75%; the conductive interconnect material is sintered silver with a thickness of 20μm (thermal conductivity >200W / (m·K)); the Si capacitor chip has a capacitance of 100nF and an area of ​​2×2mm. 2 The bottom insulating layer of the driver chip is made of polyimide with a thickness of 20μm.

[0084] The manufacturing steps are as follows, including steps 1-9.

[0085] Step 1: On the upper-side silicon-based gallium nitride wafer, a through-silicon via (TSV) pattern is defined on the back side of the chip corresponding to the source region using photolithography. Deep reactive ion etching (Bosch process) is then used to etch the silicon substrate from the back side until the AlGaN buffer layer below the front-side source metal layer is reached and then etched.

[0086] Step 2: A SiO2 insulating layer (500 nm) is deposited on the inner wall of the TSV via by plasma-enhanced chemical vapor deposition (PECVD). A TaN diffusion barrier layer (20 nm) and a Cu seed layer (100 nm) are then deposited by physical vapor deposition (PVD) sputtering. The via is then filled with copper by electroplating. Excess copper on the back side is planarized by chemical mechanical polishing.

[0087] Step 3: Thin the back side of the upper diode wafer to a target thickness of 100 μm (this step is omitted if thinning has already been performed before step 1). A Ti / Cu / Ni / Au back-side source metallization layer is formed on the back side by sputtering and electroplating.

[0088] Step 4: The lower transistor wafer is fabricated using conventional GaN HEMT technology, forming gate pads, source pads, drain pads, and a padless area on the front side. After wafer dicing, the lower transistor single chip is obtained.

[0089] Step 5: Mount the back of the lower transistor chip onto the direct copper-clad ceramic heat sink substrate using conductive silver paste.

[0090] Step 6: Screen print or dot apply sintering silver paste to the drain pad area on the front side of the lower transistor. Place the upper transistor chip on the drain area of ​​the lower transistor with the back side facing down. Sinter at 250~300℃ and 10~30MPa pressure for 15~30 minutes to achieve a strong electrical and thermal connection (i.e., SW node) between the source metallization layer on the back side of the upper transistor and the drain pad of the lower transistor.

[0091] Step 7: On the source pad area of ​​the lower transistor, solder the GND terminal of the silicon-based capacitor chip to the source pad of the lower transistor using solder bumps. The V of the capacitor chip... DC The terminal is connected to the drain pad on the front of the upper tube or the V-shaped terminal on the packaging substrate via wire bonding. DC Wiring.

[0092] Step 8: Apply a 20μm polyimide insulating layer to the pad-free area on the front side of the lower transistor. After curing, mount the gate driver chip for the upper transistor. The driver chip is connected to the gate pad and Kelvin source sensing pad on the front side of the upper transistor via wire bonding. The power supply and input signal pins of the driver chip are connected to the package pins via wire bonding.

[0093] Step 9: Complete the wire bonding of the lower transistor's gate pad to the package pin and V. DC Pin connections (to the drain pad of the upper MOSFET), GND pin connections (to the source pad of the lower MOSFET / GND terminal of the Si capacitor), and connections to all signal pins are made. Finally, molding and lead trimming are performed to form the GaN half-bridge power module.

[0094] The power module fabricated using the above process exhibits the following performance characteristics: total parasitic inductance of the power circuit is approximately 0.3nH, parasitic inductance of the drive circuit is approximately 0.3nH, and parasitic inductance of the decoupling circuit is approximately 0.5nH. Under operating conditions of 48V / 10A and 1MHz, the switching voltage overshoot is expected to be less than 3V. The module's projected area is approximately equal to the area of ​​the lower transistor chip (approximately 5×6mm²). 2 ).

[0095] The half-bridge power module, its fabrication method, and its application provided in this invention have the following advantages compared to the prior art.

[0096] (1) Extremely low parasitic inductance of power commutation circuit. Through the collaborative design of the upper TSV source back-lead process and vertical stacking direct bonding, the interconnect distance from the upper source to the lower drain is compressed to the substrate thickness level and is a full-area vertical interconnect. The power circuit inductance can be as low as 0.1~0.5nH, which is more than an order of magnitude lower than the traditional wire bonding scheme (1~5nH), supporting the efficient operation of GaN devices at MHz-level switching frequencies.

[0097] (2) Compact gate drive circuit. The upper transistor drive chip is directly stacked on top of the lower transistor chip and adjacent to the upper transistor. The drive circuit area is minimized, the drive signal transmission delay and waveform distortion are greatly reduced, and the false turn-on problem caused by voltage changes is effectively suppressed.

[0098] (3) Excellent decoupling effect. Silicon-based integrated capacitors are directly integrated inside the module in the form of chip stacking, and the parasitic inductance of the decoupling path is much lower than that of the printed circuit board level solution.

[0099] (4) Small package area and high power density. The three-dimensional stacked structure places the upper transistor, driver chip and decoupling capacitor on the lower transistor chip. The projected area of ​​the module is basically equal to the area of ​​the lower transistor chip, and the power density can reach 3 to 5 times that of the traditional side-by-side scheme.

[0100] (5) Clear thermal management path. The back of the lower MOSFET chip is directly mounted on the heat dissipation substrate; the upper MOSFET chip conducts heat downward to the drain region of the lower MOSFET through the metal filling in the TSV array and the back metallization layer, and then dissipates it through the heat dissipation substrate. Moreover, the thermal resistance requirement of the upper MOSFET is lower than that of the lower MOSFET, and the overall heat dissipation performance is controllable.

[0101] (6) Good process compatibility. The TSV process is compatible with existing silicon-based gallium nitride wafer manufacturing processes and can be completed at the wafer level. Stacking assembly can be performed using mature reflow soldering, thermoforming, or sintering processes.

[0102] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A half-bridge power module, comprising a first power switching device, a second power switching device, a drive module, and a capacitor, characterized in that: The first power switching device has a first surface and a second surface disposed opposite to each other in a set direction. The first surface has a drain electrical connection region, a source electrical connection region, a gate electrical connection region, and a non-electrical connection region distributed therein. The second power switching device has a third surface and a fourth surface disposed opposite to each other in a set direction. The third surface has a source terminal, a drain terminal, and a gate terminal distributed therein. The fourth surface has an electrical connection region distributed therein. The driving module is attached to the non-electrical connection region. The driving module is connected to the gate terminal. The second power switching device also has a conductive channel. The conductive channel passes through the second power switching device in a set direction and connects the electrical connection area of ​​the fourth surface and the source terminal. The second power switching device is attached to the drain electrical connection area through the fourth surface, and the capacitor is attached to the source electrical connection area. Alternatively, the driving module is connected to the gate electrical connection region: the second power switching device also has a conductive channel, the conductive channel passes through the second power switching device in a set direction and connects the electrical connection region of the fourth surface and the drain terminal, the second power switching device is attached to the source electrical connection region through the fourth surface, and the capacitor is attached to the drain electrical connection region.

2. The half-bridge power module according to claim 1, characterized in that, Regarding the structure of the drive module connected to the gate terminal: the drain terminal is connected to the other end of the capacitor and is used to connect to the positive terminal of the DC bus; the source electrical connection region is grounded, and the gate electrical connection region is used to connect to the external drive circuit; Regarding the structure of the drive module connected to the gate electrical connection region: the drain electrical connection region is connected to the other end of the capacitor and is used to connect to the positive terminal of the DC bus; the source terminal is grounded, and the gate terminal is used to connect to the external drive circuit.

3. The half-bridge power module according to claim 1, characterized in that, The conductive channel is a vertical conductive channel; And / or, the conductive channel includes: an array of through holes penetrating the second power switching device along a direction perpendicular to the third surface, a first insulating layer disposed on the inner wall of the through holes, a diffusion barrier layer disposed on the surface of the first insulating layer, and a conductive material filling the through holes.

4. The half-bridge power module according to claim 3, characterized in that, The diameter of the through hole is 5~100μm; And / or, the through-hole spacing is 1.5 to 5 times the through-hole diameter; And / or, the thickness of the first insulating layer is 100 nm to 1 μm; And / or, the thickness of the diffusion barrier layer is 5~50nm.

5. The half-bridge power module according to claim 1, characterized in that, Regarding the structure of the driving module connected to the gate terminal: the third surface is provided with an independent Kelvin source sensing pad, which is led out through a through-silicon via or a trace to provide an independent source reference potential for the driving module; Regarding the structure of the drive module connected to the gate electrical connection region: the first surface is provided with an independent Kelvin source sensing pad, which is led out through a through-silicon via or a trace; used to provide an independent source reference potential for the drive module.

6. The half-bridge power module according to claim 1, characterized in that, For the structure in which the driving module is connected to the gate terminal, the substrate thickness of the second power switching device is 50~200μm; for the structure in which the driving module is connected to the gate electrical connection region, the substrate thickness of the first power switching device is 50~200μm. And / or, a conductive interconnect layer is further provided between the first power switching device and the second power switching device, the thickness of the conductive interconnect layer being 5~50μm; And / or, the drive module is further provided with a second insulating layer on one side of the non-electrical connection area, the second insulating layer is located between the drive module and the non-electrical connection area, and the thickness of the second insulating layer is 5~50μm; And / or, the first surface is fixed to the device substrate by a thermally conductive adhesive medium or a conductive adhesive medium, wherein the device substrate includes a packaging substrate, a lead frame or a heat dissipation substrate; And / or, the ratio between the area of ​​the fourth surface electrical connection region and the area of ​​the fourth surface is not less than 60%.

7. The half-bridge power module according to claim 1, characterized in that, For the structure of the driving module connected to the gate terminal: the ratio between the area of ​​the drain electrical connection region and the area of ​​the first surface is 30%~50%, the ratio between the area of ​​the source electrical connection region and the area of ​​the first surface is 20%~40%, and the ratio between the area of ​​the non-electrical connection region and the area of ​​the first surface is 10%~30%. For the structure of the driving module connecting the gate electrical connection region: the ratio between the area of ​​the source electrical connection region and the area of ​​the first surface is 30%~50%, the ratio between the area of ​​the drain electrical connection region and the area of ​​the first surface is 20%~40%, and the ratio between the area of ​​the non-electrical connection region and the area of ​​the first surface is 10%~30%.

8. A method for fabricating a half-bridge power module, characterized in that, include: A first power switching device is fabricated, the first power switching device having a first surface and a second surface disposed opposite to each other in a set direction, the first surface having a drain electrical connection region, a source electrical connection region, a gate electrical connection region and a non-electrical connection region distributed thereon; A second power switching device is fabricated, the second power switching device having a third surface and a fourth surface disposed opposite to each other in a set direction, the third surface having an active terminal, a drain terminal and a gate terminal distributed thereon; Conductive channels are fabricated within the second power switching device. These conductive channels pass through the second power switching device in a predetermined direction and connect the source terminal and the fourth surface. A multilayer composite metal conductive electrode layer electrically connected to the conductive channels is fabricated on the fourth surface. The second power switching device is attached to the drain connection region, and the fourth surface is in contact with the drain connection region; The capacitor is attached to the source electrical connection area, and the drive module is attached to the non-electrical connection area; Connect the driving module to the gate terminal, connect the end of the capacitor that is not in contact with the source electrical connection region and the drain terminal to the positive terminal of the DC bus, and ground the source electrical connection region.

9. A method for fabricating a half-bridge power module, characterized in that, include: A first power switching device is fabricated, the first power switching device having a first surface and a second surface disposed opposite to each other in a set direction, the first surface having a drain electrical connection region, a source electrical connection region, a gate electrical connection region and a non-electrical connection region distributed thereon; A second power switching device is fabricated, the second power switching device having a third surface and a fourth surface disposed opposite to each other in a set direction, the third surface having an active terminal, a drain terminal and a gate terminal distributed thereon; A conductive channel is fabricated within the second power switching device. The conductive channel passes through the second power switching device in a predetermined direction and connects the drain terminal and the fourth surface. A multilayer composite metal conductive electrode layer electrically connected to the conductive channel is fabricated on the fourth surface. The second power switching device is attached to the source electrical connection region, and the fourth surface is in contact with the source electrical connection region; The capacitor is attached to the drain electrical connection area, and the driving module is attached to the non-electrical connection area; Connect the driving module to the gate electrical connection region, connect the end of the capacitor that is not in contact with the source electrical connection region and the drain electrical connection region to the positive terminal of the DC bus, and ground the source terminal.

10. A power conversion device, characterized in that, Includes the half-bridge power module as described in any one of claims 1-7.

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