Semiconductor device and manufacturing method, power module, power conversion circuit, and vehicle

Abstract

The embodiment of the application discloses a semiconductor device and a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body, a well region, a source region and a first insulating layer, wherein the semiconductor body comprises a first surface and a second surface; the source region is arranged on the first surface and is of a first conductive type; the well region is arranged on a side of the source region away from the first surface and is of a second conductive type; the first surface is provided with a gate trench and a source trench; the first insulating layer is arranged on a bottom surface of the gate trench; the first conductive type is different from the second conductive type; a metal layer is arranged in the source trench; a Schottky contact is formed between the metal layer and the semiconductor body; a gate electrode is arranged in the gate trench; a source electrode is arranged on the first surface; and a drain electrode is arranged on the second surface. The technical scheme of the embodiment of the application can reduce the device area, thereby reducing the packaging cost of the device, improving the breakdown capacity of the gate oxide layer, and improving the reliability of the semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a semiconductor device and manufacturing method, a power module, a power conversion circuit and a vehicle. BACKGROUND

[0002] Silicon carbide (SiC) and other wide bandgap semiconductor materials, as a representative of the third generation of semiconductor materials, have advantages such as high breakdown field, high thermal conductivity, high electron saturation velocity and strong radiation resistance, so semiconductor devices prepared by using SiC materials not only can operate stably at higher temperatures, but also are suitable for high-voltage and high-frequency scenarios.

[0003] The body diode of the SiC metal-oxide-semiconductor field-effect transistor (MOSFET) in the prior art often works in the third quadrant as a freewheeling diode. Since SiC is a wide bandgap material, the turn-on voltage of the body diode is relatively high, which increases the loss when the body diode is used as a freewheeling diode. After the body diode is turned on for a long time, the conduction resistance and blocking capability of the MOSFET may be degraded; and due to the poor reverse recovery characteristics of the body diode, a large current spike and turn-off surge voltage are generated in this process, which degrades the conduction characteristics of the MOSFET and may even damage the semiconductor device. Moreover, after the body diode is turned on for a long time, the conduction characteristics of the MOSFET may be degraded, and even the conduction resistance and blocking capability of the MOSFET may be degraded. The SiC MOSFET and the diode used for freewheeling are usually manufactured separately as two chips in the prior art.

[0004] However, the gate oxide layer of the existing SiC MOSFET structure has poor reliability, and the external diode not only increases the circuit size and manufacturing cost, but also introduces more parasitic capacitance and inductance, reduces the switching efficiency, and further reduces the reliability of the semiconductor device. SUMMARY

[0005] The present application provides a semiconductor device and manufacturing method, a power module, a power conversion circuit and a vehicle to reduce the device area, thereby reducing the packaging cost of the device, improving the breakdown capability of the gate oxide layer, and improving the reliability of the semiconductor device.

[0006] According to an aspect of the present application, a semiconductor device is provided, which includes: The semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a well region and a source region, the source region being configured with a first conductivity type and located on the first surface, and the well region being configured with a second conductivity type and located on the side of the source region away from the first surface; the first surface is provided with a gate trench and a source trench; the semiconductor body also includes a first insulating layer; the first insulating layer is located on the bottom surface of the gate trench; the first conductivity type and the second conductivity type are different; A metal layer is located within the source trench; a Schottky contact is formed between the metal layer and the semiconductor body. The gate is located within the gate trench; The source electrode is located on the first surface; The drain electrode is located on the second surface.

[0007] Optionally, the semiconductor body further includes a first region; the first region is configured with a second conductivity type and is located on the bottom surface of the source trench.

[0008] Optionally, the ion concentration in the first region is greater than the ion concentration in the well region.

[0009] Optionally, in the direction from the first surface to the second surface, the thickness of the first insulating layer is greater than or equal to 1000 angstroms and less than or equal to 1500 angstroms.

[0010] Optionally, the semiconductor body may include a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0011] According to another aspect of this application, a method for manufacturing a semiconductor device is provided, the method comprising: A semiconductor body is provided; the semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a well region and a source region, the source region being configured with a first conductivity type and located on the first surface, and the well region being configured with a second conductivity type and located on the side of the source region away from the first surface; the first surface is provided with a gate trench and a source trench; the semiconductor body also includes a first insulating layer; the first insulating layer is located on the bottom surface of the gate trench; the first conductivity type and the second conductivity type are different; A metal layer is formed within the source trench; a Schottky contact is formed between the metal layer and the semiconductor body. A gate is formed within the gate trench; A source electrode is formed on the first surface; A drain electrode is formed on the second surface.

[0012] Optionally, a semiconductor body is provided, including: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other; A first insulating layer is formed within the semiconductor body; A transition well region is formed within the semiconductor body; the transition well region is configured as a second conductivity type. A transition source region is formed on the first surface; the transition source region is configured with a first conductivity type. A gate trench is formed on the first surface; a first insulating layer is located on the bottom surface of the gate trench; A source trench is formed on the first surface; the transition well region retained after forming the gate trench and the source trench is used as the well region, and the retained transition source region is used as the source region.

[0013] Optionally, the semiconductor body includes: Provide a semiconductor body including a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0014] According to another aspect of this application, a power module is provided, the power module including a substrate and at least one of the above-described semiconductor devices, the substrate being used to support the semiconductor devices.

[0015] According to another aspect of this application, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one of the aforementioned semiconductor devices, which are electrically connected to the circuit board.

[0016] According to another aspect of this application, a vehicle is provided, the vehicle including a load and the aforementioned power conversion circuit, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.

[0017] The technical solution of this application provides a semiconductor device. By setting a first insulating layer as a gate oxide layer on the bottom surface of the gate trench, the problem of small gate oxide layer thickness at the bottom of the gate trench is solved. The bottom surface of the gate trench is on the surface of the first insulating layer, improving the breakdown capability of the gate oxide layer. Simultaneously, by setting a metal layer inside the source trench, forming a Schottky contact with the semiconductor body, a Schottky barrier diode (SBD) is integrated into the semiconductor device, reducing the size of the semiconductor device. This reduces the packaging cost of the semiconductor device, eliminates parasitic inductance or capacitance caused by external bonding wires, improves the switching efficiency of the semiconductor device, and ultimately enhances its reliability.

[0018] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of this application; Figure 2 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application; Figures 3-6 These are cross-sectional views corresponding to each step of a semiconductor device manufacturing method provided according to embodiments of this application; Figure 7 Provided according to the embodiments of this application Figure 2 The flowchart included in S110; Figures 8-11 Provided according to the embodiments of this application Figure 7 Cross-sectional views corresponding to each step in the process. Detailed Implementation

[0021] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0022] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] Figure 1 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of this application. For example... Figure 1As shown, the semiconductor device includes: a semiconductor body 100, including a first surface 101 and a second surface 102 disposed opposite to each other; the semiconductor body 100 also includes a well region 103 and a source region 104, the source region 104 being configured with a first conductivity type and located on the first surface 101, and the well region 103 being configured with a second conductivity type and located on the side of the source region 104 away from the first surface 101; the first surface 101 is provided with a gate trench 30 and a source trench 40; the semiconductor body 100 also includes a first insulating layer 31; the first insulating layer 31 is located on the bottom surface of the gate trench 30; the first conductivity type and the second conductivity type are different; a metal layer 41 is located in the source trench 40; a Schottky contact is formed between the metal layer 41 and the semiconductor body 100; a gate 50 is located in the gate trench 30; a source 60 is located on the first surface 101; and a drain 70 is located on the second surface 102.

[0024] In this embodiment, the semiconductor device includes, but is not limited to, an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide-bandgap semiconductor material such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type.

[0025] For example, in an N-type MOSFET, the source region 104 is an N+ doped region, and the N-type dopant ions in the N+ doped region can be phosphorus (P) ions or nitrogen (N) ions. The well region 103 is a P-well region, and the P-type dopant ions in the P-well region can be aluminum (Al) ions or boron (B) ions. The source region 104 can be formed on the first surface 101 of the semiconductor body 100 by processes such as ion implantation, ion diffusion, or vapor deposition.

[0026] like Figure 1 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of this application, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of this application, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 by one or more epitaxial processes, including chemical vapor deposition (CVE), molecular beam epitaxy (MBE), and atomic layer epitaxy (ALE).

[0027] The first surface 101 of the semiconductor body 100 is provided with a gate trench 30 and a source trench 40. The gate trench 30 and the source trench 40 can be formed by photolithography and etching processes. A first insulating layer 31 is provided on the bottom surface of the gate trench 30, and a second insulating layer 32 is provided on the bottom and sidewalls of the gate trench 30. The first insulating layer 31 and the second insulating layer 32 together serve to insulate and isolate the semiconductor body 100 and the gate 50. The first insulating layer 31 and the second insulating layer 32 can be gate oxide layers, and the materials include, but are not limited to, silicon dioxide. The material of the gate 50 can be polysilicon. The material of the metal layer 41 includes, but is not limited to, titanium (Ti), nickel (Ni), or silver (Ag). The metal layer 41 is located in the source trench 40 and forms a Schottky contact with the semiconductor body 100, thereby integrating the Schottky diode inside the semiconductor device.

[0028] In an optional embodiment of this application, the semiconductor device further includes: an interlayer insulating layer 80; the interlayer insulating layer 80 is located on the first surface 101; the vertical projection of the interlayer insulating layer 80 on the first surface 101 covers the vertical projection of the gate trench 30 on the first surface 101. The material of the interlayer insulating layer 80 may be silicon dioxide. The interlayer insulating layer 80 can achieve electrical isolation, prevent electron migration between different metal layers, and avoid diffusion or penetration between substances. The interlayer insulating layer 80 can be formed by plasma-enhanced chemical vapor deposition.

[0029] The source electrode 60 can be formed by depositing metal on the first surface 101, and the drain electrode 70 can be formed by depositing metal on the second surface 102. The deposited metal includes, but is not limited to, titanium (Ti), nickel (Ni), or silver (Ag).

[0030] In the semiconductor device of this embodiment, when the voltage applied between the gate 50 and the source 60 is greater than the threshold voltage of the semiconductor device, the gate 50 attracts minority carriers in the well region 103 to move towards the gate 50, causing the portion of the well region 103 near the gate trench 30 to invert to the first conductivity type. That is, at this time, the conductivity types of the portions of the source region 104 and the well region 103 near the gate trench 30 are the same. When a voltage is applied between the source 60 and the drain 70, current is generated, and the semiconductor device is in a conducting state. When the gate electric field disappears, the inverted channel in the well region 103 near the gate trench 30 disappears, and the conductive channel is cut off. When a motor or inductive load is turned off, a reverse induced electromotive force is generated, requiring a freewheeling channel to release energy. In the semiconductor device of this embodiment, freewheeling is accomplished by integrating an SBD. The turn-on voltage of the SBD is much lower than that of the body diode, and the freewheeling conduction voltage drop is smaller, which can reduce the heat loss of the semiconductor device.

[0031] Furthermore, for silicon carbide (and other wide-bandgap) semiconductor devices, silicon carbide has a higher breakdown field strength, making it more suitable for high-voltage applications. When a silicon carbide semiconductor device is turned on, electric field lines converge at the corners of the gate trench 30, resulting in a local electric field strength much higher than other areas. Simultaneously, the geometric structure at the corners (such as sharp corners or curvature) further enhances the electric field due to the tip effect, ultimately causing the insulating layer at the corners of the gate trench 30 to be easily broken down first, leading to semiconductor device failure. In the semiconductor device of this embodiment, a second insulating layer 32 is provided at the bottom and sidewalls of the gate trench 30, and a first insulating layer 31 is provided on the bottom surface of the gate trench 30, improving the breakdown capability of the insulating layer.

[0032] The technical solution of this application provides a semiconductor device. By setting a first insulating layer as a gate oxide layer on the bottom surface of the gate trench, the problem of small gate oxide layer thickness at the bottom of the gate trench is solved. The bottom surface of the gate trench is on the surface of the first insulating layer, improving the breakdown capability of the gate oxide layer. Simultaneously, by setting a metal layer inside the source trench, forming a Schottky contact with the semiconductor body, the SBD is integrated into the semiconductor device, reducing the size of the semiconductor device. This reduces the packaging cost of the semiconductor device, eliminates parasitic inductance or capacitance caused by external bonding wires, improves the switching efficiency of the semiconductor device, and thus enhances the reliability of the semiconductor device.

[0033] In optional embodiments of this application, reference is made to Figure 1 The semiconductor body also includes a first region 105; the first region 105 is configured as a second conductivity type and is located on the bottom surface of the source trench 40.

[0034] In this embodiment, the first region 105 is a P+ doped region. The P-type dopant ions in the P+ doped region can be aluminum (Al) ions or boron (B) ions. By setting the first region 105 on the bottom surface of the source trench 40, the boundary of the Schottky contact can be defined, thereby improving the reverse breakdown voltage capability of the Schottky diode and suppressing surface leakage current.

[0035] In optional embodiments of this application, reference is made to Figure 1 The ion concentration in the first region 105 is greater than the ion concentration in the well region 103.

[0036] In this embodiment, the ion concentration in the first region 105 is set to be greater than the ion concentration in the well region 103, so that a good ohmic contact can be formed between the metal layer 41 and the source 60.

[0037] In optional embodiments of this application, reference is made to Figure 1In the direction X from the first surface 101 to the second surface 102, the thickness of the first insulating layer 31 is greater than or equal to 1000 angstroms and less than or equal to 1500 angstroms.

[0038] In this embodiment, setting a lower limit for the thickness of the first insulating layer 31 ensures sufficient thickness for electric field mitigation, suppressing electric field breakdown at the bottom of the gate trench 30. Setting an upper limit for the thickness of the first insulating layer 31 avoids process failures and structural distortions caused by excessive thickness, and also prevents excessive increase in gate parasitic capacitance.

[0039] In optional embodiments of this application, reference is made to Figure 1 The semiconductor body 100 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0040] The semiconductor body 100 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. The semiconductor body 100 also includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.

[0041] Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high voltage withstand, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0042] Figure 2 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 2 As shown, the method for manufacturing this semiconductor device includes: S110. A semiconductor body is provided; the semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a well region and a source region, the source region is configured with a first conductivity type and located on the first surface, and the well region is configured with a second conductivity type and located on the side of the source region away from the first surface; the first surface is provided with a gate trench and a source trench; the semiconductor body also includes a first insulating layer; the first insulating layer is located on the bottom surface of the gate trench; the first conductivity type and the second conductivity type are different.

[0043] refer to Figure 3 A semiconductor body 100 is provided; the semiconductor body 100 includes a first surface 101 and a second surface 102 disposed opposite to each other; the semiconductor body 100 also includes a well region 103 and a source region 104, the source region 104 is configured with a first conductivity type and is located on the first surface 101, and the well region 103 is configured with a second conductivity type and is located on the side of the source region 104 away from the first surface 101; the first surface 101 is provided with a gate trench 30 and a source trench 40; the semiconductor body 100 also includes a first insulating layer 31; the first insulating layer 31 is located on the bottom surface of the gate trench 30; the first conductivity type and the second conductivity type are different.

[0044] In this embodiment, the semiconductor device includes, but is not limited to, an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide-bandgap semiconductor material such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type.

[0045] For example, in an N-type MOSFET, the source region 104 is an N+ doped region, and the N-type dopant ions in the N+ doped region can be phosphorus (P) ions or nitrogen (N) ions. The well region 103 is a P-well region, and the P-type dopant ions in the P-well region can be aluminum (Al) ions or boron (B) ions. The source region 104 can be formed on the first surface 101 of the semiconductor body 100 by processes such as ion implantation, ion diffusion, or vapor deposition. The semiconductor body also includes a first region 105, which is a P+ doped region. The first region 105 is located on the bottom surface of the source trench 40.

[0046] like Figure 3 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of this application, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of this application, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 by one or more epitaxial processes, including chemical vapor deposition (CVE), molecular beam epitaxy (MBE), and atomic layer epitaxy (ALE).

[0047] The first surface 101 of the semiconductor body 100 is provided with a gate trench 30 and a source trench 40. The gate trench 30 and the source trench 40 can be formed by photolithography and etching processes. The first insulating layer 31 can be a gate oxide layer, and the material includes, but is not limited to, silicon dioxide.

[0048] S120. A metal layer is formed in the source trench; a Schottky contact is formed between the metal layer and the semiconductor body.

[0049] refer to Figure 4 A metal layer 41 is formed within the source trench 40; a Schottky contact is formed between the metal layer 41 and the semiconductor body 100. The material of the metal layer 41 includes, but is not limited to, titanium (Ti), nickel (Ni), or silver (Ag). The metal layer 41 is located within the source trench 40 and forms a Schottky contact with the semiconductor body 100, thereby integrating the Schottky diode inside the semiconductor device.

[0050] S130, A gate is formed in the gate trench.

[0051] In an optional embodiment of this application, before forming the gate in the gate trench, the method further includes forming a second insulating layer at the bottom and sidewalls of the gate trench.

[0052] refer to Figure 5 A second insulating layer 32 is formed by sacrificial oxidation at the bottom and sidewalls of the gate trench 30. The first insulating layer 31 and the second insulating layer 32 together serve to insulate and isolate the semiconductor body 100 and the gate 50. The second insulating layer 32 may be a gate oxide layer, and the material may include, but is not limited to, silicon dioxide.

[0053] Continue to refer to Figure 5 Polysilicon is deposited on the side of the second insulating layer 32 away from the semiconductor body 100 within the gate trench 30 to form the gate 50.

[0054] S140, a source electrode is formed on the first surface.

[0055] refer to Figure 6 The source electrode 60 is formed by depositing metal on the first surface 101. The deposited metal includes, but is not limited to, titanium (Ti), nickel (Ni), or silver (Ag). Before forming the source electrode 60, an interlayer insulating layer 80 is formed on the first surface 101. The interlayer insulating layer 80 provides electrical isolation between the gate electrode 50 and the source electrode 60, preventing electron migration between different metal layers and avoiding diffusion or penetration between substances. The material of the interlayer insulating layer 80 can be silicon dioxide. The interlayer insulating layer 80 can be formed by plasma-enhanced chemical vapor deposition.

[0056] S150, a drain electrode is formed on the second surface.

[0057] refer to Figure 1 A drain electrode 70 is formed by depositing metal on the second surface 102. The deposited metal includes, but is not limited to, titanium (Ti), nickel (Ni), or silver (Ag).

[0058] The technical solution of this application provides a method for manufacturing a semiconductor device. By forming a first insulating layer as a gate oxide layer on the bottom surface of the gate trench, the problem of small gate oxide layer thickness at the bottom of the gate trench is solved. The bottom surface of the gate trench is on the surface of the first insulating layer, improving the breakdown capability of the gate oxide layer. Simultaneously, by forming a metal layer inside the source trench, and forming a Schottky contact between the metal layer and the semiconductor body, the SBD is integrated into the semiconductor device, reducing the size of the semiconductor device. This reduces the packaging cost of the semiconductor device, eliminates parasitic inductance or capacitance caused by external bonding wires, improves the switching efficiency of the formed semiconductor device, and thus enhances the reliability of the formed semiconductor device.

[0059] Figure 7Provided according to the embodiments of this application Figure 2 The flowchart included in S110. In optional embodiments of this application, refer to... Figure 7 S110, providing a semiconductor body, including: S1101. A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other.

[0060] refer to Figure 8 A semiconductor body 100 is provided, comprising a first surface 101 and a second surface 102 disposed opposite to each other. The semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of this application, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of this application, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 by one or more epitaxial processes.

[0061] S1102, A first insulating layer is formed within the semiconductor body.

[0062] refer to Figure 9 The first surface 101 of the semiconductor body 100 is etched to form a transition trench, and silicon oxide is deposited in the transition trench to form a first insulating layer 31.

[0063] S1103, A transition well region is formed within the semiconductor body; the transition well region is configured as a second conductivity type.

[0064] refer to Figure 9 and Figure 10 After forming the first insulating layer 31, silicon carbide is grown on the side of the first insulating layer 31 away from the second surface 102 using an epitaxial process to fill the transition trench. P-type ion implantation is then performed within the semiconductor body 100 to form a transition well region 1031.

[0065] S1104. A transition source region is formed on the first surface; the transition source region is set to a first conductivity type.

[0066] refer to Figure 10 N-type ion implantation is performed on the first surface 101 to form a transition source region 1041.

[0067] S1105, A gate trench is formed on the first surface; a first insulating layer is located on the bottom surface of the gate trench.

[0068] refer to Figure 11 A gate trench 30 is formed by etching on the first surface 101; a first insulating layer 31 is located on the bottom surface of the gate trench 30.

[0069] S1106. A source trench is formed on the first surface; the transition well region retained after forming the gate trench and the source trench is used as the well region, and the retained transition source region is used as the source region.

[0070] refer to Figure 3 Source trench 40 is formed by etching on the first surface 101; the transition well region retained after the source trench 40 is formed is called well region 103, and the retained transition source region is called source region 104.

[0071] In optional embodiments of this application, S110, providing a semiconductor body includes: providing a semiconductor body including a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0072] For details, please refer to Figure 1 The semiconductor body 100 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. The semiconductor body 100 also includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.

[0073] Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high voltage withstand, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0074] This application provides a power module including a substrate and at least one semiconductor device as described in any embodiment of this application, wherein the substrate is used to support the semiconductor device. Therefore, the beneficial effects of this power module including any semiconductor device as described in any embodiment of this application will not be elaborated further here.

[0075] This application provides a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this application, and the semiconductor device is electrically connected to the circuit board.

[0076] Therefore, the power conversion circuit incorporates the beneficial effects of any semiconductor device described in any embodiment of this application, which will not be elaborated further here.

[0077] This application embodiment also provides a vehicle, which includes a load and the aforementioned power conversion circuit. The power conversion circuit is used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

[0078] Therefore, the beneficial effects of the vehicle including any of the power conversion circuit packages described in any embodiment of this application will not be repeated here.

[0079] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.

[0080] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a well region and a source region, the source region being configured with a first conductivity type and located on the first surface, and the well region being configured with a second conductivity type and located on the side of the source region away from the first surface; the first surface is provided with a gate trench and a source trench; the semiconductor body also includes a first insulating layer; the first insulating layer is located on the bottom surface of the gate trench; the first conductivity type and the second conductivity type are different; A metal layer is located within the source trench; A Schottky contact is formed between the metal layer and the semiconductor body; The gate is located within the gate trench; The source electrode is located on the first surface; The drain electrode is located on the second surface.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor body further includes a first region; the first region is configured with a second conductivity type and is located on the bottom surface of the source trench.

3. The semiconductor device according to claim 2, characterized in that, The ion concentration in the first region is greater than the ion concentration in the well region.

4. The semiconductor device according to claim 1, characterized in that, In the direction from the first surface to the second surface, the thickness of the first insulating layer is greater than or equal to 1000 angstroms and less than or equal to 1500 angstroms.

5. The semiconductor device according to claim 1, characterized in that, The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

6. A method for manufacturing a semiconductor device, characterized in that, include: A semiconductor body is provided; the semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region and a source region, the source region being configured with a first conductivity type and located on the first surface, and the well region being configured with a second conductivity type and located on the side of the source region away from the first surface; the first surface is provided with a gate trench and a source trench; the semiconductor body further includes a first insulating layer; the first insulating layer is located on the bottom surface of the gate trench; the first conductivity type and the second conductivity type are different; A metal layer is formed within the source trench; a Schottky contact is formed between the metal layer and the semiconductor body; A gate is formed within the gate trench; A source electrode is formed on the first surface; A drain electrode is formed on the second surface.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, Provide semiconductor bodies, including: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other; A first insulating layer is formed within the semiconductor body; A transition well region is formed within the semiconductor body; the transition well region is configured with a second conductivity type. A transition source region is formed on the first surface; the transition source region is configured with a first conductivity type. A gate trench is formed on the first surface; the first insulating layer is located on the bottom surface of the gate trench; A source trench is formed on the first surface; the transition well region retained after forming the gate trench and the source trench is used as the well region, and the retained transition source region is used as the source region.

8. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The semiconductor body includes: Provide a semiconductor body including a silicon carbide semiconductor body or a gallium nitride semiconductor body.

9. A power module, characterized in that, The invention includes a substrate and the semiconductor device according to any one of claims 1-5, wherein the substrate is used to support the semiconductor device.

10. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1-5, wherein the semiconductor device is electrically connected to the circuit board.

11. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 10, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

Images