Semiconductor device structure and method of forming the same

Abstract

Various embodiments of the present disclosure provide semiconductor device structures and methods of manufacturing the same. In one embodiment, a method includes forming a semiconductor layer stack over a substrate, and the semiconductor layer stack includes a plurality of first semiconductor layers and a plurality of second semiconductor layers in an alternating stack. The method also includes removing a plurality of portions of the semiconductor layer stack, removing the second semiconductor layers, depositing a dielectric material between vertically adjacent first semiconductor layers, laterally etching the dielectric material to form a plurality of recesses, and depositing a semiconductor cap layer in the recesses. The semiconductor cap layer is a continuous film layer and connects the vertically adjacent first semiconductor layers. The method also includes forming third semiconductor layers from the semiconductor cap layer, removing the dielectric material, and forming a plurality of intermediate layers to separate the semiconductor cap layer into a plurality of portions.

Description

Technical Field

[0001] This invention relates to semiconductor device structures and methods of forming the same, and more particularly to semiconductor device structures having a semiconductor capping layer and an intermediate layer. Background Technology

[0002] The integrated circuits (IC) industry has experienced exponential growth. Advances in modern technology regarding IC materials and design have led to several generations of ICs, each with smaller and more complex circuits than the previous generation. In the development of ICs, functional density (the number of interconnects per unit wafer area) has generally increased while geometry (the smallest element (or line) that can be manufactured using the process) has decreased. This miniaturization process generally benefits production efficiency and reduces associated costs. However, this miniaturization presents new challenges. For example, to improve carrier mobility and drive current in devices, transistors employing nanostructured channels have been proposed. Inner spacers are typically placed between the metal gate and the source / drain (S / D) structure to protect the source / drain structure from damage during subsequent gate replacement processes. While the formation of inner spacers generally achieves its intended purpose, it is not entirely satisfactory in all aspects. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device structure and a method for forming the same, in order to solve at least one of the problems mentioned above.

[0004] This invention provides a method for forming a semiconductor device structure, comprising forming a semiconductor layer stack above a substrate, wherein the semiconductor layer stack includes a plurality of alternating stacked first semiconductor layers and a plurality of second semiconductor layers; removing a plurality of portions of the semiconductor layer stack; removing a second semiconductor layer; depositing a dielectric material between vertically adjacent first semiconductor layers; laterally etching the dielectric material to form a plurality of recesses; depositing a semiconductor capping layer in the recesses, wherein the semiconductor capping layer is a continuous film layer and connects the vertically adjacent first semiconductor layers; forming a third semiconductor layer from the semiconductor capping layer; removing the dielectric material; and forming a plurality of intermediate layers to divide the semiconductor capping layer into a plurality of portions.

[0005] This invention provides a method for forming a semiconductor device structure, comprising forming a semiconductor layer stack above a substrate, wherein the semiconductor layer stack includes a plurality of alternating stacked first semiconductor layers and a plurality of second semiconductor layers; removing a plurality of portions of the semiconductor layer stack; removing the second semiconductor layers; depositing a dielectric material between vertically adjacent first semiconductor layers; laterally etching the dielectric material to form a plurality of recesses; depositing a semiconductor capping layer in the recesses, wherein the semiconductor capping layer is a continuous film layer and connects the vertically adjacent first semiconductor layers; removing the dielectric material; and forming a plurality of intermediate layers and a plurality of interface layers.

[0006] This invention provides a semiconductor device structure comprising a plurality of vertically stacked first semiconductor layers, including a top first semiconductor layer, a middle first semiconductor layer, and a bottom first semiconductor layer; a semiconductor capping layer disposed on a side surface of the middle first semiconductor layer, an edge portion of the top surface of the middle first semiconductor layer, and an edge portion of the bottom surface of the middle first semiconductor layer; a second semiconductor layer disposed adjacent to the semiconductor capping layer; and an intermediate layer disposed between the top first semiconductor layer and the middle first semiconductor layer, wherein the intermediate layer and the second semiconductor layer intersect. Attached Figure Description

[0007] The embodiments of the invention can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of various components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of the invention.

[0008] Figure 1 , Figure 2 , Figure 3 , Figure 4 as well as Figure 5 These are perspective schematic diagrams illustrating various stages of manufacturing a semiconductor device structure, according to some embodiments.

[0009] Figure 6 , Figure 7 , Figure 8A , Figure 8B , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 as well as Figure 16 According to some embodiments, various stages along the fabrication of a semiconductor device structure are illustrated. Figure 5 A side view diagram of the section AA.

[0010] Figure 17 as well as Figure 18According to alternative embodiments, various stages of manufacturing a semiconductor device structure are illustrated along... Figure 5 A side view diagram of the section AA.

[0011] The attached figures are labeled as follows: 100: Semiconductor device structure 101: Substrate 104: Semiconductor layer stacking 106: First semiconductor layer 108: Second semiconductor layer 110: Oxide layer 111: Nitride layer 112: Fin structure 114: Trench 116: Substrate portion 118: Insulating materials 119: Trench 120: Isolation Zone 130: Sacrificial gate structure 132: Sacrificial gate dielectric layer 134: Sacrificial gate electrode layer 135: Oxide layer 136: Masking layer 137: Nitride layer 138: Spacer 138a: First spacer 138b: Second spacer 139: Dielectric layer 141: Opening 143: Dielectric Materials 144: Semiconductor capping layer 145: Concave hole 147: Air gap 149: Intermediate Layer 150: Basal layer 152: Semiconductor layer 154: Semiconductor layer 156: Stress layer 162: Contact Etching Stop Layer 164: Interlayer dielectric layer 180: Gate dielectric layer 181: Interface Layer 182: Work function metal layer 184: Metal filler 190: Gate structure 196: Dielectric Liner 198: Dielectric Materials AA: Section X: Direction Y: direction Z: Direction Detailed Implementation

[0012] Numerous embodiments or examples are disclosed below for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, the embodiments of the invention may repeat reference values ​​and / or letters in various examples. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0013] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," and "higher," may be used to facilitate the description of the relationship between one or more components or features in the accompanying drawings and another component or feature(s). Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0014] While embodiments of this disclosure are discussed with respect to nanostructured channel field-effect transistors (FETs), such as horizontal gate all-around (HGAA) FETs, vertical gate all-around (VGAA) FETs, and other suitable devices, it will be readily understood by those skilled in the art that other modifications may be made within the scope of this disclosure. In the case of an all-around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more optical lithography processes (including dual-patterning or multi-patterning processes). Generally, dual-patterning or multi-patterning processes combine lithography with self-alignment processes to create, for example, patterns with smaller pitch than those obtained using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. After removing the sacrificial layer, the remaining spacers can be used as a mask to pattern the GAA structure.

[0015] Figures 1 to 16 This describes a non-limiting process for manufacturing a semiconductor device structure 100 according to an embodiment of the present invention. It should be understood that for additional embodiments of the method, [further details may be needed]. Figures 1 to 16 Additional operations are provided before, during, and after the processes shown, and some of the operations described below can be replaced or deleted. The order of operations / processes is not limited to this and can be interchanged.

[0016] Figures 1 to 5 This is a perspective schematic diagram illustrating various stages of manufacturing a semiconductor device structure 100, according to some embodiments. Figure 1As shown, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed over the surface of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may contain crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), indium phosphide (InP), or combinations thereof. In one embodiment, the substrate 101 is formed of Si. The substrate 101 may be doped or undoped. The substrate 101 may be a bulk semiconductor substrate, such as a wafer-sized bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a multilayer or gradient substrate, or the like.

[0017] The substrate 101 may contain regions with various doped impurities (e.g., dopants with p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus for n-type field effect transistors (NFETs) and boron for p-type field effect transistors (PFETs).

[0018] Semiconductor layer stack 104 includes alternating semiconductor layers formed of different materials to facilitate the formation of nanosheet channels, such as nanosheet channel FETs, in multi-gate devices. In some embodiments, semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108 vertically stacked above substrate 101. In some embodiments, semiconductor layer stack 104 includes alternating first semiconductor layer 106 and second semiconductor layer 108. The first semiconductor layer 106 and the second semiconductor layer 108 are formed of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 may be formed of Si, and the second semiconductor layer 108 may be formed of SiGe. In some examples, the first semiconductor layer 106 may be formed of SiGe, and the second semiconductor layer 108 may be formed of Si. Alternatively, in some embodiments, either the first semiconductor layer 106 or the second semiconductor layer 108 may be or may contain other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0019] The first semiconductor layer 106 and the second semiconductor layer 108 can be formed by any suitable deposition process, such as epitaxy. For example, the epitaxial growth of the film layers of the semiconductor layer stack 104 can be performed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0020] The first semiconductor layer 106 or portions thereof may form nanosheet channels(s) of the semiconductor device structure 100 in subsequent manufacturing stages. As used herein, the term "nanosheet" refers to any portion of material having a nanometer or even micrometer-scale size and an elongated shape, regardless of the cross-sectional shape of this portion. Thus, the term refers both to elongated material portions with circular cross-sections and to bundled or strip-shaped material portions, including, for example, cylindrical or substantially rectangular cross-sections. The nanosheet channels(s) of the semiconductor device structure 100 may be surrounded by a gate structure. The semiconductor device structure 100 may include nanosheet transistors. Nanosheet transistors may be referred to as nanowire transistors, gate-wound-all-apart (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having a gate structure surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 will be further discussed below.

[0021] Each first semiconductor layer 106 may have a thickness ranging from about 3 nm to about 30 nm, such as from about 3 nm to about 10 nm. Each second semiconductor layer 108 may have a thickness equal to, less than, or greater than that of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness ranging from about 2 nm to about 50 nm. Figure 1 The illustration shows three first semiconductor layers 106 and three second semiconductor layers 108 in an alternating configuration, which is merely illustrative and not intended to limit the scope of this disclosure beyond what is expressly stated in the claims. It will be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels in the semiconductor device structure 100. Figure 1 As shown, an oxide layer 110 is formed on the topmost first semiconductor layer 106, and a nitride layer 111 is formed on the oxide layer 110. The oxide layer 110 may be silicon oxide and may have different etch selectivity compared to the nitride layer 111. The nitride layer 111 may contain any suitable nitride material, such as silicon nitride. In some embodiments, the oxide layer 110 and the nitride layer 111 may be a mask structure.

[0022] exist Figure 2 In this configuration, fin structures 112 are formed from a semiconductor layer stack 104. Each fin structure 112 has an upper portion comprising a first semiconductor layer 106, a second semiconductor layer 108, and a substrate portion 116 formed from a substrate 101. The fin structures 112 can be formed by performing multiple patterning operations using optical lithography and etching processes on a hard mask layer (such as an oxide layer 110 and a nitride layer 111) formed on the semiconductor layer stack 104. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The optical lithography process can include forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to the pattern, performing a post-exposure baking process, and developing the photoresist layer to form a mask element comprising the photoresist layer. In some embodiments, an electron beam lithography process can be used to pattern the photoresist layer to form the mask element. The etching process forms trenches 114 in unprotected areas that penetrate the hard mask layer, pass through the semiconductor stack 104, and extend into the substrate 101, leaving a plurality of extended fin structures 112. The trenches 114 extend in the X direction. The trenches 114 can be etched using dry etching (e.g., RIE), wet etching, and / or a combination thereof.

[0023] exist Figure 3 In this process, after forming the fin structure 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Next, a planarization operation, such as chemical mechanical polishing (CMP) and / or etch-back, is performed to expose the top of the fin structure 112. The insulating material 118 can be formed of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-dielectric-constant dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition (FCVD).

[0024] exist Figure 4 In this process, insulating material 118 is etched to form isolation region 120. The etching of insulating material 118 exposes multiple portions of fin structure 112, such as semiconductor layer stack 104. The etching of insulating material 118 exposes trenches 114 between adjacent fin structures 112. Isolation region 120 can be formed using appropriate processes, such as dry etching, wet etching, or a combination thereof. The top surface of insulating material 118 may be flush with or below the surface of the second semiconductor layer 108 in contact with the substrate portion 116 formed from the substrate 101.

[0025] exist Figure 5 In this process, one or more sacrificial gate structures 130 (two shown only) are formed over a semiconductor device structure 100. The sacrificial gate structure 130 is formed over a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a masking layer 136. In some embodiments, the masking layer 136 is a multi-layer structure. For example, the masking layer 136 includes an oxide layer 135 and a nitride layer 137 formed on the oxide layer 135. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the masking layer 136 can be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the masking layer 136, and then patterning these layers into a sacrificial gate structure 130. The sacrificial gate dielectric layer 132 may include one or more layers of dielectric material, such as silicon oxide (SiO2). x The material may be silicon oxide-based or the sacrificial gate electrode layer 134 may contain silicon, such as polycrystalline silicon or amorphous silicon. Although only two sacrificial gate structures 130 are shown, in some embodiments, two or more sacrificial gate structures 130 may be configured along the X direction.

[0026] The portions of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serve as channel regions of the semiconductor device structure 100. The fin structure 112, partially exposed on both sides of the sacrificial gate structure 130, defines the source / drain (S / D) regions of the semiconductor device structure 100. In some cases, some S / D regions can be shared among multiple transistors. For example, multiple S / D regions can be connected together and implemented as multiple functional transistors. It should be understood that source and drain regions are used interchangeably because the epitaxial components formed in these regions are substantially the same. Depending on the context, source / drain regions can refer individually to the source or drain, or collectively to the source or drain.

[0027] Figures 6 to 16 According to some embodiments, various stages of manufacturing the semiconductor device structure 100 are shown along... Figure 5 A side view diagram of a section AA taken from fin structure 112. Section AA is located at fin structure 112. Figure 5 In the plane along the direction X. Figure 5 and Figure 6 The main difference is, for ease of explanation, Figure 6 Three exemplary sacrificial gate structures 130 configured along direction X are shown. Furthermore, for simplicity, Figures 6 to 16 The mask layer 136 is omitted.

[0028] Next, as Figure 7 As shown, spacers 138 are formed on the sidewalls of the sacrificial gate structure 130. Spacers 138 can be formed by conformally depositing one or more film layers (e.g., first spacer 138a and second spacer 138b) and then anisotropically etching the aforementioned one or more film layers. The first spacer 138a and second spacer 138b can be formed of dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof.

[0029] Next, the fin structure 112 ( Figure 5 The portion not covered by the sacrificial gate structure 130 and spacer 138 is etched into the isolation region 120. Figure 5 The fin structure 112 is located at the top surface, above the top surface, or below the top surface. The etching of multiple portions of the fin structure 112 can be accomplished by an etching process, which can be an isotropic or anisotropic etching process, and can selectively etch the semiconductor materials of the first semiconductor layer 106 and the second semiconductor layer 108. The etching process can be dry etching, such as RIE, neutral beam etching (NBE), or similar processes, or wet etching, such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant. Due to the etching of multiple portions of the fin structure 112, trenches 119 are formed in the source / drain regions.

[0030] Next, as Figure 8AAs shown, the second semiconductor layer 108 is removed to form an opening 141 between vertically adjacent first semiconductor layers 106. The second semiconductor layer 108 can be removed by a selective etching process, such as a selective dry etching process, a selective wet etching process, or a combination thereof. In some embodiments, the selective etching process does not substantially affect the first semiconductor layer 106, the second spacer 138b, the mask layer 136, and the insulating material 118.

[0031] exist Figure 8B In this process, dielectric material 143 is formed in openings 141 between adjacent first semiconductor layers 106. The dielectric material 143 may be formed first in the openings 141 and on exposed surfaces of the semiconductor device structure 100, followed by an etching process to remove portions of the dielectric material 143 not formed in the openings 141. The etching process may be anisotropic etching. At this stage, the edge portions of the dielectric material 143 and the edge portions of the first semiconductor layers 106 have substantially flat surfaces, which may be flush with the side surfaces of the spacers 138, such as... Figure 8B As shown. In some embodiments, the dielectric material 143 is an oxide formed by any suitable process (e.g., atomic layer deposition (ALD), chemical vapor deposition (CVD), PECVD, or FCVD). In some embodiments, the oxide is silicon oxide, such as porous silicon oxide. Subsequently, as Figure 9 As shown, the edge portion of the dielectric material 143 is removed horizontally along the X direction. In other words, the dielectric material 143 is etched laterally along the X direction. Removing the edge portion of the dielectric material 143 forms a recess 145. In some embodiments, the edge portion of the dielectric material 143 is removed by a selective wet etching process. In some embodiments, such as Figure 9 As shown, the edges of the top and bottom surfaces of the middle and bottom first semiconductor layer 106 are exposed in the recess 145, and the edge of the bottom surface of the top first semiconductor layer 106 is also exposed in the recess 145.

[0032] Next, as Figure 10 As shown, a semiconductor capping layer 144 is formed in trench 119. In some embodiments, the semiconductor capping layer 144 comprises a crystalline semiconductor material and is epitaxially grown from the first semiconductor layer 106 and the substrate portion 116. For example, such as Figure 10 As shown, the semiconductor capping layer 144 can be grown from the side surface of the first semiconductor layer 106, the exposed edge portions of the top and bottom surfaces of the first semiconductor layer 106, and the substrate portion 116. Figure 10As shown, the semiconductor capping layer 144 can be formed in the recess 145, but due to the growth mode of the crystalline semiconductor material of the semiconductor capping layer 144, it may not completely fill the recess 145. An air gap 147 may be formed between the semiconductor capping layer 144 and the dielectric material 143. In some embodiments, the semiconductor capping layer 144 forms a continuous crystalline semiconductor surface connecting a vertically arranged first semiconductor layer 106 and adjacent vertically aligned first semiconductor layers 106. In other words, the semiconductor capping layer 144 forms a continuous crystalline semiconductor surface in each trench 119. In some embodiments, the subsequently formed semiconductor layer 152 can be grown from the continuous crystalline semiconductor surface of the semiconductor capping layer 144. Therefore, epitaxial dislocation defects can be reduced.

[0033] For an n-channel field-effect transistor (FET), the semiconductor capping layer 144 can be formed of Si, SiP, SiC, SiAs, SiSb, and SiCP, while for a p-channel field-effect transistor (FET), the semiconductor capping layer 144 can be formed of Si, SiGe, Ge, and SiGeB. For a p-channel FET, the semiconductor capping layer 144 may contain p-type dopants, such as boron (B). For an n-channel FET, the semiconductor capping layer 144 may contain n-type dopants, such as phosphorus (P) or arsenic (As). The dopant concentration of the semiconductor capping layer 144 can be low, such as from about 0% to about 15%. The thickness of the semiconductor capping layer 144 may vary depending on the growth method of the crystalline semiconductor material. In some embodiments, the thickest portion of the semiconductor capping layer 144 above and below the edge portion of the first semiconductor layer 106 along the X direction can be less than about 2 nm, such as less than about 1 nm. The low dopant concentration and small thickness of the semiconductor capping layer 144 can reduce the leakage current flowing to the substrate portion 116.

[0034] exist Figure 11In this process, a base layer 150 is formed on a semiconductor capping layer 144 at the bottom of trench 119. In some embodiments, the base layer 150 comprises a crystalline semiconductor material, such as an undoped crystalline semiconductor material, for example, undoped Si or SiGe. The term "undoped" can include unintentionally doped material. For example, the base layer 150 may be undoped during deposition but may contain dopants diffused from other regions during subsequent processes. The base layer 150 prevents current leakage from subsequently formed semiconductor layers 152 and 154 to the semiconductor capping layer 144 and the substrate portion 116 below it. The base layer 150 can be formed using epitaxial growth methods such as CVD, ALD, or MBE. The base layer 150 can be initially formed on and connected to multiple portions of the semiconductor capping layer 144 located on the first semiconductor layer 106, and an etch-back process can be performed to remove multiple portions of the base layer 150 formed on the multiple portions of the semiconductor capping layer 144. In some embodiments, the epitaxial process for growing the substrate 150 may include using an etchant to remove the substrate 150 formed on a plurality of portions of the semiconductor capping layer 144 located on and connected to the first semiconductor layer 106. In some embodiments, the substrate 150 may be a dielectric material, such as silicon oxide (SiO2) or silicon nitride (Si3N4).

[0035] Next, as Figure 11 As shown, a semiconductor layer 152 is formed from a semiconductor capping layer 144 and a base layer 150. As described above, the semiconductor capping layer 144 provides a continuous surface for the growth of the semiconductor layer 152. Without the semiconductor capping layer 144, dielectric material (not shown) may form between the edge portions of vertically adjacent first semiconductor layers 106, and epitaxial packing defects may occur in the semiconductor layer 152. In some embodiments, the base layer 150 is formed of a crystalline semiconductor material, and the semiconductor layer 152 may also grow from the base layer 150. Therefore, in some embodiments, the semiconductor layer 152 intersects with the side surface of the semiconductor capping layer 144 and the top surface of the base layer 150, such as... Figure 11As shown. Semiconductor layer 152 may contain the same material as semiconductor capping layer 144, but with a higher doping concentration. In some embodiments, the doping concentration of semiconductor layer 152 ranges from about 10% to about 40%. Subsequently, semiconductor layer 154 is formed from semiconductor layer 152. Semiconductor layer 154 may contain the same material as semiconductor layer 152, but with a higher doping concentration. In some embodiments, the doping concentration of semiconductor layer 154 ranges from about 30% to about 70%. Semiconductor layers 152, 154, and 144, located above, below, and extending from the vertically stacked first semiconductor layer 106, may be source / drain (S / D) regions. Substrate layer 150 prevents current leakage from the S / D regions to the substrate portion 116 located below it. As described above, because the portions of semiconductor capping layer 144 located above and below the edge portions of the first semiconductor layer 106 are thinner and have a lower doping concentration, leakage current through the portions of semiconductor capping layer 144 is minimized.

[0036] like Figure 12 As shown, in some embodiments, after the S / D region is formed, a stress layer 156 can be formed on the semiconductor layer 154. The stress layer 156 may contain a material capable of influencing the longitudinal stress of the S / D region. In some embodiments, the stress layer 156 contains SiN. In some embodiments, the stress layer 156 is formed on both n-type metal-oxide-semiconductor (NMOS) and p-type metal-oxide-semiconductor (PMOS) regions, and the stress layer 156 applies different types of strain to improve performance. For example, SiGe can be used as the stress layer 156 formed in the PMOS region, while SiC or SiN can be used as the stress layer 156 formed in the NMOS region. In other embodiments, the stress layer 156 is formed only in the NMOS region.

[0037] exist Figure 12 In this embodiment, a contact etch stop layer (CESL) 162 is further compliantly formed on the exposed surface of the semiconductor device structure 100. The contact etch stop layer 162 covers the second spacer 138b and the stress layer 156 (or the semiconductor layer 154 if the stress layer 156 is absent). The contact etch stop layer 162 may comprise an oxygen-containing or nitrogen-containing material, such as silicon nitride, silicon nitride carbon, silicon oxynitride, carbon nitride, silicon oxide, silicon oxide carbon, or the like, or combinations thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. In some embodiments, the contact etch stop layer 162 is a single film layer, such as... Figure 12 As shown. In some embodiments, the contact etch stop layer 162 comprises two or more layers. Next, an interlayer dielectric (ILD) 164 is formed on the contact etch stop layer 162. The material of the interlayer dielectric 164 may comprise compounds containing silicon, oxygen, carbon, and / or hydrogen, such as silicon oxide, SiCOH, or SiOC. The interlayer dielectric 164 may also use organic materials, such as polymers. The interlayer dielectric 164 may be deposited using a PECVD process or other suitable deposition techniques. In some embodiments, after forming the interlayer dielectric 164, the semiconductor device structure 100 may be thermally treated to anneal the interlayer dielectric 164. After forming the interlayer dielectric 164, a planarization operation, such as CMP, is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed, as shown. Figure 12 As shown.

[0038] It should be understood that the semiconductor device structure 100 can also undergo further processing, such as cut poly on OD edge (CPODE) processing. The CPODE process forms an isolation structure comprising a dielectric substrate 196 and a dielectric material 198, such as... Figure 12 As shown. In some embodiments, an air gap 147 is formed between the dielectric substrate 196 and the semiconductor capping layer 144.

[0039] Next, as Figure 13 As shown, the sacrificial gate structure 130 and dielectric material 143 are removed. Removing the sacrificial gate structure 130 and dielectric material 143 creates openings between spacers 138 and recesses between the first semiconductor layers 106. The interlayer dielectric layer 164 protects the S / D region during the removal process. Figure 12 The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 can be removed first by any suitable process, such as dry etching, wet etching, or a combination thereof, followed by the removal of the sacrificial gate dielectric layer 132, which can also be performed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant, such as a tetramethylammonium hydroxide (TMAH) solution, can be used to selectively remove the sacrificial gate electrode layer 134, but without removing the spacer 138, the interlayer dielectric layer 164, and the contact etch stop layer 162.

[0040] Subsequently, as Figure 14As shown, a dielectric layer 139 is formed on the exposed surface of the semiconductor device structure 100. In some embodiments, the dielectric layer 139 may be an oxide layer such as SiO or SiO2, or a film layer comprising a low dielectric constant material such as SiOC, SiOCN, or SiCN. In some embodiments, the dielectric constant of the dielectric layer 139 is lower than that of the spacer 138 and the contact etch stop layer 162. The dielectric layer 139 may be formed by any suitable process, such as CVD, PECVD, LPCVD, or ALD. In some embodiments, the dielectric layer 139 is a compliant layer and is formed via ALD. In some embodiments, the process of forming the dielectric layer 139 may also oxidize multiple portions of the semiconductor capping layer 144 and multiple portions of the first semiconductor layer 106, and the oxidized portions of the semiconductor capping layer 144 and the oxidized portions of the first semiconductor layer 106 are also part of the dielectric layer 139, such as... Figure 14 As shown. Therefore, in some embodiments, the thickness of the dielectric layer 139 located between vertically adjacent first semiconductor layers 106 is significantly greater than the thickness of the dielectric layer 139 located on a dielectric material such as spacer 138. In some embodiments, the oxidation rate of the semiconductor capping layer 144 is greater than the oxidation rate of the first semiconductor layer 106 because the first semiconductor layer 106 has a higher quality epitaxial material. Therefore, the thickness of the portion of the dielectric layer 139 adjacent to the semiconductor capping layer 144 along direction X is greater than the thickness of the portion of the dielectric layer 139 adjacent to the first semiconductor layer 106 along direction Z. In some embodiments, the dielectric layer 139 separates the continuous semiconductor capping layers 144 to form discrete portions of the semiconductor capping layer 144, and the dielectric layer 139 intersects or contacts the semiconductor layer 152, such as Figure 14 As shown, the low dielectric constant of dielectric layer 139 can reduce parasitic capacitance. In some embodiments, dielectric layer 139 can induce nitriding or carburization in multiple portions of semiconductor capping layer 144 and multiple portions of first semiconductor layer 106, depending on the composition of dielectric layer 139.

[0041] exist Figure 15In this process, dielectric layer 139 is trimmed to form interposing layer 149. In some embodiments, dielectric layer 139 may be trimmed using dry etching, wet etching, plasma etching, atomic layer etching, or any other suitable method. In some embodiments, wet etching is performed to trim dielectric layer 139. Wet etching can be controlled such that multiple portions of dielectric layer 139 on the dielectric material and the first semiconductor layer 106 are removed, while multiple portions of dielectric layer 139 adjacent to semiconductor capping layer 144 are retained due to their greater thickness. The remaining portions of dielectric layer 139 form interposing layer 149. Interposing layer 149 provides electrical isolation between the S / D region and the subsequently formed gate structure 190. In some embodiments, no etching process is performed after forming interposing layer 149 and before forming gate structure 190. Therefore, interposing layer 149 may not contain etch-resistant materials such as SiN, SiOCN, SiON, or SiC. The dielectric constant of the dielectric material in the intermediate layer 149 is lower than that of these etch-resistant materials. Therefore, parasitic capacitance is reduced. In some embodiments, the intermediate layer 149 is disposed between discrete portions of the semiconductor capping layer 144 and intersects with the semiconductor layer 152, such as... Figure 15 As shown.

[0042] Next, as Figure 16 As shown, after forming the intermediate layer 149, an alternative gate structure 190 is formed (only one is shown here as an example). Each alternative gate structure 190 may include an interfacial layer (IL) 181, a gate dielectric layer 180, one or more work function metal layers 182, and a metal filler 184. The interfacial layer 181 may contain an oxide, such as silicon oxide. In some embodiments, the interfacial layer 181 and the intermediate layer 149 contain the same material. In some embodiments, the gate dielectric layer 180 contains one or more layers of dielectric material, such as silicon oxide, silicon nitride, or a high dielectric constant dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high dielectric constant dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high dielectric constant dielectric materials, and / or combinations thereof. The gate dielectric layer 180 can be formed by CVD, ALD, or any suitable deposition technique. In some embodiments, one or more work function metal layers 182 may comprise aluminum, aluminum titanium, aluminum titanium carbide, aluminum tantalum, aluminum tantalum carbide, hafnium carbide, silicon, titanium nitride, silicon titanium nitride, tantalum nitride, tungsten nitride carbide, tungsten, molybdenum, or other suitable work function metals. The metal filler 184 may comprise any suitable metal, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, or molybdenum.

[0043] Figure 17 as well as Figure 18 According to an alternative embodiment, various stages of manufacturing the semiconductor device structure 100 are shown along... Figure 5 A side view diagram of a section taken from section AA. (See diagram below.) Figure 17 As shown, the sacrificial gate structure 130 and the dielectric material 143 are removed. Figure 17 The semiconductor device structure 100 shown is Figure 13 The semiconductor device structure 100 shown is at the same manufacturing stage. Next, as... Figure 18 As shown, with Figure 14 Unlike the deposited dielectric layer 139 shown, an oxidation process is performed on the semiconductor device structure 100. The oxidation process oxidizes exposed semiconductor materials, such as exposed portions of the semiconductor cap layer 144, exposed portions of the first semiconductor layer 106, and exposed portions of the substrate portion 116. The oxidized portion of the semiconductor cap layer 144 forms an intermediate layer 149, while the oxidized portions of the first semiconductor layer 106 and the substrate portion 116 form an interface layer 181. In some embodiments, the oxidation rate of the semiconductor cap layer 144 is greater than the oxidation rate of the first semiconductor layer 106, such as for… Figure 14 As described. A trimming process can be performed to trim the intermediate layer 149 and the interface layer 181. Therefore, in some embodiments, the first semiconductor layer 106 has a dog-bone shape, such as Figure 18 As shown. Therefore, in some embodiments, the intermediate layer 149 and the interface layer 181 are formed simultaneously by a single process, such as an oxidation process. In other words, the intermediate layer 149 is formed during the formation of the interface layer 181. The oxidation process can be any suitable oxidation process, such as a thermal oxidation process or a plasma oxidation process. Next, a replacement gate structure 190 is formed in the opening. Figure 16 ).

[0044] The various embodiments or examples described in this disclosure offer several advantages over the prior art. According to embodiments of the invention, since the semiconductor capping layer 144 is formed prior to the formation of the intermediate layer 149, the semiconductor layer 152 can be grown from the continuous semiconductor surface of the semiconductor capping layer 144. Therefore, packing defects in the semiconductor layer 152 can be reduced. Furthermore, by forming the intermediate layer 149 only after removing the dielectric material 143, losses in the intermediate layer 149 can be reduced.

[0045] A method for forming a semiconductor device structure is provided, comprising forming a semiconductor layer stack above a substrate, the semiconductor layer stack including a plurality of alternating stacked first semiconductor layers and a plurality of second semiconductor layers, removing a plurality of portions of the semiconductor layer stack, removing a second semiconductor layer, depositing a dielectric material between vertically adjacent first semiconductor layers, laterally etching the dielectric material to form a plurality of recesses, depositing a semiconductor capping layer in the recesses, the semiconductor capping layer being a continuous film layer and connecting the vertically adjacent first semiconductor layers, forming a third semiconductor layer from the semiconductor capping layer, removing the dielectric material, and forming a plurality of intermediate layers to divide the semiconductor capping layer into a plurality of portions.

[0046] In some embodiments, an air gap is formed between the semiconductor capping layer and the dielectric material. In some embodiments, the semiconductor capping layer is formed on the edge portions of the top surface and the bottom surface of one of the first semiconductor layers. In some embodiments, the method further includes forming a plurality of interface layers from the first semiconductor layer. In some embodiments, the method further includes forming a gate structure on the interface layers. In some embodiments, the step of forming the gate structure includes depositing a gate dielectric layer over the interface layers, depositing one or more work function metal layers on the gate dielectric layer, and depositing a metal filler on the one or more work function metal layers. In some embodiments, the method further includes forming a fourth semiconductor layer on the third semiconductor layer. In some embodiments, the intermediate layer is formed by depositing a dielectric layer. In some embodiments, the step of depositing a dielectric layer alters the properties of multiple portions of the semiconductor capping layer.

[0047] Another method for forming a semiconductor device structure is provided, comprising forming a semiconductor layer stack above a substrate, the semiconductor layer stack comprising a plurality of alternating stacked first semiconductor layers and a plurality of second semiconductor layers, removing a plurality of portions of the semiconductor layer stack, removing a second semiconductor layer, depositing a dielectric material between vertically adjacent first semiconductor layers, laterally etching the dielectric material to form a plurality of recesses, depositing a semiconductor capping layer in the recesses, the semiconductor capping layer being a continuous film layer and connecting the vertically adjacent first semiconductor layers, removing the dielectric material, and forming a plurality of intermediate layers and a plurality of interface layers.

[0048] In some embodiments, an interface layer is formed during the formation of an intermediate layer. In some embodiments, the interface layer and the intermediate layer are formed by an oxidation process, wherein the oxidation process oxidizes multiple portions of a semiconductor cap layer to form the intermediate layer, and the oxidation process oxidizes multiple portions of a first semiconductor layer to form the interface layer. In some embodiments, the oxidation process is a thermal oxidation process or a plasma oxidation process. In some embodiments, the method further includes forming a substrate layer on the semiconductor cap layer. In some embodiments, the method further includes forming a third semiconductor layer from the semiconductor cap layer and the substrate layer. In some embodiments, the step of forming the intermediate layer divides the semiconductor cap layer into multiple portions. In some embodiments, the intermediate layer and the third semiconductor layer are at an interface.

[0049] A semiconductor device structure is provided, comprising a plurality of vertically stacked first semiconductor layers, including a top first semiconductor layer, a middle first semiconductor layer and a bottom first semiconductor layer, a semiconductor capping layer disposed on a side surface of the middle first semiconductor layer, an edge portion of the top surface of the middle first semiconductor layer and an edge portion of the bottom surface of the middle first semiconductor layer, a second semiconductor layer disposed adjacent to the semiconductor capping layer, and an intermediate layer disposed between the top first semiconductor layer and the middle first semiconductor layer, with the intermediate layer and the second semiconductor layer at the boundary.

[0050] In some embodiments, the semiconductor capping layer comprises a semiconductor material having a first dopant concentration. In some embodiments, the second semiconductor layer comprises a semiconductor material having a second dopant concentration different from the first dopant concentration.

[0051] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the appended claims.

Claims

1. A method for forming a semiconductor device structure, comprising: A semiconductor layer is formed on a substrate, wherein the semiconductor layer stack includes a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately; Remove multiple portions of the semiconductor layer stack; Remove multiple second semiconductor layers; A dielectric material is deposited between a plurality of vertically adjacent first semiconductor layers; The dielectric material is etched laterally to form multiple recesses; A semiconductor capping layer is deposited in the plurality of said recesses, wherein the semiconductor capping layer is a continuous film layer and connects the plurality of vertically adjacent first semiconductor layers; A third semiconductor layer is formed from the semiconductor capping layer; Remove the dielectric material; as well as Multiple intermediate layers are formed to divide the semiconductor capping layer into multiple parts.

2. The method for forming a semiconductor device structure as claimed in claim 1, wherein an air gap is formed between the semiconductor capping layer and the dielectric material.

3. The method of forming a semiconductor device structure as claimed in claim 1, wherein the semiconductor capping layer is formed on the edge portion of the top surface and the edge portion of the bottom surface of one of the plurality of first semiconductor layers.

4. The method for forming a semiconductor device structure as claimed in claim 1 further includes forming a plurality of interface layers from a plurality of the first semiconductor layers.

5. The method for forming a semiconductor device structure as claimed in claim 1, wherein the plurality of intermediate layers are formed by depositing a dielectric layer.

6. A method for forming a semiconductor device structure, comprising: A semiconductor layer is formed on a substrate, wherein the semiconductor layer stack includes a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately; Remove multiple portions of the semiconductor layer stack; Remove multiple second semiconductor layers; A dielectric material is deposited between a plurality of vertically adjacent first semiconductor layers; The dielectric material is etched laterally to form multiple recesses; A semiconductor capping layer is deposited in the plurality of said recesses, wherein the semiconductor capping layer is a continuous film layer and connects the plurality of vertically adjacent first semiconductor layers; Remove the dielectric material; as well as This forms multiple intermediate layers and multiple interface layers.

7. The method of forming a semiconductor device structure as claimed in claim 6, wherein the plurality of interface layers are formed during the formation of the plurality of intermediate layers.

8. The method for forming a semiconductor device structure as described in claim 6 further includes forming a substrate layer on the semiconductor capping layer.

9. A semiconductor device structure, comprising: Multiple vertically stacked first semiconductor layers, including a top first semiconductor layer, a middle first semiconductor layer and a bottom first semiconductor layer; A semiconductor capping layer is disposed on the side surface of the intermediate first semiconductor layer, the edge portion of the top surface of the intermediate first semiconductor layer, and the edge portion of the bottom surface of the intermediate first semiconductor layer; A second semiconductor layer is disposed adjacent to the semiconductor capping layer; as well as An intermediate layer is disposed between the top first semiconductor layer and the intermediate first semiconductor layer, wherein the intermediate layer is at the boundary with the second semiconductor layer.

10. The semiconductor device structure of claim 9, wherein the semiconductor capping layer comprises: A semiconductor material having a first dopant concentration.

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