Semiconductor device including field effect transistor

Abstract

A semiconductor device includes: active patterns located on a substrate and spaced apart in a first direction; at least one source / drain pattern located on at least a first one of the active patterns; an interlayer insulating layer covering the at least one source / drain pattern; and a separation pattern located between the active patterns and extending in a second direction intersecting the first direction, wherein the interlayer insulating layer includes an embedded portion extending into the first one of the active patterns, the separation pattern includes first and second side walls opposite to each other in the first direction, and the first side wall contacts the embedded portion and the second side wall contacts the at least one source / drain pattern.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods of manufacturing the same, and more particularly to semiconductor devices including field-effect transistors (FETs) and methods of manufacturing the same. Background Technology

[0002] Semiconductor devices can include integrated circuits with metal-oxide-semiconductor FETs (MOSFETs). To meet the growing demand for semiconductor devices with smaller pattern sizes and reduced design rules, MOSFET dimensions have also been miniaturized. This miniaturization of MOSFETs can lead to a degradation in the operating characteristics of semiconductor devices. Various studies are underway to overcome the technological limitations associated with semiconductor device miniaturization and to achieve high-performance semiconductor devices.

[0003] The information disclosed in this Background section was already known to or derived by the inventors before or during the implementation of the embodiments of this application, or is technical information obtained in the process of implementing the embodiments. Therefore, it may contain information that does not constitute prior art already known to the public. Summary of the Invention

[0004] One or more example embodiments provide a semiconductor device that can have improved reliability and electrical characteristics, and a method of manufacturing said semiconductor device.

[0005] Additional aspects will be set forth in part in the description which follows, and in part will be apparent from the description or may be learned by practice of the presented embodiments.

[0006] According to one aspect of an example embodiment, a semiconductor device may include: active patterns located on a substrate and spaced apart in a first direction; at least one source / drain pattern located at least on a first active pattern among the active patterns; an interlayer insulating layer covering the at least one source / drain pattern; and a separating pattern located between the active patterns and extending in a second direction intersecting the first direction, wherein the interlayer insulating layer includes an embedded portion extending into the first active pattern among the active patterns, and the separating pattern includes a first sidewall and a second sidewall opposite to each other in the first direction, the first sidewall contacting the embedded portion and the second sidewall contacting the at least one source / drain pattern.

[0007] According to one aspect of an example embodiment, a semiconductor device may include: an active pattern located on a substrate; a source / drain pattern located on the active pattern; a cover insulating layer covering the source / drain pattern; an interlayer insulating layer located on the cover insulating layer; and a separator pattern located on the substrate and extending in a first direction, wherein the interlayer insulating layer includes an embedded portion extending into the active pattern, the cover insulating layer includes an embedded layer located between the embedded portion and the separator pattern, and the bottom surface of the embedded layer is at the same horizontal height as the bottom surface of the source / drain pattern.

[0008] According to one aspect of an example embodiment, a semiconductor device may include: a substrate including an active pattern; a device isolation pattern defining the active pattern; a first channel pattern and at least one second channel pattern located on the active pattern and spaced apart in a first direction; a first source / drain pattern and a second source / drain pattern connected to the first channel pattern and the at least one second channel pattern, respectively; a separator pattern located on the substrate and extending in a second direction intersecting the first direction; a gate electrode located on the first channel pattern and the at least one second channel pattern; a gate insulating layer located between the gate electrode, the first channel pattern, and the at least one second channel pattern; and a cover insulating layer covering the active pattern. The system comprises: a first source / drain pattern and a second source / drain pattern; a gate overlay pattern located on the upper surface of the gate electrode; an interlayer insulating layer covering the first source / drain pattern, the second source / drain pattern, and the overlay insulating layer; an active contact connected to the first source / drain pattern and the second source / drain pattern through the interlayer insulating layer; a gate contact connected to the gate electrode through the gate overlay pattern; and a first metal layer located on the interlayer insulating layer, the first metal layer including a first wiring connected to the active contact and the gate contact, wherein the interlayer insulating layer includes an embedded portion extending into the active pattern, the overlay insulating layer includes an embedded layer extending between the embedded portion and the separator pattern, and the separator pattern is located between the embedded portion and the second source / drain pattern. Attached Figure Description

[0009] The above and other aspects, features and advantages of this disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a plan view illustrating a semiconductor device according to one or more embodiments; Figure 2A It is along Figure 1 A cross-sectional view taken by line A-A' in the diagram; Figure 2B It is along Figure 1 A cross-sectional view taken by line B-B' in the diagram; Figure 2C It is along Figure 1 A cross-sectional view taken by line C-C' in the diagram; Figure 3A According to one or more embodiments Figure 2A A magnified view of part M; Figure 3B It is a plan view of a semiconductor device according to one or more embodiments; Figure 3C It is along Figure 3B A cross-sectional view taken by line D-D' in the diagram; and Figure 4 , Figure 5 , Figure 6 , Figure 7A , Figure 7B , Figure 8 , Figure 9 , Figure 10A , Figure 10B , Figure 11 , Figure 12A , Figure 12B , Figure 13 , Figure 14 , Figure 15 , Figure 16A , Figure 16B , Figure 17 , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20 , Figure 21A , Figure 21B and Figure 21C This is a diagram illustrating a method of manufacturing a semiconductor device according to one or more embodiments. Detailed Implementation

[0010] The exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same parts in the drawings, and redundant descriptions will be omitted. The embodiments described herein are exemplary embodiments, and therefore, this disclosure is not limited thereto and can be implemented in various other forms.

[0011] As used herein, expressions such as "at least one of" modify the entire list of elements when used with a list of elements, not individual elements within the list. For example, the expression "at least one of a, b, and c" should be understood as including only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0012] It will be understood that when a component or layer is described as being "above," "over," "on," "below," "below," "connected to," or "coupled to" another component or layer, that component or layer may be directly above, above, above, below, below, connected to, or coupled to the other component or layer, or there may be intermediate components or intermediate layers. Conversely, when a component is described as being "directly" located "above," "over," "on," "below," "below," "below," "directly connected to," or "directly coupled to" another component or layer, there are no intermediate components or intermediate layers.

[0013] Terms such as "first" and "second" can be used to describe various components, but only for the purpose of distinguishing one component from another. These terms do not limit the differences in the materials or structures of the components.

[0014] A singular term may include a plural term unless otherwise stated. Furthermore, when a part “includes” a component, unless otherwise stated, it means that other components may be included, rather than excluded.

[0015] The use of the term “the” and similar designated terms can correspond to both the singular and plural forms.

[0016] Unless explicitly described in sequence, the operations of the method may be performed in the appropriate order. Furthermore, all illustrative terms (e.g., etc.) are used merely for the purpose of describing the technical idea in detail, and their scope is not limited by these examples or illustrative terms unless restricted by the claims.

[0017] Figure 1 This is a plan view illustrating a semiconductor device according to one or more embodiments. Figure 2A , Figure 2B and Figure 2C This is a view illustrating a semiconductor device according to one or more embodiments, and respectively along... Figure 1 The cross-sectional views taken from lines A-A', B-B', and C-C'.

[0018] refer to Figure 1 , Figure 2A , Figure 2B and Figure 2CThe semiconductor device may include a substrate 100. A plurality of logic transistors constituting a logic circuit may be disposed on the substrate 100. For example, the substrate 100 may be an insulating substrate including a silicon-based insulating layer. For example, the substrate 100 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0019] The substrate 100 may extend along a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may intersect each other and be parallel to the upper surface of the substrate 100. For example, the first direction D1 and the second direction D2 may be orthogonal to each other.

[0020] The first active pattern AP1 and the second active pattern AP2 may be defined by a first trench TR1 and a second trench TR2 in the substrate 100. For example, each of the first active pattern AP1 or the second active pattern AP2 may be defined by the first trench TR1, and the first active pattern AP1 and the second active pattern AP2 may be defined by the second trench TR2. The first active pattern AP1 and the second active pattern AP2 may be a part of the substrate 100. For example, the first active pattern AP1 and the second active pattern AP2 may be a portion of the substrate 100 projecting in a third direction D3 perpendicular to the upper surface of the substrate 100. However, for the sake of convenience, the substrate 100 and the first active pattern AP1 and the second active pattern AP2 are defined as different elements.

[0021] Each of the first active pattern AP1 and the second active pattern AP2 may extend in the second direction D2. The first active pattern AP1 and the second active pattern AP2 may be spaced apart from each other in the first direction D1 by the device isolation pattern ST described subsequently. The first active pattern AP1 or the second active pattern AP2 may be spaced apart from each other in the first direction D1 by the separation patterns ISP1 and ISP2 described subsequently.

[0022] A device isolation pattern ST may be formed on the substrate 100. The device isolation pattern ST may fill the second trench TR2. In a plan view, the device isolation pattern ST may surround the first active pattern AP1 and the second active pattern AP2. The upper surface of the device isolation pattern ST may be coplanar with the upper surfaces of the first active pattern AP1 and the second active pattern AP2, but is not limited thereto. For example, the device isolation pattern ST may include an insulating material such as silicon oxide.

[0023] A first channel pattern CH1 and a second channel pattern CH2 may be provided on each of the first active pattern AP1 and the second active pattern AP2. The first channel pattern CH1 and the second channel pattern CH2 may be adjacent to each other in the first direction D1. The first channel pattern CH1 and the second channel pattern CH2 may be spaced apart from each other in the first direction D1 by spacer patterns ISP1 and ISP2 inserted therein. That is, as... Figure 2A As shown, the separator pattern ISP1 can be located between the sides of semiconductor patterns SP1 to SP4 within the first channel pattern CH1, and similarly between the sides of semiconductor patterns SP1 to SP4 within the channel pattern CH2. Multiple first channel patterns CH1 and multiple second channel patterns CH2 can be provided, and the multiple first channel patterns CH1 and the multiple second channel patterns CH2 can each be spaced apart from each other in the second direction D2.

[0024] Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, a third semiconductor pattern SP3, and a fourth semiconductor pattern SP4. The first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4 may be spaced apart from each other in a vertical direction (e.g., third direction D3). For example, the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4 may include crystalline silicon. Each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4 may be a nanosheet. In some embodiments, the number of semiconductor patterns in the first channel pattern CH1 and the second channel pattern CH2 may be set differently. Separating patterns (ISP1 / ISP2) may extend between each semiconductor pattern in the respective channel pattern.

[0025] A first source / drain pattern SD1 can be disposed on a first active pattern AP1, and a second source / drain pattern SD2 can be disposed on a second active pattern AP2. The first source / drain pattern SD1 on the first active pattern AP1 can be disposed on the sidewall of the first separator pattern ISP1. The second source / drain pattern SD2 on the second active pattern AP2 can be disposed on the sidewall of the second separator pattern ISP2. The first source / drain pattern SD1 and the second source / drain pattern SD2 are respectively located on the sidewalls of the first channel pattern CH1 and the second channel pattern CH2, and can be electrically connected to the first channel pattern CH1 and the second channel pattern CH2.

[0026] The first source / drain pattern SD1 may include an impurity region having a first conductivity type (e.g., p-type). The second source / drain pattern SD2 may include an impurity region having a second conductivity type (e.g., n-type). For example, the first source / drain pattern SD1 and the second source / drain pattern SD2 may include impurity regions having the same conductivity type, or they may include impurity regions having different conductivity types from each other.

[0027] The first source / drain pattern SD1 and the second source / drain pattern SD2 may include a seed pattern SE and a contact sacrificial pattern PH. The contact sacrificial pattern PH may be a part of the first source / drain pattern SD1 and the second source / drain pattern SD2 embedded in the first active pattern AP1 and the second active pattern AP2. The contact sacrificial pattern PH may include a material having etch selectivity relative to the first active pattern AP1 and the second active pattern AP2.

[0028] The seed pattern SE can be set on the contact sacrificial pattern PH. Each of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be an epitaxial pattern formed by a selective epitaxial growth (SEG) process using the seed pattern SE as a seed. For example, the first source / drain pattern SD1 and the second source / drain pattern SD2 can include either silicon or silicon germanium.

[0029] A first gate electrode GE1 may be disposed on a first active pattern AP1, and a second gate electrode GE2 may be disposed on a second active pattern AP2. The first gate electrode GE1 may be disposed on a first channel pattern CH1 on the first active pattern AP1. The second gate electrode GE2 may be disposed on a second channel pattern CH2 on the second active pattern AP2. For example, the first gate electrode GE1 may surround each of a first semiconductor pattern SP1, a second semiconductor pattern SP2, a third semiconductor pattern SP3, and a fourth semiconductor pattern SP4 of the first channel pattern CH1, and the second gate electrode GE2 may surround each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4 of the second channel pattern CH2. The first gate electrode GE1 and the second gate electrode GE2 may be spaced apart in a first direction D1 by the cut pattern CT described subsequently.

[0030] Each of the first gate electrode GE1 and the second gate electrode GE2 may include a first internal electrode PO1, a second internal electrode PO2, a third internal electrode PO3, a fourth internal electrode PO4, and an external electrode PO5. Each of the first internal electrode PO1, the second internal electrode PO2, the third internal electrode PO3, and the fourth internal electrode PO4 may be located between the first semiconductor pattern SP1 and the first active pattern AP1 or the second active pattern AP2, and between the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4. The external electrode PO5 may be located on the fourth semiconductor pattern SP4, which is the uppermost semiconductor pattern among the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4. For example, the first gate electrode GE1 and the second gate electrode GE2 may include at least one of a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), a metal nitride (e.g., nitrides such as Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), and doped polycrystalline silicon.

[0031] Separator patterns ISP1 and ISP2 may be formed on substrate 100. In a plan view, each of the separator patterns ISP1 and ISP2 extends in a second direction D2, and the separator patterns ISP1 and ISP2 may be spaced apart from each other in a first direction D1. Separator patterns ISP1 and ISP2 may include a first separator pattern ISP1 and a second separator pattern ISP2. The first separator pattern ISP1 may be formed on a first active pattern AP1, and the second separator pattern ISP2 may be formed on a second active pattern AP2. For example, separator patterns ISP1 and ISP2 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide (SiOC). In some embodiments, separator patterns ISP1 and ISP2 may consist of multiple layers or a single layer comprising different insulating materials.

[0032] Separator patterns ISP1 and ISP2 may be located in the first trench TR1. Separator patterns ISP1 and ISP2 may have a cylindrical shape extending in the third direction D3. The first separator pattern ISP1 may be located between the sides of the first active pattern AP1, and the second separator pattern ISP2 may be located between the sides of the second active pattern AP2. The first separator pattern ISP1 may extend between the sides of the first active pattern AP1, and the second separator pattern ISP2 may extend between the sides of the second active pattern AP2. The first separator pattern ISP1 may be located between first channel patterns CH1 that are adjacent to each other in the first direction D1, and the second separator pattern ISP2 may be located between second channel patterns CH2 that are adjacent to each other in the first direction D1.

[0033] The first gate electrode GE1 may include a first electrode portion GE1a and a second electrode portion GE1b. The first electrode portion GE1a and the second electrode portion GE1b of the first gate electrode GE1 may be located on the first channel pattern CH1. For example, the first electrode portion GE1a and the second electrode portion GE1b may surround three sides of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4 of the first channel pattern CH1.

[0034] In some embodiments, the first electrode portion GE1a and the second electrode portion GE1b of the first gate electrode GE1 can be spaced apart from each other in the first direction D1 by a first separator pattern ISP1. Therefore, the first electrode portion GE1a and the second electrode portion GE1b of the first gate electrode GE1 can be electrically insulated from each other. Therefore, the first channel pattern CH1 adjacent to the first separator pattern ISP1 can constitute different logic transistors.

[0035] The second gate electrode GE2 may include a first electrode portion GE2a and a second electrode portion GE2b. The first electrode portion GE2a and the second electrode portion GE2b may be located on the second channel pattern CH2. For example, the first electrode portion GE2a and the second electrode portion GE2b of the second gate electrode GE2 may surround three sides of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4 of the second channel pattern CH2.

[0036] In some embodiments, the first electrode portion GE2a and the second electrode portion GE2b of the second gate electrode GE2 can be spaced apart from each other in the first direction D1 by the second separator pattern ISP2. Therefore, the first electrode portion GE2a and the second electrode portion GE2b of the second gate electrode GE2 can be electrically insulated from each other. Therefore, the second channel pattern CH2 adjacent to the second separator pattern ISP2 can constitute different logic transistors.

[0037] A gate insulating layer GI may be disposed between the first gate electrode GE1 and the second gate electrode GE2 and the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4 of the first channel pattern CH1 and the second channel pattern CH2. The gate insulating layer GI may cover the upper surface, the bottom surface, and a sidewall of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4. The gate insulating layer GI may cover the upper sidewalls of the separator patterns ISP1 and ISP2. The gate insulating layer GI may be located between the first separator pattern ISP1 and the first gate electrode GE1, and between the second separator pattern ISP2 and the second gate electrode GE2. The gate insulating layer GI may extend between the first gate electrode GE1 and the second gate electrode GE2 and the device isolation pattern ST. The gate insulating layer GI may extend between the first gate electrode GE1 and the second gate electrode GE2 and the first active pattern AP1 and the second active pattern AP2. The gate insulating layer GI may also be located between the external electrode PO5 and the external gate spacer OGS, which will be described subsequently.

[0038] The gate insulating layer GI may include silicon oxide, silicon oxynitride, and / or a high dielectric constant material. Here, the high dielectric constant material may be a material having a higher dielectric constant than silicon oxide.

[0039] Pairs of external gate spacers (OGS) may be disposed on both sides of the external electrodes PO5 of the first gate electrode GE1 and the second gate electrode GE2. For example, the external gate spacers (OGS) may include at least one of SiON, SiCN, SiOCN, or SiN. Furthermore, the external gate spacers (OGS) may be composed of multiple layers or a single layer with different insulating materials.

[0040] A fence portion (FNP) may be disposed on the lower sidewall of each of the first source / drain pattern SD1 and the second source / drain pattern SD2. The fence portion (FNP) may be disposed on the device isolation pattern ST. The fence portion (FNP) may be part of the outer gate spacer OGS. The fence portion (FNP) may include at least one of SiON, SiCN, SiOCN, or SiN.

[0041] A gate cover pattern GP may be formed on the first gate electrode GE1 and the second gate electrode GE2. The gate cover pattern GP may cover the upper surface of the outer electrode PO5 of the first gate electrode GE1 and the second gate electrode GE2. For example, the gate cover pattern GP may include at least one of SiON, SiCN, SiOCN or SiN.

[0042] A first interlayer insulating layer 110 may be disposed on the substrate 100. The first interlayer insulating layer 110 may cover a first source / drain pattern SD1 and a second source / drain pattern SD2. The upper surface of the first interlayer insulating layer 110 may be substantially coplanar with the upper surface of the gate overlay pattern GP. For example, the first interlayer insulating layer 110 may comprise an insulating material such as silicon oxide.

[0043] A covering insulating layer CI may be disposed between the first interlayer insulating layer 110 and the first source / drain pattern SD1 and the second source / drain pattern SD2. The covering insulating layer CI may extend on the device isolation pattern ST and cover the surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2. The covering insulating layer CI may cover the fence portion FNP. For example, the covering insulating layer CI may include an insulating material different from the material of the first interlayer insulating layer 110. In some embodiments, the covering insulating layer CI may be formed of multiple layers or a single layer comprising different insulating materials.

[0044] Active contacts AC may be provided in the first interlayer insulating layer 110. The active contacts AC may penetrate a portion of the first interlayer insulating layer 110 along a third direction D3. Each of the active contacts AC may be connected to a corresponding first source / drain pattern SD1 and second source / drain pattern SD2. For example, the active contacts AC may include at least one of a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) and a metal nitride (e.g., nitrides such as Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). In some embodiments, another separating pattern comprising an insulating material may be provided between the active contacts AC. In some embodiments, a silicide pattern may be provided between the active contacts AC and the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0045] A gate contact GC may be provided in the gate cover pattern GP. The gate contact GC may be connected to the first gate electrode GE1 and the second gate electrode GE2 through the gate cover pattern GP along the third direction D3. For example, the gate contact GC may include at least one of a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) and a metal nitride (e.g., nitrides such as Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0046] A cutting pattern CT can be disposed between the first gate electrode GE1 and the second gate electrode GE2. The cutting pattern CT can extend in a third direction D3 between adjacent first gate electrodes GE1 and second gate electrodes GE2. The cutting pattern CT can penetrate the upper part of the device isolation pattern ST. For example, each of the cutting patterns CT can have a vertical length greater than the vertical length of each of the first gate electrode GE1 and the second gate electrode GE2. Therefore, the first gate electrode GE1 and the second gate electrode GE2 can be spaced apart from each other in a first direction D1 by the cutting pattern CT.

[0047] A second interlayer insulating layer 120 may be disposed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may cover the first interlayer insulating layer 110, the gate cover pattern GP, ​​the active contact AC, and the gate contact GC. The second interlayer insulating layer 120 may include an insulating material substantially the same as that of the first interlayer insulating layer 110.

[0048] An upper pass UV may be provided in the second interlayer insulating layer 120. The upper pass UV can penetrate the second interlayer insulating layer 120. Each of the upper pass UVs can be connected to a corresponding active contact AC and gate contact GC. For example, the upper pass UV may include a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0049] In some embodiments, a metal layer including wiring patterns and path patterns may be disposed on the upper path UV. The wiring patterns and path patterns of the metal layer may be electrically connected to the upper path UV. Adjacent logic transistors may exchange electrical signals with each other through the metal layer. Multiple metal layers may be disposed, and the multiple metal layers may be stacked on top of each other on the third direction D3.

[0050] In some embodiments, a power transport network layer may be provided on the bottom surface of the substrate 100. For example, the power transport network layer may include a wiring network for applying a source voltage. Alternatively, the power transport network layer may include a wiring network for applying a drain voltage. In some embodiments, the power transport network layer may include wiring patterns and via patterns. The wiring patterns and via patterns may be stacked on a third-direction D3 to be electrically connected to each other.

[0051] A back-side active contact may be provided between the power transmission network layer and the first source / drain pattern SD1 and the second source / drain pattern SD2. The back-side active contact may be connected to at least one of the first source / drain pattern SD1 and the second source / drain pattern SD2. The back-side active contact may be electrically connected to the wiring pattern and via pattern of the power transmission network layer. Therefore, at least one of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be electrically connected to the power transmission network layer. For example, the back-side active contact may include at least one of a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) or a metal nitride (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0052] Reference Figure 1 , Figure 2A , Figure 2B and Figure 2C The first interlayer insulation layer 110 and the covering insulation layer CI are described in more detail.

[0053] A cut-out region CTR may be provided on the second active pattern AP2. The cut-out region CTR may be a portion of the first active pattern AP1 and the second active pattern AP2 where the first source / drain pattern SD1 and the second source / drain pattern SD2 are not formed. Instead of forming the first source / drain pattern SD1 and the second source / drain pattern SD2, the cut-out region CTR may include an embedding portion EP and an embedding layer EL, which will be described later. Hereinafter, the embedding portion EP and the embedding layer EL may be formed only on the second active pattern AP2, but the embodiments are not limited thereto. For example, the embedding portion EP and the embedding layer EL may be formed on the first active pattern AP1.

[0054] The first source / drain pattern SD1 can be disposed on the two sidewalls of the first separator pattern ISP1 on the first active pattern AP1. The second source / drain pattern SD2 can be disposed on the first sidewall WSW1 of the second separator pattern ISP2. The first interlayer insulating layer 110 can replace the second source / drain pattern SD2 and be disposed on the second sidewall WSW2 of the second separator pattern ISP2. The first sidewall WSW1 and the second sidewall WSW2 of the second separator pattern ISP2 can face each other in the first direction D1. The second separator pattern ISP2 can be disposed between the second source / drain pattern SD2 and the first interlayer insulating layer 110.

[0055] The overlay insulating layer CI may include an embedded layer EL located between the embedded portion EP and the second active pattern AP2. The embedded layer EL may be a portion of the overlay insulating layer CI that extends into the second active pattern AP2. The embedded layer EL may cover the inner wall of the lower recess LRS formed on the second active pattern AP2. The bottom surface of the embedded layer EL may be located at substantially the same horizontal height as the bottom surface of the second source / drain pattern SD2. The thickness of the embedded layer EL may be from about 3 nm to about 10 nm, and in some embodiments from about 3 nm to about 8 nm.

[0056] The covering insulating layer CI may include a filler layer FL extending between the second separating pattern ISP2 and the first interlayer insulating layer 110. The filler layer FL may be disposed on the embedding layer EL. In other words, the filler layer FL may be a portion of the covering insulating layer CI extending along the sidewall of the second separating pattern ISP2.

[0057] The first interlayer insulating layer 110 may include a filling portion FP covering the sidewalls of the second separator pattern ISP2 and an embedded portion EP extending into the second active pattern AP2. The embedded portion EP may be disposed on the embedded layer EL to fill the remaining portion of the lower recess LRS. The filling portion FP may be disposed on the embedded portion EP. The filling layer FL may be located between the filling portion FP and the second separator pattern ISP2.

[0058] The width of the embedded portion EP in the first direction D1 and the width of the embedded portion EP in the second direction D2 can decrease in the vertical direction toward the bottom surface of the substrate 100. The width of the embedded portion EP can have a minimum value at the bottom surface of the embedded portion EP. The horizontal height of the bottom surface of the embedded portion EP can be higher than the horizontal height of the bottom surface of the second source / drain pattern SD2.

[0059] The contact sacrificial pattern PH of the second source / drain pattern SD2 can be disposed on one sidewall of the lower part of the second separator pattern ISP2, and the embedded portion EP can be disposed on the other sidewall of the lower part of the second separator pattern ISP2. The portion of the second source / drain pattern SD2 other than the contact sacrificial pattern PH can be disposed on one sidewall of the upper part of the second separator pattern ISP2, and the filling portion FP can be disposed on the other sidewall of the upper part of the second separator pattern ISP2.

[0060] The filling portion FP and the filling layer FL may be located between second channel patterns CH2 spaced apart from each other in the second direction D2. For example, the filling portion FP and the filling layer FL may be located between first semiconductor patterns SP1 spaced apart from each other in the second direction D2. The filling portion FP and the filling layer FL may be located between second semiconductor patterns SP2 spaced apart from each other in the second direction D2. The filling portion FP and the filling layer FL may be located between third semiconductor patterns SP3 spaced apart from each other in the second direction D2. The filling portion FP and the filling layer FL may be located between fourth semiconductor patterns SP4 spaced apart from each other in the second direction D2. The filling layer FL may contact the sidewalls of the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4. The filling layer FL may contact the overlay pattern CL, which will be described later.

[0061] The filling portion FP and the filling layer FL can be located between second source / drain patterns SD2 spaced apart from each other in the second direction D2. The first spacing INT1 between adjacent filling layers FL and second source / drain patterns SD2 can be the same as the second spacing INT2 between adjacent second source / drain patterns SD2 in the second direction D2. That is, the spacing between the filling layer FL and the source / drain pattern adjacent to the filling layer FL can be the same as the spacing between source / drain patterns that are adjacent to each other but not directly adjacent to the filling layer FL. The first spacing INT1 can be the distance between the filling layer FL and the second source / drain pattern SD2 in the second direction D2. The second spacing INT2 can be the distance between the sidewall of the second source / drain pattern SD2 and the sidewall of another second source / drain pattern SD2 in the second direction D2. The first spacing INT1 and the second spacing INT2 can be the same as the width of the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4 in the second direction D2.

[0062] The fill portion FP and the fill layer FL can extend onto D3. The upper surfaces of the fill portion FP and the fill layer FL can be coplanar with each other. The upper surfaces of the fill portion FP and the fill layer FL can be coplanar with the upper surface of the gate cover pattern GP. The upper surfaces of the fill portion FP and the fill layer FL can be located at the same horizontal height as the upper surface of the active contact AC.

[0063] Even if the second source / drain pattern SD2 is not formed on the second active pattern AP2, a dummy fence portion DFNP can be formed on the cut region CTR. Therefore, the dummy fence portion DFNP may not cover the sidewalls of the second source / drain pattern SD2 and can be surrounded by the first interlayer insulation layer 110. A covering insulation layer CI can surround the dummy fence portion DFNP. The covering insulation layer CI can be located between the dummy fence portion DFNP and the first interlayer insulation layer 110.

[0064] Figure 3A This illustrates one or more embodiments. Figure 2A A magnified view of part M. (Refer to...) Figure 3A The separation patterns ISP1 and ISP2 are described in more detail.

[0065] The separator patterns ISP1 and ISP2 may include a covering pattern CL and a separator wall pattern WP on the covering pattern CL. The covering pattern CL may cover the side walls and bottom surface of the separator wall pattern WP. The upper surface of the covering pattern CL may be lower than the upper surface of the separator wall pattern WP or located at the same horizontal height as the upper surface of the separator wall pattern WP. The width of the covering pattern CL in the first direction D1 may be less than the width of the separator wall pattern WP in the first direction D1. In some embodiments, the covering pattern CL may not be provided on a portion of the side walls of the separator wall pattern WP.

[0066] The cladding pattern CL may include materials having different etch selectivity relative to the separator pattern WP. The separator pattern WP may include, but is not limited to, insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. The cladding pattern CL may include, but is not limited to, at least one of SiON, SiCN, SiOCN, or SiN. For example, the separator pattern WP may include SiO2, and the cladding pattern CL may include SiN.

[0067] The overlay pattern CL may include a first portion PT1 disposed between the partition wall pattern WP and the first channel pattern CH1, and a second portion PT2 disposed between the partition wall pattern WP and the gate electrode GE. The middle portion of the first portion PT1 may contact the sidewall of the first channel pattern CH1. The edge portion of the first portion PT1 may be spaced apart from the sidewall of the first channel pattern CH1. The gate insulating layer GI may be disposed between the edge portion of the first portion PT1 and the first channel pattern CH1. The gate insulating layer GI may be disposed between the second portion PT2 and the gate electrode GE.

[0068] The first portion PT1 may have a first width W1 in the first direction D1 that is greater than the second width W2 of the second portion PT2 in the first direction D1. The first width W1 has a maximum value at the middle portion of the first portion PT1 and may decrease towards the edge portion of the first portion PT1. The second width W2 may have a minimum value at the middle portion of the second portion PT2 and may increase towards the edge portion of the second portion PT2. The second portion PT2 may have a concave profile, but is not limited thereto. In other words, the first portion PT1 may contact the semiconductor pattern, and the second portion PT2 may be spaced apart from the gate electrode in the first direction D1.

[0069] Refer again Figure 2A , Figure 2B and Figure 2C The overlay pattern CL can be located between the partition wall pattern WP and the embedded portion EP, and between the partition wall pattern WP and the fill portion FP. The overlay pattern CL can also be located between the partition wall pattern WP and the embedded layer EL, and between the partition wall pattern WP and the fill layer FL. The embedded layer EL can extend between the overlay pattern CL and the embedded portion EP, and the fill layer FL can extend between the overlay pattern CL and the fill portion FP. The fill layer FL can contact the overlay pattern CL. At least a portion of the embedded layer EL can contact the overlay pattern CL. For example, the upper portion of the embedded layer EL can contact the overlay pattern CL, and the lower portion of the embedded layer EL can also be spaced apart from the overlay pattern CL. The distance between the embedded layer EL and the overlay pattern CL can increase towards the bottom surface of the embedded layer EL.

[0070] On the other hand, when the first source / drain pattern SD1 and the second source / drain pattern SD2 are formed on the sidewalls of the separating patterns ISP1 and ISP2, the covering pattern CL can contact the sidewalls of the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0071] Figure 3B and Figure 3C This is a diagram illustrating a semiconductor device according to one or more embodiments. Figure 3B It is a plan view used to describe a semiconductor device according to one or more embodiments. Figure 3C It is along Figure 3B The cross-sectional view taken by line D-D' in the diagram.

[0072] according to Figure 3B and Figure 3C The first active pattern AP1 and the second active pattern AP2 can be separated by etching separator patterns ISP1 and ISP2. Separator patterns ISP1 and ISP2 may be over-etched, thereby forming a recessed region RCS. The etched separator patterns ISP1 and ISP2 may include recessed sidewalls etched concavely.

[0073] According to the manufacturing method described below, a first sacrificial pattern PP1 can be formed on the separator patterns ISP1 and ISP2. In this case, the first sacrificial pattern PP1 may comprise silicon (Si). During the epitaxial growth (SEG) process for forming the first source / drain pattern SD1 and the second source / drain pattern SD2, the epitaxial growth SEG can be performed together with the first sacrificial pattern PP1. Therefore, the connection pattern CNT, as an epitaxial pattern, can also be formed on the upper surface of the separator patterns ISP1 and ISP2.

[0074] Therefore, the first source / drain pattern SD1 and the second source / drain pattern SD2, which should have been separated by the separating patterns ISP1 and ISP2, may not have been separated, and the upper parts of the separating patterns ISP1 and ISP2 may be in contact with each other through the connecting pattern CNT, potentially causing a short circuit. The first source / drain pattern SD1 and the second source / drain pattern SD2 formed after removing the first sacrificial pattern PP1 may also encounter each other with the gate electrode GE, potentially causing a short circuit.

[0075] According to one or more embodiments, the first active pattern AP1 and the second active pattern AP2 can be separated by not forming the first source / drain pattern SD1 and the second source / drain pattern SD2 on the first active pattern AP1 and the second active pattern AP2, respectively. Therefore, since the separating patterns ISP1 and ISP2 are not etched, the first source / drain pattern SD1 and the second source / drain pattern SD2 can be prevented from meeting each other, or the gate electrode GE can be prevented from meeting the first source / drain pattern SD1 and the second source / drain pattern SD2, thus preventing a short circuit.

[0076] Figure 4 , Figure 5 , Figure 6 , Figure 7A , Figure 7B , Figure 8 , Figure 9 , Figure 10A , Figure 10B , Figure 11 , Figure 12A , Figure 12B , Figure 13 , Figure 14 , Figure 15 , Figure 16A , Figure 16B , Figure 17 , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20 , Figure 21A , Figure 21B and Figure 21CThis is a diagram illustrating a method of manufacturing a semiconductor device according to one or more embodiments. Figure 7A , Figure 19A and Figure 21A Along Figure 1 The line A-A' is cut off. Figure 4 , Figure 5 , Figure 6 , Figure 9 , Figure 10A , Figure 11 , Figure 13 , Figure 14 , Figure 17 , Figure 18A and Figure 21B Along Figure 1 The line B-B' is cut off. Figure 12B Along Figure 12A The line B-B' is cut off, and Figure 16A and Figure 16B Along respectively Figure 15 Lines B-B' and C-C' are cut off. Figure 7B , Figure 8 , Figure 10B , Figure 18B , Figure 19B and Figure 21C Along Figure 1 The line C-C' is cut off. Figure 20 yes Figure 2A A magnified view of part M.

[0077] refer to Figure 4 A substrate 100 can be provided. For example, the substrate 100 can be a substrate including silicon, germanium, silicon-germanium, or a compound semiconductor substrate.

[0078] A stacked pattern STP, a first protective layer PL1, and a first cover pattern CP1 can be sequentially formed on substrate 100. The stacked pattern STP may include a semiconductor layer SL and a sacrificial layer SAL alternately stacked along a third direction D3. The sacrificial layer SAL may include a material that can have etch selectivity relative to the semiconductor layer SL. In the process of removing the sacrificial layer SAL described later, the semiconductor layer SL may not be removed or may be removed in small quantities. For example, the semiconductor layer SL may include any one of silicon, germanium, and silicon-germanium, and the sacrificial layer SAL may include another one of silicon, germanium, and silicon-germanium. The first protective layer PL1 may include an insulating material. The first cover pattern CP1 may include silicon-germanium.

[0079] A first mask pattern MP1 may be formed on a first overlay pattern CP1. The first mask pattern MP1 may include a material having etch selectivity relative to the first overlay pattern CP1. For example, the first mask pattern MP1 may include silicon nitride.

[0080] Forming the stacked pattern STP, the first protective layer PL1, and the first cover pattern CP1 may include: alternately forming a semiconductor layer SL and a sacrificial layer SAL on a substrate 100; forming the first protective layer PL1 and the first cover pattern CP1; and performing a patterning process using a first mask pattern MP1 as a mask. The upper portion of the substrate 100 can be removed together by the patterning process. Therefore, a first trench TR1 and a second trench TR2 defining a first active pattern AP1 and a second active pattern AP2 can be formed. The first trench TR1 may have a relatively larger aspect ratio than the second trench TR2. Each of the first active pattern AP1 and the second active pattern AP2 may extend along a second direction D2.

[0081] An initial cladding layer PCL can be conformally formed on substrate 100. The initial cladding layer PCL can cover the sidewalls of each of the stacked pattern STP, the first protective layer PL1, the first overlay pattern CP1, and the first mask pattern MP1. The initial cladding layer PCL can cover the inner walls of each of the first trench TR1 and the second trench TR2. The initial cladding layer PCL can be formed to have a uniform thickness. The initial cladding layer PCL can include, but is not limited to, at least one of SiON, SiCN, SiOCN, or SiN. For example, the initial cladding layer PCL can include an insulating material such as silicon nitride.

[0082] refer to Figure 5 A separation wall layer (WPL) can be formed on the initial coating layer (PCL). The separation wall layer (WPL) can be formed to fill the first trench (TR1). In some embodiments, due to the large aspect ratio of the first trench (TR1), seams or air gaps may be formed inside the separation wall layer (WPL).

[0083] The separation wall layer WPL may not fill the second trench TR2. The thickness of the separation wall layer WPL may be greater than the thickness of the initial overlay layer PCL. The separation wall layer WPL may include, but is not limited to, insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. For example, the separation wall layer WPL may include SiO2.

[0084] refer to Figure 6 Separation patterns ISP1 and ISP2 can be formed in the first trench TR1. Forming separation patterns ISP1 and ISP2 may include performing a planarization process on the initial overlay layer PCL and the separation wall layer WPL until the upper surface of the first mask pattern MP1 is exposed, and removing the initial overlay layer PCL and the separation wall layer WPL from the second trench TR2.

[0085] A device isolation pattern ST can be formed in the second trench TR2. Since the second trench TR2 has a relatively smaller aspect ratio than the first trench TR1, seams or gaps may not form inside the device isolation pattern ST. The horizontal height of the upper surface of the device isolation pattern ST can be the same as the horizontal height of the upper surfaces of the first active pattern AP1 and the second active pattern AP2, or the horizontal height of the upper surface of the device isolation pattern ST can be lower than the horizontal height of the upper surfaces of the first active pattern AP1 and the second active pattern AP2.

[0086] refer to Figure 7A and Figure 7B The first cover pattern CP1 and the first mask pattern MP1 can be removed. A plurality of first sacrificial patterns PP1 intersecting the stacked pattern STP can be formed on the stacked pattern STP. Each of the first sacrificial patterns PP1 can be formed as a strip extending in a first direction D1. Forming the first sacrificial pattern PP1 may include: forming a sacrificial layer on the upper surface of the substrate 100; forming a second mask pattern MP2 on the sacrificial layer; and patterning the sacrificial layer using the second mask pattern MP2. For example, the sacrificial layer may include amorphous silicon and / or polycrystalline silicon.

[0087] The first protective layer PL1, on which the first sacrificial pattern PP1 is not formed, can be selectively removed. This exposes the upper surface of the stacked pattern STP. Alternatively, the separating patterns ISP1 and ISP2 can remain in place.

[0088] An outer gate spacer layer (OGSL) can be conformally formed on the upper surface of the substrate 100. The OGSL can cover a first sacrificial pattern PP1, a second mask pattern MP2, and a stacked pattern STP. The OGSL can consist of multiple layers or a single layer comprising different insulating materials.

[0089] refer to Figure 8 The outer gate spacer OGS can be formed by performing an anisotropic etching process on the outer gate spacer layer OGSL. The outer gate spacer layer OGSL can be removed from the upper surface of the second mask pattern MP2 and the upper surface of each stacked pattern in the stacked pattern STP by the etching process. The outer gate spacer OGS can cover the sidewalls of the second mask pattern MP2 and the sidewalls of the first sacrificial pattern PP1.

[0090] refer to Figure 9A trimming process can be performed on the separator patterns ISP1 and ISP2 on the substrate 100 where the first sacrificial pattern PP1 is not formed. Therefore, a portion of the overlay pattern CL on the upper part of the separator patterns ISP1 and ISP2 can be removed. The horizontal height of the upper surface of the overlay pattern CL can be lower than the horizontal height of the upper surface of the separator wall pattern WP. In some embodiments, the horizontal height of the upper surface of the overlay pattern CL can be lower than the horizontal height of the upper surface of the stacked pattern STP.

[0091] The outer gate spacer (OGS) on the stacked pattern STP can be removed using a trimming process. However, a portion of the outer gate spacer OGS adjacent to the device isolation pattern ST and the lower part of the stacked pattern STP can be retained to form a fence portion FNP. The fence portion FNP can be a part of the outer gate spacer OGS.

[0092] refer to Figure 10A and Figure 10B An etching process can be performed using the outer gate spacer OGS and the second mask pattern MP2 as masks. The etching process removes a portion of the stacked pattern STP and portions of the first active pattern AP1 and the second active pattern AP2. Due to the etching process, a recess LRS can be formed between adjacent first sacrificial patterns PP1 in the second direction D2. The stacked pattern STP can have a shape extending in the third direction D3 via the recess LRS. The bottom surface of the recess LRS can be lower than the top surface of the device isolation pattern ST.

[0093] refer to Figure 11 A second sacrificial pattern PP2 can be formed on the upper surface of the substrate 100. The second sacrificial pattern PP2 may include amorphous silicon and / or polycrystalline silicon. A third mask pattern MP3 can be formed on the second sacrificial pattern PP2. A third mask pattern MP3 can be formed in the region other than where the second source / drain pattern SD2 will be formed (see [reference]). Figure 12A A third mask pattern MP3 is formed in the area outside the first active pattern AP1. For example, the third mask pattern MP3 can be formed on the first active pattern AP1. It is not necessary to form the third mask pattern MP3 in the area outside the first active pattern AP1. Figure 2B A third mask pattern MP3 is formed on the embedded portion EP. The third mask pattern MP3 may include a material having etch selectivity relative to the second sacrificial pattern PP2.

[0094] A portion of the second sacrificial pattern PP2 can be etched by performing an etching process using a third mask pattern MP3 as a mask. Therefore, the first opening OP1 of the lower recess LRS exposing the second active pattern AP2 can be formed.

[0095] refer to Figure 12A and Figure 12BA second source / drain pattern SD2 can be formed on the exposed second active pattern AP2. Forming the second source / drain pattern SD2 may include: forming a contact sacrificial pattern PH in the lower groove LRS; forming a seed pattern SE; and performing a selective epitaxial growth process using the seed pattern SE as a seed layer.

[0096] The contact sacrificial pattern PH may include a material having etch selectivity relative to the second active pattern AP2. For example, the contact sacrificial pattern PH may be formed in an epitaxial growth process and may include silicon germanium. While performing a selective epitaxial growth process with a seed pattern SE as a seed layer, n-type impurities may be in-situ implanted into the second source / drain pattern SD2. In some embodiments, the impurities may be implanted after the formation of the second source / drain pattern SD2.

[0097] The upper surface of the second source / drain pattern SD2 can be at a lower horizontal level than the upper surface of the second separator pattern ISP2. The upper surface of the second source / drain pattern SD2 can be higher than the upper surface of the covering pattern CL, but is not limited thereto.

[0098] refer to Figure 13 A second sacrificial pattern PP2 can be formed again on the second source / drain pattern SD2. A fourth mask pattern MP4 can be formed on the second sacrificial pattern PP2. This can be done in the region other than where the first source / drain pattern SD1 will be formed (see...). Figure 15 The fourth mask pattern MP4 is formed in the area outside the second active pattern AP2. For example, the fourth mask pattern MP4 can be formed on the second active pattern AP2. The fourth mask pattern MP4 may include a material having etch selectivity relative to the second sacrificial pattern PP2.

[0099] refer to Figure 14 A portion of the second sacrificial pattern PP2 can be etched by performing an etching process using a fourth mask pattern MP4 as a mask. Therefore, a second opening OP2 can be formed that exposes the lower recess LRS of the first active pattern AP1. The first separating pattern ISP1 between the first active patterns AP1 can be exposed through the second opening OP2.

[0100] refer to Figure 15 , Figure 16A and Figure 16B A first source / drain pattern SD1 can be formed on the exposed first active pattern AP1. Forming the first source / drain pattern SD1 may include: forming a contact sacrificial pattern PH in the lower groove LRS; forming a seed pattern SE; and performing a selective epitaxial growth process using the seed pattern SE as a seed layer.

[0101] Forming the first source / drain pattern SD1 can be substantially the same as forming the second source / drain pattern SD2. However, while performing a selective epitaxial growth process using the seed pattern SE as the seed layer, p-type impurities can be implanted in situ into the first source / drain pattern SD1. In some embodiments, impurities can be implanted after the formation of the first source / drain pattern SD1.

[0102] The upper surface of the first source / drain pattern SD1 can be at a lower horizontal level than the upper surface of the second separator pattern ISP1. Therefore, the first source / drain patterns SD1 that are adjacent to each other in the first direction D1 can be separated by the first separator pattern ISP1. The upper surface of the first source / drain pattern SD1 can be higher than the upper surface of the covering pattern CL, but is not limited thereto.

[0103] refer to Figure 17 The second sacrificial pattern PP2 and the fourth mask pattern MP4 on the substrate 100 can be removed. Therefore, the separator patterns ISP1 and ISP2, the first source / drain pattern SD1, and the second source / drain pattern SD2 can be exposed. A covering insulating layer CI can be formed on the separator patterns ISP1 and ISP2, the first source / drain pattern SD1, and the second source / drain pattern SD2. The covering insulating layer CI can cover the fence portion FNP.

[0104] refer to Figure 18A and Figure 18B The cover insulating layer CI can cover the outer gate spacer OGS and the second mask pattern MP2. The cover insulating layer CI can conformally cover the inner wall of the lower recess LRS of the cut region CTR. The portion of the cover insulating layer CI in the lower recess LRS can be the embedded layer EL, and the portion of the cover insulating layer CI extending along the sidewall of the cover pattern CL can be the fill layer FL.

[0105] A first interlayer insulating layer 110 can be formed on the cover insulating layer CI. The first interlayer insulating layer 110 can fill the remaining portion of the lower recess LRS of the cut region CTR. The portion of the first interlayer insulating layer 110 in the lower recess LRS can be an embedded portion EP, and the portion of the first interlayer insulating layer 110 on the sidewall of the second separating pattern ISP2 can be a filling portion FP. The filling portion FP can be the portion of the first interlayer insulating layer 110 between the stacked patterns STP. Thereafter, a planarization process can be performed on the first interlayer insulating layer 110 until the upper surface of the cover insulating layer CI is exposed.

[0106] refer to Figure 19A and Figure 19BA planarization process can be performed on the first interlayer insulating layer 110 until the upper surface of the first sacrificial pattern PP1 is exposed. The second mask pattern MP2 on the first sacrificial pattern PP1 can be removed together with the planarization process. Therefore, the upper surface of the first interlayer insulating layer 110 can be coplanar with the upper surface of the first sacrificial pattern PP1, the upper surface of the overlay insulating layer CI, and the upper surface of the outer gate spacer OGS.

[0107] The exposed first sacrificial pattern PP1 can be selectively removed. Removing the first sacrificial pattern PP1 can include a wet etching process using an etchant that selectively removes polysilicon. By removing the first sacrificial pattern PP1, an external region ORG can be formed. Due to the external region ORG, the stacked pattern STP can be exposed to the outside.

[0108] The sacrificial layer SAL of the stacked pattern STP exposed through the external region ORG can be selectively removed. The sacrificial layer SAL can be selectively removed to form a first internal region IRG1, a second internal region IRG2, a third internal region IRG3, and a fourth internal region IRG4. The etching process for selectively removing the sacrificial layer SAL can remove only the sacrificial layer SAL while retaining the semiconductor layer SL. The etching process for removing the sacrificial layer SAL can have a high etch rate for silicon germanium. Therefore, the channel pattern of the logic transistor can be formed by the semiconductor layer SL. For example, a first channel pattern CH1 and a second channel pattern CH2 including a first semiconductor pattern SP1, a second semiconductor pattern SP2, a third semiconductor pattern SP3, and a fourth semiconductor pattern SP4 can be formed.

[0109] refer to Figure 20 The overlay pattern CL separating the patterns ISP1 and ISP2 can be exposed through the first internal region IRG1, the second internal region IRG2, the third internal region IRG3, and the fourth internal region IRG4. A portion of the overlay pattern CL can also be removed simultaneously with etching the sacrificial layer SAL. The second portion PT2 of the overlay pattern CL, which is the exposed portion, can be etched in a relatively larger amount than the first portion PT1 of the overlay pattern CL, where the first portion PT1 is located between the separator wall pattern WP and the first channel pattern CH1 and the second channel pattern CH2. Therefore, the average width of the first portion PT1 can be greater than the average width of the second portion PT2. The first width W1 of the first portion PT1 in the first direction D1 can be greater than the second width W2 of the second portion PT2 in the first direction D1.

[0110] Because the middle portion of the first PT1 is etched relatively less than the edge portion of the first PT1, the width of the middle portion of the first PT1 can be greater than the width of the edge portion of the first PT1. Because the middle portion of the second PT2 is etched relatively more than the edge portion of the second PT2, the width of the middle portion of the second PT2 can be smaller than the width of the edge portion of the second PT2.

[0111] Subsequently, a gate insulating layer GI with uniform thickness can be formed in the first internal region IRG1, the second internal region IRG2, the third internal region IRG3, the fourth internal region IRG4, and the external region ORG. The gate insulating layer GI can cover the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, the fourth semiconductor pattern SP4, the separator patterns ISP1 and ISP2, and the device isolation pattern ST.

[0112] refer to Figure 21A , Figure 21B and Figure 21C A first gate electrode GE1 and a second gate electrode GE2 can be formed on the gate insulating layer GI. Forming the first gate electrode GE1 and the second gate electrode GE2 may include forming a first inner electrode PO1, a second inner electrode PO2, a third inner electrode PO3, and a fourth inner electrode PO4 between the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4, and forming an outer electrode PO5 in the outer region ORG.

[0113] A gate cover pattern GP can be formed on the first gate electrode GE1 and the second gate electrode GE2. A planarization process can be performed on the gate cover pattern GP so that the upper surface of the gate cover pattern GP is coplanar with the upper surface of the first interlayer insulating layer 110.

[0114] Subsequently, a cut pattern CT can be formed that penetrates the first gate electrode GE1 and the second gate electrode GE2. The cut pattern CT can extend from the gate cover pattern GP to the device isolation pattern ST. Due to the cut pattern CT, the first gate electrode GE1 and the second gate electrode GE2 can be spaced apart from each other in the first direction D1.

[0115] The overlay pattern CL can be an inner gate spacer. The overlay pattern CL can be positioned between the spacer wall pattern WP and the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4. Therefore, the overlay pattern CL can prevent leakage current generated from the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4. This improves the electrical characteristics of the semiconductor device.

[0116] Active contacts AC can be formed in the first interlayer insulation layer 110. Each active contact in the active contacts AC can penetrate the first interlayer insulation layer 110 to connect to at least one of the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0117] Gate contacts GC can be formed in the gate cover pattern GP. Each gate contact in the gate contact GC can be connected to the first gate electrode GE1 and the second gate electrode GE2 through the gate cover pattern GP.

[0118] Refer again Figure 2A , Figure 2B , Figure 2C and Figure 3A A second interlayer insulating layer 120 can be formed on the first interlayer insulating layer 110. An upper pass UV can be formed in the second interlayer insulating layer 120. The upper pass UV can penetrate the second interlayer insulating layer 120 to connect to the active contact AC and the gate contact GC.

[0119] According to the manufacturing method of the semiconductor device, a diced region CTR without a second source / drain pattern SD2 can be formed on the second active pattern AP2. Instead of the second source / drain pattern SD2, an embedding layer EL and an embedding portion EP can be formed in the lower recess LRS on the diced region CTR. The embedding layer EL can be part of the overlay insulating layer CI, and the embedding portion EP can be part of the first interlayer insulating layer 110.

[0120] Instead of cutting the first active pattern AP1 and the second active pattern AP2 by etching the separator patterns ISP1 and ISP2, the first source / drain pattern SD1 and the second source / drain pattern SD2 can be omitted, allowing the first active pattern AP1 and the second active pattern AP2 to be separated. Therefore, it is possible to prevent the separator patterns ISP1 and ISP2 from being etched in a relatively large amount (e.g., over-etching), and it is possible to prevent the first sacrificial pattern PP1 on the separator patterns ISP1 and ISP2 from epitaxially growing together during the formation of the first source / drain pattern SD1 and the second source / drain pattern SD2, so that the first source / drain pattern SD1 and the second source / drain pattern SD2 meet. Therefore, by preventing electrical short circuits, semiconductor devices with improved electrical characteristics and reliability can be manufactured.

[0121] The semiconductor device according to the embodiment can be diced by not forming source / drain patterns on the active pattern. Instead of the source / drain patterns, an embedded portion of the first interlayer insulating layer can be formed in the lower recess. Furthermore, the source / drain patterns can be formed on one sidewall of the separator pattern, and the embedded layer and embedded portion can be formed on the other sidewall of the separator pattern. This prevents electrical short circuits with the source / drain patterns of adjacent gate electrodes that would occur when the separator pattern is etched to dice the previous active pattern. Therefore, the electrical characteristics and reliability of the semiconductor device can be improved.

[0122] According to one embodiment, a method of manufacturing a semiconductor device may include: forming an active pattern and a separator pattern on a substrate, wherein the active pattern extends in a first direction and the separator pattern extends perpendicularly between the active patterns; forming a recess in the active pattern; forming a source / drain pattern in one of the recesses; and forming a cover insulating layer and an interlayer insulating layer covering the source / drain pattern, wherein the interlayer insulating layer includes an embedded portion extending into another recess in the other recess, wherein the separator pattern has a first sidewall and a second sidewall opposing each other in a second direction intersecting the first direction, and wherein the first sidewall contacts the embedded portion and the second sidewall contacts the source / drain pattern.

[0123] In the manufacturing process of semiconductor devices, the covering insulating layer includes an embedded layer that covers the inner wall of the recess.

[0124] In the manufacturing process of semiconductor devices, the horizontal height of the bottom surface of the embedding layer is the same as the horizontal height of the bottom surface of the source / drain pattern.

[0125] In a semiconductor device manufacturing method, the separator pattern includes an overlay pattern and a separator wall pattern on the overlay pattern, wherein the overlay pattern is located between the separator wall pattern and the embedded portion.

[0126] The method of manufacturing a semiconductor device may further include forming first channel patterns spaced apart from each other on the active pattern, and the interlayer insulating layer further includes filling portions on the embedded portions, wherein the filling portions are located between the first channel patterns.

[0127] Each embodiment described above is not excluded from being associated with one or more features of another example or another embodiment that are also provided or not provided herein but are consistent with this disclosure.

[0128] Although this disclosure has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: An active pattern, wherein the active pattern is located on a substrate and spaced apart in a first direction; At least one source / drain pattern, wherein the at least one source / drain pattern is located on at least the first active pattern among the active patterns; An interlayer insulating layer covering the at least one source / drain pattern; as well as A separating pattern, wherein the separating pattern is located between the active patterns and extends in a second direction intersecting the first direction. The interlayer insulating layer includes an embedded portion that extends into the first active pattern within the active pattern. The dividing pattern includes a first sidewall and a second sidewall that are opposite to each other in the first direction, and The first sidewall contacts the embedded portion, and the second sidewall contacts the at least one source / drain pattern.

2. The semiconductor device of claim 1, further comprising a covering insulating layer located on the at least one source / drain pattern. in, The covering insulating layer includes an embedded layer located between the embedded portion and the first active pattern.

3. The semiconductor device according to claim 2, wherein, The bottom surface of the embedded layer is at the same horizontal height as the bottom surface of the at least one source / drain pattern.

4. The semiconductor device according to claim 2, wherein, The width of the embedded portion decreases in the vertical direction toward the bottom surface of the substrate, and The thickness of the embedded layer is in the range of 3nm to 10nm.

5. The semiconductor device according to claim 2, wherein, The dividing pattern includes an overlay pattern and dividing wall patterns located on the overlay pattern, and The covering pattern is located between the partition wall pattern and the embedded portion.

6. The semiconductor device according to claim 5, wherein, The covering pattern is located between the partition wall pattern and the embedded layer, and At least a portion of the embedded layer contacts the covering pattern.

7. The semiconductor device according to claim 5, further comprising: The first channel pattern is adjacent to the dividing pattern; as well as A gate electrode, the gate electrode being located on the first channel pattern and extending along the first direction. The covering pattern includes: A first portion, the first portion being located between the partition wall pattern and the first channel pattern; and The second part is located between the partition wall pattern and the gate electrode, and Wherein, the width of the first part in the first direction is greater than the width of the second part in the first direction.

8. The semiconductor device of claim 2, further comprising a first channel pattern located on the first active pattern and spaced apart in the second direction. in, The interlayer insulation layer includes a filling portion located on the embedded portion, and The filling portion is located between the first channel patterns.

9. The semiconductor device according to claim 8, wherein, The dividing pattern includes an overlay pattern and dividing wall patterns located on the overlay pattern. The covering insulating layer includes a fill layer located on the embedded layer. The filling layer is located between the filling portion and the dividing pattern, and The filling layer covers the sidewalls of the covering pattern.

10. The semiconductor device according to claim 9, wherein, The filling layer is located between the first channel pattern and the filling portion, and The filling layer contacts the sidewall of the first channel pattern and the covering pattern.

11. The semiconductor device according to claim 9, wherein, The at least one source / drain pattern includes a first source / drain pattern and a second source / drain pattern, wherein the first source / drain pattern is adjacent to the fill layer, and the second source / drain pattern is adjacent to the first source / drain pattern and spaced apart from the fill layer in the second direction. In the second direction, the first spacing between the filling layer and the first source / drain pattern is the same as the second spacing between the first source / drain pattern and the second source / drain pattern.

12. A semiconductor device, the semiconductor device comprising: An active pattern, wherein the active pattern is located on a substrate; Source / drain pattern, wherein the source / drain pattern is located on the active pattern; A covering insulating layer is provided, which covers the source / drain pattern; An interlayer insulation layer, wherein the interlayer insulation layer is located on the covering insulation layer; as well as A separating pattern, the separating pattern being located on the substrate and extending in a first direction. The interlayer insulating layer includes an embedded portion that extends into the active pattern. The covering insulating layer includes an embedded layer located between the embedded portion and the separating pattern. The bottom surface of the embedded layer is at the same horizontal level as the bottom surface of the source / drain pattern.

13. The semiconductor device according to claim 12, wherein, The width of the embedded portion in the first direction decreases toward the bottom surface of the substrate.

14. The semiconductor device according to claim 12, wherein, The embedding layer extends between the embedding portion and the active pattern, and The thickness of the embedded layer is in the range of 3nm to 10nm.

15. The semiconductor device according to claim 12, wherein, The dividing pattern includes an overlay pattern and dividing wall patterns located on the overlay pattern, and The covering pattern is located between the partition wall pattern and the embedded portion.

16. The semiconductor device according to claim 15, wherein, The covering pattern is located between the partition wall pattern and the embedded layer, and At least a portion of the embedded layer contacts the covering pattern.

17. A semiconductor device, the semiconductor device comprising: Substrate, the substrate comprising an active pattern; Device isolation pattern, wherein the device isolation pattern defines the active pattern; A first channel pattern and at least one second channel pattern, the first channel pattern and the at least one second channel pattern being located on the active pattern and spaced apart in a first direction; A first source / drain pattern and a second source / drain pattern, the first source / drain pattern and the second source / drain pattern being respectively connected to the first channel pattern and the at least one second channel pattern; A separating pattern, the separating pattern being located on the substrate and extending in a second direction intersecting the first direction; A gate electrode, the gate electrode being located on the first channel pattern and the at least one second channel pattern; A gate insulating layer is located between the gate electrode, the first channel pattern, and the at least one second channel pattern; An insulating layer is provided, which covers the first source / drain pattern and the second source / drain pattern; A gate overlay pattern, the gate overlay pattern being located on the upper surface of the gate electrode; An interlayer insulating layer, the interlayer insulating layer covering the first source / drain pattern, the second source / drain pattern and the covering insulating layer; An active contact, which passes through the interlayer insulating layer and connects to the first source / drain pattern and the second source / drain pattern; A gate contact that connects to the gate electrode through the gate cover pattern; as well as A first metal layer, situated on the interlayer insulating layer, includes a first wiring connection to the active contact and the gate contact. The interlayer insulating layer includes an embedded portion that extends into the active pattern. The covering insulating layer includes an embedded layer that extends between the embedded portion and the separating pattern. The separating pattern is located between the embedded portion and the second source / drain pattern.

18. The semiconductor device of claim 17, wherein, The at least one second channel pattern includes a plurality of semiconductor patterns, the plurality of semiconductor patterns being spaced apart in a third direction intersecting the first direction and the second direction. The interlayer insulating layer further includes a filling portion located on the embedded portion, and The filling portion is located between the plurality of semiconductor patterns.

19. The semiconductor device according to claim 18, wherein, The dividing pattern includes an overlay pattern and dividing wall patterns located on the overlay pattern. The covering insulating layer includes a fill layer located on the embedded layer. The filling layer is located between the filling portion and the dividing pattern, and The filling layer covers the sidewalls of the covering pattern.

20. The semiconductor device of claim 19, further comprising a third source / drain pattern. in, The first source / drain pattern, the second source / drain pattern, and the third source / drain pattern are spaced apart in the second direction. Wherein, the second source / drain pattern is adjacent to the filling layer, and the third source / drain pattern is adjacent to the second source / drain pattern and spaced apart from the filling layer in the second direction, and The first spacing between the filling layer and the second source / drain pattern in the second direction is the same as the second spacing between the second source / drain pattern and the third source / drain pattern in the second direction.

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