A semiconductor device and a method for manufacturing a semiconductor device

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, which comprises: a semiconductor substrate, active regions and isolation structures being formed in the semiconductor substrate; and a plurality of gate structures being distributed on the semiconductor substrate, wherein, in a first direction, the plurality of gate structures are arranged at intervals, in a second direction, the plurality of gate structures are arranged at intervals, and each gate structure is connected with a single active region or isolation structure. In the application, the connection between the gate structure and the active region or the isolation structure is arranged as a single-to-single independent structure, so that the defect of each active region with high dielectric constant medium can be detected, and the device can be effectively avoided from being scrapped, and the manufacturing efficiency of the semiconductor device is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the semiconductor device. Background Technology

[0002] In the process of integrated circuit fabrication, especially in advanced semiconductor device manufacturing, HiK (High-k Dielectric) is often used instead of Gate OX (Gate Oxide) to provide stronger insulation.

[0003] However, local or whole-wafer defects (Hik Missing) in high dielectric constant media can exist, which are fatal defects in the core of transistor manufacturing. Because semiconductor devices are small and thin, they cannot be detected by BFI (Bright Field Inspection) optical equipment and can only be detected by electron beam EBI (Electron Beam Inspection). However, in the structure of existing semiconductor devices, the polysilicon and the bottom active area (AA) are in parallel. If a Hik Missing occurs in a single active area, electrons can be conducted away from other active areas, making it impossible for EBI to detect, which can easily lead to device scrap and thus affect manufacturing efficiency. Summary of the Invention

[0004] This application provides a semiconductor device that can quickly and effectively detect defects in high dielectric constant dielectric layers, reducing device scrap and improving semiconductor device manufacturing efficiency.

[0005] To address the aforementioned technical problems, this application provides a semiconductor device comprising: a semiconductor substrate having a plurality of mutually isolated active regions and isolation structures formed therein; and a plurality of gate structures distributed on the semiconductor substrate, wherein, in a first direction, the plurality of gate structures are spaced apart, and in a second direction, the plurality of gate structures are spaced apart, and each gate structure is located on a single active region or isolation structure.

[0006] In some embodiments, adjacent active regions are isolated by the isolation structure, and the active regions extend along a first direction; the gate structure extends along a second direction, wherein, in the second direction, gate structures in the same column are spaced apart, and the first direction and the second direction are perpendicular.

[0007] In some embodiments, in the second direction, each of the gate structures is connected to a corresponding active region, and adjacent gate structures are separated by an isolation layer, wherein each of the gate structures and the corresponding active region have a first overlap portion, the first overlap portion covering at least a portion of the gate structure.

[0008] In some embodiments, in the first direction, there are multiple gate structures on the same active region, and the multiple gate structures are spaced apart.

[0009] In some embodiments, in the second direction, each of the gate structures is connected to a corresponding isolation structure, and adjacent gate structures are separated by an isolation layer, wherein each of the gate structures and the corresponding isolation structure have a second overlapping portion, the second overlapping portion covering at least a portion of the gate structure.

[0010] In some embodiments, in the first direction, there are multiple gate structures on the same isolation structure, and the multiple gate structures are spaced apart.

[0011] In some embodiments, the isolation layer is located in the cutting channel.

[0012] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, wherein an active region and an isolation structure are formed therein; forming a plurality of gate structures distributed on the semiconductor substrate, wherein, in a first direction, the plurality of gate structures are spaced apart, and in a second direction, the plurality of gate structures are spaced apart, and each gate structure is located on a single active region or isolation structure.

[0013] In some embodiments, forming a gate structure includes: forming a gate material layer on the semiconductor substrate, the gate material layer extending along a second direction, wherein, in a first direction, a plurality of the gate material layers are spaced apart; removing at least a portion of a plurality of regions of the gate material layers in the same column; and forming a plurality of gate structures in the second direction, wherein, in the second direction, adjacent gate structures are spaced apart, and each gate structure is located above a corresponding active region or isolation structure.

[0014] In some embodiments, removing at least a portion of multiple regions of the same column of the gate material layer to form a plurality of gate structures in the second direction includes: removing at least a portion of the same column of the gate material layer located above the isolation structure to form a first groove, and forming a plurality of gate structures in the second direction, wherein adjacent gate structures are isolated by the first groove in the second direction, and each gate structure is located above a corresponding active region.

[0015] In some embodiments, the method further includes: forming an isolation layer that fills the first groove and contacts the isolation structure at the bottom of the first groove, wherein adjacent gate structures are isolated by the isolation layer.

[0016] In some embodiments, removing at least a portion of multiple regions of the same column of the gate material layer to form a plurality of gate structures in the second direction includes: removing at least a portion of the same column of the gate material layer above the active region to form a second groove, and forming a plurality of gate structures in the second direction, wherein adjacent gate structures are isolated by the second groove in the second direction, and each gate structure is located above a corresponding isolation structure.

[0017] In some embodiments, the method further includes: forming an isolation layer that fills the second groove and contacts the active region at the bottom of the second groove, wherein adjacent gate structures are isolated by the isolation layer.

[0018] The semiconductor device provided in the embodiments of this application includes: a semiconductor substrate in which mutually isolated active regions and isolation structures are formed; and a plurality of gate structures distributed on the semiconductor substrate, wherein the plurality of gate structures are spaced apart in a first direction and in a second direction, and each gate structure is located on a single active region or isolation structure. That is, in this application, the connection between the gate structure and the active region or isolation structure is set as a one-to-one independent structure, so that high dielectric constant dielectric defects in each active region can be detected, thereby effectively avoiding device scrap and improving the manufacturing efficiency of the semiconductor device. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1This is a schematic diagram of the structure of the first embodiment of the semiconductor device in this application; Figure 2 This is a schematic diagram of the structure of the second embodiment of the semiconductor device in this application; Figure 3 It is in this application Figure 2 A schematic diagram of the structure in cross-section along the first direction; Figure 4 It is in this application Figure 2 A schematic diagram of the structure in cross-section along the second direction; Figure 5 This is a schematic diagram of the structure of the third embodiment of the semiconductor device in this application; Figure 6 It is in this application Figure 5 A schematic diagram of the structure in cross-section along the first direction; Figure 7 It is in this application Figure 5 A schematic diagram of the structure in cross-section along the second direction; Figure 8 This is a schematic flowchart of an embodiment of the semiconductor device manufacturing method in this application; Figure 9 This is a schematic diagram of the structure of an embodiment of the semiconductor substrate in this application; Figure 10 This is a schematic diagram of a structure of an embodiment of forming a gate material layer in this application; Figure 11 This is a schematic diagram of the structure of the first embodiment of the gate structure in this application; Figure 12 This is a schematic diagram of the structure of an embodiment of filling the first groove in this application; Figure 13 This is a schematic diagram of the structure of the second embodiment of the gate structure in this application; Figure 14 This is a schematic diagram of an embodiment of filling the second groove in this application.

[0021] In the attached figures, there is a semiconductor substrate 100, an active region 110, an isolation structure 120, a gate material layer 210, a gate structure 200, a first groove 201, a second groove 202, and an isolation layer 300. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0023] In related technologies, HiK is used to replace Gate OX in advanced semiconductor device manufacturing processes to provide stronger insulation. However, the resulting HiK missing is a fatal defect, especially HiK missing in SRAM (Static Random Access Memory). Due to its small and thin size, BFI optical equipment cannot detect it, and defect detection can only be performed by electron beam spectroscopy (EBI). When the defect occurs, the polysilicon (poly) and the bottom active area (AA) are in parallel, making them undetectable by EBI. Furthermore, after the poly is removed, HiK is exposed. While electron beam defect scanning has high detection sensitivity, it is slow, and the high-energy electron injection of the gate structure by EBI can degrade the semiconductor device, rendering it unusable. It also causes a decrease in detection sensitivity and a longer manufacturing cycle, reducing the manufacturing efficiency of semiconductor devices.

[0024] Therefore, a semiconductor device is provided that can quickly and effectively detect defects in high dielectric constant dielectric layers, reduce device scrap, and improve the manufacturing efficiency of semiconductor devices.

[0025] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the semiconductor device in this application.

[0026] like Figure 1 As shown, the semiconductor device includes a semiconductor substrate 100 and a plurality of gate structures 200.

[0027] A plurality of mutually isolated active regions 110 and isolation structures 120 are formed in a semiconductor substrate 100; a plurality of gate structures 200 are distributed on the semiconductor substrate 100, wherein, in a first direction, the plurality of gate structures 200 are spaced apart, and in a second direction, the plurality of gate structures 200 are spaced apart, and each gate structure 200 is located on a single active region 110 or isolation structure 120, that is, each gate structure 200 is connected to a single active region 110 or isolation structure 120.

[0028] The semiconductor substrate 100 can be made of any suitable semiconductor material in the art, including but not limited to: silicon, germanium, silicon-germanium, silicon-germanium carbide, silicon carbide, and other semiconductor materials. For example, in this embodiment, the semiconductor substrate 100 is made of silicon, or the semiconductor substrate 100 is an SOI (Silicon On Insulator) substrate. The gate structure 200 refers to any suitable gate structure in the art, such as a polysilicon gate or a metal gate, and may include a gate oxide layer or a high-dielectric-constant dielectric layer (not shown in the figure), a gate (not shown in the figure), and sidewall structures on both sides of the gate (not shown in the figure). The isolation structure 120 refers to any suitable isolation material in the art, used to isolate adjacent active regions 110. The first direction refers to the X direction, and the second direction refers to the Y direction, that is, the first direction and the second direction are perpendicular to each other on the same horizontal plane.

[0029] Specifically, the semiconductor substrate 100 has mutually isolated active regions 110 and isolation structures 120, i.e., the isolation structure 120 isolates adjacent active regions 110; a plurality of gate structures 200 are distributed on the semiconductor substrate 100, and in a first direction, the plurality of gate structures 200 are spaced apart, and in a second direction, a plurality of gate structures 200 are also spaced apart, and each gate structure 200 distributed on the semiconductor substrate 100 is located on and connected to only a single active region 110; or each gate structure 200 is located on and connected to only a single isolation structure 120. It is understood that "connection" refers to "contact".

[0030] Understandably, when each gate structure 200 is connected to only a single active region 110, if a high-dielectric-constant dielectric layer defect exists beneath the gate structure 200, electrons from the gate structure 200 cannot be conducted away from the active region 110 beneath it, nor from other active regions 110. Therefore, the high-dielectric-constant dielectric layer defect can be detected. Similarly, when each gate structure 200 is connected to only a single isolation structure 120, a high-dielectric-constant dielectric layer defect beneath the gate structure 200 can also be detected without compromising the semiconductor device.

[0031] In this embodiment, the connection between the gate structure and the active region or isolation structure is set as a one-to-one independent structure, so that high dielectric constant dielectric defects in each active region can be detected, thereby effectively avoiding device scrapping and improving the manufacturing efficiency of semiconductor devices.

[0032] In some embodiments, a plurality of active regions 110 are formed in the semiconductor substrate 100, adjacent active regions 110 are isolated by an isolation structure 120, and the active regions 110 extend along a first direction. The gate structure 200 extends along a second direction, wherein, in the second direction, gate structures 200 in the same column are spaced apart, and the first direction and the second direction are perpendicular.

[0033] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of the second embodiment of the semiconductor device in this application.

[0034] Each active region 110 is surrounded by an isolation structure 120, thereby isolating adjacent active regions 110.

[0035] Specifically, a plurality of active regions 110 are formed in the semiconductor substrate 100, and the active regions 110 extend along a first direction, that is, the plurality of active regions 110 are spaced apart in a second direction. The gate structure 200 is located on the semiconductor substrate 100, extends along the second direction, and in the second direction, gate structures 200 in the same column are spaced apart, and the gate structure 200 is located on the active regions 110; it can be understood that the gate structures 200 in the same column are formed after being separated by the same gate material layer.

[0036] It is understandable that the active region 110 extending along the first direction does not directly connect to the gate structure 200. Subsequent doping of the active region 110 is required, and the gate structure 200 must have corresponding contact pillars to connect to the active region for electrical connection to be achieved. Furthermore, it is understandable that the active region 110 extending along the first direction is separated by multiple gate structures 200, meaning that each gate structure serves as a boundary line dividing the active region. These can subsequently be used as a common source / drain, with each gate structure corresponding to an independent MOS transistor, forming a series transistor chain.

[0037] In some embodiments, in the second direction, each gate structure is connected to a corresponding active region, and adjacent gate structures 200 are separated by an isolation layer 300, wherein each gate structure 200 and the corresponding active region 110 have a first overlapping portion, the first overlapping portion covering at least a portion of the gate structure 200.

[0038] In this configuration, the gate structure 200 is connected to the active region 110, meaning that the gate material layer on the isolation structure 120 is isolated by the isolation layer. The first overlapping portion refers to the overlap between the orthographic projection of the gate structure 200 and the orthographic projection of the connected active region 110 in the vertical direction.

[0039] Specifically, when forming the gate structure 200, at least a portion of the gate material layer on the isolation structure 120 is removed and filled with an isolation layer 300; thereby, in the second direction, each gate structure 200 is connected to only one corresponding active region 110, and the portion above the isolation structure 120 is filled with the isolation layer 300, that is, adjacent gate structures 200 are separated by the isolation layer 300. Furthermore, in some embodiments, at least a portion of the gate structure 200 may extend above the isolation structure 120, but adjacent gate structures 200 are separated by the isolation layer 300, that is, a single gate structure 200 only needs to be located above one active region 110, i.e., only one active region 110 needs to be connected.

[0040] In some embodiments, in a first direction, a plurality of gate structures 200 are connected to the same active region 110, and the plurality of gate structures 200 are spaced apart.

[0041] The active region 110 extends along a first direction, while the gate structure 200 extends along a second direction. Therefore, multiple gate structures 200 are connected to the same active region 110.

[0042] Specifically, the active region 110 in the semiconductor substrate 100 extends along a first direction, and the gate structure 200 above the semiconductor substrate 100 extends along a second direction, so there are multiple gate structures 200 above the active region 110; and the active region 110 is cut with each gate structure 200 as a dividing line, and the sub-active regions after the cut can be used as common source and drain, that is, the sub-active region on one side of the gate structure 200 is used as the first source and drain, and the sub-active region on the other side is used as the second source and drain; each gate structure 200 corresponds to an independent MOS transistor, and the whole constitutes a series transistor chain.

[0043] In some embodiments, the active region 110 may be a single line extending along the first direction. Alternatively, multiple active regions 110 may be arranged at intervals in the same row along the first direction, serving as independent short silicon islands.

[0044] Understandably, since the gate structure 200 is located on only one active region 110 and connected to only one active region 110, if the gate structure 200 has a high dielectric constant dielectric layer defect, electrons cannot be conducted downwards, that is, they will not be conducted away from the sub-active region. Therefore, connecting multiple gate structures 200 to the same active region 110 does not affect the detection of high dielectric constant dielectric layer defects in the gate structure 200.

[0045] In some embodiments, the isolation layer 300 is located in the cutting channel.

[0046] Specifically, the isolation layer 300 used to isolate the gate structure 200 is located in the dicing channel, so as not to affect subsequent dicing.

[0047] To illustrate this more clearly, we can also use a cross-sectional view.

[0048] Please see Figure 3 and Figure 4 , Figure 3 It is in this application Figure 2 A schematic diagram of the structure in cross-section along the first direction; Figure 4 It is in this application Figure 2 A schematic diagram of the structure in cross-section along the second direction.

[0049] Specifically, the first direction is the X direction, which includes the X1 direction. Figure 3 yes Figure 2 A schematic diagram of the structure along the cross-section of the X1 direction; the second direction is the Y direction, which includes the Y1 direction. Figure 4 yes Figure 2 A schematic diagram of the structure in cross section along the Y1 direction.

[0050] like Figure 3 and Figure 4 As shown, in a first direction, the semiconductor device includes a semiconductor substrate 100, in which an isolation structure 120 and an active region 110 are formed; a gate structure 200 is also formed on the active region 110. In a second direction, the gate structure 200 is located on the active region 110, gate structures 200 in the same column are spaced apart, and an isolation layer 300 is provided between adjacent gate structures 200.

[0051] In some embodiments, the isolation layer 300 may be slightly higher than the gate structure 200, slightly lower than the gate structure 200, or flush with the gate structure 200. The material of the isolation layer 300 may be silicon dioxide. In some embodiments, an interlayer dielectric layer may be subsequently used to cover the gate structure 200 and the isolation layer 300, thereby forming connection pillars in the interlayer dielectric layer to bring out the source and drain electrodes on both sides of the gate structure 200.

[0052] In this embodiment, the connection between the gate structure and the active region is set as a one-to-one independent structure, so that high dielectric constant dielectric defects in the gate structure above each active region can be detected, thereby effectively avoiding device scrapping and improving the manufacturing efficiency of semiconductor devices.

[0053] In some embodiments, in the second direction, each gate structure 200 is located on a corresponding isolation structure 120, that is, connected to a corresponding isolation structure 120, and adjacent gate structures 200 are separated by an isolation layer 300, wherein each gate structure 200 and the corresponding isolation structure 120 have a second overlapping portion, the second overlapping portion covering at least a portion of the gate structure 200.

[0054] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of the third embodiment of the semiconductor device in this application.

[0055] like Figure 5 As shown, a plurality of active regions 110 are formed in the semiconductor substrate 100, and the active regions 110 extend along a first direction, that is, the plurality of active regions 110 are spaced apart in a second direction. The gate structure 200 is located on the semiconductor substrate 100, extends along the second direction, and in the second direction, gate structures 200 in the same column are spaced apart, and the gate structures 200 are located on the isolation structure 120; it can be understood that the gate structures 200 in the same column are formed after being separated by the same gate material layer. It can be understood that the active regions 110 are located beneath the isolation layer 300.

[0056] Each active region 110 is isolated by an isolation structure 120, thereby isolating adjacent active regions 110. The gate structure 200 is connected to the isolation structure 120, meaning that the gate material layer above the active regions 110 is isolated by the isolation layer 300. The second overlapping portion refers to the overlap between the orthographic projection of the gate structure 200 and the orthographic projection of the connected isolation structure 120 in the vertical direction.

[0057] Specifically, when forming the gate structure 200, at least a portion of the gate material layer on the active region 110 is removed and filled with an isolation layer 300; thereby, in the second direction, each gate structure 200 is located on only one corresponding isolation structure 120, that is, it is only connected to one corresponding isolation structure 120, and the portion above the active region 110 is filled with an isolation layer 300, that is, adjacent gate structures 200 are separated by the isolation layer 300.

[0058] It is understandable that the connection between the gate structure 200 and the isolation structure 120 is a contact.

[0059] In some embodiments, in a first direction, there are multiple gate structures 200 on the same isolation structure 120, that is, multiple gate structures 200 are connected and the multiple gate structures 200 are spaced apart.

[0060] Wherein, the active region 110 extends along the first direction, the isolation structure 120 also extends along the first direction, and the gate structure 200 extends along the second direction. Therefore, there are multiple gate structures 200 connected by the same isolation structure 120.

[0061] Specifically, the active region 110 in the semiconductor substrate 100 extends along a first direction, and the isolation structure 120 also extends along the first direction; while the gate structure 200 above the semiconductor substrate 100 extends along a second direction, so there are multiple gate structures 200 above the isolation structure 120. Since the gate structure 200 is not connected to the active region 110, high dielectric constant dielectric layer defects can be detected in each gate structure 200, and accurate detection results can be obtained.

[0062] In some embodiments, the isolation layer 300 is located in the cutting channel.

[0063] Specifically, the isolation layer 300 used to isolate the gate structure 200 is located in the dicing channel, so as not to affect subsequent dicing.

[0064] To illustrate this more clearly, we can also use a cross-sectional view.

[0065] Please see Figure 6 and Figure 7 , Figure 6 It is in this application Figure 5 A schematic diagram of the structure in cross-section along the first direction; Figure 7 It is in this application Figure 5 A schematic diagram of the structure in cross-section along the second direction.

[0066] It is understandable that the first direction is the X direction, and the X direction includes the X2 direction. Figure 6 yes Figure 5 A schematic diagram of the structure along the X2 direction; the second direction is the Y direction, which includes the Y2 direction. Figure 7 yes Figure 5 A schematic diagram of the structure in cross section along the Y2 direction.

[0067] like Figure 6 and Figure 7 As shown, in a first direction, the semiconductor device includes a semiconductor substrate 100, in which an isolation structure 120 and an active region 110 are formed; a gate structure 200 is also formed on the isolation structure 120. In a second direction, the gate structure 200 is located on the isolation structure 120, and gate structures 200 in the same column are spaced apart, with an isolation layer 300 disposed between adjacent gate structures 200.

[0068] In some embodiments, the isolation layer 300 also covers the gate structure 200.

[0069] In this embodiment, the connection between the gate structure and the isolation structure is set as a one-to-one independent structure, so that high dielectric constant dielectric defects in the gate structure on each isolation structure can be detected, thereby effectively avoiding device scrapping and improving the manufacturing efficiency of semiconductor devices.

[0070] This application also provides a method for manufacturing a semiconductor device.

[0071] Please see Figure 8 , Figure 8 This is a schematic flowchart of an embodiment of the semiconductor device manufacturing method in this application.

[0072] like Figure 8 As shown, the method for manufacturing the semiconductor device in this application includes the following.

[0073] S10. Provide a semiconductor substrate in which mutually isolated active regions and isolation structures are formed.

[0074] S20. A plurality of gate structures are formed and distributed on a semiconductor substrate, wherein the plurality of gate structures are spaced apart in a first direction and in a second direction, and each gate structure is located on a single active region or isolation structure.

[0075] The manufacturing method will now be described in conjunction with the accompanying drawings.

[0076] Please see Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 , Figure 9 This is a schematic diagram of the structure of an embodiment of the semiconductor substrate in this application; Figure 10 This is a schematic diagram of a structure of an embodiment of forming a gate material layer in this application; Figure 11 This is a schematic diagram of the structure of the first embodiment of the gate structure in this application; Figure 12 This is a schematic diagram of the structure of an embodiment of filling the first groove in this application; Figure 13 This is a schematic diagram of the structure of the second embodiment of the gate structure in this application; Figure 14 This is a schematic diagram of an embodiment of filling the second groove in this application.

[0077] First, a semiconductor substrate 100 is provided.

[0078] Please see Figure 9 The semiconductor substrate 100 has mutually isolated active regions 110 and isolation structures 120 formed therein. The active regions 110 extend along a first direction, and each active region 110 is surrounded by the isolation structure 120. In some embodiments, multiple active regions 110 are arranged at intervals in the same row, and each active region 110 is an independent short silicon island.

[0079] Next, a gate material layer 210 is formed on the semiconductor substrate 100. The gate material layer 210 extends along a second direction, wherein, in the first direction, a plurality of gate material layers 210 are spaced apart.

[0080] Please see Figure 10 A gate material layer 210 is formed on the semiconductor substrate 100, and a plurality of gate material layers 210 are spaced apart in a first direction, while in a second direction the gate material layers 210 extend along a second direction. That is, the gate material layer 210 covers at least a portion of the plurality of active regions 110 in the second direction, i.e., connects the plurality of active regions 110, and the active regions 110 have a plurality of gate material layers 210 in the first direction, i.e., connect the plurality of gate material layers 210.

[0081] Next, at least a portion of multiple regions of the gate material layer 210 in the same column is removed to form a plurality of gate structures 200 distributed on the semiconductor substrate 100. In a first direction, the plurality of gate structures 200 are spaced apart, and in a second direction, the plurality of gate structures 200 are spaced apart. Each gate structure 200 is located on a single active region 110, i.e., connected to a single active region 110.

[0082] In the first direction, multiple rows of gate material layers 210 are spaced apart. Then, for each row of gate material layers 210, at least a portion of multiple regions of the same row of gate material layers 210 is removed to form multiple gate structures 200 in the second direction. In the second direction, adjacent gate structures are spaced apart, and each gate structure 200 is located on a corresponding active region 110 or isolation structure 120, that is, connected to a corresponding active region 110 or isolation structure 120.

[0083] It is understandable that "multiple regions" refers to multiple isolated areas, that is, the gate material layer 210 is separated into multiple gate structures 200.

[0084] In some embodiments, removing at least a portion of multiple regions of the same column of gate material layer to form multiple gate structures in a second direction may include the following steps.

[0085] Please see Figure 11 At least a portion of the gate material layer 210 in the same column located on the isolation structure 120 is removed to form a first groove 201. A plurality of gate structures 200 are formed in a second direction, wherein adjacent gate structures 200 are isolated by the first groove 201 in the second direction, and each gate structure 200 is located on a corresponding active region 110, that is, connected to a corresponding active region 110.

[0086] It is understood that the first groove 201 extends along the first direction to isolate the gate material layer 210; and there are multiple first grooves 201, which are spaced apart in the second direction and are all located on the isolation structure 120. That is, a corresponding first groove 201 is formed on each isolation structure 120 extending along the first direction. This causes the same gate material layer 210 to be isolated into multiple gate structures 200, and each gate structure 200 is located on the active region 110.

[0087] Please refer to the following: Figure 12 An isolation layer 300 is formed, filling the first groove 201 and contacting the isolation structure 120 at the bottom of the first groove 201, wherein adjacent gate structures 200 are isolated by the isolation layer 300.

[0088] In other embodiments, removing at least a portion of multiple regions of the same column of gate material layer to form multiple gate structures in a second direction may include the following steps.

[0089] Please see Figure 13 At least a portion of the gate material layer 210 in the same column located above the active region 110 is removed to form a second groove 202, and a plurality of gate structures 200 are formed in the second direction, wherein adjacent gate structures 200 are isolated by the second groove 202 in the second direction, and each gate structure 200 is located on a corresponding isolation structure 120, that is, connected to a corresponding isolation structure 120.

[0090] It is understood that the second groove 202 extends along the first direction to isolate the gate material layer 210; and there are multiple second grooves 202, which are spaced apart in the second direction and are all located on the active region 110. That is, a corresponding second groove 202 is formed on each active region 110 extending along the first direction. This causes the same gate material layer 210 to be isolated into multiple gate structures 200, and each gate structure 200 is located on the isolation structure 120.

[0091] See next Figure 14 An isolation layer 300 is formed, which fills the second groove 202 and contacts the active region 110 at the bottom of the second groove 202, wherein the adjacent gate structure 200 is isolated by the isolation layer 300.

[0092] In one embodiment of this application, the connection between the gate structure and the active region or isolation structure is set as a one-to-one independent structure, so that high dielectric constant dielectric defects in each active region can be detected, thereby effectively avoiding device scrapping and improving the manufacturing efficiency of semiconductor devices.

[0093] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor substrate having a plurality of mutually isolated active regions and isolation structures formed therein; Multiple gate structures are distributed on the semiconductor substrate, wherein the multiple gate structures are spaced apart in a first direction and in a second direction, and each gate structure is located on a single active region or isolation structure.

2. The semiconductor device according to claim 1, characterized in that, The adjacent active regions are isolated by the isolation structure, and the active regions extend along a first direction; The gate structure extends along a second direction, wherein, in the second direction, the gate structures in the same column are spaced apart, and the first direction and the second direction are perpendicular.

3. The semiconductor device according to claim 2, characterized in that, In the second direction, each of the gate structures is connected to a corresponding active region, and adjacent gate structures are separated by an isolation layer, wherein each of the gate structures and the corresponding active region have a first overlapping portion, the first overlapping portion covering at least a portion of the gate structure.

4. The semiconductor device according to claim 3, characterized in that, In the first direction, there are multiple gate structures on the same active region, and the multiple gate structures are spaced apart.

5. The semiconductor device according to claim 2, characterized in that, In the second direction, each of the gate structures is connected to a corresponding isolation structure, and adjacent gate structures are separated by an isolation layer, wherein each of the gate structures and the corresponding isolation structure have a second overlapping portion, the second overlapping portion covering at least a portion of the gate structure.

6. The semiconductor device according to claim 5, characterized in that, In the first direction, there are multiple gate structures on the same isolation structure, and the multiple gate structures are spaced apart.

7. The semiconductor device according to claim 3 or 5, characterized in that, The isolation layer is located in the cutting channel.

8. A method for manufacturing a semiconductor device, characterized in that, include: A semiconductor substrate is provided in which a plurality of mutually isolated active regions and isolation structures are formed; Multiple gate structures are formed and distributed on the semiconductor substrate, wherein the multiple gate structures are spaced apart in a first direction and in a second direction, and each gate structure is located on a single active region or isolation structure.

9. The manufacturing method according to claim 8, characterized in that, The formation of the gate structure includes: A gate material layer is formed on the semiconductor substrate, the gate material layer extending along a second direction, wherein, in a first direction, a plurality of the gate material layers are spaced apart; At least a portion of multiple regions of the gate material layer in the same column is removed to form a plurality of gate structures in the second direction, wherein adjacent gate structures are spaced apart in the second direction, and each gate structure is located on a corresponding active region or isolation structure.

10. The manufacturing method according to claim 9, characterized in that, Removing at least a portion of multiple regions of the gate material layer in the same column to form multiple gate structures in the second direction includes: At least a portion of the gate material layer in the same column located above the isolation structure is removed to form a first groove, and a plurality of gate structures are formed in the second direction, wherein adjacent gate structures are isolated by the first groove in the second direction, and each gate structure is located above a corresponding active region.

11. The manufacturing method according to claim 10, characterized in that, Also includes: An isolation layer is formed to fill the first groove and to contact the isolation structure at the bottom of the first groove, wherein adjacent gate structures are isolated by the isolation layer.

12. The manufacturing method according to claim 9, characterized in that, Removing at least a portion of multiple regions of the gate material layer in the same column to form multiple gate structures in the second direction includes: At least a portion of the gate material layer in the same column located above the active region is removed to form a second groove, and a plurality of gate structures are formed in the second direction, wherein adjacent gate structures are isolated by the second groove in the second direction, and each gate structure is located above a corresponding isolation structure.

13. The manufacturing method according to claim 12, characterized in that, Also includes: An isolation layer is formed to fill the second groove and to contact the active region at the bottom of the second groove, wherein adjacent gate structures are isolated by the isolation layer.

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