Semiconductor device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor device and a manufacturing method thereof. The device includes a first field effect transistor and a second field effect transistor disposed on a support substrate. The first field effect transistor and the second field effect transistor include a plurality of channel layers, source / drain layers, and gate stacks stacked apart from each other in a vertical direction. The source / drain layers are in contact with the plurality of channel layers on opposite sides of the plurality of channel layers in a first direction. The gate stacks extend across the plurality of channel layers in a second direction that intersects the first direction. A buried oxide layer is in contact with a lowermost channel layer of the plurality of channel layers of the first field effect transistor and is between the lowermost channel layer of the first field effect transistor and the support substrate. A gate stack of the second field effect transistor is formed between a lowermost channel layer of the plurality of channel layers of the second field effect transistor and the support substrate, spacing the lowermost channel layer of the second field effect transistor from the support substrate.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] With the continuous development of semiconductor technology, field-effect transistors (FETs), as one of the core components of integrated circuits, face numerous challenges in improving their performance. Therefore, for monolithically integrated multi-transistor devices, designing a transistor structure that can achieve different driving capabilities for each transistor unit in order to meet the differentiated functional requirements of each transistor unit in the integrated circuit has become extremely challenging. Summary of the Invention

[0003] In view of the above problems, this disclosure provides a semiconductor device and a method for manufacturing the same.

[0004] According to a first aspect of the present disclosure, a semiconductor device is provided. The device includes a first field-effect transistor (FET) and a second FET, respectively disposed on a support substrate. Each of the first and second FETs includes a plurality of channel layers, source / drain layers, and a gate stack stacked and spaced apart from each other in a vertical direction. The source / drain layers are located on opposite sides of the plurality of channel layers in a first direction and are in contact with the plurality of channel layers. The gate stack extends along a second direction intersecting the first direction to intersect the plurality of channel layers; a buried oxide layer is located between the lowest channel layer of the first FET and the support substrate, and is adjacent to the lowest channel layer of the first FET. The gate stack of the second FET is formed between the lowest channel layer of the second FET and the support substrate, separating the lowest channel layer of the second FET from the support substrate.

[0005] According to embodiments of this disclosure, the first field-effect transistor is a P-type field-effect transistor and the second field-effect transistor is an N-type field-effect transistor; or the first field-effect transistor is an N-type field-effect transistor and the second field-effect transistor is a P-type field-effect transistor.

[0006] According to embodiments of the present disclosure, the portion of the gate stack between the lowest channel layer of the plurality of channel layers of the second field-effect transistor and the supporting substrate is substantially flush with the buried oxide layer, and the corresponding channel layers of the plurality of channel layers of the first and second field-effect transistors are located at substantially the same height.

[0007] According to embodiments of the present disclosure, the height of the portion of the gate stack between the lowest channel layer of the plurality of channel layers of the second field-effect transistor and the supporting substrate is different from the height of the portion of the gate stack between the plurality of channel layers of the second field-effect transistor.

[0008] According to embodiments of the present disclosure, the first field-effect transistor and the second field-effect transistor each further include a sidewall extending along the sidewall of the gate stack, the sidewall including an inner sidewall adjacent to a plurality of channel layers and a gate sidewall above the inner sidewall, the upper surface of the uppermost inner sidewall being adjacent to the gate sidewall.

[0009] According to a second aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes: providing a substrate including a support substrate, a buried oxide layer on the support substrate, and an SOI layer on the buried oxide layer, and having a first region and a second region for a first field-effect transistor and a second field-effect transistor, respectively; removing the SOI layer and the buried oxide layer in the second region, and forming a first sacrificial layer and a first semiconductor layer on the exposed support substrate; forming an epitaxial layer on the SOI layer and the first semiconductor layer, the epitaxial layer including alternately stacked second sacrificial layers and second semiconductor layers; and forming a first field-effect transistor based on the SOI layer and the epitaxial layer in the first region, and forming a second field-effect transistor based on the first semiconductor layer and the epitaxial layer in the second region, using a full-around-gate nanosheet process.

[0010] According to an embodiment of this disclosure, before removing the SOI layer and the buried oxide layer in the second region, the above method includes: forming a patterned mask layer on the SOI layer in the first region to mask the SOI layer in the first region.

[0011] According to embodiments of the present disclosure, forming a first sacrificial layer and a first semiconductor layer on the exposed support substrate includes: forming a first sacrificial layer substantially flush with the buried oxide layer in the first region on the support substrate in a second region; and forming a first semiconductor layer substantially flush with the SOI layer in the first region on the first sacrificial layer.

[0012] According to embodiments of this disclosure, the SOI layer in the first pattern and the second semiconductor layer in the epitaxial layer are used as multiple channel layers of the first field-effect transistor, and the first semiconductor layer in the second pattern and the second semiconductor layer in the epitaxial layer are used as multiple channel layers of the second field-effect transistor.

[0013] According to embodiments of this disclosure, a first field-effect transistor is formed in a first region based on an SOI layer and an epitaxial layer using a fully surrounding gate nanosheet process, and a second field-effect transistor is formed in a second region based on a first semiconductor layer and an epitaxial layer. The process includes: patterning the SOI layer and epitaxial layer in the first region into a first pattern extending along a first direction and used for the first field-effect transistor; and patterning the first sacrificial layer, the first semiconductor layer, and the epitaxial layer in the second region into a second pattern extending along the first direction and used for the second field-effect transistor; and forming a dummy gate on the epitaxial layer that extends along a second direction intersecting the first direction and intersects with the first and second patterns. Source / drain layers of a first field-effect transistor and a second field-effect transistor are formed on opposite sides of a dummy gate in a first direction. The source / drain layers of the first field-effect transistor are connected to the SOI layer in the first pattern and the second semiconductor layer in the epitaxial layer. The source / drain layers of the second field-effect transistor are connected to the first semiconductor layer in the second pattern and the second semiconductor layer in the epitaxial layer. The dummy gate is removed and the first sacrificial layer and the second sacrificial layer in the epitaxial layer are selectively etched to release the gate space. A gate dielectric layer is formed in the gate space, surrounding multiple channel layers of the first and second field-effect transistors. A gate conductor is formed in the gate space in which the gate dielectric layer is formed.

[0014] According to embodiments of this disclosure, a semiconductor device is provided. The device has a first field-effect transistor (FET) and a second field-effect transistor (FET) disposed on the same supporting substrate. The lowest channel layer of the plurality of channel layers of the first FET is adjacent to a buried oxide layer on the supporting substrate, and the lowest channel layer of the plurality of channel layers of the second FET is spaced apart from the supporting substrate by a gate stack. Therefore, since the bottom surface of the lowest channel layer of the second FET can also be used as a channel layer, the channel width of the second FET is greater than that of the first FET. This allows transistors to be constructed on different structures in a monolithically integrated multi-transistor device according to specific application requirements, achieving different driving capabilities in the first and second FETs. Attached Figure Description

[0015] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0016] Figure 1 The diagram illustrates a top view of a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 2 A schematic diagram illustrating the structure of a first field-effect transistor of a semiconductor device according to an embodiment of the present disclosure along a cross section A-A' is shown.

[0018] Figure 3This schematically illustrates a structural diagram of a second field-effect transistor of a semiconductor device according to an embodiment of the present disclosure along a cross section B-B'.

[0019] Figure 4 A schematic diagram illustrating the structure of a first field-effect transistor of a semiconductor device according to another embodiment of the present disclosure along a cross section A-A' is shown.

[0020] Figure 5 A schematic diagram illustrating the structure of a second field-effect transistor of a semiconductor device according to another embodiment of the present disclosure along a cross section B-B' is shown.

[0021] Figure 6 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown schematically.

[0022] Figures 7-31 The diagrams illustrate the structure of some stages in a method for manufacturing a semiconductor device according to embodiments of the present disclosure. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0024] The endpoints and any values ​​of the ranges disclosed in this disclosure are not limited to the precise ranges or values, and such ranges or values ​​should be understood to include values ​​close to such ranges or values. For numerical ranges, the endpoint values ​​of the various ranges, the endpoint values ​​of the various ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be regarded as specifically disclosed in this disclosure.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0026] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0027] In the description of this disclosure, it should be understood that the terms "longitudinal", "length", "circumferential", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the subsystem or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0028] Similarly, to simplify this disclosure and aid in understanding one or more of the various aspects of the disclosure, in the above description of exemplary embodiments of the present disclosure, various features of the present disclosure are sometimes grouped together in a single embodiment, figure, or description thereof. The use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refers to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the present disclosure. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0029] Figure 1 The diagram illustrates a top view of a semiconductor device according to an embodiment of the present disclosure. Figure 2 The schematic diagram illustrates the structure of a first field-effect transistor of a semiconductor device according to an embodiment of the present disclosure along a cross section A-A'. Figure 3 The schematic diagram illustrates the structure of a second field-effect transistor of a semiconductor device according to an embodiment of the present disclosure along a cross section B-B'. Figure 4 The schematic diagram illustrates the structure of a first field-effect transistor of a semiconductor device according to another embodiment of the present disclosure along a cross section A-A'. Figure 5 A schematic diagram illustrating the structure of a second field-effect transistor of a semiconductor device according to another embodiment of the present disclosure along a cross section B-B' is provided. For ease of description, Figure 1 Only the active regions and gate conductors of the first and second field-effect transistors are shown in the diagram.

[0030] refer to Figures 1-5The semiconductor device in this embodiment may include a first field-effect transistor and a second field-effect transistor respectively disposed on a substrate. The substrate may be a semiconductor-on-insulator (SOI) substrate, including a support substrate 101 and a buried oxide layer 102 on the support substrate 101. A silicon layer may be present on the buried oxide layer 102. The support substrate 101 may be formed of a semiconductor material, such as bulk silicon, and the buried oxide layer 102 may be formed of a semiconductor oxide, such as silicon dioxide. The buried oxide layer 102 may be located between the support substrate 101 and the first field-effect transistor. According to some embodiments, the first and second field-effect transistors may form a complementary metal-oxide-semiconductor (CMOS) configuration. For example, the first field-effect transistor may be a P-channel field-effect transistor (PFET) and the second field-effect transistor may be an N-channel field-effect transistor (NFET), or the first field-effect transistor may be an NFET and the second field-effect transistor may be a PFET.

[0031] refer to Figure 2 and Figure 4 The first field-effect transistor may include a plurality of channel layers, source / drain layers (111A or 111C), and gate stacks stacked and spaced apart from each other in a vertical direction. The plurality of channel layers of the first field-effect transistor may include an SOI layer 103 on a buried oxide layer 102 in a substrate and a plurality of second semiconductor layers 108. The plurality of channel layers of the first field-effect transistor (e.g., SOI layer 103 and second semiconductor layers 108) may include a plurality of nanosheet structures.

[0032] The lowest channel layer of the plurality of channel layers of the first field-effect transistor (SOI layer 103 in this example) may be adjacent to the buried oxide layer 102. The source / drain layers (111A or 111C) of the first field-effect transistor are located on opposite sides of the plurality of channel layers in a first direction and are adjacent to the plurality of channel layers. The gate stack of the first field-effect transistor may extend along a second direction intersecting the first direction, thereby intersecting the plurality of channel layers. The first direction may be... Figure 2 and Figure 4 The horizontal direction on the paper, the second direction can be Figure 2 and Figure 4 The direction perpendicular to the paper (corresponding to) Figure 1 (Vertical direction on the paper).

[0033] refer to Figure 3 and Figure 5 The second field-effect transistor may include a plurality of channel layers, source / drain layers (111B or 111D), and a gate stack stacked and spaced apart from each other in a vertical direction. The plurality of channel layers of the second field-effect transistor may include a first semiconductor layer 106 and a plurality of second semiconductor layers 108. The plurality of channel layers of the second field-effect transistor (e.g., the first semiconductor layer 106 and the second semiconductor layer 108) may include a plurality of nanosheet structures. The source / drain layers (111B or 111D) of the second field-effect transistor are located on opposite sides of the plurality of channel layers in a first direction and are in contact with the plurality of channel layers.

[0034] The gate stack of the second field-effect transistor can extend along a second direction intersecting the first direction, thereby intersecting with multiple channel layers. The first direction can be... Figure 3 and Figure 5 The horizontal direction on the paper, the second direction can be Figure 3 and Figure 5 The direction perpendicular to the paper (corresponding to) Figure 1 (Vertical direction on the paper). The lowest channel layer of the plurality of channel layers of the second field-effect transistor (in this example, the first semiconductor layer 106) may be spaced apart from the support substrate 101, and the gate stack of the second field-effect transistor may pass between the lowest channel layer of the plurality of channel layers of the second field-effect transistor (e.g., the first semiconductor layer 106) and the support substrate 101. The gate stack of the second field-effect transistor may be adjacent to the support substrate 101.

[0035] Continue to refer to Figures 2-5 The gate stack may include a gate dielectric layer 113 and a gate conductor 114. The gate dielectric layer 113 may include a high-k dielectric material layer, and the gate conductor 114 may include a work function layer and a metal layer. Here, although the first field-effect transistor and the second field-effect transistor are shown to have the same gate stack structure, they may have different gate stack structures, such as different work function layers.

[0036] In addition, Figure 1 The first and second field-effect transistors are shown as being adjacent to each other in a second direction and their respective gate stacks aligned with each other and extending continuously in the second direction. However, this disclosure is not limited thereto. The layout of the first and second field-effect transistors can be varied according to the device design, and their respective gate stacks can be separated from each other.

[0037] According to embodiments of this disclosure, a semiconductor device is provided. The device has a first field-effect transistor (FET) and a second field-effect transistor (FET) disposed on the same supporting substrate. The lowest channel layer of the plurality of channel layers of the first FET is adjacent to a buried oxide layer on the supporting substrate, and the lowest channel layer of the plurality of channel layers of the second FET is spaced apart from the supporting substrate by a gate stack. Therefore, since the bottom surface of the lowest channel layer of the second FET can also be used as a channel layer, the channel width of the second FET is greater than that of the first FET. This allows transistors to be constructed on different structures in a monolithically integrated multi-transistor device according to specific application requirements, thereby achieving different driving capabilities in the first and second FETs.

[0038] In some embodiments, the gate stack is located in the lowest channel layer of the plurality of channel layers of the second field-effect transistor (e.g., Figure 3 and Figure 5 The portion between the first semiconductor layer 106 and the supporting substrate 101 can be connected to the buried oxide layer 102 (such as... Figure 2 and Figure 4 (As shown in the diagram) The vertical heights can be substantially the same. For example, they can be substantially flush. The corresponding channel layers in the plurality of channel layers of the first and second field-effect transistors can be located at substantially the same height. For example, the lowest channel layer of the plurality of channel layers of the first field-effect transistor and the lowest channel layer of the plurality of channel layers of the second field-effect transistor can be located at substantially the same height, for example, they are substantially coplanar; the second channel layer from bottom to top in the plurality of channel layers of the first field-effect transistor and the second channel layer from bottom to top in the plurality of channel layers of the second field-effect transistor can be located at substantially the same height, for example, they are substantially coplanar; and so on.

[0039] Continue to refer to Figure 3 and Figure 5 The height of the portion of the gate stack between the lowest channel layer (in this example, the first semiconductor layer 106) of the plurality of channel layers of the second field-effect transistor and the supporting substrate 101 may differ from the height of the portion of the gate stack between the plurality of channel layers of the second field-effect transistor. For example, if the height of the buried oxide layer is greater than the height of the epitaxially grown second sacrificial layer, the height of the portion between the lowest channel layer of the plurality of channel layers of the second field-effect transistor and the supporting substrate may be greater than the height of the portion between the plurality of channel layers of the second field-effect transistor; if the height of the buried oxide layer is less than the height of the epitaxially grown second sacrificial layer, the height of the portion between the lowest channel layer of the plurality of channel layers of the second field-effect transistor and the supporting substrate may be less than the height of the portion between the plurality of channel layers of the second field-effect transistor.

[0040] In some embodiments, the first field-effect transistor and the second field-effect transistor may each further include a sidewall extending along the sidewalls of the gate stack. The sidewall may include an inner sidewall 110B adjacent to the plurality of channel layers and a gate sidewall 110A above the inner sidewall 110B, the upper surface of the uppermost inner sidewall of the inner sidewall 110B being adjacent to the gate sidewall 110A. The sidewall may include a nitride such as silicon nitride.

[0041] According to some embodiments, for example, referencing Figure 2 and Figure 3 The source / drain layer 111A of the first field-effect transistor comprises germanium-silicon, and the source / drain layer 111B of the second field-effect transistor comprises silicon. The source / drain layer 111A of the first field-effect transistor can be doped, and the doping material can include a P-type dopant such as boron. The source / drain layer 111B of the second field-effect transistor can be doped, and the doping material can include an N-type dopant such as phosphorus.

[0042] According to other embodiments, for example, referencing Figure 4 and Figure 5 The first field-effect transistor has a source / drain layer 111C comprising silicon, and the second field-effect transistor has a source / drain layer 111D comprising germanium-silicon. The source / drain layer 111C of the first field-effect transistor can be doped, and the doping material can include an N-type dopant such as phosphorus. The source / drain layer 111D of the second field-effect transistor can be doped, and the doping material can include a P-type dopant such as boron.

[0043] In some embodiments, the semiconductor device may further include an interlayer dielectric layer 112 on the first field-effect transistor and the second field-effect transistor, and a contact plug 115 that penetrates the interlayer dielectric layer 112 and electrically connects the source / drain layer of the first field-effect transistor, the source / drain layer of the second field-effect transistor, and the gate stack.

[0044] The method of manufacturing a semiconductor device according to embodiments of the present disclosure will be described in more detail below with reference to examples.

[0045] Figure 6 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown schematically.

[0046] like Figure 6 As shown, the manufacturing method of this embodiment may include operations S610 to S640.

[0047] In operation S610, a substrate is provided, the substrate including a support substrate, a buried oxide layer on the support substrate and an SOI layer on the buried oxide layer, and having a first region and a second region for the first field-effect transistor and the second field-effect transistor, respectively.

[0048] In operation S620, in the second region, the SOI layer and buried oxide layer are removed, and a first sacrificial layer and a first semiconductor layer are formed on the exposed support substrate.

[0049] In operation S630, an epitaxial layer is formed on the SOI layer and the first semiconductor layer.

[0050] In some embodiments, the epitaxial layer may include an alternately stacked second sacrificial layer and a second semiconductor layer.

[0051] In operation S640, a first field-effect transistor is formed in a first region based on an SOI layer and an epitaxial layer using a fully surrounding gate nanosheet process, and a second field-effect transistor is formed in a second region based on a first semiconductor layer and an epitaxial layer.

[0052] To better understand the manufacturing method of the semiconductor device of this disclosure, the following is based on schematic diagrams of the structure obtained during the manufacturing process of the semiconductor device according to the embodiments of this disclosure, combined with... Figures 1-5 , Figures 7-31 The manufacturing method of the embodiments of this disclosure will be described below.

[0053] Figures 7-31 The diagrams schematically illustrate some stages of a method for manufacturing a semiconductor device according to embodiments of the present disclosure. It should be noted that... Figure 7 , Figure 9 , Figure 23 A top view of a semiconductor device according to an embodiment of the present disclosure at certain stages is shown as a structural schematic diagram; Figure 8 The diagram shows a schematic representation of the structure of a semiconductor device according to embodiments of the present disclosure along some stages of a cross section A-A' or B-B'. Figure 10 , Figure 13 , Figure 15 , Figure 17 , Figure 19 , Figure 21 , Figure 24 , Figure 26 , Figure 28 and Figure 30 Schematic diagrams of the structure of a first field-effect transistor of a semiconductor device according to an embodiment of the present disclosure are shown at some stages along cross section A-A'. Figure 11 , Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 、and 25、 Figure 27 , Figure 29 and Figure 31 Schematic diagrams of the structure of a second field-effect transistor of a semiconductor device according to an embodiment of the present disclosure are shown at some stages along the B-B' cross section.

[0054] It should be noted that the following description of the manufacturing method of the first field-effect transistor being a PFET and the second field-effect transistor being an NFET in a semiconductor device is merely an example. Those skilled in the art can set the first field-effect transistor to an NFET and the second field-effect transistor to a PFET based on their needs. Alternatively, the first field-effect transistor and the second field-effect transistor can be set to the same type, such as an NFET or a PFET. This disclosure will not elaborate further.

[0055] refer to Figure 7 and Figure 8 A substrate may be provided. The substrate may be an SOI substrate, including a support substrate 101, a buried oxide layer 102, and an SOI layer 103. The substrate may be pretreated by cleaning or other pretreatment operations, and active regions may be defined on the substrate by, for example, shallow trench isolation (STI), such as a first region S1 for a first field-effect transistor and a second region S2 for a second field-effect transistor.

[0056] refer to Figure 9 and Figure 10 A patterned mask layer 104 can be formed on the SOI layer 103 in the first region S1 to block the first region S1 used for the first field-effect transistor.

[0057] refer to Figure 9 and Figure 11 Within the second region S2, the buried oxide layer 102 and the SOI layer 103 can be etched away, and the etching stops at the supporting substrate 101.

[0058] A first sacrificial layer 105 and a first semiconductor layer 106 may be formed on the support substrate 101 exposed in the second region S2. For example, the material of the first sacrificial layer 105 may be SiGe, and the material of the first semiconductor layer 106 may be silicon.

[0059] For example, refer to Figure 12 In the second region, a first sacrificial layer 105 can be epitaxially grown on the support substrate 101. The first sacrificial layer 105 can be substantially flush with the buried oxide layer 102 in the first region. A first semiconductor layer 106 can be epitaxially grown on the first sacrificial layer 105. The first semiconductor layer 106 can be substantially flush with the SOI layer 103 in the first region, thereby making the lowest channel layer (SOI layer 103) of the plurality of channel layers of the first field-effect transistor substantially flush with the lowest channel layer (first semiconductor layer 106) of the plurality of channel layers of the second field-effect transistor.

[0060] Then, an epitaxial layer can be formed on the SOI layer 103 and the first semiconductor layer 106 using an epitaxial growth process. Before performing epitaxial growth, the mask layer 104 on the SOI layer 103 in the first region can be removed.

[0061] For example, refer to Figure 13 and Figure 14 Epitaxial layers can be formed on the SOI layer 103 and the first semiconductor layer 106. The epitaxial layers may include alternately grown second sacrificial layers 107 and second semiconductor layers 108. For example, the material of the second sacrificial layer 107 may be SiGe, and the material of the second semiconductor layer 108 may be silicon. The thickness of the epitaxially grown second semiconductor layer 108 may be substantially the same as the thickness of the first semiconductor layer 106, thereby allowing the respective channel layers of the first field-effect transistor and the respective channel layers of the second field-effect transistor to be located at substantially the same height.

[0062] The SOI layer 103 and the epitaxial layer can be patterned in a first region as a first pattern for a first field-effect transistor, and the first semiconductor layer 106 and the epitaxial layer can be patterned in a second region as a second pattern for a second field-effect transistor.

[0063] For example, the SOI layer 103 and the epitaxial layer, as well as the first semiconductor layer 106 and the epitaxial layer, can be patterned along a first direction ( Figure 13 and Figure 14 A fin-like pattern extending horizontally on the paper surface. The patterning of the SOI layer 103 and the epitaxial layer can stop at the buried oxide layer 102. The patterning of the first semiconductor layer 106 and the epitaxial layer can stop at the supporting substrate 101.

[0064] refer to Figure 15 and Figure 16 A dummy gate 109 and gate sidewalls 110A can be formed on the epitaxial layer. A dummy gate material and a mask material (not shown in the figure) can be deposited on the epitaxial layer, and the dummy gate 109 is formed using photolithography based on a patterned mask. The dummy gate 109 can be formed along a second direction ( Figure 15 and Figure 16 The dummy gate 109 extends in a direction perpendicular to the plane of the paper. The material of the dummy gate 109 can be polycrystalline silicon or amorphous silicon, etc. Gate sidewalls 110A can be formed on the sidewalls of the dummy gate 109 using a sidewall forming process. The material of the gate sidewalls 110A can be a nitride such as silicon nitride, etc.

[0065] refer to Figure 17 The second sacrificial layer 107 and the second semiconductor layer 108 in the epitaxial layer and the SOI layer 103 in the substrate can be etched according to the pattern of the dummy gate 109 and the gate sidewall 110A. The etching can stop at the buried oxide layer 102, thereby exposing the side surfaces of the SOI layer 103 on the buried oxide layer 102 and the second sacrificial layer 107 and the second semiconductor layer 108 in the epitaxial layer, respectively, in a first direction. The first direction can be the horizontal direction in the plane of the paper.

[0066] Similarly, refer to Figure 18The second sacrificial layer 107, the second semiconductor layer 108, the first semiconductor layer 106, and the first sacrificial layer 105 in the epitaxial layer can be etched according to the pattern of the dummy gate 109 and the gate sidewall 110A. Etching can stop at the support substrate 101, thereby exposing the side surfaces of the first sacrificial layer 105, the first semiconductor layer 106, and the second sacrificial layer 107 and the second semiconductor layer 108 in the epitaxial layer, respectively, in a first direction located on the support substrate 101. The first direction can be a horizontal direction in the plane of the paper.

[0067] refer to Figure 17 Described etching process and reference Figure 18 The etching process described can be performed simultaneously using the same etching technique.

[0068] Therefore, the SOI layer 103 and the epitaxial layer can be patterned into a first pattern for the first field-effect transistor in the first region, and the first semiconductor layer 106 and the epitaxial layer can be patterned into a second pattern for the second field-effect transistor in the second region.

[0069] According to some embodiments, such as reference Figure 19 and Figure 20 By utilizing the etch selectivity ratio of the second sacrificial layer 107 and the second semiconductor layer 108, as well as the first sacrificial layer 105 and the first semiconductor layer 106, through the exposed side surface, the first sacrificial layer 105 and the second sacrificial layer 107 can be selectively etched, such that the ends of the first sacrificial layer 105 and the second sacrificial layer 107 in the first direction are recessed relative to the first semiconductor layer 106 and the second semiconductor layer 108. Based on this, the space released by the selective etching of the first sacrificial layer 105 and the second sacrificial layer 107 can be filled with dielectric material to form an inner sidewall 110B, as... Figure 21 and Figure 22 As shown. The material of the inner wall 110B can be a nitride such as silicon nitride.

[0070] The source / drain layers of the first and second field-effect transistors can be formed respectively.

[0071] For example, refer to Figure 23 and Figure 24 Based on the first pattern, source / drain materials can be epitaxially grown on the sidewalls of the SOI layer 103 and the second semiconductor layer 108 in the epitaxial layer, thereby forming the source / drain layer 111A of the first field-effect transistor. The material of the source / drain layer 111A of the first field-effect transistor can be SiGe, etc. The source / drain layer 111A of the first field-effect transistor can be in-situ doped to form a doped source / drain layer 111A of the first field-effect transistor. The doping material can be boron, etc. (Reference) Figure 23 and Figure 25Based on the second pattern, source / drain materials can be epitaxially grown on the sidewalls of the second semiconductor layer 108 in the first semiconductor layer 106 and the epitaxial layer, thereby forming the source / drain layer 111B of the second field-effect transistor. The material of the source / drain layer 111B of the second field-effect transistor can be Si or the like. The source / drain layer 111B of the second field-effect transistor can be in-situ doped to form a doped source / drain layer 111B of the second field-effect transistor. The doping material can be phosphorus or the like. In addition, the source / drain layer 111A of the first field-effect transistor and the source / drain layer 111B of the second field-effect transistor can be activated by annealing or the like.

[0072] The formation order of the source / drain layer 111A of the first field-effect transistor and the source / drain layer 111B of the second field-effect transistor can be interchanged. When processing a region of the first field-effect transistor, the region of the second field-effect transistor can be shielded; and vice versa. Furthermore, the source / drain layer 111A of the first field-effect transistor and the source / drain layer 111B of the second field-effect transistor are not limited to being formed separately, but can also be formed simultaneously (thus, they can both have the same material).

[0073] refer to Figure 26 and Figure 27 An interlayer dielectric layer 112, such as SiO2, can be formed to shield the source / drain layer 111A of the first field-effect transistor and the source / drain layer 111B of the second field-effect transistor. For example, a dielectric material can be deposited on a substrate, and then the deposited dielectric material can be planarized, such as by chemical mechanical polishing (CMP), to obtain the interlayer dielectric layer 112. The planarization process can stop at the gate sidewall 110A and can expose the dummy gate 109.

[0074] The dummy gate, the first sacrificial layer, and the second sacrificial layer can be removed to free up gate space.

[0075] For example, refer to Figure 28 and Figure 29 The dummy gate 109 on the first and second patterns can be removed using a reverse etching process, forming an opening on the inner side of the gate sidewall 110A. Then, the second sacrificial layer 107 in the epitaxial layer of the first pattern, as well as the first sacrificial layer 105 and the second sacrificial layer 107 in the second pattern, can be selectively etched, thereby freeing up space on the inner sidewall 110B at the original locations of the first and second sacrificial layers 105 and 107. The space freed up by the removal of the dummy gate 109, the first sacrificial layer 105, and the second sacrificial layer 107 is subsequently used to form a gate stack and is therefore referred to hereinafter as the gate space.

[0076] Continue to refer to Figure 28 and Figure 29In the first pattern, the SOI layer 103 and the second semiconductor layer 108 serve as multiple channel layers of the first field-effect transistor, and in the second pattern, the first semiconductor layer 106 and the second semiconductor layer 108 serve as multiple channel layers of the second field-effect transistor.

[0077] refer to Figure 30 and Figure 31 A gate stack can be formed around multiple channel layers in the gate space. The gate stack may include a gate dielectric layer 113 and a gate conductor 114. The gate dielectric layer 113 may include a high-k dielectric material layer, and the gate conductor 114 may include a work function layer and a metal layer.

[0078] Return to reference Figures 1-3 Dielectric materials such as SiO2 can be deposited on the gate stack. The deposited dielectric material and the previous interlayer dielectric layer 112 can together form an interlayer dielectric layer (still referred to as 112 here), and can form a contact plug 115 that penetrates the interlayer dielectric layer 112 and electrically connects the source / drain layer 111A of the first field-effect transistor, the source / drain layer 111B of the second field-effect transistor, and the gate stack. Figures 1-3 As shown, the first field-effect transistor includes multiple channel layers (SOI layer 103 and second semiconductor layer 108) in a first pattern, source / drain layer 111A and corresponding gate stack, and the second field-effect transistor includes multiple channel layers (first semiconductor layer 106 and second semiconductor layer 108) in a second pattern, source / drain layer 111B and corresponding gate stack.

[0079] Those skilled in the art will understand that the features described in the various embodiments of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0080] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A first field-effect transistor and a second field-effect transistor are respectively disposed on a support substrate, wherein the first field-effect transistor and the second field-effect transistor each include: a plurality of channel layers stacked at intervals in a vertical direction; source / drain layers located on opposite sides of the plurality of channel layers in a first direction and connected to the plurality of channel layers; and a gate stack extending along a second direction intersecting the first direction to intersect the plurality of channel layers. A buried oxide layer is located between the lowest channel layer of the plurality of channel layers of the first field-effect transistor and the supporting substrate, the buried oxide layer being adjacent to the lowest channel layer of the plurality of channel layers of the first field-effect transistor. The gate stack of the second field-effect transistor is formed between the lowest channel layer of the plurality of channel layers of the second field-effect transistor and the supporting substrate, thereby separating the lowest channel layer of the plurality of channel layers of the second field-effect transistor from the supporting substrate.

2. The semiconductor device according to claim 1, characterized in that, The first field-effect transistor is a P-type field-effect transistor, and the second field-effect transistor is an N-type field-effect transistor; or The first field-effect transistor is an N-type field-effect transistor, and the second field-effect transistor is a P-type field-effect transistor.

3. The semiconductor device according to claim 2, characterized in that, The portion of the gate stack between the lowest channel layer of the plurality of channel layers of the second field-effect transistor and the supporting substrate is substantially flush with the buried oxide layer, wherein the corresponding channel layers of the plurality of channel layers of the first field-effect transistor and the second field-effect transistor are located at substantially the same height.

4. The semiconductor device according to claim 3, characterized in that, The height of the portion of the gate stack between the lowest channel layer of the plurality of channel layers of the second field-effect transistor and the supporting substrate is different from the height of the portion of the gate stack between the plurality of channel layers of the second field-effect transistor.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The first field-effect transistor and the second field-effect transistor each further include a sidewall extending along the sidewall of the gate stack, the sidewall including an inner sidewall adjacent to the plurality of channel layers and a gate sidewall above the inner sidewall, the upper surface of the uppermost inner sidewall being adjacent to the gate sidewall.

6. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, the substrate comprising a support substrate, a buried oxide layer on the support substrate and an SOI layer on the buried oxide layer, and having a first region and a second region for a first field-effect transistor and a second field-effect transistor, respectively; In the second region, the SOI layer and the buried oxide layer are removed, and a first sacrificial layer and a first semiconductor layer are formed on the exposed support substrate. An epitaxial layer is formed on the SOI layer and the first semiconductor layer, the epitaxial layer comprising an alternately stacked second sacrificial layer and a second semiconductor layer; Using a fully encircling gate nanosheet process, the first field-effect transistor is formed in the first region based on the SOI layer and the epitaxial layer, and the second field-effect transistor is formed in the second region based on the first semiconductor layer and the epitaxial layer.

7. The manufacturing method according to claim 6, characterized in that, Before removing the SOI layer and the buried oxide layer in the second region, the method includes: Within the first region, a patterned mask layer is formed on the SOI layer to mask the SOI layer in the first region.

8. The manufacturing method according to claim 6, characterized in that, The formation of the first sacrificial layer and the first semiconductor layer on the exposed support substrate includes: In the second region, a first sacrificial layer is formed on the supporting substrate that is substantially flush with the buried oxide layer in the first region; A first semiconductor layer is formed on the first sacrificial layer, which is substantially flush with the SOI layer in the first region.

9. The manufacturing method according to claim 6, characterized in that, The SOI layer in the first region and the second semiconductor layer in the epitaxial layer are used as multiple channel layers of the first field-effect transistor, and the first semiconductor layer in the second region and the second semiconductor layer in the epitaxial layer are used as multiple channel layers of the second field-effect transistor.

10. The manufacturing method according to claim 8, characterized in that, The method of forming a first field-effect transistor in the first region based on the SOI layer and the epitaxial layer using a fully surrounding gate nanosheet process, and forming a second field-effect transistor in the second region based on the first semiconductor layer and the epitaxial layer, includes: The SOI layer and the epitaxial layer in the first region are patterned into a first pattern extending along a first direction and used for the first field-effect transistor, and the first sacrificial layer, the first semiconductor layer and the epitaxial layer in the second region are patterned into a second pattern extending along a first direction and used for the second field-effect transistor. A dummy gate is formed on the epitaxial layer, extending along a second direction that intersects the first direction and intersects the first pattern and the second pattern; Source / drain layers of the first field-effect transistor and the second field-effect transistor are formed on opposite sides of the dummy gate in the first direction, respectively. The source / drain layer of the first field-effect transistor is connected to the SOI layer in the first pattern and the second semiconductor layer in the epitaxial layer. The source / drain layer of the second field-effect transistor is connected to the first semiconductor layer in the second pattern and the second semiconductor layer in the epitaxial layer. Remove the dummy gate and selectively etch the first sacrificial layer and the second sacrificial layer in the epitaxial layer to release the gate space; A gate dielectric layer is formed within the gate space, the gate dielectric layer surrounding a plurality of channel layers of the first field-effect transistor and the second field-effect transistor; A gate conductor is formed within the gate space where the gate dielectric layer is formed.

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