Semiconductor device and contact structure

Abstract

A semiconductor device and a contact structure are provided. The semiconductor device includes a first source / drain pattern located on a substrate and disposed at a first height in a substantially vertical direction, a first channel pattern connected to the first source / drain pattern, a second source / drain pattern disposed at a second height higher than the first height, a second channel pattern connected to the second source / drain pattern, a gate electrode located on the first channel pattern and the second channel pattern, and a contact substantially perpendicularly connected to at least one of the first source / drain pattern and the second source / drain pattern. The contact can be disposed in a bottleneck shape having a diameter at the second height smaller than a diameter at a height other than the second height.

Description

Technical Field

[0001] Embodiments of this disclosure relate to semiconductor devices and methods of manufacturing the semiconductor devices, and more specifically, to semiconductor devices including field-effect transistors and methods of manufacturing the semiconductor devices. Background Technology

[0002] Semiconductor devices include integrated circuits, which include metal-oxide-semiconductor field-effect transistors (MOSFETs). As the size and design rules of semiconductor devices continue to miniaturize, the miniaturization of MOSFETs is also accelerating. Reducing the size of MOSFETs can degrade the operating characteristics of semiconductor devices. Therefore, ongoing research is underway into various methods to form semiconductor devices with improved performance while mitigating the problems caused by the high integration density of semiconductor devices. Summary of the Invention

[0003] Embodiments of this disclosure provide a field-effect transistor semiconductor device configured to provide stable performance and improved reliability.

[0004] According to one or more embodiments, a semiconductor device includes: a first source / drain pattern located on a substrate and disposed at a first height in a substantially vertical direction; a first channel pattern connected to the first source / drain pattern; a second source / drain pattern disposed at a second height above the first height; a second channel pattern connected to the second source / drain pattern; a gate electrode located on the first channel pattern and the second channel pattern; and a contact substantially vertically connected to at least one of the first source / drain pattern and the second source / drain pattern. The contact may be configured in a bottleneck shape, the diameter of which at the second height is smaller than its diameter at heights other than the second height.

[0005] According to one or more embodiments, a contact structure includes: a first source / drain pattern; a second source / drain pattern stacked on the first source / drain pattern; and a contact penetrating the second source / drain pattern and disposed in a groove recessed from the upper surface of the first source / drain pattern. The contact may be configured as a bottleneck structure having a first diameter at the height of the first source / drain pattern and a second diameter smaller than the first diameter at the height of the second source / drain pattern.

[0006] According to one or more embodiments, a semiconductor device includes: a first transistor disposed on a substrate and including a first source / drain pattern; a second transistor stacked on the first transistor and including a second source / drain pattern overlapping the first source / drain pattern; and a contact disposed substantially perpendicular to the first source / drain pattern and the second source / drain pattern. The second source / drain pattern may include: a first epitaxial layer having a first impurity concentration; a second epitaxial layer having a second impurity concentration higher than the first impurity concentration; and a third epitaxial layer protruding inwards from the contact and having a third impurity concentration higher than the first impurity concentration. The diameter of the contact in the region where the third epitaxial layer is disposed may be smaller than the diameter in other regions adjacent to the third epitaxial layer.

[0007] According to one or more embodiments, a method of manufacturing a semiconductor device includes: forming a first source / drain pattern on a substrate at a first height in a substantially vertical direction; forming a second source / drain pattern, wherein the second source / drain pattern is disposed at a second height above the first height and perpendicularly overlaps with the first source / drain pattern; and forming a contact, wherein the contact is substantially perpendicularly connected to at least one of the first source / drain pattern and the second source / drain pattern. The contact may be formed in a bottleneck shape, the diameter of which at the second height is smaller than its diameter at heights other than the second height.

[0008] The formation of the contact may include a first contact formation operation in which the contact is formed in the first source / drain pattern. The first contact formation operation may include: forming a groove in a substantially vertical direction within the first source / drain pattern and the second source / drain pattern; forming a first sacrificial insulating layer within the groove; removing a portion of the first sacrificial insulating layer to form a second sacrificial insulating layer exposing a side surface of the second source / drain pattern; forming an epitaxial layer protruding inward from the side surface of the second source / drain pattern in a substantially horizontal direction toward the inside of the groove; removing the second sacrificial insulating layer; and forming a conductive material within the groove.

[0009] The thickness of the first sacrificial insulating layer on the first source / drain pattern can be greater than the thickness of the first sacrificial insulating layer on the second source / drain pattern.

[0010] Removing a portion of the first sacrificial insulation layer may include removing the first sacrificial insulation layer on the second source / drain pattern.

[0011] The portion of the first sacrificial insulating layer can be removed by dry etching.

[0012] The method may also include forming an ohmic contact layer on the protruding epitaxial layer.

[0013] The conductive material can be formed within the groove by chemical vapor deposition.

[0014] The method may further include a second contact forming operation to form the contact in the second source / drain pattern. The second contact forming operation may include forming an additional groove in a substantially vertical direction within the second source / drain pattern and forming a conductive material within the additional groove.

[0015] The method may further include a second contact formation operation to form the contact in the second source / drain contact. The second contact formation operation may include forming an epitaxial layer that protrudes horizontally from the side surface of the second source / drain pattern toward the inside of the groove, and forming a conductive material within the groove.

[0016] The method may further include forming a first channel pattern and a second channel pattern that are substantially perpendicularly overlapping on the substrate, and forming a gate electrode on the first channel pattern and the second channel pattern. Attached Figure Description

[0017] Figure 1 It is a plan view of a semiconductor device according to one or more embodiments.

[0018] Figure 2A It is along Figure 1 A cross-sectional view taken from line A-A', and Figure 2B It is along Figure 1 A cross-sectional view taken from the B-B' line.

[0019] Figure 3 It is a portion of a cross-sectional view showing a single contact, and is Figure 2A A magnified cross-sectional view of part P1.

[0020] Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A, Figure 14B , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 and Figure 21 It is a view that sequentially illustrates methods of manufacturing a semiconductor device according to one or more embodiments. Detailed Implementation

[0021] The following description, with reference to the accompanying drawings, is provided to aid in a comprehensive understanding of the various embodiments of this disclosure.

[0022] Figure 1 This is a plan view illustrating a semiconductor device according to one or more embodiments. Figure 2A It is along Figure 1 A cross-sectional view taken from line A-A', and Figure 2B It is along Figure 1 A cross-sectional view taken from the B-B' line.

[0023] refer to Figure 1 , Figure 2A and Figure 2B The semiconductor device may include: a plurality of active patterns AP that protrude from the substrate 100 in a vertical direction (third direction DR3) and extend in a first horizontal direction (first direction DR1); a first transistor TR1 located on the active patterns AP and disposed at a first vertical height; and a second transistor TR2 located on the active patterns AP and disposed at a second vertical height above the first vertical height. The first transistor TR1 and the second transistor TR2 may be configured to overlap each other in the vertical direction (e.g., third direction DR3). The second direction DR2, not described herein, is a direction perpendicular to both the first direction DR1 and the third direction DR3. The term "height" as used in this disclosure refers to the distance from the upper surface of the substrate 100 in the vertical direction (third direction DR3 or the direction opposite to third direction DR3).

[0024] Substrate 100 may include semiconductors such as Si or Ge, or compound semiconductors such as SiGe, SiC, GaAs, InAs, InGaAs, or InP. As used herein, the terms “SiGe,” “SiC,” “GaAs,” “InAs,” “InGaAs,” and “InP” refer to materials composed of elements included in the respective terms and are not chemical formulas indicating stoichiometric relationships.

[0025] The first channel pattern CH1 and the second channel pattern CH2, which provide the channel regions for the first transistor TR1 and the second transistor TR2, can be set on the active pattern AP.

[0026] The first transistor TR1 may include: a plurality of first channel patterns CH1 disposed on an active pattern AP; a pair of first source / drain patterns SD1 disposed on opposite sides of the first channel patterns CH1 and in contact with each first channel pattern CH1; and a first gate electrode GE1 disposed on the first channel pattern CH1. The pair of first source / drain patterns SD1 constituting the first transistor TR1 may each fill a second recess RC2 formed on the active pattern AP. The first channel pattern CH1 may be disposed at a first separation distance directly above the upper surface of the active pattern AP. The first gate electrode GE1 may surround each of the corresponding semiconductor patterns S1 and S2 within the first channel pattern CH1.

[0027] The second transistor TR2 may include: a plurality of second channel patterns CH2 arranged vertically upwards in a second direction DR2 from the upper surface of the active pattern AP (on the third direction DR3) at a second separation distance greater than a first separation distance; a pair of second source / drain patterns SD2 disposed on opposite sides of the second channel patterns CH2 and in contact with each of the second channel patterns CH2; and a second gate electrode GE2 disposed on the second channel pattern CH2. The second channel patterns CH2 may be spaced apart from the upper surface of the active pattern AP in the vertical direction (e.g., on the third direction DR3), with a first channel pattern CH1 located between the second channel pattern CH2 and the active pattern AP. The pair of second source / drain patterns SD2 may overlap with the first source / drain pattern SD1 in the vertical direction (e.g., on the third direction DR3). The second source / drain pattern SD2 may be spaced apart from the active pattern AP in a vertical direction (e.g., on the third direction DR3), and the first source / drain pattern SD1 is located between the second source / drain pattern SD2 and the active pattern AP. The second gate electrode GE2 may surround each of the corresponding semiconductor patterns S1 and S2 within the second channel pattern CH2.

[0028] In one or more embodiments, a first gate electrode GE1 and a second gate electrode GE2 that overlap each other perpendicularly can be connected to form a single gate electrode GE.

[0029] The minimum separation distance in the vertical direction (e.g., on the third direction DR3) between the first channel pattern CH1 and the second channel pattern CH2 can be greater than the minimum separation distance between the plurality of first semiconductor patterns S1 and S2 included in the first channel pattern CH1. The minimum separation distance in the vertical direction (e.g., on the third direction DR3) between the first channel pattern CH1 and the second channel pattern CH2 can be greater than the minimum separation distance between the plurality of second semiconductor patterns S1 and S2 included in the second channel pattern CH2.

[0030] The first source / drain pattern SD1 and the second source / drain pattern SD2 may each include an epitaxially grown semiconductor layer.

[0031] In one or more embodiments, one of the first transistor TR1 and the second transistor TR2 may be an N-type metal-oxide-semiconductor (NMOS) field-effect transistor, and the other of the first transistor TR1 and the second transistor TR2 may be a P-type metal-oxide-semiconductor (PMOS) field-effect transistor. In an example embodiment, the first transistor TR1 may be a PMOS field-effect transistor. In an example embodiment, the second transistor TR2 may be an NMOS field-effect transistor.

[0032] The contacts may be connected to at least one of the first source / drain patterns SD1 and SD2 of the first transistor TR1 and the second transistor TR2. The contacts may extend in a vertical direction (e.g., a third direction DR3) to connect to at least one of the first source / drain patterns SD1 and SD2. In an example embodiment, the contacts may include a first contact CT1 and a second contact CT2, the first contact CT1 being connected to at least one of the first source / drain patterns SD1 of the first transistor TR1, and the second contact CT2 being connected to at least one of the second source / drain patterns SD2 of the second transistor TR2. The contacts may have a bottleneck shape or bottleneck structure with different diameters depending on their position in the vertical direction. For example, the contacts may have a smaller diameter at a second height than at locations other than a second height.

[0033] The structure of a semiconductor device according to one or more embodiments will be described in detail below with reference to the accompanying drawings.

[0034] Shallow trench isolation patterns (STIs) can be disposed on substrate 100. Shallow trench isolation patterns (STIs) can fill trenches (TR). Shallow trench isolation patterns (STIs) can include silicon oxide. Shallow trench isolation patterns (STIs) may not cover active patterns (APs).

[0035] A first channel pattern CH1 may be disposed on an active pattern AP. The first channel pattern CH1 may include stacked semiconductor patterns S1 and S2. Semiconductor patterns S1 and S2 may be spaced apart from each other. In one or more embodiments, the first channel pattern CH1 may include two semiconductor patterns: a first semiconductor pattern S1 and a second semiconductor pattern S2, which are vertically stacked and spaced apart from each other. However, the number of semiconductor patterns is not limited to this and may be provided in various quantities, such as one, three, or more.

[0036] Each of the first semiconductor pattern S1 and the second semiconductor pattern S2 of the first channel pattern CH1 may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). For example, each of the first semiconductor pattern S1 and the second semiconductor pattern S2 of the first channel pattern CH1 may include monocrystalline silicon.

[0037] The first gate electrode GE1 can be disposed on the first semiconductor pattern S1 and the second semiconductor pattern S2 of the first channel pattern CH1. The first gate electrode GE1 can be stacked perpendicularly to the first semiconductor pattern S1 and the second semiconductor pattern S2 of the first channel pattern CH1. For example, the first gate electrode GE1 can be alternately stacked with the first semiconductor pattern S1 and the second semiconductor pattern S2 of the first channel pattern CH1 on a third-direction DR3. For example, the first gate electrode GE1 can be located between the first semiconductor pattern S1 and the second semiconductor pattern S2 of the first channel pattern CH1. The first gate electrode GE1 can be disposed above the topmost semiconductor pattern of the first semiconductor pattern S1 and the second semiconductor pattern S2 of the first channel pattern CH1, and below the bottommost semiconductor pattern of the first semiconductor pattern S1 and the second semiconductor pattern S2 of the first channel pattern CH1. Therefore, the first gate electrode GE1 can be perpendicularly overlapped with the first channel pattern CH1.

[0038] The first gate electrode GE1 may surround the first channel pattern CH1. The first gate electrode GE1 may surround each of the first semiconductor pattern S1 and the second semiconductor pattern S2 of the first channel pattern CH1. For example, the first gate electrode GE1 may be disposed on the upper surface, lower surface, front surface, and rear surface of each of the first semiconductor pattern S1 and the second semiconductor pattern S2 of the first channel pattern CH1. Therefore, the transistor according to these embodiments may be a three-dimensional field-effect transistor (e.g., a multi-bridge channel field-effect transistor (MBCFET) or a gate-all-around field-effect transistor (GAAFET)), wherein the first gate electrode GE1 is configured to surround the channel in three dimensions.

[0039] The first gate electrode GE1 may extend in a planar manner on the upper surface of the substrate 100. In one or more embodiments, the first gate electrode GE1 may be disposed between the substrate 100 and the lowermost semiconductor pattern of the first semiconductor pattern S1 and the second semiconductor pattern S2 of the first channel pattern CH1, and may extend in the second direction DR2.

[0040] A gate insulating layer GI may be disposed between the first gate electrode GE1 and the first semiconductor pattern S1 and the second semiconductor pattern S2 of the first channel pattern CH1. The gate insulating layer GI may be disposed on the first semiconductor pattern S1 and the second semiconductor pattern S2 of the first channel pattern CH1. The gate insulating layer GI may surround each of the first semiconductor pattern S1 and the second semiconductor pattern S2 of the first channel pattern CH1. For example, the gate insulating layer GI may be disposed on the upper surface, lower surface, front surface, and rear surface of each of the first semiconductor pattern S1 and the second semiconductor pattern S2 of the first channel pattern CH1. The gate insulating layer GI may be in contact with the first semiconductor pattern S1 and the second semiconductor pattern S2.

[0041] In the plan view, the gate insulating layer GI may extend above the upper surface of the substrate 100. The gate insulating layer GI may contact the upper surface of the active pattern AP. The gate insulating layer GI may be disposed between the upper surface of the substrate 100 and the first gate electrode GE1.

[0042] The gate insulating layer GI may include an interface layer and a high-k dielectric layer. The interface layer may include at least one of silicon oxide and silicon oxynitride. The high-k dielectric layer may include a high-k dielectric material having a higher dielectric constant than silicon oxide. In one or more embodiments, the high-k dielectric layer may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0043] Although not shown, a diffusion barrier pattern may be disposed on the gate insulating layer GI surrounding each of the first semiconductor pattern S1 and the second semiconductor pattern S2. The diffusion barrier pattern may be disposed between the gate insulating layer GI and the first gate electrode GE1. The diffusion barrier pattern can reduce the exchange of material between the first gate electrode GE1 and the gate insulating layer GI. For example, the diffusion barrier pattern can significantly reduce the diffusion of metal elements included in the first gate electrode GE1 into the gate insulating layer GI.

[0044] A first source / drain pattern SD1 may be disposed on at least one side of a first channel pattern CH1. The first source / drain pattern SD1 may also be disposed on the opposite side of the first channel pattern CH1, and the first channel pattern CH1 may be connected to the first source / drain pattern SD1 on the opposite side. For example, a first semiconductor pattern S1 and a second semiconductor pattern S2 may be connected to the first source / drain pattern SD1 disposed on their opposite sides.

[0045] Although not shown, a seed pattern may be disposed below the first source / drain pattern SD1. The seed pattern may be disposed in the second groove RC2 defined between the active patterns AP. The second groove RC2 may be formed from the upper surface of the substrate 100 along the depth direction. The first source / drain pattern SD1 may be formed from the seed pattern by a selective epitaxial growth process.

[0046] A second channel pattern CH2 may be disposed on a first channel pattern CH1. The second channel pattern CH2 may include a first semiconductor pattern S1 and a second semiconductor pattern S2 stacked sequentially. The first semiconductor pattern S1 and the second semiconductor pattern S2 may be spaced apart from each other. In one or more embodiments, the second channel pattern CH2 may include two semiconductor patterns, the first semiconductor pattern S1 and the second semiconductor pattern S2, stacked vertically and spaced apart from each other. However, the number of semiconductor patterns in the second channel pattern CH2 is not limited to this, and the semiconductor patterns in the second channel pattern CH2 may be provided in various quantities, such as one, three, or more.

[0047] The first semiconductor pattern S1 and the second semiconductor pattern S2 of the second channel pattern CH2 can be located at a higher height than the first semiconductor pattern S1 and the second semiconductor pattern S2 of the first channel pattern CH1. The number of semiconductor patterns in the second channel pattern CH2 can be the same as or different from the number of semiconductor patterns in the first channel pattern CH1.

[0048] Each of the first semiconductor pattern S1 and the second semiconductor pattern S2 of the second channel pattern CH2 may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The first semiconductor pattern S1 and the second semiconductor pattern S2 of the second channel pattern CH2 may be formed of the same material as the first semiconductor pattern S1 and the second semiconductor pattern S2 of the first channel pattern CH1. For example, each of the first semiconductor pattern S1 and the second semiconductor pattern S2 of the second channel pattern CH2 may include monocrystalline silicon.

[0049] The second gate electrode GE2 can be disposed on the first semiconductor pattern S1 and the second semiconductor pattern S2 of the second channel pattern CH2. The second gate electrode GE2 can be stacked perpendicularly to the first semiconductor pattern S1 and the second semiconductor pattern S2 of the second channel pattern CH2. For example, the second gate electrode GE2 can be alternately stacked with the first semiconductor pattern S1 and the second semiconductor pattern S2 of the second channel pattern CH2 on a third-direction DR3. For example, the second gate electrode GE2 can be located between the first semiconductor pattern S1 and the second semiconductor pattern S2 of the second channel pattern CH2. The second gate electrode GE2 can also be disposed above the uppermost semiconductor pattern of the first semiconductor pattern S1 and the lowermost semiconductor pattern of the first semiconductor pattern S1 and the second semiconductor pattern S2. Therefore, the second gate electrode GE2 can be perpendicularly overlapped with the second channel pattern CH2.

[0050] The second gate electrode GE2 may surround the second channel pattern CH2. The second gate electrode GE2 may surround each of the first semiconductor pattern S1 and the second semiconductor pattern S2. For example, the second gate electrode GE2 may be disposed on the upper surface, lower surface, front surface, and rear surface of each of the first semiconductor pattern S1 and the second semiconductor pattern S2. Therefore, the transistor according to these embodiments may be a three-dimensional field-effect transistor (e.g., MBCFET or GAAFET), wherein the second gate electrode GE2 is configured to surround the channel in three dimensions.

[0051] The gate electrode GE can be formed of a metal, a metal nitride, a metal carbide, or a combination thereof. The metal can be selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. The metal nitride can be selected from TiN or TaN. The metal carbide can be TiAlC. However, the materials forming the gate electrode GE are not limited to the examples above.

[0052] The second gate electrode GE2 can be integrally formed with the first gate electrode GE1 without separation to connect with each other. However, the first gate electrode GE1 and the second gate electrode GE2 can be formed separately. When the first gate electrode GE1 and the second gate electrode GE2 are formed separately, at least one of the two gate electrodes GE can extend onto the third direction DR3, such that the first gate electrode GE1 and the second gate electrode GE2 can connect with each other.

[0053] A gate insulating layer GI may be disposed between the second gate electrode GE2 and the first semiconductor pattern S1 and the second semiconductor pattern S2 of the second channel pattern CH2. The gate insulating layer GI may be disposed on the first semiconductor pattern S1 and the second semiconductor pattern S2 of the second channel pattern CH2. The gate insulating layer GI may surround each of the first semiconductor pattern S1 and the second semiconductor pattern S2 of the second channel pattern CH2. For example, the gate insulating layer GI may be disposed on the upper surface, lower surface, front surface, and rear surface of each of the first semiconductor pattern S1 and the second semiconductor pattern S2 of the second channel pattern CH2. The gate insulating layer GI may be in contact with the first semiconductor pattern S1 and the second semiconductor pattern S2 of the second channel pattern CH2.

[0054] Although not shown, a diffusion barrier pattern can also be disposed on the gate insulating layer GI, which surrounds each of the first semiconductor pattern S1 and the second semiconductor pattern S2 of the second channel pattern CH2. The diffusion barrier pattern can also be disposed between the gate insulating layer GI and the second gate electrode GE2. For example, the diffusion barrier pattern can separate the gate insulating layer GI and the second gate electrode GE2. Therefore, the gate insulating layer GI does not need to be in direct contact with the second gate electrode GE2.

[0055] In an example embodiment, the first semiconductor pattern S1 and the second semiconductor pattern S2 of the first channel pattern CH1 and the first semiconductor pattern S1 and the second semiconductor pattern S2 of the second channel pattern CH2 can be formed from semiconductor layers having the same elements. In one example, the first semiconductor pattern S1 and the second semiconductor pattern S2 of the first channel pattern CH1 and the second channel pattern CH2 can each be formed from a Si layer. In an example embodiment, the first semiconductor pattern S1 and the second semiconductor pattern S2 of the first channel pattern CH1 and the second channel pattern CH2 can each be formed from an undoped Si layer. In an example embodiment, the first semiconductor pattern S1 and the second semiconductor pattern S2 of the first channel pattern CH1 can each be formed from a silicon (Si) layer doped with impurities of the same conductivity type as the first source / drain pattern SD1, and the first semiconductor pattern S1 and the second semiconductor pattern S2 of the second channel pattern CH2 can be formed from a silicon (Si) layer doped with impurities of the same conductivity type as the second source / drain pattern SD2. In an example embodiment, the first semiconductor pattern S1 and the second semiconductor pattern S2 of the first channel pattern CH1 can be formed by a silicon (Si) layer doped with impurities of a conductivity type opposite to that of the first source / drain pattern SD1, and the first semiconductor pattern S1 and the second semiconductor pattern S2 of the second channel pattern CH2 can be formed by a silicon (Si) layer doped with impurities of a conductivity type opposite to that of the second source / drain pattern SD2.

[0056] A pair of gate spacers GS may be disposed on the second channel pattern CH2. The gate spacers GS may extend on the third direction DR3. The pair of gate spacers GS may be spaced apart from each other. The gate spacers GS may include at least one of SiCN, SiCON, or SiN. Alternatively, the gate spacers GS may have a multilayer structure formed of at least two of SiCN, SiCON, or SiN.

[0057] A gate cover pattern 160 may be disposed between the paired gate spacers GS. The gate cover pattern 160 may fill the space between the paired gate spacers GS. The gate cover pattern 160 may be disposed on the second channel pattern CH2. The gate cover pattern 160 may be disposed on the gate electrode GE.

[0058] The gate cover pattern 160 may include a material that is etch-selective with respect to the first interlayer insulating layer 140 and the second interlayer insulating layer 170, which will be described later. For example, the gate cover pattern 160 may include at least one of SiON, SiCN, SiCON, or SiN.

[0059] The second source / drain pattern SD2 can be disposed on at least one side of the second channel pattern CH2. The second source / drain pattern SD2 can be disposed on the opposite side of the second channel pattern CH2, and the second channel pattern CH2 can connect the second source / drain patterns SD2 on the opposite sides to each other. For example, the first semiconductor pattern S1 and the second semiconductor pattern S2 can be connected to the second source / drain pattern SD2 located on their opposite sides.

[0060] The first source / drain pattern SD1 and the second source / drain pattern SD2 can each be formed from an epitaxially grown semiconductor layer. In an example embodiment, the first source / drain pattern SD1 and the second source / drain pattern SD2 can each be formed from a group IV element semiconductor, a group IV-IV compound semiconductor, or a combination thereof.

[0061] One of the first transistor TR1 and the second transistor TR2 can be an NMOS transistor, and the other of the first transistor TR1 and the second transistor TR2 can be a PMOS transistor. Therefore, depending on the type of the first transistor TR1 and the second transistor TR2, the first source / drain pattern SD1 and the second source / drain pattern SD2 can be doped with impurities of different conductivity types. For example, the first source / drain pattern SD1 can be an impurity region of a first conductivity type, and the second source / drain pattern SD2 can be an impurity region of a second conductivity type. For example, the first source / drain pattern SD1 can be a P-type impurity region, and the second source / drain pattern SD2 can be an N-type impurity region. Conversely, the first source / drain pattern SD1 can be an N-type impurity region, and the second source / drain pattern SD2 can be a P-type impurity region. P-type impurities can be selected from boron (B) and gallium (Ga). N-type impurities can be selected from phosphorus (P), arsenic (As), and antimony (Sb).

[0062] In one or more embodiments, the first source / drain pattern SD1 may include the same semiconductor elements as the substrate 100. The second source / drain pattern SD2 may include semiconductor elements (e.g., SiGe) having a larger lattice constant than the semiconductor elements of the substrate 100. Thus, the paired second source / drain patterns SD2 may provide compressive stress to the second channel pattern CH2 therebetween.

[0063] Each first source / drain pattern SD1 may include a first epitaxial layer SD1a and a second epitaxial layer SD1b with different impurity concentrations. For example, the second epitaxial layer SD1b may have a higher impurity concentration than the first epitaxial layer SD1a.

[0064] For example, when the first transistor TR1 is a PMOS transistor, the first source / drain pattern SD1 may include silicon-germanium (SiGe), and the germanium (Ge) concentration of the second epitaxial layer SD1b may be higher than that of the first epitaxial layer SD1a. For example, the germanium (Ge) concentration of the first epitaxial layer SD1a may be in the range of approximately 1 at% to approximately 15 at%, and the germanium (Ge) concentration of the second epitaxial layer SD1b may be in the range of approximately 20 at% to approximately 100 at%. Furthermore, the second epitaxial layer SD1b may have a higher doping concentration of dopant (e.g., impurities) than the first epitaxial layer SD1a. The impurities may be at least one of boron (B), gallium (Ga), or indium (In).

[0065] Each second source / drain pattern SD2 may further include a first epitaxial layer SD2a and a second epitaxial layer SD2b with different impurity concentrations. The second epitaxial layer SD2b of each second source / drain pattern SD2 may have a higher impurity concentration than the first epitaxial layer SD2a. For example, when the first transistor TR1 is an NMOS transistor, the germanium (Ge) concentration of the second epitaxial layer SD2b may be higher than the germanium (Ge) concentration of the first epitaxial layer SD2a. For example, the germanium (Ge) concentration of the first epitaxial layer SD2a may be in the range of approximately 0 at% to approximately 15 at%, and the germanium (Ge) concentration of the second epitaxial layer SD2b may be in the range of approximately 20 at% to approximately 100 at%. Furthermore, the second epitaxial layer SD2b may have a higher doping concentration of dopant (e.g., impurities) than the first epitaxial layer SD2a. The impurities may be at least one of phosphorus (P), arsenic (As), or antimony (Sb).

[0066] A first interlayer insulating layer 140 may be disposed on the substrate 100. The first interlayer insulating layer 140 may cover the second source / drain pattern SD2. The upper surface of the first interlayer insulating layer 140 may be substantially coplanar with the upper surface of the gate overlay pattern 160 and the gate spacer GS.

[0067] A protective insulating pattern 150 may be disposed on the first interlayer insulating layer 140. The protective insulating pattern 150 may protect the first interlayer insulating layer 140 and the second source / drain pattern SD2 disposed therebelow.

[0068] A second interlayer insulating layer 170 may be disposed on the first interlayer insulating layer 140 to cover the gate overlay pattern 160. The second interlayer insulating layer 170 may be disposed on the protective insulating pattern 150. The second interlayer insulating layer 170 may cover the gate spacer GS and the protective insulating pattern 150. In one or more embodiments, the first interlayer insulating layer 140 and the second interlayer insulating layer 170 may include silicon oxide. The protective insulating pattern 150 may include a silicon nitride layer.

[0069] An intermediate isolation pattern 130 can be disposed between the first channel pattern CH1 and the second channel pattern CH2. The first channel pattern CH1, the intermediate isolation pattern 130, and the second channel pattern CH2 can form a stacked structure. The first channel pattern CH1, the intermediate isolation pattern 130, and the second channel pattern CH2 can be stacked sequentially.

[0070] The intermediate isolation pattern 130 can separate the stacked first channel pattern CH1 and second channel pattern CH2.

[0071] The gate insulating layer GI can also be disposed on the intermediate isolation pattern 130. The gate insulating layer GI can surround the intermediate isolation pattern 130. For example, the gate insulating layer GI can be disposed on the upper surface, lower surface, front surface, and rear surface of the intermediate isolation pattern 130. The gate insulating layer GI can be in contact with the intermediate isolation pattern 130.

[0072] The first gate electrode GE1 on the first channel pattern CH1 can extend to the intermediate isolation pattern 130. The second gate electrode GE2 on the second channel pattern CH2 can extend to the intermediate isolation pattern 130. The first gate electrode GE1 and the second gate electrode GE2 can be connected on the intermediate isolation pattern 130.

[0073] The additional isolation pattern 135 can be disposed on one side of the intermediate isolation pattern 130. The additional isolation pattern 135 can be disposed on the opposite side of the intermediate isolation pattern 130.

[0074] An additional isolation pattern 135 may be disposed between the first source / drain pattern SD1 and the second source / drain pattern SD2. For example, the additional isolation pattern 135 may be disposed on the first source / drain pattern SD1. The additional isolation pattern 135 may be disposed below the second source / drain pattern SD2. For example, the first source / drain pattern SD1, the additional isolation pattern 135, and the second source / drain pattern SD2 may be stacked sequentially. The upper surface of the additional isolation pattern 135 may contact the lower surface of the second source / drain pattern SD2.

[0075] The first interlayer insulating layer 140 may be stacked on the additional isolation pattern 135. The first interlayer insulating layer 140 may surround the second source / drain pattern SD2. For example, the lower surface of the first interlayer insulating layer 140 may be substantially coplanar with the lower surface of the second source / drain pattern SD2. The upper surface of the first interlayer insulating layer 140 may be disposed above the second source / drain pattern SD2.

[0076] Contacts for electrical connection with other components may be provided in the first source / drain pattern SD1 and / or the second source / drain pattern SD2.

[0077] Figure 3 It is a portion of a cross-sectional view showing a single contact, and is Figure 2A A magnified cross-sectional view of part P1.

[0078] refer to Figure 3 The contacts may include a first contact CT1 and a second contact CT2, wherein the first contact CT1 is perpendicularly connected to at least one of the first source / drain patterns SD1, and the second contact CT2 is perpendicularly connected to at least one of the second source / drain patterns SD2.

[0079] The first contact CT1 can be formed in the third recess RC3. The third recess RC3 can be disposed in the first source / drain pattern SD1 and the second source / drain pattern SD2, which are vertically stacked on the active pattern AP. The third recess RC3 can vertically penetrate the second source / drain pattern SD2 and the additional isolation pattern 135, and can have a shape that is vertically recessed downward from the upper surface of the first source / drain pattern SD1. For example, the third recess RC3 can vertically penetrate the second interlayer insulating layer 170, the protective insulating pattern 150, the gate cover pattern 160, the second source / drain pattern SD2, and the additional isolation pattern 135, and can have a shape that is vertically recessed downward from the upper surface of the first source / drain pattern SD1.

[0080] The first contact CT1 may be formed from a single conductive material, but the embodiments are not limited thereto. The first contact CT1 may include a variety of conductive materials. The conductive materials may include metals and / or metal nitrides. The metal may be selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. The metal nitride may be selected from TiN or TaN.

[0081] Furthermore, the first contact CT1 can be formed as a multilayer structure. In one or more embodiments, the first contact CT1 may include two conductive layers. One of the two conductive layers may be a barrier layer, and the other conductive layer may be a contact plug disposed on the barrier layer. The first contact CT1 may include, for example, a first conductive layer M1, a second conductive layer M2, and a third conductive layer M3. At least one of the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3 may include a material different from the remaining layers. In one or more embodiments, the first conductive layer M1 may include titanium, the second conductive layer M2 may include titanium nitride, and the third conductive layer M3 may include cobalt.

[0082] The third groove RC3 may have a different diameter in the vertical direction. In the following text, the term "diameter" for a particular component refers to the distance between opposite ends of a component in a direction parallel to the substrate surface of substrate 100 (e.g., the first direction DR1). The "diameter" of an empty space, such as a groove, refers to the distance between opposite surfaces (e.g., groove surfaces) exposed by the empty space in a direction parallel to the substrate surface of substrate 100 (e.g., the first direction DR1).

[0083] The third epitaxial layer SD2c can be disposed in the second source / drain pattern SD2 and protrude toward the third groove RC3. The third epitaxial layer SD2c can be epitaxially grown from the second source / drain pattern SD2 along the horizontal direction.

[0084] The third epitaxial layer SD2c may contain a relatively high concentration of germanium. For example, the germanium concentration of the third epitaxial layer SD2c may be from about 20 at% to about 100 at%, for example, from about 30 at% to about 70 at%. In one or more embodiments of the invention, N-type impurities may be highly doped into the pattern of the third epitaxial layer SD2c. For example, the N-type impurities may be phosphorus, arsenic, or antimony.

[0085] The impurity concentration of the third epitaxial layer SD2c can be higher than that of the first epitaxial layer SD2a and / or the second epitaxial layer SD2b. Alternatively, the impurity concentration of the third epitaxial layer SD2c can be substantially the same as that of the second epitaxial layer SD2b.

[0086] Due to the formation of the third epitaxial layer SD2c, the third groove RC3 can have different diameters depending on its vertical position, and in particular, the third groove RC3 can have a bottleneck shape. The diameter of the first contact CT1 in the region where the third epitaxial layer SD2c is disposed is smaller than its diameter in other regions adjacent to said region. Specifically, the diameter of the third groove RC3 can have different values ​​depending on the vertical height in the direction upward from the substrate 100. When the diameter of the third groove RC3 at a point on the first source / drain pattern SD1 is a first diameter D1, and the diameter of the third groove RC3 at a point on the second source / drain pattern SD2 is a second diameter D2, the second diameter D2 can be smaller than the first diameter D1. Furthermore, when the diameter of the third groove RC3 at a point on the first interlayer insulating layer 140 is a third diameter D3, the second diameter D2 can be smaller than the third diameter D3. The first diameter D1, second diameter D2, and third diameter D3 of the third groove RC3 can refer to the width of the first contact CT1 in the first direction DR1.

[0087] An ohmic contact layer (OCT) may be selectively disposed between a first source / drain pattern SD1 and a first contact CT1, and between a second source / drain pattern SD2 and the first contact CT1. The ohmic contact layer (OCT) is configured to have low contact resistance between the first contact CT1 and the first source / drain pattern SD1, and / or between the first contact CT1 and the second source / drain pattern SD2. The ohmic contact layer (OCT) may include a metal silicide. In one or more embodiments, the metal silicide may be formed of a material such as CoSi, NiSi, TiSi, NiPtSi, or NiTiSi.

[0088] Return to Figure 2A The second contact CT2 can be set in the fourth groove RC4.

[0089] The fourth recess RC4 may have a shape that is recessed vertically downward from the upper surface of the second source / drain pattern SD2. For example, the fourth recess RC4 may penetrate the second interlayer insulating layer 170, the protective insulating pattern 150, and the gate cover pattern 160, and may have a shape that is recessed vertically downward from the upper surface of the second source / drain pattern SD2.

[0090] The second contact CT2 may be formed from a single conductive material, but the example embodiments are not limited thereto. The second contact CT2 may include a variety of conductive materials. The conductive materials may include metals and / or metal nitrides. The metal may be selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. The metal nitride may be selected from TiN or TaN.

[0091] Furthermore, the second contact CT2 can be formed as a multilayer. In one or more embodiments, the second contact CT2 may include two conductive layers. Alternatively, the second contact CT2 may include a first conductive layer M1, a second conductive layer M2, and a third conductive layer M3. At least one of the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3 may include a material different from the remaining layers. In one or more embodiments, the first conductive layer M1 may include titanium, the second conductive layer M2 may include titanium nitride, and the third conductive layer M3 may include cobalt.

[0092] An ohmic contact layer OCT can be selectively disposed between the second source / drain pattern SD2 and the second contact CT2. The ohmic contact layer OCT can be configured to have low contact resistance between the second contact CT2 and the second source / drain pattern SD2. The ohmic contact layer OCT may include a metal silicide. In one or more embodiments, the metal silicide may be formed of a material such as CoSi, NiSi, TiSi, NiPtSi, or NiTiSi.

[0093] The semiconductor device according to one or more embodiments may include a first transistor TR1 and a second transistor TR2 located on an active pattern AP, the first transistor TR1 and the second transistor TR2 being configured to overlap each other in a vertical direction (third direction DR3), and the first transistor TR1 and the second transistor TR2 may have channel types with opposite conductivity types. When the area of ​​the semiconductor device is reduced due to miniaturization, the first transistor TR1 and the second transistor TR2 with opposite conductivity types can be stacked in a direction perpendicular to the upper surface of the substrate 100. Therefore, the number of transistors per unit area can be further increased to improve the integration of the semiconductor device.

[0094] In a semiconductor device according to one or more embodiments, when a second source / drain pattern SD2 is connected to a second transistor TR2, a third epitaxial layer SD2c containing a relatively high concentration of impurities may be provided to reduce the contact resistance between the first contact CT1 and the second source / drain pattern SD2.

[0095] When the third epitaxial layer SD2c is not provided, the second epitaxial layer SD2b in the second source / drain pattern SD2 may be excessively removed due to the formation of the third groove RC3 during the manufacturing process. Therefore, only a small amount of the second epitaxial layer SD2b may remain in the second source / drain pattern SD2. Alternatively, the second epitaxial layer SD2b may be almost entirely removed, leaving only the first epitaxial layer SD2a. When only a small amount of the second epitaxial layer SD2b or only the first epitaxial layer SD2a is retained in the third groove RC3, the contact resistance between the second source / drain pattern SD2 and the first contact CT1 in the third groove RC3 may increase. In one or more embodiments, a heavily doped third epitaxial layer SD2c may be provided in the second source / drain pattern SD2 to reduce the contact resistance between the first contact CT1 and the second source / drain pattern SD2.

[0096] Various modifications can be made without departing from the inventive concept. In the above embodiments, the third epitaxial layer SD2c corresponding to the second contact CT2 is not formed in the second source / drain pattern SD2, but the embodiments are not limited thereto. In exemplary embodiments, the third epitaxial layer SD2c may also be formed in the second source / drain pattern SD2 corresponding to the second contact CT2.

[0097] Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 and Figure 21 It is a view that sequentially illustrates methods of manufacturing a semiconductor device according to one or more embodiments. Figure 4A , Figure 5A, Figures 6 to 10 , Figure 11A , Figure 12A , Figure 13A , Figure 14A and Figures 15 to 21 It is along Figure 1 A cross-sectional view taken from line A-A', and Figure 4B , Figure 5B , Figure 11B , Figure 12B , Figure 13B and Figure 14B It is along Figure 1 A cross-sectional view taken from the B-B' line.

[0098] refer to Figure 4A and Figure 4B A first preliminary stacked pattern ST1a, an intermediate semiconductor pattern 131, and a second preliminary stacked pattern ST2a can be sequentially formed on the substrate 100. The first preliminary stacked pattern ST1a and the second preliminary stacked pattern ST2a may each include different material layers arranged alternately to facilitate the formation of the first channel pattern CH1 and the second channel pattern CH2.

[0099] A first preliminary stacking pattern ST1a may be formed on the substrate 100. The first preliminary stacking pattern ST1a may include alternately stacked first semiconductor layers 110 and second semiconductor layers 120. The first semiconductor layers 110 and second semiconductor layers 120 may have different compositions. The first semiconductor layers 110 and second semiconductor layers 120 may provide different etch selectivity and / or different oxidation rates.

[0100] In one or more embodiments, the first preliminary stacking pattern ST1a may include three first semiconductor layers 110 and two second semiconductor layers 120. However, the number of semiconductor layers included in the first preliminary stacking pattern ST1a is not limited thereto. In one or more embodiments, the first preliminary stacking pattern ST1a may include more or fewer semiconductor layers. For example, in some embodiments, the number of first semiconductor layers 110 and second semiconductor layers 120 in the first preliminary stacking pattern ST1a may be from one to ten.

[0101] Semiconductor layer 110 may include one of silicon (Si), germanium (Ge), or silicon-germanium (SiGe). Second semiconductor layer 120 may include materials other than those forming the first semiconductor layer 110, such as compound semiconductors like Si, Ge, SiC, GeAs, GaP, InP, InAs, and / or InSb; alloy semiconductors like SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof. In one or more embodiments, first semiconductor layer 110 may include silicon-germanium (SiGe), and second semiconductor layer 120 may include silicon (Si).

[0102] The first semiconductor layer 110 and the second semiconductor layer 120 can be formed using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. A portion of the first semiconductor layer 110 and the second semiconductor layer 120 can be removed in subsequent processes and can be used to define the vertical distance between adjacent channel patterns of the semiconductor device to be ultimately formed. In one or more embodiments, the thickness of each of the first semiconductor layer 110 and the second semiconductor layer 120 may vary depending on the embodiment.

[0103] An intermediate semiconductor pattern 131 may be formed on a first preliminary stacked pattern ST1a. For example, the intermediate semiconductor pattern 131 may be formed on the uppermost semiconductor layer of an alternately stacked first semiconductor layer 110 and second semiconductor layer 120 of the first preliminary stacked pattern ST1a. The intermediate semiconductor pattern 131 may include one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe). In one or more embodiments, the intermediate semiconductor pattern 131 may be formed of the same material as the first semiconductor layer 110.

[0104] The intermediate semiconductor pattern 131 may have etch selectivity relative to the first semiconductor layer 110 and / or the second semiconductor layer 120. In one or more embodiments, the concentration of the silicon-germanium (SiGe) intermediate semiconductor pattern 131 may be higher than the concentration of the silicon-germanium (SiGe) first semiconductor layer 110. Therefore, the intermediate semiconductor pattern 131 may have etch selectivity relative to the first semiconductor layer 110.

[0105] A second preliminary stacked pattern ST2a can be formed on the intermediate semiconductor pattern 131. The second preliminary stacked pattern ST2a may include alternately stacked first semiconductor layers 110 and second semiconductor layers 120. The first semiconductor layers 110 and second semiconductor layers 120 may have different compositions. The first semiconductor layers 110 and second semiconductor layers 120 may provide different etch selectivity and / or different oxidation rates.

[0106] The second preliminary stacking pattern ST2a may include two first semiconductor layers 110 and two second semiconductor layers 120. However, the number of first semiconductor layers 110 and second semiconductor layers 120 included in the second preliminary stacking pattern ST2a is not limited thereto. In one or more embodiments, the second preliminary stacking pattern ST2a may include more or fewer semiconductor layers. For example, in some embodiments, the number of first semiconductor layers 110 and second semiconductor layers 120 in the second preliminary stacking pattern ST2a may be from one to ten.

[0107] The number of first semiconductor layer 110 and second semiconductor layer 120 in the first preliminary stacking pattern ST1a and the number of first semiconductor layer 110 and second semiconductor layer 120 in the second preliminary stacking pattern ST2a may be the same or different.

[0108] In one or more embodiments, the first semiconductor layer 110 in the first preliminary stacked pattern ST1a and the second preliminary stacked pattern ST2a may be formed of the same material, but the embodiments are not limited thereto. The first semiconductor layer 110 in the first preliminary stacked pattern ST1a and the second preliminary stacked pattern ST2a may be formed of different materials. Additionally, the second semiconductor layer 120 in the first preliminary stacked pattern ST1a and the second preliminary stacked pattern ST2a may be formed of the same material, but the embodiments are not limited thereto. The second semiconductor layer 120 in the first preliminary stacked pattern ST1a and the second preliminary stacked pattern ST2a may be formed of different materials.

[0109] A mask pattern can be formed on the active pattern AP of the substrate 100. The mask pattern can be used as an etching mask to perform a patterning process of the stacked pattern and the substrate 100 to form a trench TR defining the active pattern AP. The trench TR can be formed on opposite sides of the active pattern AP.

[0110] Shallow trench isolation patterns (STIs) can fill trenches (TRs). For example, an insulating layer covering the active pattern (AP) and the stacked pattern can be formed on the entire surface of substrate 100. The insulating layer can be recessed until the stacked pattern is exposed to form a shallow trench isolation pattern (STI). Shallow trench isolation patterns (STIs) can be formed using high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or other suitable deposition processes.

[0111] Shallow trench isolation patterns (STIs) may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric materials, or combinations thereof. In one or more embodiments, the shallow trench isolation pattern (STI) may include silicon oxide. Stacked patterns may be exposed above the shallow trench isolation pattern (STI). For example, stacked patterns may project vertically upwards from the shallow trench isolation pattern (STI).

[0112] The sacrificial pattern SF can be made of various materials, such as polysilicon. In subsequent processes, the sacrificial pattern SF can be replaced by the gate electrode GE of the semiconductor device. Therefore, the width of the sacrificial pattern SF can be substantially the same as the width of the gate electrode GE of the semiconductor device to be replaced later.

[0113] Forming a sacrificial pattern SF may include forming a sacrificial layer on the entire surface of the substrate 100, forming a mask pattern on the sacrificial layer, and using the mask pattern as an etch mask to pattern the sacrificial layer.

[0114] The sacrificial layer can be deposited using CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes, including low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical vapor deposition (PECVD). A portion of the sacrificial layer can be removed using plasma dry etching and / or wet etching. In some embodiments, when the sacrificial layer is polycrystalline silicon, wet etching can be performed to selectively remove a portion of the sacrificial layer, and various etchants such as tetramethylammonium hydroxide (TMAH) solution can be used.

[0115] Pairs of gate spacers GS can be formed on opposite sidewalls of each sacrificial pattern SF. Forming the gate spacers GS may include conformally forming a gate spacer layer on the upper surface of the substrate 100 and anisotropically etching the gate spacer layer. The gate spacers GS may include materials such as SiO2. x Materials include SiCN, SiCON, SiN, or SiON. In another example, the gate spacer GS may have a multilayer structure including at least two of SiCN, SiCON, or SiN. The gate spacer (GS) layer can be formed using CVD, PVD, ALD, or other suitable processes including LPCVD and PECVD.

[0116] refer to Figure 5A and Figure 5BAn initial intermediate isolation pattern 133 may be formed between the first initial stacked pattern ST1a and the second initial stacked pattern ST2a. For example, forming the initial intermediate isolation pattern 133 may include removing the intermediate semiconductor pattern 131 and filling the space where the intermediate semiconductor pattern 131 has been removed with the initial intermediate isolation pattern 133. In one or more embodiments, the initial intermediate isolation pattern 133 may include SiOCN.

[0117] refer to Figure 6 The first recess RC1 can be formed in the second preliminary stacked pattern ST2a on the active pattern AP. For example, the first recess RC1 can be formed by etching the second preliminary stacked pattern ST2a on the active pattern AP using a gate mask GM and a gate spacer GS as etching masks. The first recess RC1 can correspond to the region in which the second source / drain pattern SD2 will be formed.

[0118] A first semiconductor pattern S1 and a second semiconductor pattern S2, stacked and spaced apart from each other, can be formed through the first groove RC1. A second stacked pattern STP2 can be formed between the first semiconductor layer 110 and the second semiconductor layer 120 between adjacent first grooves RC1.

[0119] A protective pad PL can be formed on the surface of the second stacked pattern STP2 and the first groove RC1.

[0120] refer to Figure 7 The second recess RC2 can be formed in the initial intermediate isolation pattern 133 and the first initial stacked pattern ST1a on the active pattern AP. The second recess RC2 can be formed corresponding to the region where the additional isolation pattern 135 and the second source / drain pattern SD2 are to be formed. For example, the second recess RC2 can be formed by sequentially etching the initial intermediate isolation pattern 133 and the first initial stacked pattern ST1a on the active pattern AP using the gate mask GM and the gate spacer GS as etching masks.

[0121] Through the second groove RC2, a first semiconductor pattern S1 and a second semiconductor pattern S2, which are stacked and spaced apart from each other, and an intermediate isolation pattern 130 can be formed. The first semiconductor layer 110 and the second semiconductor layer 120 between adjacent second grooves RC2 can form a first stacked pattern STP1.

[0122] A portion of the first preliminary stacked pattern ST1a and the second preliminary stacked pattern ST2a can be removed using suitable dry etching and / or wet etching processes to remove the gate spacer GS, the first semiconductor layer 110, and the second semiconductor layer 120 together or separately. The etching process can be performed anisotropically using the sacrificial pattern SF and the gate spacer GS disposed on the stacked patterns as masks.

[0123] Although not shown, an additional groove may be formed below the second groove RC2. The additional groove may be located at a position corresponding to the seed pattern used to form the first source / drain pattern SD1.

[0124] refer to Figure 8 A first source / drain pattern SD1 can be formed in the second groove RC2. The first source / drain pattern SD1 can be formed from an epitaxially grown semiconductor layer. The first source / drain pattern SD1 can be grown using the first semiconductor pattern S1 and the second semiconductor pattern S2 exposed by the second groove RC2 as seed crystals. In one or more embodiments, the selective epitaxial growth process can include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0125] In one or more embodiments, a seed pattern may be formed in an additional groove. The seed pattern may fill the additional second groove RC2. The seed pattern may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The seed pattern may be used as a seed layer to perform a selective epitaxial growth process to form an epitaxial layer filling the second groove RC2.

[0126] The first source / drain pattern SD1 can be formed on the opposite side of the first stacked pattern STP1.

[0127] To form the first source / drain pattern SD1, the inner wall of the second trench RC2 can be used as a seed layer to perform a first selective epitaxial growth (SEG) process to form the first epitaxial layer SD1a. The first semiconductor pattern S1 and the second semiconductor pattern S2 exposed by the second trench RC2, along with the substrate 100 or the seed pattern, can be used as seeds to grow the first epitaxial layer SD1a. For example, the first SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0128] The first epitaxial layer SD1a may include a semiconductor element (e.g., SiGe) having a larger lattice constant than the semiconductor element of the substrate 100. The first epitaxial layer SD1a may contain a relatively low concentration of germanium. In one or more embodiments, the first epitaxial layer SD1a may contain only silicon (Si) other than germanium. The germanium concentration of the first epitaxial layer SD1a may be from 0 at% to 10 at%.

[0129] A second SEG process can be performed on the first epitaxial layer SD1a to form a second epitaxial layer SD1b. The second epitaxial layer SD1b may contain a relatively high concentration of germanium. For example, the germanium concentration of the second epitaxial layer SD1b may be from 30 at% to 70 at%.

[0130] During the formation of the first epitaxial layer SD1a and the second epitaxial layer SD1b, impurities (e.g., P-type impurities such as boron, gallium, or indium) can be implanted in situ into the first source / drain pattern SD1. For example, impurities can be implanted into the first source / drain pattern SD1 after its formation.

[0131] Forming a first source / drain pattern SD1 can result in the formation of a first channel pattern CH1 between two first source / drain patterns SD1. The first channel pattern CH1 may include a first semiconductor pattern S1 and a second semiconductor pattern S2 stacked sequentially.

[0132] refer to Figure 9 An additional isolation pattern 135 may be formed on the first source / drain pattern SD1. For example, the additional isolation pattern 135 may be formed around the first source / drain pattern SD1. The additional isolation pattern 135 may fill the second recess RC2 up to the height corresponding to the upper surface of the intermediate isolation pattern 130. The additional isolation pattern 135 may include silicon oxide.

[0133] A second source / drain pattern SD2 can be formed on the additional isolation pattern 135. Before forming the second source / drain pattern SD2, the protective pad PL can be removed from the inner wall of the first groove RC1.

[0134] The second source / drain pattern SD2 can be formed from an epitaxially grown semiconductor layer. The second source / drain pattern SD2 can be grown using the first semiconductor pattern S1 and the second semiconductor pattern S2 exposed by the first trench RC1 as seed crystals. In one or more embodiments, the selective epitaxial growth process can include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0135] In one or more embodiments, the second source / drain pattern SD2 may include the same semiconductor element as the substrate 100 (e.g., Si). During the formation of the second source / drain pattern SD2, impurities (e.g., phosphorus, arsenic, or antimony) that allow the second source / drain pattern SD2 to have N-type characteristics may be implanted in situ. In one or more embodiments, impurities may also be implanted into the second source / drain pattern SD2 after its formation.

[0136] The second source / drain pattern SD2 can be formed on the opposite side of the second stacked pattern STP2.

[0137] To form the second source / drain pattern SD2, the inner wall of the first trench RC1 can be used as a seed layer to perform a first SEG process to form the first epitaxial layer SD2a. The first semiconductor pattern S1 and the second semiconductor pattern S2 exposed by the first trench RC1, along with the substrate 100 or the seed pattern, can be used as seeds to grow the first epitaxial layer SD2a. For example, the first SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0138] The first epitaxial layer SD2a may include a semiconductor element (e.g., SiGe) having a larger lattice constant than the semiconductor element of the substrate 100. The first epitaxial layer SD2a may contain a relatively low concentration of germanium. In one or more embodiments, the first epitaxial layer SD2a may contain only silicon (Si) other than germanium. The germanium concentration of the first epitaxial layer SD2a may be from 0 at% to 10 at%. A second SEG process may be performed on the first epitaxial layer SD2a to form a second epitaxial layer SD2b. The second epitaxial layer SD2b may contain a relatively high concentration of germanium (Ge). For example, the germanium concentration of the second epitaxial layer SD2b may be from 30 at% to 70 at%.

[0139] During the formation of the first epitaxial layer SD2a and the second epitaxial layer SD2b, impurities (e.g., N-type impurities such as phosphorus, arsenic, or antimony) can be implanted in situ into the second source / drain pattern SD2. In another example, impurities can be implanted into the second source / drain pattern SD2 after its formation.

[0140] Forming a second source / drain pattern SD2 can result in the formation of a second channel pattern CH2 between the two second source / drain patterns SD2. The second channel pattern CH2 may include a first semiconductor pattern S1 and a second semiconductor pattern S2 stacked sequentially.

[0141] refer to Figure 10 A first interlayer insulating layer 140 may be formed on the second source / drain pattern SD2. For example, the first interlayer insulating layer 140 may be formed around the second source / drain pattern SD2. The first interlayer insulating layer 140 may include silicon oxide.

[0142] The first interlayer insulating layer 140 can be filled to the height corresponding to the upper surface of the gate spacer GS and the height corresponding to the upper surface of the gate mask GM.

[0143] A protective insulating pattern 150 may be formed in the first interlayer insulating layer 140. For example, the first interlayer insulating layer 140 may be recessed, and the protective insulating pattern 150 may fill the recessed first interlayer insulating layer 140.

[0144] refer to Figure 11A and Figure 11B Then, the gate mask GM and the sacrificial pattern SF can be selectively removed using photolithography. Removing the gate mask GM and the sacrificial pattern SF can result in the formation of the outer region OR, which exposes the uppermost surface of the second channel pattern CH2. The sacrificial pattern SF can be removed by a wet etching process. For example, in a wet etching process, an etchant can be used to selectively etch the polysilicon.

[0145] Then, the first semiconductor layer 110 exposed through the external region OR can be selectively removed to form the internal region IR. The internal region IR can be the region between the substrate 100 and the first semiconductor pattern S1, the region between adjacent first semiconductor patterns S1 and second semiconductor patterns S2 of the first stacked pattern STP1, the region between the uppermost second semiconductor pattern S2 of the first stacked pattern STP1 and the intermediate isolation pattern 130, the region between the intermediate isolation pattern 130 and the lowermost first semiconductor pattern S1 of the second stacked pattern STP2, and the region between adjacent first semiconductor patterns S1 and second semiconductor patterns S2 of the second stacked pattern STP2. For example, a selective etching process can be performed on the first semiconductor layer 110 to remove only the first semiconductor layer 110 without removing the first semiconductor patterns S1 and S2. The etching process is based on the fact that silicon-germanium with a relatively high germanium concentration can have a high etching rate compared to silicon-germanium with a low germanium concentration. For example, for silicon-germanium with a germanium concentration greater than 10 at% , the etching process can have a high etching rate. In one or more embodiments, the first semiconductor layer 110 may be selectively etched using a wet etchant, which is not limited to ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution.

[0146] refer to Figure 12A and Figure 12B A gate insulating layer GI can be conventionally formed in the internal region IR and the external region OR exposed on the active pattern AP.

[0147] The gate insulating layer GI may include an interface layer and a high-k dielectric layer located on the interface layer. In one or more embodiments, the high-k dielectric layer may be thicker than the interface layer. The interface layer may include a silicon oxide or silicon oxynitride layer. The high-k dielectric layer may include a high-k dielectric material having a higher dielectric constant than silicon oxide. For example, the high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0148] The gate insulating layer GI can be formed using atomic layer deposition (ALD), chemical vapor deposition (CVD), or other suitable methods.

[0149] refer to Figure 13A and Figure 13B A gate electrode GE can be formed on the gate insulating layer GI. The gate electrode GE can be formed as a portion filling the inner region IR and the outer region OR. The gate electrode GE can include portions formed in the inner region IR and portions formed in the outer region OR, respectively. The gate electrode GE can include a first gate electrode GE1 located between the first source / drain patterns SD1 and a second gate electrode GE2 located between the second source / drain patterns SD2, and the first gate electrode GE1 and the second gate electrode GE2 can be formed simultaneously in a single process. The first gate electrode GE1 and the second gate electrode GE2 can be formed integrally without separation.

[0150] A gate cover pattern 160 can be formed on the gate electrode. The gate cover pattern 160 can fill the space between paired gate spacers GS. The upper surface of the gate cover pattern 160 can be substantially coplanar with the upper surfaces of the gate spacers GS and the protective insulating pattern 150. The gate cover pattern 160 can include SiN.

[0151] refer to Figure 14A and Figure 14B A second interlayer insulating layer 170 may be formed on the gate cover pattern 160. The second interlayer insulating layer 170 may cover the protective insulating pattern 150 and the gate spacer GS. The second interlayer insulating layer 170 may include silicon oxide.

[0152] At least one contact for electrical connection to other components is formed in a first source / drain pattern SD1 and / or a second source / drain pattern SD2. The contact may include a first contact CT1 and a second contact CT2, the first contact CT1 being perpendicularly connected to at least one first source / drain pattern SD1, and the second contact CT2 being perpendicularly connected to at least one second source / drain pattern SD2. In one or more embodiments, the first contact CT1 may be formed first, and then the second contact CT2 may be formed. However, the embodiments are not limited thereto, and the second contact CT2 may be formed first, and then the first contact CT1 may be formed. Alternatively, a portion of the process for forming the first contact CT1 and a portion of the process for forming the second contact CT2 may be performed simultaneously. Hereinafter, for clarity, an example of forming the first contact CT1 first and then the second contact CT2 is provided.

[0153] refer to Figure 14A and Figure 14BA third groove RC3 can be formed in the first source / drain pattern SD1 and the second source / drain pattern SD2, which are vertically stacked on the active pattern AP. The third groove RC3 can penetrate the second source / drain pattern SD2 and the additional isolation pattern 135 vertically, and can have a shape that is recessed vertically downward from the upper surface of the first source / drain pattern SD1.

[0154] For example, the third groove RC3 can vertically penetrate the second interlayer insulating layer 170, the protective insulating pattern 150, the gate cover pattern 160, the second source / drain pattern SD2, and the additional isolation pattern 135, and can have a shape that is recessed vertically downward from the upper surface of the first source / drain pattern SD1.

[0155] The third groove RC3 can have a diameter that varies in the vertical direction. The diameter of the third groove RC3 can decrease from the top to the bottom in the vertical direction. The diameter variation of the third groove RC3, depending on its vertical position, may be due to process margins or may be intended by the design. When the groove is formed in a vertically elongated shape, the diameter of the groove can decrease downwards due to the difference in etching rates between the upper and lower portions.

[0156] In one or more embodiments, the third groove RC3 may be formed having a diameter smaller than that of the second epitaxial layer SD2b in the second source / drain pattern SD2, and may be disposed within the second epitaxial layer SD2b in the second source / drain pattern SD2. A portion of the second epitaxial layer SD2b may be exposed to the outside. However, the shape of the third groove RC3 is not limited thereto, and the third groove RC3 may be formed having a diameter larger than that of the second epitaxial layer SD2b in the second source / drain pattern SD2. The third groove RC3 may be formed within the first epitaxial layer SD2a in the second source / drain pattern SD2, and a portion of the first epitaxial layer SD2a may be exposed. Furthermore, even when the third groove RC3 is formed having a diameter smaller than that of the second epitaxial layer SD2b in the second source / drain pattern SD2, a portion of the location may be offset within process tolerances. At least a portion of the third groove RC3 may be formed within the first epitaxial layer SD2a in the second source / drain pattern SD2. In one or more embodiments, the third groove RC3 may be formed in the second epitaxial layer SD1b in the second epitaxial layer SD2b and / or the first source / drain pattern SD1.

[0157] In one or more embodiments, forming the third groove RC3 may result in excessive removal of the second epitaxial layer SD2b in the second source / drain pattern SD2. Therefore, only a small amount of the second epitaxial layer SD2b may be retained, or the second epitaxial layer SD2b may be removed substantially entirely, and only the first epitaxial layer SD2a may be retained. In the case where only a small amount of the second epitaxial layer SD2b is retained in the third groove RC3, or the second epitaxial layer (SD2b) is substantially removed and only the first epitaxial layer SD2a is retained, the contact resistance between the first contact CT1 and the second source / drain pattern SD2 may increase when the first contact CT1 is subsequently formed.

[0158] In one or more embodiments of the present invention, a process is performed to form a relatively heavily doped third epitaxial layer SD2c to reduce the contact resistance between the first contact CT1 and the second source / drain pattern SD2.

[0159] refer to Figure 15 A first sacrificial insulating layer SL1 can be formed in the third groove RC3. The first sacrificial insulating layer SL1 can correspond to the pattern that temporarily protects the first source / drain pattern SD1 through a subsequent partial etching process.

[0160] The first sacrificial insulating layer SL1 can be formed of silicon oxide. However, the material of the first sacrificial insulating layer SL1 is not limited to this, and other materials can be used, as long as they can temporarily protect the first source / drain pattern SD1 through a partial etching process.

[0161] The first sacrificial insulating layer SL1 can have a thickness that varies depending on the vertical position. For example, the first sacrificial insulating layer SL1 can have a thickness that increases from top to bottom in the vertical direction. The thickness of the first sacrificial insulating layer SL1 refers to the thickness in the vertical direction starting from the surface of the third groove RC3. The third groove RC3 has a diameter that decreases in the direction from top to bottom, such that the first sacrificial insulating layer SL1 can be formed to have a greater thickness in the downward direction. For example, the thickness of the first sacrificial insulating layer SL1 on the first source / drain pattern SD1 can be greater than the thickness of the first sacrificial insulating layer SL1 on the second source / drain pattern SD2. If the thickness of the first sacrificial insulating layer SL1 on the first source / drain pattern SD1 is a first thickness W1, and the thickness of the first sacrificial insulating layer SL1 on the second source / drain pattern SD2 is a second thickness W2, then the first thickness W1 can be greater than the second thickness W2.

[0162] refer to Figure 16A portion of the first sacrificial insulating layer SL1 is removed to form the second sacrificial insulating layer SL2. The first sacrificial insulating layer SL1 can be etched until a portion of the first sacrificial insulating layer SL1 on the first source / drain pattern SD1 is retained and the first sacrificial insulating layer SL1 on the second source / drain pattern SD2 is completely removed. The etching of the first sacrificial insulating layer SL1 can be performed isotropically or anisotropically. The thickness of the first sacrificial insulating layer SL1 on the first source / drain pattern SD1 is greater than its thickness on the second source / drain pattern SD2, such that even if the first sacrificial insulating layer SL1 is etched, the first sacrificial insulating layer SL1 on the second source / drain pattern SD2 can be removed without removing a portion of the first sacrificial insulating layer SL1 on the first source / drain pattern SD1.

[0163] The etching of a portion of the first sacrificial insulating layer SL1 can be performed using dry etching. For example, a portion of the first sacrificial insulating layer SL1 can be removed using plasma dry etching. Dry etching methods can include dry etching under various conditions (e.g., plasma-assisted dry etching known as SiCoNi etching).

[0164] refer to Figure 17 A third epitaxial layer SD2c can be formed in the third groove RC3. The third epitaxial layer SD2c can be epitaxially grown from the second source / drain pattern SD2 in the horizontal direction and can protrude into the inside of the third groove RC3.

[0165] The inner wall of the second source / drain pattern SD2 exposed by the third groove RC3 can be used as a seed to selectively grow the third epitaxial layer SD2c. For example, the inner wall of the first epitaxial layer SD2a and / or the second epitaxial layer SD2b exposed by the third groove RC3 can be used as a seed to selectively grow the third epitaxial layer SD2c.

[0166] In one or more embodiments, the selective epitaxial growth process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process. The first source / drain pattern SD1 is covered by a second sacrificial insulating layer SL2, preventing epitaxial growth from occurring. In one or more embodiments, a third epitaxial layer SD2c may be formed using a process substantially identical to the second SEG process.

[0167] The third epitaxial layer SD2c can contain a relatively high concentration of germanium. For example, the germanium concentration of the third epitaxial layer SD2c can be from about 20 at% to about 100 at%, for example, from about 30 at% to about 70 at%. During the formation of the third epitaxial layer SD2c, impurities can be implanted in situ into the second source / drain pattern SD2. For example, impurities can be implanted into the third epitaxial layer SD2c after its formation.

[0168] In one or more embodiments of the present invention, N-type impurities may be highly doped into the pattern of the third epitaxial layer SD2c. For example, the N-type impurity may be phosphorus, arsenic, or antimony.

[0169] The impurity concentration of the third epitaxial layer SD2c can be higher than that of the first epitaxial layer SD2a and / or the second epitaxial layer SD2b. Alternatively, the impurity concentration of the third epitaxial layer SD2c can be substantially the same as that of the second epitaxial layer SD2b.

[0170] Due to the formation of the third epitaxial layer SD2c, the third groove RC3 can have a diameter that varies depending on its vertical position. Therefore, the third groove RC3 can have a bottleneck shape. For example, the diameter of the third groove RC3 can have different values ​​depending on its vertical height in the upward direction from the substrate 100. If the diameter of the third groove RC3 at a point on the first source / drain pattern SD1 is a first diameter D1, and the diameter of the third groove RC3 at a point on the second source / drain pattern SD2 is a second diameter D2, then the second diameter D2 can be smaller than the first diameter D1. Furthermore, if the diameter of the third groove RC3 at a point on the first interlayer insulating layer 140 is a third diameter D3, then the second diameter D2 can be smaller than the third diameter D3.

[0171] refer to Figure 18 The second sacrificial insulating layer SL2 on the first source / drain pattern SD1 can be removed. The second sacrificial insulating layer SL2 can be removed by various methods such as dry etching or wet etching. For example, the second sacrificial insulating layer SL2 can be removed by dry etching. For example, plasma dry etching can be used to remove the second sacrificial insulating layer SL2. For example, dry etching can include plasma-assisted dry etching known as SiCoNi etching. Removing the second sacrificial insulating layer SL2 can result in the exposure of the upper surface of the first source / drain pattern SD1 within the third recess RC3.

[0172] Next, an ohmic contact layer OCT can be selectively formed on the first source / drain pattern SD1 and the second source / drain pattern SD2 exposed in the third groove RC3. The ohmic contact layer OCT can be formed to subsequently have low contact resistance between the contact and the first source / drain pattern SD1 and / or the second source / drain pattern SD2. The ohmic contact layer OCT may include a metal silicide. In one or more embodiments, the metal silicide may be formed of a material such as CoSi, NiSi, TiSi, NiPtSi, or NiTiSi. The ohmic contact layer OCT can be selectively formed only on the first source / drain pattern SD1 and the second source / drain pattern SD2 by forming a metal layer, performing annealing, and then removing the remaining metal.

[0173] refer to Figure 19 Conductive material can be formed in the third groove RC3 to form the first contact CT1.

[0174] There are no limitations on the method for forming the conductive material in the third groove RC3, and various methods can be used. For example, the operation of forming the conductive material in the third groove RC3 can be performed by chemical vapor deposition.

[0175] The first contact CT1 may be formed from a single conductive material, but the embodiments are not limited thereto. The first contact CT1 may include a variety of conductive materials. The conductive materials may include metals and / or metal nitrides. The metal may be selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. The metal nitride may be selected from TiN or TaN.

[0176] The first contact CT1 can be formed with a multilayer structure. In one or more embodiments, the first contact CT1 can have a two-layer or three-layer structure. When the first contact CT1 has a two-layer structure, the first conductive layer M1 can be a barrier layer, and the second conductive layer M2 can be a contact plug disposed on the barrier layer. When the first contact CT1 has a three-layer structure, the first contact CT1 may include a first conductive layer M1, a second conductive layer M2, and a third conductive layer M3. At least one of the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3 may include a material different from the material of the remaining layers. In one or more embodiments, the first conductive layer M1 may include titanium, the second conductive layer M2 may include titanium nitride, and the third conductive layer M3 may include cobalt.

[0177] refer to Figure 20Additional recesses, such as a fourth recess RC4, can be formed in the second source / drain pattern SD2. The fourth recess RC4 can have a shape that is recessed vertically downward from the upper surface of the second source / drain pattern SD2. For example, the fourth recess RC4 can penetrate the second interlayer insulating layer 170, the protective insulating pattern 150, and the gate cover pattern 160, and can have a shape that is recessed vertically downward from the upper surface of the second source / drain pattern SD2.

[0178] The fourth groove RC4 may also have a diameter that decreases from top to bottom in the vertical direction. However, the vertical depth of the fourth groove RC4 is less than the vertical depth of the third groove RC3, so that the diameter difference of the fourth groove RC4 according to the vertical position can be relatively smaller than the diameter difference of the third groove RC3.

[0179] In one or more embodiments, the fourth groove RC4 may be formed in the second epitaxial layer SD2b of the second source / drain pattern SD2. In one or more embodiments, the fourth groove RC4 may also be formed in the first epitaxial layer SD2a of the second source / drain pattern SD2.

[0180] In one or more embodiments, the fourth groove RC4 may not have a bottleneck shape, but the embodiments are not limited thereto. Similar to the third groove RC3, the fourth groove RC4 may also have a bottleneck shape. An additional third epitaxial layer SD2c may be formed from the second source / drain pattern SD2.

[0181] refer to Figure 21 An ohmic contact layer OCT can be selectively formed on the second source / drain pattern SD2 exposed in the fourth recess RC4. The ohmic contact layer OCT may include a metal silicide. By forming a metal layer, performing annealing, and then removing the remaining metal, the ohmic contact layer OCT can be selectively formed only on the second source / drain pattern SD2. A conductive material is formed in the fourth recess RC4 to form the second contact CT2.

[0182] There are no limitations on the method for forming the conductive material in the fourth groove RC4, and various methods can be used. For example, the formation of the conductive material in the fourth groove RC4 can be performed by chemical vapor deposition.

[0183] The second contact CT2 may be formed from a single conductive material, but the embodiments are not limited thereto. The second contact CT2 may include a variety of conductive materials. The conductive materials may include metals and / or metal nitrides. The metal may be selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. The metal nitride may be selected from TiN or TaN.

[0184] The second contact CT2 can be formed with a multilayer structure. In one or more embodiments, the second contact CT2 may include a first conductive layer M1, a second conductive layer M2, and a third conductive layer M3. At least one of the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3 may include a material different from the materials of the remaining layers. In one or more embodiments, the first conductive layer M1 may include titanium, the second conductive layer M2 may include titanium nitride, and the third conductive layer M3 may include cobalt.

[0185] In one or more embodiments, the second contact CT2 may comprise substantially the same material as the first contact CT1 and may be formed to have substantially the same shape as the first contact CT1.

[0186] As described above, according to the embodiments, the contact resistance between the source / drain electrodes and the contacts of the field-effect transistor can be reduced to ensure the stable performance of the field-effect transistor. Therefore, the reliability of the semiconductor device can be improved.

[0187] While various embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: A first source / drain pattern is located on a substrate and is disposed at a first height in a substantially vertical direction; A first channel pattern, the first channel pattern being connected to the first source / drain pattern; The second source / drain pattern is disposed at a second height higher than the first height; The second channel pattern is connected to the second source / drain pattern; A gate electrode, the gate electrode being located on the first channel pattern and the second channel pattern; and The contact is substantially perpendicularly connected to at least one of the first source / drain pattern and the second source / drain pattern. in: The contact is configured in a bottleneck shape, the diameter of which at the second height is smaller than its diameter at heights other than the second height.

2. The semiconductor device according to claim 1, wherein: The contact includes a first contact, which is connected to at least one of the first source / drain patterns in the first source / drain pattern; and The first contact has a first diameter at the first height and a second diameter at the second height that is smaller than the first diameter.

3. The semiconductor device according to claim 2, wherein: The first contact penetrates substantially perpendicularly through at least one of the second source / drain patterns in the second source / drain pattern to connect to at least one of the first source / drain patterns in the first source / drain pattern.

4. The semiconductor device according to claim 2, wherein: The first contact has a third diameter at a third height above the second height, wherein the third diameter is larger than the second diameter.

5. The semiconductor device according to claim 2, wherein: At least one of the second source / drain patterns is epitaxially grown in a substantially horizontal direction to protrude toward the contact.

6. The semiconductor device according to claim 2, further comprising: An ohmic contact layer is disposed between the second source / drain pattern and the contact.

7. The semiconductor device according to claim 1, wherein: Each of the second source / drain patterns includes a first epitaxial layer and a second epitaxial layer with different impurity concentrations.

8. The semiconductor device according to claim 7, wherein: In each of the second source / drain patterns, the impurity concentration of the second epitaxial layer is higher than that of the first epitaxial layer.

9. The semiconductor device according to claim 8, wherein: At least one of the second source / drain patterns includes a third epitaxial layer that is epitaxially grown from the first epitaxial layer and / or the second epitaxial layer in a substantially horizontal direction to protrude toward the contact.

10. The semiconductor device according to claim 9, wherein: The impurity concentration of the third epitaxial layer is higher than or equal to the impurity concentration of the second epitaxial layer.

11. The semiconductor device according to claim 1, wherein: The contact also includes a second contact that is connected to the second source / drain pattern.

12. The semiconductor device according to claim 1, further comprising: A gate insulating layer is disposed between the gate electrode and the first channel pattern and between the gate electrode and the second channel pattern.

13. The semiconductor device according to claim 12, wherein: The first source / drain pattern, the first channel pattern, and the gate electrode form a first transistor; The second source / drain pattern, the second channel pattern, and the gate electrode form a second transistor; and One of the first transistor and the second transistor is an NMOS transistor, and the other of the first transistor and the second transistor is a PMOS transistor.

14. The semiconductor device according to claim 13, wherein: The first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

15. The semiconductor device according to claim 1, further comprising: An intermediate isolation pattern is disposed between the first channel pattern and the second channel pattern.

16. The semiconductor device according to claim 1, wherein: The first source / drain pattern and the second source / drain pattern overlap in the substantially vertical direction.

17. The semiconductor device according to claim 1, wherein: At least one of the first channel pattern and the second channel pattern comprises a plurality of semiconductor patterns that are substantially vertically stacked and spaced apart from each other.

18. The semiconductor device according to claim 17, wherein: The gate electrode surrounds each of the semiconductor patterns in the respective channel patterns of the first channel pattern and the second channel pattern.

19. A contact structure, the contact structure comprising: First source / drain pattern; The second source / drain pattern is stacked on the first source / drain pattern; and The contact penetrates the second source / drain pattern and is disposed in a groove recessed from the upper surface of the first source / drain pattern; in: The contact is configured with a bottleneck structure having a first diameter at the height of the first source / drain pattern and a second diameter smaller than the first diameter at the height of the second source / drain pattern.

20. A semiconductor device, the semiconductor device comprising: A first transistor, the first transistor being disposed on a substrate and including a first source / drain pattern; The second transistor is stacked on the first transistor and includes a second source / drain pattern that overlaps with the first source / drain pattern; and The contact is configured to be substantially perpendicular to the first source / drain pattern and the second source / drain pattern. in: The second source / drain pattern includes: A first epitaxial layer, wherein the first epitaxial layer has a first impurity concentration; A second epitaxial layer, wherein the second epitaxial layer has a second impurity concentration higher than the first impurity concentration; and A third epitaxial layer protrudes inward from the contact and has a third impurity concentration higher than the first impurity concentration; and The diameter of the contact in the region where the third epitaxial layer is disposed is smaller than the diameter in other regions adjacent to the region.

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