Semiconductor device and method of formation

Abstract

Semiconductor devices including electrostatic discharge (ESD) protection circuits are disclosed. An exemplary ESD protection circuit includes a trigger configuration coupled between reference voltage nodes to provide an ESD event indication, a first clamp configuration including a first clamp transistor coupled between the reference voltage nodes to activate in response to the ESD event indication, and a second clamp configuration including a second clamp transistor coupled in parallel with the first clamp transistor between the reference voltage nodes to activate concurrently in response to the ESD event indication.

Description

Technical Field

[0001] This disclosure relates to an apparatus and a method, and more particularly to a semiconductor apparatus and a method of forming it. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are susceptible to damage due to electrostatic discharge (ESD) events. Therefore, integrated circuits and other electronic devices include circuits that provide protection against excessive voltage and / or current during ESD events. Summary of the Invention

[0003] This disclosure discloses a semiconductor device comprising: a first interface coupled to a first reference voltage node; a second interface coupled to a second reference voltage node; a trigger configuration coupled between the first and second reference voltage nodes to provide an indication of a discharge event at an output node of the trigger configuration; a first clamping configuration including a first clamping transistor coupled between the first and second reference voltage nodes, wherein the first clamping configuration is configured to activate the first clamping transistor in response to the indication of the discharge event at the output node; and a second clamping configuration including a second clamping transistor coupled between the first and second reference voltage nodes, wherein the second clamping configuration is configured to activate the second clamping transistor in response to the indication of the discharge event at the output node.

[0004] This disclosure discloses a method of manufacturing a semiconductor device, comprising: forming a first trigger configuration coupled between a first reference voltage node coupled to a first interface and a second reference voltage node coupled to a second interface to provide a first indication of a discharge event at a first output node of the first trigger configuration; forming a first clamping configuration including a first clamping transistor; coupling the first clamping transistor of the first clamping configuration to the first trigger configuration, located between the first reference voltage node and the second reference voltage node; forming a second trigger configuration coupled between the first reference voltage node and the second reference voltage node to provide a second indication of the discharge event at a second output node of the second trigger configuration; forming a second clamping configuration including a second clamping transistor; and coupling the second clamping transistor of the second clamping configuration to the second trigger configuration, located between the first reference voltage node and the second reference voltage node.

[0005] This disclosure discloses a method of manufacturing a semiconductor device, comprising: coupling a first trigger configuration between a first reference voltage node and a second reference voltage node to provide a first indication of a discharge event at a first output node of the first trigger configuration; coupling a first clamping configuration to the first trigger configuration, the first clamping configuration including a first clamping transistor coupled between the first reference voltage node and the second reference voltage node, wherein the first clamping configuration is configured to activate the first clamping transistor in response to the first indication of the discharge event at the first output node; coupling a second trigger configuration between the first reference voltage node and the second reference voltage node to provide a second indication of the discharge event at a second output node of the second trigger configuration; and coupling a second clamping configuration to the second trigger configuration, the second clamping configuration including a second clamping transistor coupled between the first reference voltage node and the second reference voltage node, wherein the second clamping configuration is configured to activate the second clamping transistor in response to the second indication of the discharge event at the second output node. Attached Figure Description

[0006] The various aspects of this disclosure are best understood when read in conjunction with the following detailed description and accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A block diagram of a semiconductor device including electrostatic discharge (ESD) protection circuitry according to one or more embodiments; Figure 2-18 Suitable for use in various embodiments Figure 1 Schematic diagrams of different implementations of discharge protection circuits in ESD protection circuits of semiconductor devices; and Figure 19 A flowchart illustrating a process for manufacturing a semiconductor device according to various embodiments. Detailed Implementation

[0008] The following disclosure provides many different embodiments or examples to implement various features of the provided inventive subject matter. Specific examples of elements and configurations are described below to simplify the disclosure. Of course, these are merely examples and not intended to be limiting.

[0009] For the sake of brevity, conventional techniques associated with the fabrication of conventional semiconductor devices may not be described in detail herein. Furthermore, the various tasks and processes described herein can be incorporated into more comprehensive procedures or processes with additional functionality not described in detail herein. In particular, various processes in the fabrication of semiconductor devices are well-known; therefore, for the sake of brevity, many conventional processes will be mentioned only briefly or omitted entirely without providing well-known process details. As will be readily apparent to those skilled in the art upon a full reading of this disclosure, the structures disclosed herein can be used with various techniques and incorporated into various semiconductor devices and products. Furthermore, it should be noted that semiconductor device structures include varying numbers of elements, and a single element shown in the figures may represent multiple elements.

[0010] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, parts, and / or segments, these elements, components, regions, layers, parts, and / or segments should not be limited to these terms. These terms are used only to distinguish one element, component, region, layer, part, or segment from another. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, part, or segment discussed below may be referred to as the second element, component, region, layer, part, or segment.

[0011] Furthermore, for ease of explanation, this document may use spatial relative terms such as "over," "overlying," "above," "upper," "top," "under," "underlying," "below," "lower," and "bottom" to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein may be interpreted accordingly. When spatial relative terms (such as those listed above) are used to describe a first element relative to a second element, the first element may be directly on the other element, or there may be intervening elements or layers.

[0012] Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. This repetition is for the purpose of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] It should be noted that references to "one embodiment," "an embodiment," "an example embodiment," "exemplary," "example," etc., in the specification indicate that the described embodiment may include specific features, structures, or characteristics, but each embodiment may not need to include specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, its effect in conjunction with other embodiments on that feature, structure, or characteristic will be within the knowledge of those skilled in the art.

[0014] It should be understood that the wording or terminology used herein is for descriptive purposes and not restrictive, and that the terminology or terminology used herein should be interpreted by those skilled in the art based on the teachings herein.

[0015] The following disclosure provides numerous different embodiments or examples to implement different features of the disclosed object. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. Throughout this description, unless otherwise specified, the same reference numerals in different figures refer to the same or similar components formed using the same or similar materials and by the same or similar methods.

[0016] Figure 1 A block diagram depicts an exemplary semiconductor device 100 according to one or more exemplary embodiments. The semiconductor device 100 includes protection circuitry 102 and functional circuitry 104, which are fabricated on one or more semiconductor substrates and packaged in a common device package or integrated circuit to obtain the semiconductor device 100. The illustrated semiconductor device 100 includes a first input interface 106 (e.g., pins, pads, terminals, etc.) for receiving a positive or supply reference DC voltage (e.g., VDD) and a second input interface 108 for receiving a negative or ground reference DC voltage (e.g., VSS). It should be understood that... Figure 1 This is a simplified representation of the semiconductor device 100, used for purposes of explanation and ease of description, and Figure 1 It is not intended to limit the application or scope of the subject matter in any way. Therefore, although Figure 1 Depicting direct electrical connections between components, alternative embodiments may employ intervening circuit elements and / or components, operating in a substantially similar manner. Actual embodiments of the semiconductor device 100 will also include one or more additional input / output (I / O) interfaces (e.g., pins, pads, terminals, etc.) configured to support communication between external devices, components, or systems and the functional circuitry 104 of the semiconductor device 100.

[0017] Functional circuit 104 generally refers to a component in semiconductor device 100 configured to provide the required functions for semiconductor device 100. In this regard, functional circuit 104 may be implemented as processing circuitry (e.g., one or more processing cores, processors, controllers, microcontrollers, microprocessors, etc.), logic circuitry, memory or other data storage elements, discrete components, analog and / or digital components, or other hardware components and / or any suitable combination of circuitry, configured to provide the required functions for a particular application. For example, in one or more embodiments, functional circuit 104 is implemented as a power management integrated circuit (PMIC) associated with a thin-film transistor (TFT) display system or module (e.g., light-emitting diode (LED) display, liquid crystal display (LCD), etc.), wherein the input DC voltage between input interfaces 106, 108 is greater than 5 volts and corresponds to the nominal input DC voltage of the TFT display system (e.g., 12 volts, 24 volts, etc.). That is, the subject matter described herein is not limited to any particular type or configuration of functional circuit 104 or any particular nominal input DC voltage associated with input interfaces 106, 108.

[0018] Protection circuit 102 typically refers to a component in semiconductor device 100 configured to detect or otherwise identify an ESD event and conduct a discharge current through protection circuit 102 between supply and ground reference voltage nodes, thereby protecting functional circuitry 104 from potentially damaging discharge currents or voltages. As described in more detail below, in an exemplary embodiment, protection circuit 102 includes a trigger configuration configured to detect or otherwise identify an ESD event based on voltage detection at one of the reference voltage nodes and activate a clamping configuration configured to conduct current between reference voltage nodes in response to the ESD event, thereby clamping the voltage difference between the reference voltage nodes.

[0019] Figure 2 An exemplary embodiment of the discharge protection circuit 200 is depicted, suitable for use as... Figure 1Protection circuit 102 in semiconductor device 100. Discharge protection circuit 200 includes RC trigger configuration 206 coupled between a positive or supply reference voltage node 202 (which may be coupled to input interface 106) and a negative reference voltage node 204 (which may be coupled to input interface 108). RC trigger configuration 206 is configured to detect or otherwise identify an ESD event based on the voltage difference between the respective nodes 202, 204, and provide a corresponding indication at output node 208. In this regard, RC trigger configuration 206 includes a resistive element 210 coupled between the positive reference voltage node 202 and output node 208, and a capacitive element 212 coupled between output node 208 and negative reference voltage node 204, such that the capacitive element 212 responds to an ESD event by pulling the voltage at output node 208 down or toward the negative reference voltage (VSS), but otherwise maintains the voltage at output node 208 closer to the positive reference voltage (VDD) during normal operation without an ESD event.

[0020] In practical applications, resistor element 210 can be implemented using any type of resistor assembly or structure, including but not limited to titanium nitride (TiN) resistor structures, polycrystalline silicon oxide (PO) resistor structures, N-well resistor structures, or another suitable resistor structure fabricated on a semiconductor substrate associated with protection circuit 200. Similarly, capacitor element 212 can be implemented using any type of capacitor assembly or structure, including but not limited to metal-insulator-metal (MiM) capacitors, metal-oxide-metal (MOM) capacitors, N-type metal-oxide-semiconductor (NMOS) capacitors, or another suitable capacitor structure fabricated on a semiconductor substrate associated with protection circuit 200.

[0021] exist Figure 2 In one embodiment, the protection circuit 200 includes a plurality of clamping configurations 220, 230, 240, each clamping configuration being coupled to an ESD trigger output node 208 and configured to be electrically parallel to each other in response to an indication of an ESD event at the ESD trigger output node 208, providing a parallel path via respective clamping transistors 226, 236, 246. In an exemplary embodiment, the clamping configurations 220, 230, 240 are substantially identical (e.g., within manufacturing tolerances and variations) or otherwise equivalent to each other to uniformly distribute discharge current and / or ESD voltage spikes among the clamping configurations 220, 230, 240.

[0022] The first clamping configuration 220 includes a complementary metal-oxide-semiconductor (CMOS) inverter configuration 221 having an input coupled to an ESD trigger output node 208, and the CMOS inverter configuration 221 is configured to provide a logical inversion of the signal at the ESD trigger output node 208 at the inverter output node 228. The CMOS inverter configuration 221 includes a PMOS transistor 222 having a source coupled to a positive reference voltage node 202, a body coupled to a positive reference voltage node 202, a drain coupled to an inverter output node 228, and a gate coupled to an ESD trigger output node 208; and an NMOS transistor 224 having a drain coupled to an inverter output node 228, a gate coupled to an ESD trigger output node 208, a source coupled to a negative reference voltage node 204, and a body coupled to a negative reference voltage node 204. The inverter output node 228 is connected to the gate of the clamped NMOS transistor 226, which has a drain coupled to the positive reference voltage node 202, a source coupled to the negative reference voltage node 204, and a body coupled to the negative reference voltage node 204.

[0023] When an ESD event causes a transient voltage difference between reference voltage nodes 202 and 204, capacitor element 212 of RC trigger configuration 206 is effectively short-circuited, allowing inrush current through resistor element 210. This, in turn, creates a voltage drop across resistor element 210, causing RC trigger configuration 206 to effectively pull the voltage at output node 208 down or toward the negative reference voltage (VSS) in response to the ESD event. When output node 208 is pulled toward the negative reference voltage (VSS), PMOS transistor 222 of CMOS inverter configuration 221 is actively or otherwise activated, thereby pulling the voltage at inverter output node 228 up or toward the positive reference voltage (VDD). As a result, clamping NMOS transistor 226 is turned on or otherwise activated to conduct at least a portion of the ESD discharge current between reference voltage nodes 202 and 204. In a similar manner, when the RC trigger configuration 206 pulls the voltage at output node 208 toward the negative reference voltage (VSS) in response to an ESD event, the respective inverter configurations 231 and 241 of the other clamping configurations 230 and 240 turn on or otherwise activate their respective clamping NMOS transistor instances 236 and 246, simultaneously with the first clamping NMOS transistor 226, to conduct their respective ESD discharge current portions between reference voltage nodes 202 and 204 in parallel with the clamping NMOS transistor 226.

[0024] By distributing the ESD discharge current across multiple clamping transistor instances 226, 236, and 246, the size of each clamping transistor instance 226, 236, and 246 can be reduced, allowing the clamping transistors 226, 236, and 246 to conduct and respond more quickly to relatively short ESD events (e.g., charged device model (CDM) ESD pulses of 1 nanosecond or less). In this regard, when individual clamping transistors are used for nominal voltages in the range of approximately 12 volts to approximately 48 volts between reference nodes 202 and 204, the thickness of the gate oxide or other gate insulator is increased to a thickness in the range of approximately 50 nanometers (nm) to approximately 120 nm to achieve the required gate oxide integrity to prevent gate oxide breakdown and improve reliability. This increases the threshold voltage of the individual clamping transistor to a voltage in the range of approximately 3 volts to approximately 5 volts, which in turn increases the amount of time required for the voltage at the gate terminal to exceed the threshold voltage. Therefore, for relatively short CDM ESD events of 1 nanosecond or less, the time period during which the voltage at the gate terminal exceeds the threshold voltage may be reduced, resulting in individual clamped transistors not being fully turned on and unable to completely dissipate discharge current as the duration of the ESD event decreases. Furthermore, the total width of individual clamped transistors perpendicular to the current flow direction is increased to approximately 10,000 micrometers or in the range of micrometers (µm) to approximately 40,000 µm to achieve lower resistance and prevent failure during ESD events. Conversely, by... Figure 2 The embodiments utilize multiple parallel clamping transistors 226, 236, and 246, each with a reduced device width. This allows the clamping transistors 226, 236, and 246 to turn on faster than individual clamping transistors to effectively discharge short-duration ESD events, with the discharge current distributed or distributed across the parallel clamping transistors 226, 236, and 246. For example, in the illustrated embodiment including three parallel clamping transistors 226, 236, and 246, the total width of the clamping transistors 226, 236, and 246 can be reduced to approximately 1500 µm to approximately 4000 µm, thereby reducing the amount of time required to turn on each individual clamping transistor 226, 236, and 246.

[0025] In addition to reducing the dimensions of clamping transistors 226, 236, and 246 (e.g., gate insulator thickness and device width), the dimensions of the respective transistors in the respective inverter configurations 221, 231, and 241 can also be reduced accordingly. For example, the total width of the PMOS transistors associated with the respective inverter configurations 221, 231, and 241 (e.g., PMOS transistor 222 associated with inverter configuration 221) can be in the range of about 100µm to about 600µm, relative to the total width of the corresponding PMOS transistors in the individual clamping transistor configurations of about 1500µm to about 4000µm. Similarly, the total width of the NMOS transistors associated with the respective inverter configurations 221, 231, and 241 (e.g., NMOS transistor 224 associated with inverter configuration 221) can be in the range of about 10µm to about 100µm, relative to the total width of the corresponding NMOS transistors in the individual clamping transistor configurations of about 1500µm to about 4000µm. Since the NMOS transistors in the respective inverter configurations 221, 231, and 241 are effectively open or inactive during an ESD event, the size of the NMOS transistors can be smaller than that of the PMOS transistors, which are active during ESD events and responsible for pulling high the inverter output node 228 coupled to the gates of the respective parallel clamping transistors 226, 236, and 246. In this respect, the size of the PMOS transistors can be increased relative to the NMOS transistors to reduce the response time associated with turning on the respective parallel clamping transistors 226, 236, and 246 and to avoid the collapse of the PMOS transistors during an ESD event.

[0026] It should be noted that the discharge protection circuit 200 reduces effective resistance and achieves faster and more efficient turn-on by using parallel clamping transistors 226, 236, and 246 to dissipate current during ESD events, thereby providing improved short-CDM ESD performance. Furthermore, it should be noted that in practice, different regions or locations on the die or substrate associated with the semiconductor device 100 may have different design specifications or priorities. For example, general purpose input / output (GPIO) circuit regions closer to I / O interfaces 106, 108 may prioritize ESD performance due to proximity to and / or exposure to ESD events and the resulting discharge current, while digital-to-analog converter (DAC) design regions or other areas on the die or substrate farther from I / O interfaces 106, 108 may be more sensitive to area usage and prioritize density over ESD performance. In this regard, the discharge protection circuit 200 may be suitable for use at a location on a die or substrate associated with the semiconductor device 100 corresponding to an intermediate region (e.g., a logic region or other digital operation region), where density is not a priority but improved CDM ESD performance is required.

[0027] Figure 3 An exemplary embodiment of the discharge protection circuit 300 is depicted, suitable for use as... Figure 1 The protection circuit 102 in the semiconductor device 100. Similar to Figure 2 In one embodiment, the discharge protection circuit 300 includes a plurality of parallel clamping configurations 220, 230, 240, each having its own clamping transistors 226, 236, 246. Figure 3 In the discharge protection circuit 300 embodiment, the inputs of the CMOS inverter configurations 221, 231, and 241 of the respective clamping configurations 220, 230, and 240 are coupled to the output nodes of the respective instances of the RC trigger configurations 206, 302, and 304. In this respect, relative to... Figure 2 The respective additional RC trigger configurations 302 and 304 associated with clamp configurations 230 and 240 are substantially the same (e.g., contain devices of the same type and / or size) or otherwise equivalent to the RC trigger configuration 206 associated with the first clamp configuration 220, to uniformly distribute discharge current and / or ESD voltage spikes, such that the parallel clamp configurations 220, 230, and 240 respond to ESD events in substantially the same time and in substantially the same manner, such that the respective clamp transistors 226, 236, and 246 simultaneously activate to conduct discharge current in a distributed manner.

[0028] It should be noted that discharge protection circuit 300 may provide improved 250-volt CDM ESD performance compared to discharge protection circuit 200 because each clamping configuration 220, 230, 240 has its own RC trigger configuration 206, 302, 304, which can be designed or otherwise configured to improve the conduction or ESD performance of the respective clamping configuration 220, 230, 240. Therefore, discharge protection circuit 300 can be used in the GPIO circuit region or other locations on the die or substrate associated with semiconductor device 100 closer to the I / O interfaces 106, 108.

[0029] Figure 4 An exemplary embodiment of the discharge protection circuit 400 is depicted, suitable for use as... Figure 1The semiconductor device 100 includes a protection circuit 102. The discharge protection circuit 400 includes a clamping configuration 402 comprising a plurality of CMOS inverter configurations 404, 406, and 408 disposed in a tapered buffer inverter configuration 410, the output of which is coupled to the gate of an NMOS clamping transistor 426. Similarly, the tapered buffer inverter configuration 410 includes a first CMOS inverter configuration 404 comprising a PMOS transistor 412 having a source coupled to a positive reference voltage node 202, a body coupled to a positive reference voltage node 202, a drain coupled to an inverter output node, and a gate coupled to an ESD trigger output node 208; and an NMOS transistor 414 having a drain coupled to an inverter output node, a gate coupled to an ESD trigger output node 208, a source coupled to a negative reference voltage node 204, and a body coupled to a negative reference voltage node 204.

[0030] In the tapered buffer configuration, the inverter output node of the first inverter configuration 404 is coupled to the input of the second inverter configuration 406. The second inverter configuration 406 includes a PMOS transistor 416 having a source coupled to the positive reference voltage node 202, a body coupled to the positive reference voltage node 202, a drain coupled to the second inverter output node, and a gate coupled to the output node of the first inverter configuration 404; and an NMOS transistor 418 having a drain coupled to the second inverter output node, a gate coupled to the output node of the first inverter configuration 404, a source coupled to the negative reference voltage node 204, and a body coupled to the negative reference voltage node 204. The third inverter configuration 408 includes a PMOS transistor 420 having a source coupled to the positive reference voltage node 202, a body coupled to the positive reference voltage node 202, a drain coupled to the output node of the tapered buffer inverter configuration 410, and a gate coupled to the output node of the previous inverter configuration 406, and an NMOS transistor 422 having a drain coupled to the output node of the tapered buffer inverter configuration 410, a gate coupled to the output node of the previous inverter configuration 406, a source coupled to the negative reference voltage node 204, and a body coupled to the negative reference voltage node 204.

[0031] An ESD event that causes RC trigger configuration 206 to pull ESD trigger output node 208 low (e.g., toward VSS) causes PMOS transistor 412 of first inverter configuration 404 to pull output node of first inverter configuration 404 high (e.g., toward VDD), which causes NMOS transistor 418 of second inverter configuration 406 to pull output node of second inverter configuration 406 low (e.g., toward VSS), which in turn causes PMOS transistor 420 of third inverter configuration 408 to pull output node of tapered buffer inverter configuration 410 high (e.g., toward VDD) to activate NMOS clamp transistor 426. By means of a tapered buffer configuration, the NMOS transistor 418 of the second inverter configuration 406 pulls the output node of the second inverter configuration 406 lower than the ESD trigger output node 208 (e.g., closer to the VSS voltage at the negative reference voltage node 204), which in turn pulls the voltage at the gate of the PMOS transistor 420 lower (e.g., closer to the VSS voltage at the negative reference voltage node 204). This causes the PMOS transistor 420 to increase the voltage at the gate of the NMOS clamp transistor 426 by pulling the voltage at the gate of the NMOS clamp transistor 426 closer to the voltage at the positive reference voltage node 202 (e.g., closer to VDD). This increases the magnitude of the gate-to-source voltage difference associated with the PMOS transistor 420, thereby reducing the on-state resistance and the magnitude of the drain-to-source voltage difference associated with the PMOS transistor 420. As a result, the tapered buffer inverter configuration 410 is able to more quickly turn on or otherwise activate the NMOS clamp transistor 426 in response to an ESD event, and keep the NMOS clamp transistor 426 in the on state for a longer duration, thereby increasing the amount of ESD current discharged by the NMOS clamp transistor 426.

[0032] exist Figure 4In the tapered buffer inverter configuration, the individual transistors of inverter configurations 404, 406, and 408 can have different dimensions than each other, such that the dimensions of the individual transistors of inverter configurations 404, 406, and 408 that are off or not enabled during an ESD event can be reduced relative to the corresponding transistors that are enabled or turned on during an ESD event in a similar manner to that described above. For example, the dimensions of the first and third stage NMOS transistors 414, 422 (or odd-level NMOS transistors) and the second stage PMOS transistor 416 (or even-level PMOS transistors) that are off during an ESD event can be reduced to a total width perpendicular to the current flow direction ranging from about 10 µm to about 100 µm, while the total width of the first and third stage PMOS transistors 412, 420 (or odd-level PMOS transistors) and the second stage NMOS transistor 418 (or even-level NMOS transistors) that are turned on during an ESD event can range from about 100 µm to about 600 µm, in order to achieve the desired performance while avoiding collapse during an ESD event. In various embodiments, the widths of the devices in the first and third stages may be the same or different from each other. In this regard, it should be noted that although... Figure 4 The diagram depicts a tapered buffer inverter configuration 410 including three-stage inverter configurations 404, 406, and 408; however, in practice, any odd-numbered inverter configuration may be utilized in a practical embodiment.

[0033] By employing a tapered buffer inverter configuration, clamp configuration 402 can achieve a larger or more complete voltage swing at the gate of clamp transistor 426 by pulling the gate voltage closer to VDD, thereby achieving better turn-on capability than clamp configurations with a single inverter stage. This allows for improved current handling and breakdown performance of clamp transistor 426 by utilizing individual clamp transistors 426 with larger dimensions (e.g., thicker gate insulators, larger device widths, etc.), while simultaneously pulling the gate terminal of clamp transistor 426 to a higher voltage faster than a single CMOS inverter stage, resulting in better turn-on time for relatively short CDM ESD events of 1 nanosecond or less. For example, by using a tapered buffer inverter configuration to improve the on-time of clamping transistor 426 to conduct ESD current and mitigate voltage rise, the total width of clamping transistor 426 can be in the range of approximately 5000 µm to approximately 9000 µm (compared to the range of approximately 10,000 µm to approximately 40,000 µm for individual clamping transistors in discharge protection circuits lacking a tapered buffer inverter configuration). In this regard, it should be noted that... Figure 4 The overall size or area of ​​the discharge protection circuit 400 depicted can be reduced to less than [the required size] by decreasing the total number of transistors and their respective area requirements. Figure 2The discharge protection circuit 200. Therefore, the discharge protection circuit 300 can be utilized in a DAC design region or other circuit region or location on the die or substrate associated with the semiconductor device 100, which is far from the I / O interfaces 106, 108, where density or area takes precedence over ESD performance.

[0034] Figure 5 An exemplary embodiment of the discharge protection circuit 500 is depicted, suitable for use as... Figure 1 The protection circuit 102 in the semiconductor device 100. The discharge protection circuit 500 is similar to... Figure 2 The discharge protection circuit 200; however, the respective clamping configurations 520, 530, and 540 of the discharge protection circuit 500 include a plurality of parallel inverter configurations electrically connected in parallel with each other for pulling up the voltage at the gate terminals of the respective clamping transistors 226, 236, and 246. In this respect, by means of the parallel inverter configuration, the size of the respective transistors in the inverter configuration can be reduced (e.g., relative to...). Figure 2 The discharge protection circuit 200 is reduced by approximately one-third or a factor inverse of the total number of parallel paths, thereby correspondingly reducing the on-time of the respective clamping transistors 226, 236, and 246, thus improving ESD performance relative to the discharge protection circuit 200. For example, the total width of the PMOS transistors in the inverter configuration can be in the range of approximately 30 µm to approximately 200 µm (compared to...). Figure 2 In the embodiments, from 100 µm to approximately 600 µm), the total width of the NMOS transistor in the inverter configuration can be in the range of approximately 3 µm to approximately 30 µm (compared to...). Figure 2 (10 µm to approximately 100 µm in the examples). It should be noted that, although Figure 5 Each clamping configuration 520, 530, 540 is depicted as having three parallel inverters, but in practical applications, clamping configurations 520, 530, 540 may include any number of parallel inverter configurations connected in parallel with each other.

[0035] Figure 6 An exemplary embodiment of the discharge protection circuit 600 is depicted, suitable for use as... Figure 1 The protection circuit 102 in the semiconductor device 100. The discharge protection circuit 600 is similar to... Figure 5The discharge protection circuit 500; however, the respective clamping configurations 620, 630, 640 of the discharge protection circuit 600 include a plurality of parallel NMOS transistors, which are electrically connected in parallel with the NMOS transistors of the respective CMOS inverter configurations 221, 231, 241, but the respective clamping configurations 620, 630, 640 do not include parallel PMOS transistors. In this respect, the parallel NMOS transistors reduce the leakage current associated with the discharge protection circuit 600 during normal operation without ESD events (e.g., current flowing through the off-state of clamping transistors 226, 236, 246) by pulling the voltage at the gate terminals of the respective clamping transistors 226, 236, 246 closer to the negative reference voltage (e.g., VSS) at node 204. It should be noted that, although Figure 6 Each clamping configuration 620, 630, 640 is depicted as having two additional parallel NMOS transistors, but in practical applications, clamping configurations 620, 630, 640 may include any number of parallel NMOS transistors configured in parallel with each other.

[0036] Figure 7 An exemplary embodiment of the discharge protection circuit 700 is depicted, suitable for use as... Figure 1 The protection circuit 102 in the semiconductor device 100. The discharge protection circuit 700 is similar to... Figure 5 The discharge protection circuit 500; however, the respective clamping configurations 720, 730, and 740 of the discharge protection circuit 700 include a plurality of parallel PMOS transistors, which are electrically connected in parallel with the PMOS transistors of the respective CMOS inverter configurations 221, 231, and 241, but the respective clamping configurations 720, 730, and 740 do not include parallel NMOS transistors. In this respect, the parallel PMOS transistors can reduce the size of the PMOS transistors (e.g., relative to the size of the PMOS transistors). Figure 2 The discharge protection circuit 200 is reduced by one-third to achieve faster turn-on, thereby reducing the turn-on time of the respective clamping transistors 226, 236, and 246, and pulling the voltage at the gate terminals of the respective clamping transistors 226, 236, and 246 closer to the positive reference voltage (e.g., VDD) at node 202 more quickly. It should be noted that although... Figure 7 Each clamping configuration 720, 730, 740 is depicted as having two additional parallel PMOS transistors, but in practical applications, clamping configurations 720, 730, 740 may include any number of parallel PMOS transistors configured in parallel with each other.

[0037] Figure 8 An exemplary embodiment of the discharge protection circuit 800 is depicted, suitable for use as... Figure 1 The protection circuit 102 in the semiconductor device 100. The discharge protection circuit 800 is similar to... Figure 3The discharge protection circuit 300; however, the respective clamping configurations 820, 830, 840 of the discharge protection circuit 800 include a plurality of parallel inverter configurations, which are electrically connected in parallel with each other, for pulling up the voltage at the gate terminals of the respective clamping transistors 226, 236, 246 and similar to those described above. Figure 5 The methods described in the context reduce conduction time. It should be noted that, although... Figure 8 Each clamping configuration 820, 830, 840 is depicted as having three parallel inverters, but in practical applications, clamping configurations 820, 830, 840 may include any number of parallel inverter configurations connected in parallel with each other.

[0038] Figure 9 An exemplary embodiment of the discharge protection circuit 900 is depicted, suitable for use as... Figure 1 The protection circuit 102 in the semiconductor device 100. The discharge protection circuit 900 is similar to... Figure 8 The discharge protection circuit 800; however, the respective clamping configurations 920, 930, and 940 of the discharge protection circuit 900 include a plurality of parallel NMOS transistors, which are electrically connected in parallel with the NMOS transistors of their respective CMOS inverter configurations 221, 231, and 241, in a manner similar to that described above. Figure 6 The methods described in the context reduce leakage current associated with the discharge protection circuit 900 during normal operation without ESD events, but the respective clamping configurations 920, 930, and 940 do not include parallel PMOS transistors. It should be noted that, although... Figure 9 Each clamping configuration 920, 930, 940 is depicted as having two additional parallel NMOS transistors, but in practical applications, clamping configurations 920, 930, 940 may include any number of parallel NMOS transistors configured in parallel with each other.

[0039] Figure 10 An exemplary embodiment of the discharge protection circuit 1000 is depicted, suitable for use as... Figure 1 The protection circuit 102 in the semiconductor device 100. The discharge protection circuit 1000 is similar to... Figure 8 The discharge protection circuit 800; however, the respective clamping configurations 1020, 1030, and 1040 of the discharge protection circuit 1000 include a plurality of parallel PMOS transistors, which are electrically connected in parallel with the PMOS transistors of their respective CMOS inverter configurations 221, 231, and 241, in a manner similar to that described above. Figure 7 The methods described in the context reduce the turn-on time of the respective clamping transistors 226, 236, and 246, but the respective clamping configurations 1020, 1030, and 1040 do not include parallel NMOS transistors. It should be noted that, although... Figure 10Each clamping configuration 1020, 1030, 1040 is depicted as having two additional parallel PMOS transistors, but in practical applications, clamping configurations 1020, 1030, 1040 may include any number of parallel PMOS transistors configured in parallel with each other.

[0040] Figure 11 An exemplary embodiment of the discharge protection circuit 1100 is depicted, suitable for use as... Figure 1 The protection circuit 102 in the semiconductor device 100. The discharge protection circuit 1100 is similar to... Figure 4 The discharge protection circuit 400; however, the discharge protection circuit 1100 includes a plurality of parallel CMOS inverter configurations 1104, 1106, 1108 configured in a tapered buffer inverter configuration. For example, the first parallel CMOS inverter configuration 1104 includes a first CMOS inverter configuration 1110 having an input coupled to an ESD trigger output node 208 corresponding to the input of the parallel CMOS inverter configuration 1104, a second CMOS inverter configuration 1112 having an input coupled to the ESD trigger output node 208, and a third CMOS inverter configuration 1114 having an input coupled to the ESD trigger output node 208, wherein the outputs of the CMOS inverter configurations 1110, 1112, 1114 are coupled to each other at the output of the parallel CMOS inverter configuration 1104. Regarding this, CMOS inverter configurations 1110, 1112, and 1114 are connected in parallel between the ESD trigger output node 208 and the output of the parallel CMOS inverter configuration 1104, such that the parallel CMOS inverter configuration 1104 serves as the first stage of the tapered buffer inverter configuration. Similarly, the second parallel CMOS inverter configuration 1106 includes respective CMOS inverter configurations connected in parallel and configured to provide the second stage of the tapered buffer inverter configuration between the output of the first-stage parallel CMOS inverter configuration 1104 and the input of the third-stage parallel CMOS inverter configuration 1108. The third-stage parallel CMOS inverter configuration 1108 similarly includes respective CMOS inverter configurations connected in parallel and configured between the output of the second-stage parallel CMOS inverter configuration 1106 and the gate of the clamping transistor 426.

[0041] The inverters in each stage of the parallel tapered buffer inverter configuration, and the respective parallel CMOS inverter configurations 1104, 1106, and 1108, can be configured to respond to ESD events more quickly by adjusting the transistor size of the respective CMOS inverter configuration of each stage of the respective parallel CMOS inverter configuration 1104, 1106, and 1108. It should be noted that although... Figure 11Each parallel CMOS inverter configuration 1104, 1106, 1108 is depicted with two additional parallel CMOS inverters, but in practical applications, the parallel CMOS inverter configurations 1104, 1106, 1108 may include any number of parallel CMOS inverters configured in parallel with each other.

[0042] Figure 12 An exemplary embodiment of the discharge protection circuit 1200 is depicted, suitable for use as... Figure 1 The protection circuit 102 in the semiconductor device 100. The discharge protection circuit 1200 is similar to... Figure 11 The discharge protection circuit 1100; however, the parallel CMOS inverter configurations 1204, 1206, and 1208 configured in the tapered buffer inverter configuration include parallel NMOS transistors, which are electrically connected in parallel with the NMOS transistors of their respective CMOS inverter configurations, similar to the above. Figure 6 The methods described in the context reduce leakage current. Regarding the NMOS parallel CMOS inverter configurations 1204, 1206, and 1208, parallel PMOS transistors are not included.

[0043] Figure 13 An exemplary embodiment of the discharge protection circuit 1300 is depicted, suitable for use as... Figure 1 The protection circuit 102 in the semiconductor device 100. The discharge protection circuit 1200 is similar to... Figure 11 The discharge protection circuit 1100; however, the parallel CMOS inverter configurations 1304, 1306, and 1308 configured in the tapered buffer inverter configuration include parallel PMOS transistors, which are electrically connected in parallel with the PMOS transistors of their respective CMOS inverter configurations, similar to the above. Figure 7 The method described in the context enables faster turn-on. Regarding the PMOS parallel CMOS inverter configurations 1304, 1306, and 1308, parallel NMOS transistors are not included.

[0044] Figure 14 An exemplary embodiment of the discharge protection circuit 1400 is depicted, suitable for use as... Figure 1 The protection circuit 102 in the semiconductor device 100. The discharge protection circuit 1400 is similar to... Figure 11 The discharge protection circuit 1100; however, the discharge protection circuit 1400 alternately includes only those having similar characteristics. Figure 12 The NMOS parallel CMOS inverter configurations of the parallel NMOS transistors 1204 and 1208, and only those with similar characteristics Figure 13The PMOS parallel CMOS inverter configuration 1306 is a parallel PMOS transistor configuration. Regarding the odd-numbered stages of the tapered buffer inverter configuration, the NMOS parallel CMOS inverter configurations 1204 and 1208 are implemented, configured similarly to those described above. Figure 6 The manner described in the context reduces leakage current through clamping transistor 426, while the even-numbered stage of the tapered buffer inverter configuration is implemented as a PMOS parallel CMOS inverter configuration 1306 to facilitate faster turn-on in response to ESD events.

[0045] Figure 15 An exemplary embodiment of the discharge protection circuit 1500 is depicted, suitable for use as... Figure 1 The protection circuit 102 in the semiconductor device 100. The discharge protection circuit 1500 is similar to... Figure 11 The discharge protection circuit 1100 and Figure 14 The discharge protection circuit 1400; however, the discharge protection circuit 1500 alternately includes PMOS parallel CMOS inverter configurations 1304 and 1308 with only parallel PMOS transistors, and NMOS parallel CMOS inverter configuration 1206 with only parallel NMOS transistors, the configurations being relative to Figure 14 As an alternative configuration, the odd-numbered stages of the tapered buffer inverter configuration are implemented as PMOS parallel CMOS inverter configurations 1304 and 1308, while the even-numbered stages of the tapered buffer inverter configuration are implemented as NMOS parallel CMOS inverter configuration 1206, to achieve faster turn-on in response to ESD events.

[0046] With similar Figure 14-15 The manner described in the context above Figure 5-10 In different embodiments of the discharge protection circuit described in the context, one or more clamping configurations may alternately utilize PMOS parallel CMOS inverter configurations and / or NMOS parallel CMOS inverter configurations configured as desired to achieve the desired trade-off between ESD performance, leakage current, and area loss or component density. For example, refer to Figure 5 One or more of clamping configurations 520, 530, and 540 may include a PMOS parallel CMOS inverter configuration to improve the on-time of their respective clamping transistors 226, 236, and 246, while one or more of the other clamping configurations 520, 530, and 540 may include an NMOS parallel CMOS inverter configuration to facilitate a reduction in leakage current through their respective clamping transistors 226, 236, and 246, such that the cumulative effect of the combination of PMOS parallel and NMOS parallel CMOS inverter configurations achieves the desired trade-off between ESD performance and leakage current.

[0047] It should be understood that, despite Figure 2-15An embodiment of a discharge protection circuit utilizing an N-type clamping transistor is described. This discharge protection circuit can be implemented in an equivalent manner using a P-type clamping transistor, with corresponding modifications to the inverter configuration (e.g., by adding an additional inverter stage) to provide the required control signal at the gate or control terminal of the P-type clamping transistor to respond to an ESD event or otherwise turn on the P-type clamping transistor. Regarding this, Figure 16 An exemplary embodiment of the discharge protection circuit 1600 is depicted, suitable for use as... Figure 1 The protection circuit 102 in the semiconductor device 100 corresponds to Figure 2 The discharge protection circuit 200 is implemented in P-type.

[0048] Similar to discharge protection circuit 200, discharge protection circuit 1600 includes a plurality of clamping configurations 1620, 1630, and 1640, each coupled to ESD trigger output node 208 and configured to be electrically parallel to each other, providing parallel shunt paths via respective clamping transistors 1626, 1636, and 1646 in response to an ESD event indication at ESD trigger output node 208. However, with Figure 2 In contrast to the N-type embodiment, in the P-type configuration, clamping transistors 1626, 1636, and 1646 are implemented as PMOS transistors, each having a respective body terminal coupled to the positive reference voltage node 202, wherein the gates of the PMOS clamping transistors 1626, 1636, and 1646 are pulled to the negative reference voltage node 204 in response to an ESD event. Regarding clamping configurations 1620, 1630, and 1640, an even number of CMOS inverters are configured between the ESD trigger output node 208 and the gates of the respective PMOS clamping transistors 1626, 1636, and 1646 to pull the gates to the negative reference voltage node 204 when the ESD trigger output node 208 drops below the threshold voltage of the respective CMOS inverter-configured NMOS transistor.

[0049] For example, the first clamping configuration 1620 includes a first CMOS inverter configuration 1622 having an input coupled to the ESD trigger output node 208 to provide a logical inversion of the signal at the ESD trigger output node 208 at the input of the second CMOS inverter configuration 1624, the second CMOS inverter configuration 1624 having an output connected to the gate of the clamping PMOS transistor 1626 having a drain coupled to the negative reference voltage node 204, a source coupled to the positive reference voltage node 202, and a body coupled to the positive reference voltage node 202. When an ESD event causes a transient voltage difference between reference voltage nodes 202 and 204, which causes RC trigger configuration 206 to effectively pull the voltage at output node 208 low or toward the negative reference voltage (VSS), the PMOS transistor of the first CMOS inverter configuration 1622 is actively or otherwise activated, thereby pulling the voltage at the input of the second CMOS inverter configuration 1624 high or toward the positive reference voltage (VDD), which in turn pulls the voltage at the gate of clamp PMOS transistor 1626 low or toward the negative reference voltage (VSS). As a result, clamp PMOS transistor 1626 is turned on or otherwise activated to conduct at least a portion of the ESD discharge current between reference voltage nodes 202 and 204. In a similar manner, when the RC trigger configuration 206 responds to an ESD event by pulling the voltage at output node 208 toward the negative reference voltage (VSS), the respective inverter configurations of the other clamping configurations 1630 and 1640 turn on or otherwise activate their respective instances of clamping PMOS transistors 1636 and 1646, simultaneously and in parallel with the first clamping PMOS transistor 1626, to conduct their respective portions of the ESD discharge current between reference voltage nodes 202 and 204.

[0050] By distributing the ESD discharge current to the clamping PMOS transistors 1626, 1636, and 1646, the size of each instance of the clamping transistors 1626, 1636, and 1646 can be reduced to respond more quickly to relatively short ESD events. This is in contrast to the aforementioned... Figure 5-7 In a similar manner to that described in the context of the discharge protection circuit 1600, additional parallel transistors and / or inverters can be added to clamp configurations 1620, 1630, and 1640 to achieve the desired trade-off between ESD performance, leakage current, and area. Furthermore, in conjunction with... Figure 14-15 In a similar manner to that described in the context, in various implementations of the discharge protection circuit 1600, one or more of the clamping configurations 1620, 1630, 1640 may alternatively utilize a PMOS parallel CMOS inverter configuration and / or an NMOS parallel CMOS inverter configuration configured as desired to achieve the desired trade-off between ESD performance, leakage current and area loss or component density.

[0051] Figure 17 An exemplary embodiment of the discharge protection circuit 1700 is depicted, suitable for use as... Figure 1 The protection circuit 102 in the semiconductor device 100 corresponds to Figure 3 The discharge protection circuit 300 is a P-type implementation. The discharge protection circuit 1700 includes clamping configurations 1620, 1630, and 1640 with PMOS clamping transistors 1626, 1636, and 1646, wherein the input of the CMOS inverter configuration of each clamping configuration 1620, 1630, and 1640 is coupled to the output node of each instance of the RC trigger configurations 206, 302, and 304. This is in accordance with the above-described... Figure 3 In a similar manner to that described in the context above, discharge protection circuit 1700 can provide improved CDM ESD performance relative to discharge protection circuit 1600 because each clamping configuration 1620, 1630, 1640 has its own RC trigger configuration 206, 302, 304, which can be designed or otherwise configured to improve the conduction or ESD performance of the respective clamping configuration 1620, 1630, 1640. This is in accordance with the above description in... Figure 8-10 In a similar manner to that described in the context of the discharge protection circuit 1700, additional parallel transistors and / or inverters can be added to clamp configurations 1620, 1630, and 1640 to achieve the desired trade-off between ESD performance, leakage current, and area. Furthermore, in conjunction with... Figure 14-15 In a similar manner to that described in the context, in various implementations of the discharge protection circuit 1700, one or more of the clamping configurations 1620, 1630, 1640 may alternatively utilize a PMOS parallel CMOS inverter configuration and / or an NMOS parallel CMOS inverter configuration configured as desired to achieve the desired trade-off between ESD performance, leakage current and area loss or component density.

[0052] Figure 18 An exemplary embodiment of the discharge protection circuit 1800 is depicted, suitable for use as... Figure 1 The protection circuit 102 in the semiconductor device 100 corresponds to Figure 4 The discharge protection circuit 400 is implemented in a P-type configuration. Specifically, the discharge protection circuit 1800 includes a tapered buffer inverter configuration 1810 having an even number of CMOS inverter configurations, the output of which is coupled to the gate of a PMOS clamping transistor 1826. This is consistent with the above-described... Figure 4In a manner similar to that described in the context, an ESD event that causes the RC-triggered configuration 206 to pull the ESD-triggered output node low (e.g., toward VSS) causes the last even-stage NMOS transistor to pull the output node of the tapered buffer inverter configuration 1810 low (e.g., toward VSS) to activate the PMOS clamp transistor 1826. With the tapered buffer configuration, the NMOS transistor pulls the voltage at the gate of the PMOS clamp transistor 1826 closer to the voltage at the negative reference voltage node 204 (e.g., closer to VSS), thereby increasing the magnitude of the gate-to-source voltage difference associated with the PMOS clamp transistor 1826 to reduce the on-state resistance associated with the PMOS clamp transistor 1826. As a result, the tapered buffer inverter configuration 1810 is able to respond to an ESD event by fully turning on or otherwise activating the PMOS clamping transistor 1826 more quickly and keeping the PMOS clamping transistor 1826 in the on state for a longer duration, thereby increasing the amount of ESD current discharged by the PMOS clamping transistor 1826.

[0053] In accordance with the above Figure 11-13 In a similar manner to that described in the context of the discharge protection circuit 1800, additional parallel transistors and / or inverters can be added to the respective inverters of the tapered buffer inverter configuration 1810 to achieve the desired trade-off between ESD performance, leakage current, and area. Furthermore, in conjunction with... Figure 14-15 In a similar manner to that described in the context, in various implementations, the discharge protection circuit 1800 may alternatively utilize a PMOS parallel CMOS inverter configuration and / or an NMOS parallel CMOS inverter configuration configured as desired to achieve the desired trade-off between ESD performance, leakage current, and area loss or component density.

[0054] It should be understood that Figure 2-18 The simplified representation depicting ESD protection circuitry is for explanation and ease of description purposes only and is not intended to limit the application or scope of the subject matter in any way. Therefore, although... Figure 2-18 The description depicts direct electrical connections between components; alternative embodiments may employ intervening circuit elements and / or components, while operating in a substantially similar manner.

[0055] Figure 19 An exemplary embodiment of a fabrication process 1900 suitable for manufacturing a semiconductor device including a discharge protection circuit is depicted. (Refer to...) Figure 19 And continue to refer to Figure 1-18The fabrication process 1900 begins at 1902 by forming interfaces to be coupled to respective reference voltage nodes. The fabrication process 1900 continues at 1904 by forming a trigger configuration on or above the semiconductor substrate, the trigger configuration being coupled between the first and second reference voltage nodes to provide indication of a discharge event at the output node of the trigger configuration. The fabrication process 1900 continues at 1906 by forming one or more clamping configurations between the reference voltage nodes, the clamping configurations being configured to activate in response to a discharge event indication at the output node. For example, in some embodiments, the fabrication process forms a first clamping configuration including a first clamping transistor coupled between the first and second reference voltage nodes, wherein the first clamping configuration is configured to activate the first clamping transistor in response to a discharge event indication at the output node. In some embodiments, the fabrication process forms a second clamping configuration including a second clamping transistor coupled between the first and second reference voltage nodes, wherein the second clamping configuration is configured to activate the second clamping transistor in response to a discharge event indication at the output node. In 1908, fabrication process 1900 forms the functional circuitry coupled to the reference voltage node before encapsulating the functional circuitry and discharge protection circuitry (including trigger and clamp configurations) into a common device package including an interface for receiving the supply reference voltage. In this respect, in some embodiments, the interface formed in 1902 connects to pins, pads, or other terminals of the device package or integrated circuit for receiving the input supply voltage, such that the first reference voltage node corresponds to the supply voltage bus of the device package.

[0056] In one embodiment, the semiconductor device includes a first interface coupled to a first reference voltage node, a second interface coupled to a second reference voltage node, a trigger configuration coupled between the first and second reference voltage nodes to provide a discharge event indication at an output node of the trigger configuration, a first clamp configuration including a first clamp transistor coupled between the first and second reference voltage nodes, wherein the first clamp configuration is configured to activate the first clamp transistor in response to a discharge event indication at the output node, and a second clamp configuration including a second clamp transistor coupled between the first and second reference voltage nodes, wherein the second clamp configuration is configured to activate the second clamp transistor in response to a discharge event indication at the output node.

[0057] In one implementation, the first clamping configuration includes a first inverter configuration coupled between a first reference voltage node and a second reference voltage node, the first inverter configuration having an input node coupled to an output node of a trigger configuration and an inverter output node coupled to a first gate of a first clamping transistor; and the second clamping configuration includes a second inverter configuration coupled between the first reference voltage node and the second reference voltage node, the second inverter configuration having a second input node coupled to an output node of a trigger configuration and a second inverter output node coupled to a second gate of a second clamping transistor.

[0058] In one embodiment, the semiconductor device includes a third clamping configuration, the third clamping configuration including a third clamping transistor coupled between a first reference voltage node and a second reference voltage node, wherein the third clamping configuration includes a third inverter configuration coupled between the first reference voltage node and the second reference voltage node, the third inverter configuration having a third input node coupled to an output node of a trigger configuration and a third inverter output node coupled to a third gate of the third clamping transistor.

[0059] In one implementation, the first clamping configuration includes a first group of one or more parallel inverter configurations coupled between the first reference voltage node and the second reference voltage node and connected in parallel to the first inverter configuration, wherein each parallel inverter configuration of the first group of one or more parallel inverter configurations includes a respective input node coupled to the output node of the trigger configuration and a respective output node coupled to the first gate of the first clamping transistor; and the second clamping configuration includes a second group of one or more parallel inverter configurations coupled between the first reference voltage node and the second reference voltage node and connected in parallel to the second inverter configuration, wherein each parallel inverter configuration of the second group of one or more parallel inverter configurations includes a respective input node coupled to the output node of the trigger configuration and a respective output node coupled to the second gate of the second clamping transistor.

[0060] In one embodiment, the first clamping configuration includes a first set of one or more parallel transistors coupled between a first gate of the first clamping transistor and a second reference voltage node, wherein each of the first set of one or more parallel transistors includes a respective gate coupled to an output node of the triggering configuration to activate the respective parallel transistor in response to a discharge event indication at the output node; and the second clamping configuration includes a second set of one or more parallel transistors coupled between a second gate of the second clamping transistor and a second reference voltage node, wherein each of the second set of one or more parallel transistors includes a respective gate coupled to an output node of the triggering configuration to activate the respective parallel transistor in response to a discharge event indication at the output node.

[0061] In one embodiment, the first clamping configuration includes a first group of one or more parallel transistors coupled between a first reference voltage node and a first gate of the first clamping transistor, wherein each parallel transistor of the first group of one or more parallel transistors includes a respective gate coupled to the output node of the triggering configuration to activate the respective parallel transistor in response to a discharge event indication at the output node; and the second clamping configuration includes a second group of one or more parallel transistors coupled between the first reference voltage node and the second gate of the second clamping transistor, wherein each parallel transistor of the second group of one or more parallel transistors includes a respective gate coupled to the output node of the triggering configuration to activate the respective parallel transistor in response to a discharge event indication at the output node.

[0062] In one implementation, the total width of the first clamping transistor and the second clamping transistor is in the range of 1500 µm to 4000 µm.

[0063] In another embodiment, the semiconductor device includes a first interface coupled to a first reference voltage node, a second interface coupled to a second reference voltage node, a first trigger configuration coupled between the first and second reference voltage nodes to provide a first indication of a discharge event at a first output node of the first trigger configuration, a first clamping configuration coupled to the first trigger configuration, the first clamping configuration including a first clamping transistor coupled between the first and second reference voltage nodes, wherein the first clamping configuration is configured to activate the first clamping transistor in response to the first indication of a discharge event at the first output node, a second trigger configuration coupled between the first and second reference voltage nodes to provide a second indication of a discharge event at a second output node of the second trigger configuration, and a second clamping configuration coupled to the second trigger configuration, the second clamping configuration including a second clamping transistor coupled between the first and second reference voltage nodes, wherein the second clamping configuration is configured to activate the second clamping transistor in response to the second indication of a discharge event at the second output node.

[0064] In one implementation, the first clamping configuration includes a first inverter configuration coupled between a first reference voltage node and a second reference voltage node, the first inverter configuration having an input node coupled to a first output node of a first trigger configuration and an inverter output node coupled to a first gate of a first clamping transistor; and the second clamping configuration includes a second inverter configuration coupled between the first reference voltage node and the second reference voltage node, the second inverter configuration having a second input node coupled to a second output node of a second trigger configuration and a second inverter output node coupled to a second gate of a second clamping transistor.

[0065] In one embodiment, the semiconductor device further includes a third trigger configuration coupled between a first reference voltage node and a second reference voltage node to provide a third indication of a discharge event at a third output node of the third trigger configuration, and a third clamping configuration including a third clamping transistor coupled between the first reference voltage node and the second reference voltage node, wherein the third clamping configuration includes a third inverter configuration coupled between the first reference voltage node and the second reference voltage node, the third inverter configuration having a third input node coupled to the third output node of the third trigger configuration and a third inverter output node coupled to the third gate of the third clamping transistor.

[0066] In one implementation, the first clamping configuration includes a first group of one or more parallel inverter configurations coupled between the first reference voltage node and the second reference voltage node and connected in parallel to the first inverter configuration, wherein each parallel inverter configuration of the first group of one or more parallel inverter configurations includes a respective input node coupled to a first output node of the first trigger configuration and a respective output node coupled to a first gate of the first clamping transistor; and the second clamping configuration includes a second group of one or more parallel inverter configurations coupled between the first reference voltage node and the second reference voltage node and connected in parallel to the second inverter configuration, wherein each parallel inverter configuration of the second group of one or more parallel inverter configurations includes a respective input node coupled to a second output node of the second trigger configuration and a respective output node coupled to a second gate of the second clamping transistor.

[0067] In one embodiment, a first clamping configuration includes a first set of one or more parallel transistors coupled between a first gate of a first clamping transistor and a second reference voltage node, wherein each of the first set of one or more parallel transistors includes a respective gate coupled to a first output node of a first triggering configuration to activate the respective parallel transistor in response to a first indication of a discharge event at the first output node; and a second clamping configuration includes a second set of one or more parallel transistors coupled between a second gate of a second clamping transistor and a second reference voltage node, wherein each of the second set of one or more parallel transistors includes a respective gate coupled to a second output node of a second triggering configuration to activate the respective parallel transistor in response to a second indication of a discharge event at the second output node.

[0068] In one embodiment, the first clamping configuration includes a first set of one or more parallel transistors coupled between a first reference voltage node and a first gate of the first clamping transistor, wherein each of the first set of one or more parallel transistors includes a respective gate coupled to a first output node of a first triggering configuration to activate the respective parallel transistor in response to a first indication of a discharge event at the first output node; and the second clamping configuration includes a second set of one or more parallel transistors coupled between the first reference voltage node and a second gate of the second clamping transistor, wherein each of the second set of one or more parallel transistors includes a respective gate coupled to a second output node of a second triggering configuration to activate the respective parallel transistor in response to a second indication of a discharge event at the second output node.

[0069] In one implementation, the total width of the first clamping transistor and the second clamping transistor is in the range of 1500 µm to 4000 µm.

[0070] In another embodiment, a method of manufacturing a semiconductor device is provided. The method involves forming a first trigger configuration coupled between a first reference voltage node coupled to a first interface and a second reference voltage node coupled to a second interface to provide a first indication of a discharge event at a first output node of the first trigger configuration; forming a first clamping configuration coupled to the first trigger configuration, the first clamping configuration including a first clamping transistor coupled between the first and second reference voltage nodes, wherein the first clamping configuration is configured to activate the first clamping transistor in response to the first indication of a discharge event at the first output node; forming a second trigger configuration coupled between the first and second reference voltage nodes to provide a second indication of a discharge event at a second output node of the second trigger configuration; and forming a second clamping configuration coupled to the second trigger configuration, the second clamping configuration including a second clamping transistor coupled between the first and second reference voltage nodes, wherein the second clamping configuration is configured to activate the second clamping transistor in response to the second indication of a discharge event at the second output node.

[0071] In one implementation, forming a first clamping configuration involves forming a first inverter configuration coupled between a first reference voltage node and a second reference voltage node, the first inverter configuration having an input node coupled to a first output node of a first trigger configuration and an inverter output node coupled to a first gate of a first clamping transistor; and forming a second clamping configuration involves forming a second inverter configuration coupled between the first reference voltage node and the second reference voltage node, the second inverter configuration having a second input node coupled to a second output node of a second trigger configuration and a second inverter output node coupled to a second gate of a second clamping transistor.

[0072] In one embodiment, the method involves forming a third trigger configuration coupled between a first reference voltage node and a second reference voltage node to provide a third indication of a discharge event at a third output node of the third trigger configuration, and forming a third clamping configuration including a third clamping transistor coupled between the first reference voltage node and the second reference voltage node, wherein the third clamping configuration includes a third inverter configuration coupled between the first reference voltage node and the second reference voltage node, the third inverter configuration having a third input node coupled to the third output node of the third trigger configuration and a third inverter output node coupled to the third gate of the third clamping transistor.

[0073] In one implementation, forming a first clamping configuration involves forming a first group of one or more parallel inverter configurations coupled between a first reference voltage node and a second reference voltage node and connected in parallel to a first inverter configuration, wherein each parallel inverter configuration in the first group of one or more parallel inverter configurations includes a respective input node coupled to a first output node of a first trigger configuration and a respective output node coupled to a first gate of a first clamping transistor; and forming a second clamping configuration involves forming a second group of one or more parallel inverter configurations coupled between a first reference voltage node and a second reference voltage node and connected in parallel to a second inverter configuration, wherein each parallel inverter configuration in the second group of one or more parallel inverter configurations includes a respective input node coupled to a second output node of a second trigger configuration and a respective output node coupled to a second gate of a second clamping transistor.

[0074] In one implementation, forming a first clamping configuration involves forming a first group of one or more parallel transistors coupled between a first gate of a first clamping transistor and a second reference voltage node, wherein each parallel transistor in the first group of one or more parallel transistors includes a respective gate coupled to a first output node of a first triggering configuration to activate the respective parallel transistor in response to a first indication of a discharge event at the first output node; and forming a second clamping configuration involves forming a second group of one or more parallel transistors coupled between a second gate of a second clamping transistor and a second reference voltage node, wherein each parallel transistor in the second group of one or more parallel transistors includes a respective gate coupled to a second output node of a second triggering configuration to activate the respective parallel transistor in response to a second indication of a discharge event at the second output node.

[0075] In one implementation, forming a first clamping configuration involves forming a first group of one or more parallel transistors coupled between a first reference voltage node and a first gate of a first clamping transistor, wherein each parallel transistor in the first group of one or more parallel transistors includes a respective gate coupled to a first output node of a first triggering configuration to activate the respective parallel transistor in response to a first indication of a discharge event at the first output node; and forming a second clamping configuration involves forming a second group of one or more parallel transistors coupled between a first reference voltage node and a second gate of a second clamping transistor, wherein each parallel transistor in the second group of one or more parallel transistors includes a respective gate coupled to a second output node of a second triggering configuration to activate the respective parallel transistor in response to a second indication of a discharge event at the second output node.

[0076] In one implementation, the total width of the first clamping transistor and the second clamping transistor is in the range of 1500 µm to 4000 µm.

[0077] In another embodiment, a method of manufacturing a semiconductor device is provided. The method involves forming a first trigger configuration coupled between a first reference voltage node and a second reference voltage node to provide a first indication of a discharge event at a first output node of the first trigger configuration; forming a first clamping configuration coupled to the first trigger configuration, the first clamping configuration including a first clamping transistor coupled between the first and second reference voltage nodes, wherein the first clamping configuration is configured to activate the first clamping transistor in response to the first indication of a discharge event at the first output node; forming a second trigger configuration coupled between the first and second reference voltage nodes to provide a second indication of a discharge event at a second output node of the second trigger configuration; and forming a second clamping configuration coupled to the second trigger configuration, the second clamping configuration including a second clamping transistor coupled between the first and second reference voltage nodes, wherein the second clamping configuration is configured to activate the second clamping transistor in response to the second indication of a discharge event at the second output node.

[0078] In one implementation, forming a first clamping configuration includes forming a first inverter configuration coupled between a first reference voltage node and a second reference voltage node, the first inverter configuration having an input node coupled to a first output node of a first trigger configuration and an inverter output node coupled to a first gate of a first clamping transistor; and forming a second clamping configuration includes forming a second inverter configuration coupled between the first reference voltage node and the second reference voltage node, the second inverter configuration having a second input node coupled to a second output node of a second trigger configuration and a second inverter output node coupled to a second gate of a second clamping transistor.

[0079] In one embodiment, the method involves forming a third trigger configuration coupled between a first reference voltage node and a second reference voltage node to provide a third indication of a discharge event at a third output node of the third trigger configuration, and forming a third clamping configuration including a third clamping transistor coupled between the first reference voltage node and the second reference voltage node, wherein the third clamping configuration includes a third inverter configuration coupled between the first reference voltage node and the second reference voltage node, the third inverter configuration having a third input node coupled to the third output node of the third trigger configuration and a third inverter output node coupled to the third gate of the third clamping transistor.

[0080] In one implementation, forming a first clamping configuration includes forming a first set of one or more parallel inverter configurations coupled between a first reference voltage node and a second reference voltage node and connected in parallel to a first inverter configuration, wherein each parallel inverter configuration of the first set of one or more parallel inverter configurations includes a respective input node coupled to a first output node of a first trigger configuration and a respective output node coupled to a first gate of a first clamping transistor; and forming a second clamping configuration includes forming a second set of one or more parallel inverter configurations coupled between a first reference voltage node and a second reference voltage node and connected in parallel to a second inverter configuration, wherein each parallel inverter configuration of the second set of one or more parallel inverter configurations includes a respective input node coupled to a second output node of a second trigger configuration and a respective output node coupled to a second gate of a second clamping transistor.

[0081] In one embodiment, forming a first clamping configuration includes forming a first set of one or more parallel transistors coupled between a first gate of a first clamping transistor and a second reference voltage node, wherein each of the first set of one or more parallel transistors includes a respective gate coupled to a first output node of a first triggering configuration to activate the respective parallel transistor in response to a first indication of a discharge event at the first output node; and forming a second clamping configuration includes forming a second set of one or more parallel transistors coupled between a second gate of a second clamping transistor and a second reference voltage node, wherein each of the second set of one or more parallel transistors includes a respective gate coupled to a second output node of a second triggering configuration to activate the respective parallel transistor in response to a second indication of a discharge event at the second output node.

[0082] In one implementation, forming a first clamping configuration includes forming a first set of one or more parallel transistors coupled between a first reference voltage node and a first gate of a first clamping transistor, wherein each of the first set of one or more parallel transistors includes a respective gate coupled to a first output node of a first triggering configuration to activate the respective parallel transistor in response to a first indication of a discharge event at the first output node, and forming a second clamping configuration includes forming a respective gate coupled to a second output node of a second triggering configuration to activate the respective parallel transistor in response to a second indication of a discharge event at the second output node.

[0083] In one embodiment, a method of manufacturing a semiconductor device involves forming a first trigger configuration coupled between a first reference voltage node coupled to a first interface and a second reference voltage node coupled to a second interface to provide a first indication of a discharge event at a first output node of the first trigger configuration; forming a first clamping configuration including a first clamping transistor; coupling the first clamping transistor of the first clamping configuration to a first trigger configuration between the first reference voltage node and the second reference voltage node; forming a second trigger configuration coupled between the first reference voltage node and the second reference voltage node to provide a second indication of a discharge event at a second output node of the second trigger configuration; forming a second clamping configuration including a second clamping transistor; and coupling the second clamping transistor of the second clamping configuration to a second trigger configuration between the first reference voltage node and the second reference voltage node.

[0084] In one implementation, the method further includes activating a first clamping transistor in response to a first indication of a discharge event at a first output node by a first clamping configuration.

[0085] In one implementation, the method further includes activating a second clamping transistor in response to a second indication of a discharge event at a second output node by a second clamping configuration.

[0086] In one implementation, forming a first clamping configuration involves forming a first inverter configuration coupled between a first reference voltage node and a second reference voltage node, the first inverter configuration having an input node coupled to a first output node of a first trigger configuration and an inverter output node coupled to a first gate of a first clamping transistor; and forming a second clamping configuration involves forming a second inverter configuration coupled between the first reference voltage node and the second reference voltage node, the second inverter configuration having a second input node coupled to a second output node of a second trigger configuration and a second inverter output node coupled to a second gate of a second clamping transistor.

[0087] In one embodiment, the method further includes coupling a third trigger configuration between a first reference voltage node and a second reference voltage node to provide a third indication of a discharge event at a third output node of the third trigger configuration, and forming a third clamping configuration including a third clamping transistor coupled between the first reference voltage node and the second reference voltage node, wherein the third clamping configuration includes a third inverter configuration coupled between the first reference voltage node and the second reference voltage node, the third inverter configuration having a third input node coupled to the third output node of the third trigger configuration and a third inverter output node coupled to the third gate of the third clamping transistor.

[0088] In one implementation, forming a first clamping configuration involves forming a first set of one or more parallel inverter configurations coupled between a first reference voltage node and a second reference voltage node and connected in parallel to a first inverter configuration, wherein each parallel inverter configuration of the first set of one or more parallel inverter configurations includes a respective input node coupled to a first output node of a first trigger configuration and a respective output node coupled to a first gate of a first clamping transistor; and forming a second clamping configuration involves forming a second set of one or more parallel inverter configurations coupled between a first reference voltage node and a second reference voltage node and connected in parallel to a second inverter configuration, wherein each parallel inverter configuration of the second set of one or more parallel inverter configurations includes a respective input node coupled to a second output node of a second trigger configuration and a respective output node coupled to a second gate of a second clamping transistor.

[0089] In one implementation, the total width of the first clamping transistor and the second clamping transistor is in the range of 1500 µm to 4000 µm.

[0090] In one embodiment, a method of manufacturing a semiconductor device involves coupling a first trigger configuration between a first reference voltage node and a second reference voltage node to provide a first indication of a discharge event at a first output node of the first trigger configuration; coupling a first clamping configuration to the first trigger configuration, the first clamping configuration including a first clamping transistor coupled between the first and second reference voltage nodes, wherein the first clamping configuration is configured to activate the first clamping transistor in response to the first indication of a discharge event at the first output node; coupling a second trigger configuration between the first and second reference voltage nodes to provide a second indication of a discharge event at a second output node of the second trigger configuration; and coupling a second clamping configuration to a second trigger configuration, the second clamping configuration including a second clamping transistor coupled between the first and second reference voltage nodes, wherein the second clamping configuration is configured to activate the second clamping transistor in response to the second indication of a discharge event at the second output node.

[0091] In one embodiment, the method involves forming a first inverter configuration coupled between a first reference voltage node and a second reference voltage node, the first inverter configuration having an input node coupled to a first output node of a first trigger configuration and an inverter output node coupled to a first gate of a first clamping transistor, and forming a second inverter configuration coupled between the first reference voltage node and the second reference voltage node, the second inverter configuration having a second input node coupled to a second output node of a second trigger configuration and a second inverter output node coupled to a second gate of a second clamping transistor.

[0092] In one embodiment, the method involves coupling a third trigger configuration between a first reference voltage node and a second reference voltage node to provide a third indication of a discharge event at a third output node of the third trigger configuration, and forming a third clamping configuration including a third clamping transistor coupled between the first and second reference voltage nodes, wherein the third clamping configuration includes a third inverter configuration coupled between the first and second reference voltage nodes, the third inverter configuration having a third input node coupled to the third output node of the third trigger configuration and a third inverter output node coupled to the third gate of the third clamping transistor.

[0093] While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that numerous variations exist. It should also be understood that the exemplary embodiments or multiple exemplary embodiments are merely examples and are not intended to limit the scope, applicability, or configuration of this disclosure in any way. Rather, the foregoing detailed description will provide a convenient roadmap for those skilled in the art to implement the exemplary embodiments of this disclosure. It should be understood that various changes can be made to the function and configuration of the elements described in the exemplary embodiments without departing from the scope of this disclosure as set forth in the appended claims.

Claims

1. A semiconductor device, characterized in that, include: The first interface is coupled to the first reference voltage node; The second interface is coupled to the second reference voltage node; A trigger configuration, coupled between the first reference voltage node and the second reference voltage node, provides an indication of a discharge event at the output node of the trigger configuration; A first clamping configuration includes a first clamping transistor coupled between a first reference voltage node and a second reference voltage node, wherein the first clamping configuration is configured to activate the first clamping transistor in response to an indication of a discharge event at the output node; as well as A second clamping configuration includes a second clamping transistor coupled between the first reference voltage node and the second reference voltage node, wherein the second clamping configuration is configured to activate the second clamping transistor in response to an indication of a discharge event at the output node.

2. The semiconductor device according to claim 1, wherein: The first clamping configuration includes a first inverter configuration coupled between the first reference voltage node and the second reference voltage node. The first inverter configuration has an input node coupled to the output node of the trigger configuration, and an inverter output node coupled to the first gate of the first clamping transistor. as well as The second clamping configuration includes a second inverter configuration coupled between the first reference voltage node and the second reference voltage node. The second inverter configuration has a second input node coupled to the output node of the trigger configuration, and a second inverter output node coupled to the second gate of the second clamping transistor.

3. The semiconductor device of claim 2, further comprising a third clamping configuration including a third clamping transistor coupled between the first reference voltage node and the second reference voltage node, wherein the third clamping configuration includes a third inverter configuration coupled between the first reference voltage node and the second reference voltage node, the third inverter configuration having a third input node coupled to the output node of the trigger configuration, and a third inverter output node coupled to the third gate of the third clamping transistor.

4. The semiconductor device according to claim 2, wherein: The first clamping configuration includes a first group of one or more parallel inverter configurations coupled between the first reference voltage node and the second reference voltage node, and connected in parallel with the first inverter configuration. Each parallel inverter configuration of the first group of one or more parallel inverter configurations includes a respective input node coupled to the output node of the trigger configuration, and a respective output node coupled to the first gate of the first clamping transistor. as well as The second clamping configuration includes a second group of one or more parallel inverter configurations coupled between the first reference voltage node and the second reference voltage node, and connected in parallel with the second inverter configuration, wherein each of the second group of one or more parallel inverter configurations includes a respective input node coupled to the output node of the trigger configuration, and a respective output node coupled to the second gate of the second clamping transistor.

5. The semiconductor device according to claim 2, wherein: The first clamping configuration includes a first group of one or more parallel transistors coupled between the first gate of the first clamping transistor and the second reference voltage node, wherein each of the first group of one or more parallel transistors includes a respective gate coupled to the output node of the triggering configuration to activate the respective parallel transistor in response to the indication of the discharge event at the output node; as well as The second clamping configuration includes a second group of one or more parallel transistors coupled between the second gate of the second clamping transistor and the second reference voltage node, wherein each of the second group of one or more parallel transistors includes a respective gate coupled to the output node of the triggering configuration to activate the respective parallel transistor in response to the indication of the discharge event at the output node.

6. The semiconductor device according to claim 2, wherein: The first clamping configuration includes a first group of one or more parallel transistors coupled between the first reference voltage node and the first gate of the first clamping transistor, wherein each of the first group of one or more parallel transistors includes a respective gate coupled to the output node of the triggering configuration to activate the respective parallel transistor in response to the indication of the discharge event at the output node; as well as The second clamping configuration includes a second group of one or more parallel transistors coupled between the first reference voltage node and the second gate of the second clamping transistor, wherein each of the second group of one or more parallel transistors includes a respective gate coupled to the output node of the triggering configuration to activate the respective parallel transistor in response to the indication of the discharge event at the output node.

7. A method for manufacturing a semiconductor device, characterized in that, The method includes: A first trigger configuration is formed, coupled between a first reference voltage node coupled to a first interface and a second reference voltage node coupled to a second interface, to provide a first indication of a discharge event at a first output node of the first trigger configuration; Forming a first clamping configuration, including a first clamping transistor; The first clamping transistor of the first clamping configuration is coupled to the first trigger configuration, located between the first reference voltage node and the second reference voltage node; A second trigger configuration is formed, coupled between the first reference voltage node and the second reference voltage node, to provide a second indication of the discharge event at the second output node of the second trigger configuration; Forming a second clamping configuration, including a second clamping transistor; and The second clamping transistor of the second clamping configuration is coupled to the second trigger configuration, located between the first reference voltage node and the second reference voltage node.

8. The method of claim 7, further comprising activating the first clamping transistor in response to the first indication of the discharge event at the first output node by the first clamping configuration.

9. The method of claim 8, further comprising activating the second clamping transistor in response to a second indication of the discharge event at the second output node by the second clamping configuration.

10. A method for manufacturing a semiconductor device, characterized in that, The method includes: A first trigger configuration is coupled between a first reference voltage node and a second reference voltage node to provide a first indication of a discharge event at a first output node of the first trigger configuration; A first clamping configuration is coupled to a first triggering configuration, the first clamping configuration including a first clamping transistor coupled between a first reference voltage node and a second reference voltage node, wherein the first clamping configuration is configured to activate the first clamping transistor in response to a first indication of a discharge event at the first output node; A second trigger configuration is coupled between the first reference voltage node and the second reference voltage node to provide a second indication of the discharge event at the second output node of the second trigger configuration; and A second clamping configuration is coupled to a second triggering configuration, the second clamping configuration including a second clamping transistor coupled between the first reference voltage node and the second reference voltage node, wherein the second clamping configuration is configured to activate the second clamping transistor in response to a second indication of a discharge event at the second output node.

Images