Semiconductor device and method of manufacturing the same

Abstract

The embodiment of the present application discloses a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises a circuit region and an edge region, a sealing ring is located in the edge region and surrounds the periphery of the circuit region, the sealing ring extends downward along the upper surface of the semiconductor device along a stacking direction, and an electrical isolation structure of the sealing ring is used to reduce the concentration of two-dimensional electron gas located thereunder. The sealing ring surrounding the circuit region and extending in the stacking direction achieves physical protection, and the electrical isolation structure used in the sealing ring achieves electrical protection, which can reduce the electrical influence of traps or defects at the edge of the cutting path on the internal device, and improve the stability and packaging reliability of the device.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to a semiconductor device and its manufacturing method. Background Technology

[0002] With increasing market demands for smaller size and higher energy efficiency in power devices, wide-bandgap semiconductor GaN devices have become widely used in high-frequency power conversion systems due to their lower power loss and faster switching capabilities. During device fabrication, multiple device regions on a wafer are divided by a grid-like dicing process. After fabricating these regions, the wafer is diced along the dicing lines to separate them into individual devices for packaging. However, during wafer dicing, the device regions near the dicing lines may experience mechanical impact, leading to localized cracking or defects on the cross-section of the diced individual devices.

[0003] A sealing ring is typically placed around the device to protect it from mechanical shock. Common sealing rings are formed using a metal interconnect layer or passivation layer to resist mechanical stress during cutting and to prevent moisture and contaminants from entering. However, after cutting, because the sealing ring cannot provide electrical protection, the internal devices of the sealing ring are connected to the carrier channels at the edge of the cut track. Traps and defects formed by cracks or breaks at the edge of the cut track can affect the electrical properties of the internal devices. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a semiconductor device and a method for manufacturing the same, thereby reducing the electrical impact of traps or defects at the dicing edge on the internal device and improving the stability and packaging reliability of the device.

[0005] In a first aspect, embodiments of the present invention provide a semiconductor device, comprising: A circuit region and an edge region, wherein the circuit region is located within the edge region; A sealing ring located in the edge region, the sealing ring surrounding the periphery of the circuit region; The sealing ring extends downward from near the upper surface of the semiconductor device along the stacking direction of the semiconductor device; The sealing ring includes an electrical isolation structure for reducing the concentration of two-dimensional electron gas located below it.

[0006] Optionally, the semiconductor device further includes an underlying structure, the sealing ring being located on or within the underlying structure, a heterojunction structure being formed within the underlying structure, and a two-dimensional electron gas being formed at the interface of the heterojunction structure.

[0007] Optionally, the sealing ring further includes a physical isolation structure located above the electrical isolation structure, the physical isolation structure including multiple metal layers and a plurality of through-hole structures connecting adjacent metal layers.

[0008] Optionally, the projected width of the electrical isolation structure along the stacking direction perpendicular to the underlying structure is less than or equal to the projected width of the physical isolation structure along the stacking direction perpendicular to the underlying structure.

[0009] Optionally, the electrical isolation structure for reducing the concentration of two-dimensional electron gas located below it includes: the electrical isolation structure for depleting the two-dimensional electron gas located below it to isolate the circuit region from the carrier channels at the dicing edge of the semiconductor device.

[0010] Optionally, the sealing ring extends downward along the stacking direction of the semiconductor device to the upper surface of the underlying structure.

[0011] Optionally, the electrical isolation structure includes a ring-shaped isolation structure located on the underlying structure, the ring-shaped isolation structure surrounding the periphery of the circuit region, the ring-shaped isolation structure being used to deplete the two-dimensional electron gas located below it.

[0012] Optionally, the ring-shaped isolation structure material is a P-type doped III-V compound, which includes one or more of P-type GaN, P-type AlGaN, P-type AlN, and P-type InGaN.

[0013] Optionally, the electrical isolation structure further includes an annular metal structure located on the annular isolation structure.

[0014] Optionally, the projection of the annular isolation structure along the direction perpendicular to the stacking direction of the underlying structure completely covers the projection of the annular metal structure along the direction perpendicular to the stacking direction of the underlying structure.

[0015] Optionally, the electrical isolation structure for reducing the concentration of two-dimensional electron gas located below it includes: the electrical isolation structure for isolating the two-dimensional electron gas located below it to isolate the circuit region from the carrier channels at the edge of the cut track.

[0016] Optionally, the sealing ring extends downward along the stacking direction of the semiconductor device into the barrier layer of the underlying structure or the channel layer of the underlying structure.

[0017] Optionally, the electrical isolation structure includes a ring-shaped through-hole structure, which is located in or extends through the barrier layer.

[0018] Optionally, the electrical isolation structure is a single ring structure.

[0019] Optionally, the electrical isolation structure includes multiple concentric ring structures.

[0020] Optionally, the ring structure can be one of the following shapes: a rectangular ring structure, a rounded rectangular ring structure, a chamfered rectangular ring structure, or a circular ring structure.

[0021] Optionally, the periphery of the electrical isolation structure and the physical isolation structure further includes an insulating structure.

[0022] Optionally, the insulation structure includes: The dielectric layer covering the outside of the electrical isolation structure; The first interlayer dielectric layer covering the outside of the dielectric layer; The N+1 interlayer dielectric layer covering the outside of the via structure between the Nth metal layer and the N+1th metal layer; And the passivation layer covering the outside of the top metal layer; Where N is a positive integer greater than or equal to 1.

[0023] Optionally, the underlying structure includes a substrate, a buffer layer, a channel layer, and a barrier layer stacked from bottom to top, wherein the channel layer and the barrier layer form a heterojunction structure.

[0024] Optionally, the electrical isolation structure is located on the upper surface of the barrier layer.

[0025] Optionally, the semiconductor device further includes a gate structure, a source structure, and a drain structure located within the circuit region. The gate structure is located on the upper surface of the barrier layer, and the source structure and the drain structure extend downward along the stacking direction of the semiconductor device to the upper surface of the channel layer, the interior of the channel layer, or the barrier layer. The source structure and the drain structure are located on both sides of the gate structure and are spaced apart from the gate structure.

[0026] Optionally, the gate structure includes a P-type doped III-V compound material structure and a gate metal structure located on the P-type doped III-V compound material structure.

[0027] Optionally, the upper surfaces of the source structure, the gate metal structure, and the drain structure are respectively connected to the first metal layer through a contact structure.

[0028] In a second aspect, embodiments of the present invention provide a method for manufacturing a semiconductor device, comprising: Forming the underlying structure; A gate structure is formed on the underlying structure; A ring-shaped electrical isolation structure is formed on the underlying structure, the electrical isolation structure surrounds the periphery of the gate structure, and a circuit region is formed on the inner side surrounded by the electrical isolation structure; A source structure and a drain structure are formed on both sides of the gate structure, and both the source structure and the drain structure are located in the circuit region; The electrical isolation structure is used to reduce the concentration of two-dimensional electron gas located below it.

[0029] Optionally, the method further includes: while forming the metal interconnect structure of the semiconductor device, forming a ring-shaped physical isolation structure above the electrical isolation structure, wherein the metal interconnect structure is located inside the physical isolation structure, and the metal interconnect structure includes a gate metal interconnect structure, a drain metal interconnect structure, and a source metal interconnect structure; Wherein, the projection of the physical isolation structure along the stacking direction perpendicular to the bottom layer completely covers the projection of the electrical isolation structure, and the electrical isolation structure is used to reduce the current carrier channels between the circuit region and the edge of the cut channel; The electrical isolation structure and the physical isolation structure together form a sealing ring.

[0030] Optionally, forming a gate structure on the underlying structure and forming a ring-shaped electrical isolation structure on the underlying structure includes: A P-type doped III-V compound material layer is formed on the underlying structure; A gate metal layer is formed on the P-type doped gate material layer; The gate metal layer is patterned and etched to form a gate metal structure; Patterning etching of the P-type doped III-V compound material layer to simultaneously form a P-type doped III-V compound material structure and at least one annular isolation structure surrounding the outside of the III-V compound material structure; The electrical isolation structure includes the ring-shaped isolation structure.

[0031] Optionally, forming a gate structure on the underlying structure and forming a ring-shaped electrical isolation structure on the underlying structure includes: A P-type doped III-V compound material layer is formed on the underlying structure; A gate metal layer is formed on the p-type doped III-V compound material layer; The gate metal layer is patterned and etched to simultaneously form a gate metal structure and a ring metal structure; Using the gate metal structure and the ring metal structure as masks respectively, the P-type doped III-V compound material layer is patterned and etched to simultaneously form the P-type doped III-V compound material structure and the ring isolation structure surrounding the outside of the III-V compound material structure. The ring-shaped metal structure is located on the ring-shaped isolation structure outside the P-type doped III-V compound material structure, and the electrical isolation structure includes the ring-shaped metal structure and the ring-shaped isolation structure.

[0032] Optionally, forming a gate structure on the underlying structure and forming a ring-shaped electrical isolation structure on the underlying structure includes: A P-type doped III-V compound material layer is formed on the underlying structure; A gate metal layer is formed on the p-type doped III-V compound material layer; The gate metal layer is patterned and etched to form a gate metal structure; Patterning etching of the P-type doped III-V compound material layer to form a P-type doped III-V compound material structure; The barrier layer of the underlying structure is patterned and etched to form a groove-shaped structure surrounding the outside of the III-V compound material structure, and the groove-shaped structure is the electrical isolation structure.

[0033] Optionally, after forming the gate structure and the ring-shaped electrical isolation structure, and before forming the source structure and the drain structure, the method further includes: A dielectric layer is formed on the underlying structure, wherein the dielectric layer covers the gate structure and the electrical isolation structure.

[0034] Optionally, after forming the source structure and the drain structure and before forming the metal interconnect structure of the semiconductor device, the method further includes: forming a first interlayer dielectric layer on the dielectric layer, wherein the first interlayer dielectric layer covers the source structure and the drain structure.

[0035] Optionally, while forming the metal interconnect structure and the physical isolation structure of the semiconductor device, the method further includes forming an insulating structure covering the metal interconnect structure.

[0036] Optionally, after forming the first interlayer dielectric layer and before forming the metal interconnect structure, the method further includes forming a source contact structure, a drain contact structure, and a gate contact structure on the source structure, the drain structure, and the gate structure, respectively.

[0037] Optionally, the method for forming the source contact structure, drain contact structure, and gate contact structure includes: The first interlayer dielectric layer is patterned and etched to form source structure contact holes, drain structure contact holes and gate structure contact holes, respectively. The source structure contact holes, drain structure contact holes and gate structure contact holes extend from the upper surface of the first interlayer dielectric layer of the insulating structure to the source structure, the drain structure and the gate structure, respectively. Conductive material is filled into the source structure contact hole, the drain structure contact hole, and the gate structure contact hole to form the source contact structure, the drain contact structure, and the gate contact structure, respectively.

[0038] Optionally, a method for forming an insulating structure covering the metal interconnect structure while forming the metal interconnect structure and the physical isolation structure of the semiconductor device includes: A first metallic material layer is formed on the upper surface of the first interlayer dielectric layer; The first metal material layer is patterned and etched to form the first metal layer; A second interlayer dielectric layer is formed on the first interlayer dielectric layer, and the second interlayer dielectric layer covers the first metal layer; Multiple through-hole structures are formed on the first metal layer, and the multiple through-hole structures extend from the upper surface of the second interlayer dielectric layer to the first metal layer. A second metallic material layer is formed on the upper surface of the second interlayer dielectric layer; The second metal material layer is patterned and etched to form a second metal layer, which is electrically connected to the plurality of via structures. A passivation layer is formed, the passivation layer covering the second metal layer, wherein the projections of the first metal layer and the second metal layer in a direction perpendicular to the underlying structure at least partially overlap.

[0039] Optionally, while forming the source contact structure, the drain contact structure, and the gate contact structure, the method further includes forming an isolation contact structure at a position corresponding to the electrical isolation structure, the isolation contact structure being connected to the first metal layer.

[0040] Optionally, the projected width of the electrical isolation structure along the direction perpendicular to the underlying structure layer is less than or equal to the projected width of the physical isolation structure along the direction perpendicular to the underlying structure layer.

[0041] Optionally, the sealing ring may be one of the following shapes: rectangular ring structure, rounded rectangular ring structure, chamfered rectangular ring structure, or circular ring structure.

[0042] Optionally, the electrical isolation structure includes multiple concentric ring structures.

[0043] This invention provides a semiconductor device and its manufacturing method. The semiconductor device includes a circuit region and an edge region. A sealing ring is located in the edge region and surrounds the periphery of the circuit region. The sealing ring extends downward along the upper surface of the semiconductor device in the stacking direction. The electrical isolation structure of the sealing ring is used to reduce the concentration of two-dimensional electron gas located below it. The sealing ring, which surrounds the circuit region and extends in the stacking direction, provides physical protection, while the electrical isolation structure within the sealing ring provides electrical protection. This reduces the electrical impact of traps or defects at the dicing edge on the internal device, improving the stability of the device and the reliability of the package. Attached Figure Description

[0044] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which: Figure 1-2 This is a schematic diagram of a semiconductor device structure according to an embodiment of the present invention; Figure 3 This is a flowchart of a semiconductor device manufacturing method according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the underlying structure of an embodiment of the present invention; Figure 5 This is a flowchart of a method for forming a gate structure and an electrical isolation structure according to an embodiment of the present invention; Figure 6-8 This is a schematic diagram of the various steps in forming an electrical isolation structure according to an embodiment of the present invention; Figure 9 This is a flowchart of a method for forming a gate structure and an electrical isolation structure according to another embodiment of the present invention; Figure 10-11 This is a schematic diagram of the various steps in forming an electrical isolation structure according to another embodiment of the present invention; Figure 12 This is a flowchart of a method for forming a gate structure and an electrical isolation structure according to another embodiment of the present invention; Figure 13-14 This is a schematic diagram of the various steps in forming an electrical isolation structure according to another embodiment of the present invention; Figure 15-18 These are schematic diagrams of semiconductor device structures after the formation of the dielectric layer in several embodiments of the present invention; Figures 19-20 This is a schematic diagram of the various steps in forming the source and drain structures according to an embodiment of the present invention; Figure 21 This is a schematic diagram of a semiconductor device structure after the formation of the first interlayer dielectric layer according to an embodiment of the present invention; Figure 22 This is a flowchart of a method for forming a contact structure according to an embodiment of the present invention; Figure 23 This is a schematic diagram of the semiconductor device structure after the contact structure is formed according to an embodiment of the present invention; Figure 24 This is a schematic diagram of the semiconductor device structure after the formation of the contact structure according to another embodiment of the present invention; Figure 25 This is a flowchart of a method for forming a physical isolation structure and an insulating structure simultaneously, according to an embodiment of the present invention. Figure 26-32 This is a schematic diagram of the various steps in forming a metal interconnect structure while simultaneously forming a physical isolation structure and an insulating structure, according to an embodiment of the present invention. Figure 33 This is a schematic diagram showing the positional relationship between the electrical isolation structure and the source structure, gate structure and drain structure according to an embodiment of the present invention; Figure 34 This is a schematic diagram of an embodiment of the present invention where the electrical isolation structure is formed in the shape of a rounded rectangle; Figure 35 This is a schematic diagram of an electrical isolation structure formed in another embodiment of the present invention, which is a multi-layered rounded rectangular shape; Figure 36 This is a schematic diagram of an electrical isolation structure formed into a rectangular shape according to an embodiment of the present invention; Figure 37 This is a schematic diagram of an electrical isolation structure formed in a multi-layered rectangular shape according to another embodiment of the present invention; Figure 38 This is a schematic diagram of an embodiment of the electrical isolation structure of the present invention, which is formed into a chamfered rectangular shape; Figure 39 This is a schematic diagram of an electrical isolation structure formed in another embodiment of the present invention, which is a multi-layered chamfered rectangular shape.

[0045] Explanation of reference numerals in the attached figures: 100 - Bottom layer; 101 - Substrate; 102 - Buffer layer; 103 - Channel layer; 104 - Barrier layer; 105 - P-type doped III-V compound material layer; 1051 - P-type doped III-V compound material structure; 1052 - Ring-shaped isolation structure; 106 - Gate metal layer; 1061 - Gate metal structure; 1062 - Ring-shaped metal structure; 107 - Dielectric layer; 108 - Contact structure; 1081 - Source contact structure; 1082 - Drain contact structure; 1083 - Gate contact structure; 1084 - Isolation contact structure; 109 - First interlayer dielectric layer; 1101 - First metal layer; 11011 - First source metal layer; 11012 - First drain metal layer; 11013 - First gate metal layer Layer; 11014-First physical protection structure; 111-Second interlayer dielectric layer; 1102-Second metal layer; 11021-Second source metal layer; 11022-Second drain metal layer; 11023-Second gate metal layer; 11024-Second physical protection structure; 113-Through-hole structure; 1131-Source through-hole structure; 1132-Drain through-hole structure; 1133-Gate through-hole structure; 1134-First metal through-hole structure; 114-Passivation layer; 115-Physical isolation structure; 116-Electrical isolation structure; 1161-Inner ring; 1162-Outer ring; 2-Gate structure; 3-Source structure; 4-Drain structure; 5-Cut-outline; 6-Sealing ring; 7-Two-dimensional electron gas; 81-Circuit region; 82-Edge region. Detailed Implementation

[0046] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0047] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0048] Unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0049] For ease of explanation, spatially related terms such as “inside,” “outside,” “below,” “below,” “lower,” “above,” “upper,” etc., are used herein to describe the relationship between one element or feature illustrated in the figure and another. It will be understood that spatially related terms may be intended to encompass different orientations of the device in use or operation besides those depicted in the figure. For example, if the device in the figure is flipped, an element described as “below” or “below” another element or feature would then be positioned “above” that other element or feature. Thus, the exemplified term “below” can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptive terms used herein should be interpreted accordingly.

[0050] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0051] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0052] In the fabrication of semiconductor devices, after the device region is completed, multiple devices on the wafer are not yet independently separated by a grid-like dicing channel. Separation of the devices requires external structures to cut along the dicing channel. Existing semiconductor devices typically use sealing rings around the device to protect against the mechanical impact of wafer dicing and prevent damage to internal devices. Wide-bandgap semiconductor GaN devices operate by confining electrons in a heterojunction to form a two-dimensional electron gas (2DEG). This 2DEG fills the space between the channel layer and the barrier layer. For an independent GaN device, the carrier channels at its edge are connected to the internal devices. Wafer dicing causes cracks and defects at the dicing edge, forming traps and defects. Existing sealing rings cannot provide electrical isolation, allowing these traps and defects to electrically affect the internal devices through the connected 2DEG. Therefore, it is necessary to cut off the electrically connected channels between the device's interior and its edges.

[0053] Reference Figure 1 , Figure 2The semiconductor device of this embodiment includes a circuit region 81, an edge region 82, and a sealing ring 6. The circuit region 81 is the region that performs the function of the semiconductor device. The circuit region 81 is located within the edge region 82. The edge region 82 does not perform the function of the semiconductor device itself; it provides space for wafer dicing and protects the circuit region 81 during wafer dicing. The sealing ring 6 is located within the edge region 82 and provides physical and electrical protection for the internal structure of the circuit region 81. The sealing ring 6 surrounds the periphery of the circuit region 81, does not occupy the space of the circuit region 81, and does not affect the circuit region 81.

[0054] Reference Figure 1 , Figure 4 The semiconductor device also includes an underlying structure 100, with a sealing ring 6 located on the underlying structure 100. The underlying structure 100 provides physical support and restricts the flow range of charge carriers. Specifically, a heterojunction structure is formed within the underlying structure 100, and a two-dimensional electron gas 7 is formed at the interface of the heterojunction structure. The two-dimensional electron gas 7 is extremely thin and highly conductive, enabling the device in the circuit region 81 to operate efficiently and normally. The higher the concentration of the two-dimensional electron gas 7, the stronger the current driving capability, the lower the gate voltage required to start conduction, and the easier it is to conduct.

[0055] Reference Figure 1 , Figure 2 The sealing ring 6 extends downwards from near the upper surface of the semiconductor device along the stacking direction, forming effective protection in the stacking direction. The sealing ring 6 includes an electrical isolation structure 116, which provides electrical protection by reducing the concentration of the two-dimensional electron gas 7 located beneath it, making it difficult for charge carriers at the edge of the dicing channel 5 to enter the circuit region 81 inside the electrical isolation structure 116. This avoids the electrical influence of the charge carrier channels inside the semiconductor device. Since the GaN device operates through the two-dimensional electron gas 7, reducing the concentration of the two-dimensional electron gas 7 creates a region where current is difficult to conduct, achieving isolation. The two-dimensional electron gas 7 within the isolation edge region 82 effectively prevents the current generated by edge traps from affecting the circuit region 81.

[0056] like Figure 1 , Figure 2As shown, the sealing ring 6 also includes a physical isolation structure 115, which provides physical protection against mechanical impact during cutting. The physical isolation structure 115 is located above the electrical isolation structure 116 and includes multiple metal layers and multiple through-hole structures 113 connecting adjacent metal layers. The stacking of the metal layers and through-holes above the electrical isolation structure 116 isolates the devices within the circuit region 81 from external mechanical impact. Typically, the physical isolation structure 115 located in the edge region 82 is formed simultaneously with the metal interconnect structure located in the circuit region 81, where the metal interconnect structure is used to implement the functions of semiconductor devices.

[0057] In some embodiments, refer to Figure 1 , Figure 2 The projected width of the electrical isolation structure 116 along the stacking direction perpendicular to the bottom layer structure 100 is less than or equal to the projected width of the physical isolation structure 115 along the stacking direction perpendicular to the bottom layer structure 100. In other words, in the stacking direction perpendicular to the bottom layer structure 100, the projection of the physical isolation structure 115 completely covers the projection of the electrical isolation structure 116. Since the structural integrity of the electrical isolation structure 116 affects the effectiveness of electrical isolation, the electrical isolation structure 116 needs to be protected by the physical isolation structure 115 to prevent damage to the electrical isolation structure 116 during cutting, which would make it difficult to effectively reduce the two-dimensional electron gas 7 beneath it and thus fail to isolate the charge carriers in the edge region 82.

[0058] In practical applications, different electrical isolation structures 116 can be used to achieve isolation. In one embodiment, referring to... Figure 8 The electrical isolation structure 116 is used to reduce the concentration of the two-dimensional electron gas 7 located below it by: depleting the two-dimensional electron gas 7 located below it to isolate the charge carrier channels between the circuit region 81 and the edge of the cutting channel 5. That is, in this embodiment, the electrical isolation structure 116 is formed to deplete the two-dimensional electron gas 7 to achieve electrical isolation. The location where the two-dimensional electron gas 7 is depleted is the part where the two-dimensional electron gas 7 is cut off, making it difficult for charge carriers in the edge region 82 to cross the cut-off two-dimensional electron gas 7 to enter the circuit region 81. It should be understood that in reality, there is a possibility that the two-dimensional electron gas 7 is not completely depleted; effectively reducing the two-dimensional electron gas 7 can also block the current.

[0059] It should be clarified that the "depletion" process described in this application is essentially the upward lifting of the band structure of the heterojunction through the electrical isolation structure 116. When the lifting is sufficient to make the quantum state energy level at the bottom of the interface potential well exceed the Fermi level, the two-dimensional electron gas that was originally accumulated due to the polarization effect will completely disappear due to the lack of state occupation.

[0060] like Figure 1 , Figure 4 As shown, the sealing ring 6 extends downwards along the stacking direction of the semiconductor device to the upper surface of the bottom layer structure 100. An electrical isolation structure 116 is disposed on the upper surface of the bottom layer structure 100 to deplete the two-dimensional electron gas 7 below it. To achieve complete protection of the circuit region 81, the electrical isolation structure 116 needs to completely surround the circuit region 81, cutting off carrier channels in all directions. Specifically, the electrical isolation structure 116 includes an annular isolation structure 1052 located on the bottom layer structure 100. The annular isolation structure 1052 surrounds the periphery of the circuit region 81, providing protection for the circuit region 81. The annular isolation structure 1052 depletes the two-dimensional electron gas 7 located below it, cutting off the two-dimensional electron gas 7 that connects to the edge region 82 in all directions of the circuit region 81, thus preventing the devices within the circuit region 81 from being affected by external carriers.

[0061] In some embodiments, the ring-shaped isolation structure 1052 is made of a p-type doped III-V compound, including one or more of p-type GaN, p-type AlGaN, p-type AlN, and p-type InGaN. The two-dimensional electron gas 7 is equivalent to an electron-rich N-type conductive channel, and the p-type doped compound can cooperate with it to effectively deplete the two-dimensional electron gas 7 in the region, forming isolation. Simultaneously, III-V compounds have strong polarization effects, and using a p-type doped III-V compound can achieve better depletion effects. Preferably, p-type GaN is typically chosen as the material for the ring-shaped isolation structure 1052.

[0062] In some embodiments, such as Figure 1 , Figure 10 , Figure 11 As shown, the electrical isolation structure 116 also includes an annular metal structure 1062 located on the annular isolation structure 1052. The annular metal structure 1062 is a structure formed together with the gate metal structure 1061 in the circuit region 81. When disposed on the annular isolation structure 1052, it can improve the depletion effect of the annular isolation structure 1052. In some embodiments, the projection of the annular isolation structure 1052 along the stacking direction perpendicular to the bottom layer structure 100 completely covers the projection of the annular metal structure 1062 along the stacking direction perpendicular to the bottom layer structure 100, that is, the width of the annular metal structure 1062 is less than or equal to the width of the annular isolation structure 1052. Preferably, the width of the annular metal structure 1062 is generally smaller than the width of the annular isolation structure 1052 to avoid defects that may be caused by the complex shape of the material edge.

[0063] In some embodiments, refer to Figure 1 , Figure 14The electrical isolation structure 116 is used to reduce the concentration of the two-dimensional electron gas 7 located below it by: the electrical isolation structure 116 is used to block the two-dimensional electron gas 7 located below it, so as to isolate the circuit region 81 from the carrier channel at the edge of the cut channel 5. That is, in this embodiment, the electrical isolation structure 116 is formed as a disconnection structure that disrupts the heterojunction to achieve electrical isolation. The location where the two-dimensional electron gas 7 is blocked is the part where the heterojunction plane is cut off. The carriers in the edge region 82 have difficulty crossing the cut-off two-dimensional electron gas 7 to enter the circuit region 81.

[0064] like Figure 1 , Figure 14 As shown, the sealing ring 6 extends downward along the stacking direction of the semiconductor device to the interface of the heterojunction structure, where the electrical isolation structure 116 is formed by a disconnected structure. Specifically, the sealing ring 6 extends downward into the barrier layer 104 of the bottom layer structure 100. The electrical isolation structure 116 includes a ring-shaped through-hole structure, which is located in or extends through the barrier layer 104. Due to the disruption of the heterojunction structure, a structure that blocks the continuity of the two-dimensional electron gas 7 is naturally formed. The two-dimensional electron gas 7 in the edge region 82 and the two-dimensional electron gas 7 in the circuit region 81 are each two unconnected regions. At this time, the charge carriers in the edge region 82 are confined within the two-dimensional electron gas 7 in the edge region 82. To achieve complete protection of the circuit region 81, the electrical isolation structure 116 needs to completely disconnect the circuit region 81 from the edge region 82, cutting off the charge carrier channels in all directions. This ensures that the two-dimensional electron gas 7 connected to the edge region 82 in all directions of the circuit region 81 is cut off, preventing the devices in the circuit region 81 from being affected by external charge carriers. Since the two-position electron gas is typically formed in the plane between the channel layer 103 and the barrier layer 104 in the underlying structure 100, in this embodiment, referring to... Figure 14 The heterojunction is destroyed by etching the barrier layer 104 to form a ring-shaped through-hole structure.

[0065] Depending on the actual situation, the width and number of turns of the electrical isolation structure 116 can be adjusted according to the actual device size and requirements. Generally, a wider, multi-turn electrical isolation structure 116 is more effective, but occupies more space and is more expensive; a narrower, single-turn electrical isolation structure 116 is less effective, but occupies less space, is less expensive, and is easier to miniaturize. Specifically, in some embodiments, refer to... Figures 33-39The electrical isolation structure 116 is a single ring structure; in other embodiments, the electrical isolation structure 116 includes multiple concentric ring structures. The width of the ring structure can be adjusted according to actual conditions, and is not limited in this embodiment. In some embodiments, preferably, the width of the inner ring 1161 of the ring structure can be greater than or equal to the width of the adjacent outer ring 1162. For the case of multiple concentric ring structures, since a large number of rings will occupy too much space, it is preferable to form the electrical isolation structure 116 with two concentric ring structures. The shape of the ring structure is one of the following: rectangular ring structure, rounded rectangular ring structure, chamfered rectangular ring structure, and circular ring structure. It should be understood that the shape and number of ring structures are not limited to the above embodiments. Depending on the actual situation, the ring structure can also be other shapes that better meet the needs of the device, so as to balance space occupation and isolation effect.

[0066] In some embodiments, refer to Figure 21 The electrical isolation structure 116 and the physical isolation structure 115 are further surrounded by an insulating structure. The insulating structure is used for support and makes the circuit structure inside the metal interconnect structure and the physical isolation structure 115 clear, preventing electrical short circuits and controlling parasitic capacitance.

[0067] Specifically, such as Figures 21-24 , Figures 25-32As shown, the insulating structure includes a dielectric layer 107, an interlayer dielectric layer, and a passivation layer 114. In this embodiment, the interlayer dielectric layer includes a first interlayer dielectric layer 109 and a second interlayer dielectric layer 111. The dielectric layer 107 covers the outside of the electrical isolation structure 116, isolating the electrical isolation structure 116 from the physical isolation structure 115, preventing the electrical isolation structure 116 from being electrically connected to the physical isolation structure 115 and thus destroying the isolation function. The first interlayer dielectric layer 109 covers the outside of the dielectric layer 107, filling the space between the dielectric layer 107 and the physical isolation structure 115 and the metal interconnect structure, so that the physical isolation structure 115 and the metal interconnect structure can be formed on the planar surface. Since the physical isolation structure 115 and the metal interconnect structure usually have multiple layers of metal layers and multiple layers of via structures 113 inside, the interlayer dielectric layer located outside the physical isolation structure 115 and the metal interconnect structure often also has multiple layers, so that each metal layer is formed on the planar surface and different metal layers are connected by vias. The number of metal layers and interlayer dielectric layers is not fixed, but the number of interlayer dielectric layers is usually the same as the number of metal layers, ensuring that each metal layer is supported and filled with insulating material. Specifically, the (N+1)th interlayer dielectric layer covers the outside of the via structure 113 between the Nth metal layer and the N+1th metal layer, where N is a positive integer greater than or equal to 1. A passivation layer 114 covers the outside of the top metal layer to protect the underlying device structure. Depending on the specific requirements, an opening is typically made in the passivation layer 114 corresponding to the location of the top metal layer to facilitate electrical connection between the external circuit structure and the top metal layer.

[0068] Based on this, the underlying structure 100 includes a substrate 101, a buffer layer 102, a channel layer 103, and a barrier layer 104 stacked from bottom to top. The channel layer 103 and the barrier layer 104 form a heterojunction structure, and a two-dimensional electron gas 7 is formed on the surface between the channel layer 103 and the barrier layer 104. An electrical isolation structure 116 is located above the channel layer 103. Specifically, in an embodiment that uses the depletion of the two-dimensional electron gas 7 for isolation, an annular isolation structure 1052 is formed on the upper surface of the barrier layer 104 to form the electrical isolation structure 116; in an embodiment that uses the disconnected heterojunction structure for isolation, the electrical isolation structure 116 is formed as a disconnected structure of the barrier layer 104, and the disconnected portion is filled by the dielectric layer 107.

[0069] Reference Figure 1 , Figure 2 The electrical isolation structure 116 and the physical isolation structure 115 together form a sealing ring 6. The physical isolation structure 115, which surrounds the circuit area 81 and extends in the stacking direction, provides physical protection, while the electrical isolation structure 116 provides electrical protection. This reduces the electrical impact of traps or defects at the edge of the cut track 5 on the internal components, thereby improving the stability of the components and the reliability of the package.

[0070] Reference Figure 1 , Figure 19 , Figure 20 The semiconductor device also includes a gate structure 2, a source structure 3, and a drain structure 4 located within the circuit region 81. The gate structure 2 is located on the upper surface of the barrier layer 104. The source structure 3 and the drain structure 4 extend downward along the stacking direction of the semiconductor device to the upper surface of the channel layer 103, the interior of the channel layer 103, or the barrier layer 104. The source structure 3 and the drain structure 4 are located on both sides of the gate structure 2 and are spaced apart from it. The source structure 3, the gate structure 2, and the drain structure 4 work together to control the switching and amplification functions of the semiconductor device. Specifically, the gate structure 2 includes a P-type doped III-V compound material structure 1051 and a gate metal structure 1061 located on the P-type doped III-V compound material structure 1051. The P-type doped III-V compound provides a higher barrier for the gate structure 2. The gate metal structure 1061 and the P-type doped III-V compound material structure 1051 form a Schottky junction, which enables efficient gate control.

[0071] like Figure 1 , Figure 2 As shown, the upper surfaces of the source structure 3, gate structure 2, and drain structure 4 are electrically connected to the metal interconnect structure within the circuit region 81, enabling conduction with the external circuit. In some embodiments, the upper surfaces of the source structure 3, gate metal structure 1061, and drain structure 4 are electrically connected to the first metal layer 1101 of the metal interconnect structure via contact structure 108, enabling electrical conduction. Specifically, the metal interconnect structure further includes at least one metal layer of gate metal interconnect structure, drain metal interconnect structure, and source metal interconnect structure. The gate metal interconnect structure is electrically connected to the gate structure 2 via gate contact structure 1083, the source metal interconnect structure is electrically connected to the source structure 3 via source contact structure 1081, and the drain metal interconnect structure is electrically connected to the drain structure 4 via drain contact structure 1082. When the semiconductor device is connected to an external circuit, the switching of the semiconductor device can be controlled by controlling the external circuit.

[0072] Based on this, embodiments of the present invention also disclose a method for manufacturing a semiconductor device to form the semiconductor device described above. (Refer to...) Figure 3 The manufacturing methods include: Step S100: Form the underlying structure 100.

[0073] Specifically, such as Figure 4As shown, the bottom layer structure 100 includes a substrate 101, a buffer layer 102, a channel layer 103, and a barrier layer 104 stacked from top to bottom. The substrate 101 can be made of Si, SiC, sapphire, AlN, Al2O3, or other materials. The material of the substrate 101 is not limited in this embodiment according to actual needs. Preferably, p-type Si is selected as the substrate 101 in this embodiment. The channel layer 103 is made of the same material as the buffer layer 102, such as GaN. In this embodiment, GaN is selected as both the channel layer 103 and the buffer layer 102. The barrier layer 104 can be made of III-V compound materials, such as AlGaN, InGaN, InAlGaN, GaN, AlN, GaAs, etc. Preferably, GaN or AlGaN is used as the barrier layer 104 in this embodiment. The channel layer 103 and the barrier layer 104 form a heterojunction, and a two-dimensional electron gas 7 is generated at the interface between the channel layer 103 and the barrier layer 104. The processes for forming a buffer layer 102 on the substrate 101, forming a channel layer 103 on the buffer layer 102, and forming a barrier layer 104 on the channel layer 103 can be epitaxy, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0074] Step S200: A gate structure 2 is formed on the bottom layer structure 100, and an annular electrical isolation structure 116 is formed on the bottom layer structure 100.

[0075] Specifically, refer to Figure 1 , Figure 18-19 , Figures 15-16 An electrical isolation structure 116 surrounds the gate structure 2. The inner side of the area surrounded by the electrical isolation structure 116 forms a circuit region 81, and the gate structure 2 is located within the circuit region 81. The location of the electrical isolation structure 116 and the outer side it surrounds form an edge region 82. The electrical isolation structure 116 is ring-shaped, providing protection for the circuit region 81 in all directions. Charge carriers within the edge region 82 are isolated by the electrical isolation structure 116, making it difficult for them to enter the circuit region 81, thus achieving electrical protection for the devices inside the circuit region 81. The gate structure 2 includes a gate metal structure 1061 and a p-type doped III-V compound material structure 1051. Depending on different requirements and manufacturing processes, the composition of the electrical isolation structure 116 can be varied, and the methods of its formation can also be diverse.

[0076] like Figure 5 , Figure 9 , Figure 12 As shown, forming a gate structure 2 on the underlying structure 100 and forming a ring-shaped electrical isolation structure 116 on the underlying structure 100 includes: Step S211: Form a P-type doped III-V compound material layer 105 on the underlying structure 100.

[0077] Step S212: Form a gate metal layer 106 on the P-type doped gate material layer.

[0078] Specifically, such as Figure 6 As shown, a P-type doped III-V compound material layer 105 and a gate metal layer 106 are sequentially formed by deposition or epitaxy. The P-type doped III-V compound material layer 105 covers the underlying structure 100, and the gate metal layer 106 covers the P-type doped III-V compound material layer 105. Preferably, in this embodiment, the material of the P-type doped III-V compound material layer 105 is P-type GaN.

[0079] Step S213: Pattern the gate metal layer 106 to form the gate metal structure 1061.

[0080] At this time, refer to Figure 1 , Figure 7 The resulting pattern is located only within the circuit region 81, and the remaining portion forms the gate metal structure 1061, which is a part of the gate structure 2. The gate metal layer 106 can be made of materials such as Ni, Au, W, Ti, or TiN.

[0081] Step S214: Patterning and etching the P-type doped III-V compound material layer 105 to simultaneously form a P-type doped III-V compound material structure 1051 and at least one annular isolation structure 1052 surrounding the outside of the III-V compound material structure.

[0082] Specifically, such as Figure 8 As shown, the pattern of the etched P-type doped III-V compound material layer 105 is located in both the circuit region 81 and the edge region 82. The portion located in the circuit region 81 is formed as the P-type doped III-V compound material structure 1051, which is another part of the gate structure 2. After removing the excess material, the P-type doped III-V compound material structure 1051 and the gate metal structure 1061 together form the gate structure 2. The portion located in the edge region 82 is formed as the annular isolation structure 1052, which is a part of the electrical isolation structure 116.

[0083] Based on actual needs, refer to Figures 33-39The annular isolation structure 1052 of the electrical isolation structure 116 can be rectangular, rounded rectangular, chamfered rectangular, or circular. The annular isolation structure 1052 can be a single ring or comprise multiple concentric rings. In the case of multiple concentric rings, since a large number of rings would occupy too much space, two concentric rings are preferred as the shape of the annular isolation structure. It should be understood that the shape and number of the annular isolation structure 1052 described above are merely examples and not limitations. In practical applications, the annular isolation structure 1052 can also be of other shapes.

[0084] Reference Figure 1 , Figure 8 In this embodiment, the electrical isolation structure 116 includes an annular isolation structure 1052. The material of the annular isolation structure 1052 is GaN, which can deplete the two-dimensional electron gas 7 below it, so that the carrier channels of the circuit region 81 and the edge of the cutting channel 5 are cut off, thereby achieving electrical protection.

[0085] Step S221: Form a P-type doped III-V compound material layer 105 on the underlying structure 100.

[0086] Step S222: Form a gate metal layer 106 on the P-type doped gate material layer.

[0087] Step S223: Pattern the gate metal layer 106 to form the gate metal structure 1061 and the annular metal structure 1062.

[0088] Specifically, refer to Figure 1 , Figure 10 The pattern of the etched gate metal layer 106 is located simultaneously in the circuit region 81 and the edge region 82. The portion located in the circuit region 81 is formed as the gate metal structure 1061, i.e., a part of the gate structure 2; the portion located in the edge region 82 is formed as the annular metal structure 1062, i.e., a part of the electrical isolation structure 116. Similarly, the shape of the annular isolation structure 1052 is not limited, nor is the number of annular rings within the annular isolation structure 1052 limited.

[0089] Step S224: Using the gate metal structure 1061 and the annular metal structure 1062 as masks, the P-type doped III-V compound material layer 105 is patterned and etched to simultaneously form the P-type doped III-V compound material structure 1051 and the annular isolation structure 1052 surrounding the III-V compound material structure.

[0090] Specifically, such as Figure 1 , Figure 10As shown, since the gate metal structure 1061 and the annular metal structure 1062 are used as masks, the pattern of the P-type doped III-V compound material layer 105 is simultaneously located in the circuit region 81 and the edge region 82. The part located in the circuit region 81 is formed as the P-type doped III-V compound material structure 1051, which is another part of the gate structure 2. After removing the excess material, the P-type doped III-V compound material structure 1051 and the gate metal structure 1061 together form the gate structure 2. The part located in the edge region 82 is formed as the annular isolation structure 1052 and is similar in shape to the annular metal structure 1062, which is a part of the electrical isolation structure 116.

[0091] Reference Figure 11 , Figures 33-39 When the annular metal structure 1062 is formed into multiple concentric rings, the annular isolation structure 1052 is also formed into multiple annular structures. The projection of the annular isolation structure 1052 along the stacking direction perpendicular to the bottom layer structure 100 completely covers the projection of the annular metal structure 1062 along the stacking direction perpendicular to the bottom layer structure 100. That is, the width of the annular metal structure 1062 is less than or equal to the width of the annular isolation structure 1052. Preferably, the width of the annular metal structure 1062 is usually smaller than the width of the annular isolation structure 1052 to avoid defects that may arise from the complex shape of the material edges.

[0092] Reference Figure 1 , Figure 10 , Figure 11 In this embodiment, the electrical isolation structure 116 includes an annular isolation structure 1052 and an annular metal structure 1062. The material of the annular isolation structure 1052 is GaN, which can deplete the two-dimensional electron gas 7 below it. The annular metal structure 1062 can enhance the depletion effect of the annular isolation structure 1052, so that the carrier channels of the circuit region 81 and the edge of the cutting channel 5 are cut off, thereby achieving electrical protection.

[0093] Step S231: Form a P-type doped III-V compound material layer 105 on the underlying structure 100.

[0094] Step S232: Form a gate metal layer 106 on the P-type doped gate material layer.

[0095] Step S233: Pattern the gate metal layer 106 to form the gate metal structure 1061.

[0096] Step S234: Patterning and etching the P-type doped III-V compound material layer 105 to form the P-type doped III-V compound material structure 1051.

[0097] At this time, as Figure 1 , Figure 13 As shown, the pattern formed is only located within the circuit region 81, and the remaining part is formed as a P-type doped III-V compound material structure 1051, which is part of the gate structure 2, and together with the gate metal structure 1061, it forms the gate structure 2.

[0098] Step S235: Patterning and etching the barrier layer 104 of the underlying structure 100 to form the electrical isolation structure 116 surrounding the outside of the III-V compound material structure.

[0099] Specifically, such as Figure 1 , Figure 14 As shown, the portion to be removed from the barrier layer 104 is located only within the edge region 82. After etching, a ring-shaped through-hole structure is formed on the barrier layer 104 outside the circuit region 81, which is the formed electrical isolation structure 116, separating the circuit region 81 from the edge region 82 and achieving electrical isolation by destroying the heterojunction at the groove structure. Similarly, the shape of the groove structure formed by etching is not limited, nor is the number of rings within the groove structure limited.

[0100] like Figure 1 , Figure 14 As shown, the electrical isolation structure 116 formed in this embodiment includes a ring-shaped groove structure on the channel layer 103, which can reduce the two-dimensional electron gas 7 located below it, i.e., on the upper surface of the channel layer 103, so that the carrier channels of the circuit region 81 and the edge of the cutting channel 5 are cut off, thereby achieving electrical protection.

[0101] Step S300: Form a dielectric layer 107 on the underlying structure 100.

[0102] Specifically, such as Figures 15-18 As shown, a dielectric layer 107 is formed by deposition or epitaxy, covering the gate structure 2 and the electrical isolation structure 116. Since the gate structure 2 and the electrical isolation structure 116 have already been formed, the dielectric layer 107 also covers the gate structure 2 and the electrical isolation structure 116. For the electrical isolation structure 116, the dielectric layer 107 can isolate it from the metal interconnect structure, preventing the electrical isolation structure 116 from being connected to the metal interconnect structure and thus compromising the isolation function.

[0103] Step S400: A source structure 3 and a drain structure 4 are formed on both sides of the gate structure 2, respectively.

[0104] Specifically, such as Figure 1 , Figures 19-20As shown, both the source structure 3 and the drain structure 4 are located in circuit region 81. Based on the corresponding positions of the source structure 3 and the drain structure 4, the dielectric layer 107 and the barrier layer 104 are patterned. Openings accommodating the source structure 3 and the drain structure 4 are etched on both sides of the gate structure 2 to form low-resistance ohmic contacts. In some embodiments, the opening size on the dielectric layer 107 is larger than the opening size on the barrier layer 104, forming an opening structure that is wider at the top and narrower at the bottom. Metal is filled into the openings to form the source structure 3 and the drain structure 4. Typically, metals such as Ti, Au, Al, and Ni, or alloys such as TiN and TiAl, are selected. The filled metal forms an ohmic contact with the barrier layer 104.

[0105] Step S500: Form a first interlayer dielectric layer 109 on the dielectric layer 107.

[0106] Reference Figure 21 A first interlayer dielectric layer 109 is formed by deposition, covering the source structure 3 and the drain structure 4. Since the gate structure 2, the electrical isolation structure 116, the source structure 3, and the drain structure 4 have already been formed, the first interlayer dielectric layer 109 also covers the gate structure 2 and the electrical isolation structure 116, ultimately forming a flat upper surface. The first interlayer dielectric layer 109 fills the space between the dielectric layer 107 and the metal interconnect structure, allowing the metal interconnect structure to be formed on the planar surface.

[0107] Step S600: A source contact structure 1081, a drain contact structure 1082, and a gate contact structure 1083 are formed on the source structure 3, the drain structure 4, and the gate structure 2, respectively, and an isolation contact structure 1084 is formed at the position corresponding to the electrical isolation structure 116.

[0108] A contact structure 108 is used to achieve the connection between the semiconductor and the metal. For example... Figure 22 As shown, the method for forming the source contact structure 1081, the drain contact structure 1082, and the gate contact structure 1083 includes: Step S601: Pattern the first interlayer dielectric layer 109 to form the source structure 3 contact hole, the drain structure 4 contact hole and the gate structure 2 contact hole respectively.

[0109] Specifically, refer to Figure 23The first interlayer dielectric layer 109 is etched at positions corresponding to the source structure 3, drain structure 4, and gate structure 2 to form through-holes, typically trapezoidal contact holes that are wider at the top and narrower at the bottom. Since the gate structure 2 is covered by the dielectric layer 107, when forming the contact holes, the dielectric layer 107 corresponding to the positions of the gate structure 2 needs to be further etched to expose the gate metal structure 1061 at the top of the gate structure 2, forming the contact hole for the gate structure 2. The first interlayer dielectric layer 109 is etched at positions corresponding to the source structure 3 and drain structure 4 to expose the metal of the source structure 3 and the metal of the drain structure 4, forming the source structure contact hole and the drain structure contact hole, respectively.

[0110] Step S602: Fill the source structure contact hole, drain structure contact hole and gate structure contact hole with conductive material to form source contact structure 1081, drain contact structure 1082 and gate contact structure 1083 respectively.

[0111] Contact structure 108 is formed using metals such as W as conductive materials, for example. Figure 23 As shown, the top of the filled conductive material is exposed on the first interlayer dielectric layer 109. Depending on the actual requirements, planarization processes such as chemical mechanical polishing (CMP) are used to treat the top of the conductive material and the surface of the first interlayer dielectric layer 109 to create a flat surface, facilitating the formation of a metal interconnect structure on the flat surface. Specifically, the source contact structure 1081 penetrates the first interlayer dielectric layer 109 and contacts the source structure 3; the drain contact structure 1082 penetrates the first interlayer dielectric layer 109 and contacts the drain structure 4; and the gate contact structure 1083 penetrates the first interlayer dielectric layer 109 and the dielectric layer 107 and contacts the gate structure 2. Contact structures 108 are provided to enable semiconductor-metal connections at the source structure 3, gate structure 2, and drain structure 4.

[0112] like Figure 1 , Figure 24 As shown, in some embodiments, an isolation contact structure 1084 is also formed at the position corresponding to the electrical isolation structure 116. Specifically, while etching to form contact holes in the circuit region 81, etching is also performed at the position corresponding to the electrical isolation structure 116 in the edge region 82 to form isolation contact holes penetrating the first interlayer dielectric layer 109. When conductive material is filled into the contact holes in the circuit region 81, since the isolation contact holes are exposed, the conductive material will also be deposited in the isolation contact holes to form the isolation contact structure 1084. The isolation contact structure 1084 penetrates the first interlayer dielectric layer 109, and its bottom contacts the dielectric layer 107 but does not penetrate the dielectric layer 107, thus avoiding electrical connection with the electrical isolation structure 116.

[0113] Step S700: While forming the metal interconnect structure of the semiconductor device, an annular physical isolation structure 115 is formed above the electrical isolation structure 116 to form an insulating structure covering the outside of the metal interconnect structure.

[0114] Specifically, refer to Figure 1 , Figure 2 The metal interconnect structure and the physical isolation structure 115 are formed simultaneously, with the metal interconnect structure located inside the physical isolation structure 115. The metal interconnect structure includes a gate metal interconnect structure, a drain metal interconnect structure, and a source metal interconnect structure, and is electrically connected to the contact holes of the gate structure 2, the drain structure 4, and the source structure 3, respectively. Along the stacking direction perpendicular to the bottom layer structure 100, the projection of the physical isolation structure 115 completely covers the projection of the electrical isolation structure 116. The physical isolation structure 115 is used to resist mechanical shock, and the electrical isolation structure 116 is used to reduce the carrier channels between the circuit region 81 and the edge of the cut channel 5. The electrical isolation structure 116 and the physical isolation structure 115 form a sealing ring 6.

[0115] like Figure 25 As shown, the method for forming an insulating structure covering the outside of the metal interconnect structure while forming the metal interconnect structure and physical isolation structure 115 of the semiconductor device includes: Step S701: A first metallic material layer is formed on the upper surface of the first interlayer dielectric layer 109.

[0116] Step S702: Pattern etching the first metal material layer to form the first metal layer 1101.

[0117] Specifically, refer to Figure 26 A first metal material layer is deposited on the upper surface of the first interlayer dielectric layer 109. Since the contact structure 108 is exposed on the first interlayer dielectric layer 109, the first metal material layer also covers the contact structure 108. The first metal material layer is patterned, leaving material corresponding to the positions of the source structure 3, gate structure 2, drain structure 4, and electrical isolation structure 116. After etching away excess material, a first metal layer 1101 is formed. Depending on the position, the first metal layer 1101 includes a first source metal layer 11011 electrically connected to the source contact structure 1081, a first gate metal layer 11013 electrically connected to the gate contact structure 1083, a first drain metal layer 11012 electrically connected to the drain contact structure 1082, and a first physical protection structure 11014. Figure 27 As shown, when the isolation contact structure 1084 is formed, the first physical protection structure 11014 is electrically connected to the isolation contact structure 1084.

[0118] Step S703: Form a second interlayer dielectric layer 111 on the first interlayer dielectric layer 109.

[0119] Specifically, refer to Figure 28 A second interlayer dielectric layer 111 is formed on the first interlayer dielectric layer 109. The thickness of the second interlayer dielectric layer 111 is greater than the thickness of the first metal layer 1101 and covers the first metal layer 1101, providing support and insulation.

[0120] Step S704: A plurality of through-hole structures 113 are formed on the first metal layer 1101.

[0121] Reference Figure 29 The second interlayer dielectric layer 111 is etched at positions corresponding to the source structure 3, drain structure 4, gate structure 2, and electrical isolation structure 116, forming through-holes. Multiple through-hole structures 113 extend from the upper surface of the second interlayer dielectric layer 111 to the first metal layer 1101, typically forming trapezoidal through-holes that are wider at the top and narrower at the bottom. After etching, the first source metal layer 11011, the first gate metal layer 11013, the first drain metal layer 11012, and the first physical protection structure 11014 are partially exposed.

[0122] Using metals such as Cu as conductive materials to form through-hole structures 113, such as Figure 29 As shown, the top of the filled conductive material is exposed to the first interlayer dielectric layer 109. According to actual needs, planarization processes such as chemical mechanical polishing (CMP) are used to treat the top of the conductive material and the surface of the second interlayer dielectric layer 111 to a flat surface, facilitating the further formation of the second metal layer 1102 and the second physical protection structure 11024 on the flat surface. Specifically, the source via structure 1131 penetrates the second interlayer dielectric layer 111 and contacts the first source metal layer 11011; the drain via structure 1132 penetrates the second interlayer dielectric layer 111 and contacts the first drain metal layer 11012; the gate via structure 1133 penetrates the second interlayer dielectric layer 111 and contacts the first gate metal layer 11013; and the first metal via structure 1134 penetrates the second interlayer dielectric layer 111 and contacts the first physical protection structure 11014. The via structures 113 enable electrical connections between the metal layers within the metal interconnect structure.

[0123] Step S705: A second metallic material layer is formed on the upper surface of the second interlayer dielectric layer 111.

[0124] Step S706: Pattern the second metal material layer to form the second metal layer 1102.

[0125] Specifically, such as Figure 30As shown, a second metal material layer is deposited on the upper surface of the second interlayer dielectric layer 111. Since the via structure 113 is exposed on the second interlayer dielectric layer 111, the second metal material layer also covers the via structure 113. The second metal material layer is patterned, leaving material at the locations corresponding to the source structure 3, gate structure 2, drain structure 4, and electrical isolation structure 116, respectively. After etching away excess material, a second metal layer 1102 is formed. Depending on the location, the second metal layer 1102 includes a second source metal layer 11021 electrically connected to the source contact structure 1081, a second gate metal layer 11023 electrically connected to the gate contact structure 1083, a second drain metal layer 11022 electrically connected to the drain contact structure 1082, and a second physical protection structure 11024 electrically connected to the isolation contact structure 1084. The projections of the first metal layer 1101 and the second metal layer 1102 along a direction perpendicular to the underlying structure 100 at least partially overlap, that is, the positions of the first metal layer 1101 and the second metal layer 1102 are correspondingly set.

[0126] It should be understood that the number of metal layers and the number of interlayer dielectric layers 107 are not limited. Depending on actual needs, the number of metal layers and interlayer dielectric layers 107 often has multiple layers, such that each metal layer is formed on a planar surface and connected to different metal layers by vias. The number of metal layers and interlayer dielectric layers 107 is not fixed, but the number of interlayer dielectric layers 107 is usually the same as the number of metal layers, ensuring that each metal layer is supported and filled with insulating material. Specifically, the (N+1)th interlayer dielectric layer 107 covers the outside of the via structure 113 between the Nth metal layer and the (N+1)th metal layer, where N is a positive integer greater than or equal to 1.

[0127] In this embodiment, a structure with two metal layers and two interlayer dielectric layers is used as an example. The resulting physical isolation structure 115 consists of a first physical protection structure 11014, a first metal via structure 1134, and a second physical protection structure 11024. In another embodiment, the resulting physical isolation structure 115 consists of an isolation contact structure 1084, a first physical protection structure 11014, a first metal via structure 1134, and a second physical protection structure 11024. As the number of metal layers and interlayer dielectric layers 107 increases, the number of via structures 113 between the metal layers also increases. The final physical isolation structure 115 is actually composed of an isolation contact structure 1084, multiple physical protection structures, and multiple metal via structures 113. The projected width of the electrical isolation structure 116 along the direction perpendicular to the bottom layer 100 is less than or equal to the projected width of the physical isolation structure 115 along the direction perpendicular to the bottom layer 100.

[0128] Specifically, refer to Figures 33-39The electrical isolation structure 116 comprises a plurality of concentric ring structures. In some embodiments, the electrical isolation structure 116 is a single ring structure; in other embodiments, the electrical isolation structure 116 comprises a plurality of concentric ring structures. In the case of multiple concentric ring structures, since a large number of rings would occupy too much space, it is preferable that two concentric ring structures form the electrical isolation structure 116. The physical isolation structure 115 and the electrical isolation structure 116 together form a sealing ring 6. Depending on the actual situation, the shape of the sealing ring 6 can be one of the following: a rectangular ring structure, a rounded rectangular ring structure, a chamfered rectangular ring structure, or a circular ring structure.

[0129] Step S707: Form a passivation layer 114, which covers the second metal layer 1102.

[0130] like Figure 31 , Figure 32 As shown, a passivation layer 114 is deposited to cover the second metal layer 1102, and a second interlayer dielectric layer 111 not covered by the second metal layer 1102 is also deposited. Further, to facilitate connection with external circuits, openings are typically etched on the passivation layer 114 at locations corresponding to the positions of the second gate metal layer 11023, the second source metal layer 11021, and the second drain metal layer 11022, thus exposing the upper surfaces of the second gate metal layer 11023, the second source metal layer 11021, and the second drain metal layer 11022.

[0131] Depending on the actual situation, such as Figure 1 , Figure 31 As shown, to facilitate subsequent wafer dicing, the dicing position on the outside of the sealing ring 6 is typically etched to form the dicing channel 5 before the passivation layer 114 is formed. After the dicing channel 5 is formed, the passivation layer 114 is deposited to facilitate guidance during wafer dicing, further preventing damage to the circuit area 81, thereby improving device stability and package reliability.

[0132] This application provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a circuit region and an edge region. A sealing ring is located in the edge region and surrounds the periphery of the circuit region. The sealing ring extends downward along the upper surface of the semiconductor device in the stacking direction. The electrical isolation structure of the sealing ring is used to reduce the concentration of two-dimensional electron gas located below it. The sealing ring, which surrounds the circuit region and extends in the stacking direction, provides physical protection, while the electrical isolation structure within the sealing ring provides electrical protection. This reduces the electrical impact of traps or defects at the dicing edge on the internal device, improving the stability of the device and the reliability of the package.

[0133] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor device, characterized in that, include: A circuit region and an edge region, wherein the circuit region is located within the edge region; A sealing ring located in the edge region, the sealing ring surrounding the periphery of the circuit region; The sealing ring extends downward from near the upper surface of the semiconductor device along the stacking direction of the semiconductor device; The sealing ring includes an electrical isolation structure for reducing the concentration of two-dimensional electron gas located below it.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes an underlying structure, the sealing ring being located on or within the underlying structure, a heterojunction structure being formed within the underlying structure, and a two-dimensional electron gas being formed at the interface of the heterojunction structure.

3. The semiconductor device according to claim 2, characterized in that, The sealing ring also includes a physical isolation structure located above the electrical isolation structure. The physical isolation structure includes multiple metal layers and a plurality of through-hole structures connecting adjacent metal layers.

4. The semiconductor device according to claim 3, characterized in that, The projected width of the electrical isolation structure along the stacking direction perpendicular to the underlying structure is less than or equal to the projected width of the physical isolation structure along the stacking direction perpendicular to the underlying structure.

5. The semiconductor device according to claim 2, characterized in that, The electrical isolation structure for reducing the concentration of two-dimensional electron gas located below it includes: the electrical isolation structure for depleting the two-dimensional electron gas located below it to isolate the circuit region from the carrier channels at the dicing edge of the semiconductor device.

6. The semiconductor device according to claim 5, characterized in that, The sealing ring extends downward along the stacking direction of the semiconductor device to the upper surface of the underlying structure.

7. The semiconductor device according to claim 6, characterized in that, The electrical isolation structure includes a ring-shaped isolation structure located on the underlying structure, the ring-shaped isolation structure surrounding the periphery of the circuit region, and the ring-shaped isolation structure being used to deplete the two-dimensional electron gas located below it.

8. The semiconductor device according to claim 7, characterized in that, The ring-shaped isolation structure material is a P-type doped III-V compound, which includes one or more of P-type GaN, P-type AlGaN, P-type AlN, and P-type InGaN.

9. The semiconductor device according to claim 7, characterized in that, The electrical isolation structure also includes a ring-shaped metal structure located on the ring-shaped isolation structure.

10. The semiconductor device according to claim 9, characterized in that, The projection of the annular isolation structure along the direction perpendicular to the stacking direction of the underlying structure completely covers the projection of the annular metal structure along the direction perpendicular to the stacking direction of the underlying structure.

11. The semiconductor device according to claim 2, characterized in that, The electrical isolation structure for reducing the concentration of two-dimensional electron gas located below it includes: the electrical isolation structure for isolating the two-dimensional electron gas located below it to isolate the circuit region from the carrier channels at the edge of the cut track.

12. The semiconductor device according to claim 11, characterized in that, The sealing ring extends downward along the stacking direction of the semiconductor device into the barrier layer of the underlying structure or the channel layer of the underlying structure.

13. The semiconductor device according to claim 12, characterized in that, The electrical isolation structure includes a ring-shaped through-hole structure, which is located in or extends through the barrier layer.

14. The semiconductor device according to claim 1, characterized in that, The electrical isolation structure is a single ring structure.

15. The semiconductor device according to claim 1, characterized in that, The electrical isolation structure comprises multiple concentric ring structures.

16. The semiconductor device according to claim 14 or 15, characterized in that, The ring structure can be one of the following shapes: rectangular ring structure, rounded rectangular ring structure, chamfered rectangular ring structure, or circular ring structure.

17. The semiconductor device according to claim 3, characterized in that, The electrical isolation structure and the physical isolation structure are further surrounded by an insulation structure.

18. The semiconductor device according to claim 17, characterized in that, The insulating structure includes: The dielectric layer covering the outside of the electrical isolation structure; The first interlayer dielectric layer covering the outside of the dielectric layer; The N+1 interlayer dielectric layer covering the outside of the via structure between the Nth metal layer and the N+1th metal layer; And the passivation layer covering the outside of the top metal layer; Where N is a positive integer greater than or equal to 1.

19. The semiconductor device according to claim 2, characterized in that, The underlying structure includes a substrate, a buffer layer, a channel layer, and a barrier layer stacked from bottom to top, wherein the channel layer and the barrier layer form a heterojunction structure.

20. The semiconductor device according to claim 19, characterized in that, The electrical isolation structure is located on the upper surface of the barrier layer.

21. The semiconductor device according to claim 19, characterized in that, The semiconductor device further includes a gate structure, a source structure, and a drain structure located within the circuit region. The gate structure is located on the upper surface of the barrier layer. The source structure and the drain structure extend downward along the stacking direction of the semiconductor device to the upper surface of the channel layer, the interior of the channel layer, or the barrier layer. The source structure and the drain structure are located on both sides of the gate structure and are spaced apart from the gate structure.

22. The semiconductor device according to claim 21, characterized in that, The gate structure includes a P-type doped III-V compound material structure and a gate metal structure located on the P-type doped III-V compound material structure.

23. The semiconductor device according to claim 22, characterized in that, The upper surfaces of the source structure, the gate metal structure, and the drain structure are respectively connected to the first metal layer through contact structures.

24. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: Forming the underlying structure; A gate structure is formed on the underlying structure; A ring-shaped electrical isolation structure is formed on the underlying structure, the electrical isolation structure surrounds the periphery of the gate structure, and a circuit region is formed on the inner side surrounded by the electrical isolation structure; A source structure and a drain structure are formed on both sides of the gate structure, and both the source structure and the drain structure are located in the circuit region; The electrical isolation structure is used to reduce the concentration of two-dimensional electron gas located below it.

25. The manufacturing method according to claim 24, characterized in that, The method further includes: while forming the metal interconnect structure of the semiconductor device, forming a ring-shaped physical isolation structure above the electrical isolation structure, wherein the metal interconnect structure is located inside the physical isolation structure, and the metal interconnect structure includes a gate metal interconnect structure, a drain metal interconnect structure, and a source metal interconnect structure; Wherein, the projection of the physical isolation structure along the stacking direction perpendicular to the bottom layer completely covers the projection of the electrical isolation structure, and the electrical isolation structure is used to reduce the current carrier channels between the circuit region and the edge of the cut channel; The electrical isolation structure and the physical isolation structure together form a sealing ring.

26. The manufacturing method according to claim 24, characterized in that, The formation of a gate structure on the underlying structure and the formation of a ring-shaped electrical isolation structure on the underlying structure include: A P-type doped III-V compound material layer is formed on the underlying structure; A gate metal layer is formed on the P-type doped gate material layer; The gate metal layer is patterned and etched to form a gate metal structure; Patterning etching of the P-type doped III-V compound material layer to simultaneously form a P-type doped III-V compound material structure and at least one annular isolation structure surrounding the outside of the III-V compound material structure; The electrical isolation structure includes the ring-shaped isolation structure.

27. The manufacturing method according to claim 24, characterized in that, Forming a gate structure on the underlying structure and forming a ring-shaped electrical isolation structure on the underlying structure includes: A P-type doped III-V compound material layer is formed on the underlying structure; A gate metal layer is formed on the p-type doped III-V compound material layer; The gate metal layer is patterned and etched to simultaneously form a gate metal structure and a ring metal structure; Using the gate metal structure and the ring metal structure as masks respectively, the P-type doped III-V compound material layer is patterned and etched to simultaneously form the P-type doped III-V compound material structure and the ring isolation structure surrounding the outside of the III-V compound material structure. The ring-shaped metal structure is located on the ring-shaped isolation structure outside the P-type doped III-V compound material structure, and the electrical isolation structure includes the ring-shaped metal structure and the ring-shaped isolation structure.

28. The manufacturing method according to claim 25, characterized in that, Forming a gate structure on the underlying structure and forming a ring-shaped electrical isolation structure on the underlying structure includes: A P-type doped III-V compound material layer is formed on the underlying structure; A gate metal layer is formed on the p-type doped III-V compound material layer; The gate metal layer is patterned and etched to form a gate metal structure; Patterning etching of the P-type doped III-V compound material layer to form a P-type doped III-V compound material structure; The barrier layer of the underlying structure is patterned and etched to form a groove-shaped structure surrounding the outside of the III-V compound material structure, and the groove-shaped structure is the electrical isolation structure.

29. The manufacturing method according to claim 25, characterized in that, After forming the gate structure and the ring-shaped electrical isolation structure, and before forming the source structure and the drain structure, the method further includes: A dielectric layer is formed on the underlying structure, wherein the dielectric layer covers the gate structure and the electrical isolation structure.

30. The manufacturing method according to claim 29, characterized in that, After forming the source structure and the drain structure, and before forming the metal interconnect structure of the semiconductor device, the method further includes: forming a first interlayer dielectric layer on the dielectric layer, wherein the first interlayer dielectric layer covers the source structure and the drain structure.

31. The manufacturing method according to claim 30, characterized in that, While forming the metal interconnect structure and the physical isolation structure of the semiconductor device, the method further includes forming an insulating structure covering the metal interconnect structure.

32. The manufacturing method according to claim 31, characterized in that, After forming the first interlayer dielectric layer and before forming the metal interconnect structure, the method further includes forming a source contact structure, a drain contact structure, and a gate contact structure on the source structure, the drain structure, and the gate structure, respectively.

33. The manufacturing method according to claim 32, characterized in that, The method for forming the source contact structure, drain contact structure, and gate contact structure includes: The first interlayer dielectric layer is patterned and etched to form source structure contact holes, drain structure contact holes and gate structure contact holes, respectively. The source structure contact holes, drain structure contact holes and gate structure contact holes extend from the upper surface of the first interlayer dielectric layer of the insulating structure to the source structure, the drain structure and the gate structure, respectively. Conductive material is filled into the source structure contact hole, the drain structure contact hole, and the gate structure contact hole to form the source contact structure, the drain contact structure, and the gate contact structure, respectively.

34. The manufacturing method according to claim 33, characterized in that, A method for forming an insulating structure covering the metal interconnect structure while forming the metal interconnect structure and the physical isolation structure of the semiconductor device includes: A first metallic material layer is formed on the upper surface of the first interlayer dielectric layer. The first metal material layer is patterned and etched to form the first metal layer; A second interlayer dielectric layer is formed on the first interlayer dielectric layer, and the second interlayer dielectric layer covers the first metal layer; Multiple through-hole structures are formed on the first metal layer, and the multiple through-hole structures extend from the upper surface of the second interlayer dielectric layer to the first metal layer. A second metallic material layer is formed on the upper surface of the second interlayer dielectric layer; The second metal material layer is patterned and etched to form a second metal layer, which is electrically connected to the plurality of via structures. A passivation layer is formed, the passivation layer covering the second metal layer, wherein the projections of the first metal layer and the second metal layer in a direction perpendicular to the underlying structure at least partially overlap.

35. The manufacturing method according to claim 34, characterized in that, While forming the source contact structure, the drain contact structure, and the gate contact structure, the method further includes forming an isolation contact structure at a position corresponding to the electrical isolation structure, the isolation contact structure being connected to the first metal layer.

36. The manufacturing method according to claim 25, characterized in that, The projected width of the electrical isolation structure along the direction perpendicular to the bottom layer is less than or equal to the projected width of the physical isolation structure along the direction perpendicular to the bottom layer.

37. The manufacturing method according to claim 24, characterized in that, The sealing ring can be one of the following shapes: rectangular ring structure, rounded rectangular ring structure, chamfered rectangular ring structure, or circular ring structure.

38. The manufacturing method according to claim 24, characterized in that, The electrical isolation structure comprises multiple concentric ring structures.

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