Power module and method of forming the same

Abstract

The application provides a power module, a plurality of wafers are arranged on one side of a substrate and are electrically connected to the substrate, a lead frame is arranged on the substrate and the plurality of wafers, a bottom surface of the lead frame has a recessed area, the plurality of wafers are accommodated in the recessed area, and the bottom surface of the lead frame is electrically connected to the substrate, a first sintering layer is accommodated in the recessed area and is located between the plurality of wafers and the lead frame, wherein the recessed area comprises a first recess, the first recess has a first bottom wall and a first side wall surrounding the first bottom wall, the first bottom wall has a second recess, the first sintering layer is located in the second recess and is in physical contact with and electrically connected to the plurality of wafers, and a normal projection of the plurality of wafers towards the lead frame falls in the second recess, wherein at the bottom wall of the second recess, the lead frame and the first sintering layer are fusion welded together. Embodiments of the application provide a power module and a forming method thereof, and at least the thickness of the power module is reduced.

Description

Technical Field

[0001] Embodiments of the present invention relate to power modules and methods for forming the same. Background Technology

[0002] To reduce energy loss, power module products are evolving towards high-voltage, high-current applications. Driven by the trend towards high current, high voltage, and low material costs, and to increase the product's withstand capability at high currents, reduce energy loss during current transmission, and decrease product thickness, the electrical conduction method has shifted from aluminum wire bonding to leadframes or clips, coupled with direct metal-to-metal bonding methods such as direct terminal bonding and flip-chip bonding (DBC) to increase product reliability and reduce material costs. Currently, the highest voltage and current values ​​for power module products on the market are 1200V and 450A, with a product thickness of 6mm to 8mm. Summary of the Invention

[0003] This invention provides a power module, comprising: a substrate; a plurality of laterally spaced wafers disposed on one side of the substrate and electrically connected to the substrate; a lead frame disposed on the substrate and the plurality of wafers, the bottom surface of the lead frame having a recessed region, the plurality of wafers being accommodated in the recessed region, the bottom surface of the lead frame being electrically connected to the substrate; and a first sintered layer accommodated in the recessed region and located between the plurality of wafers and the lead frame, wherein the recessed region includes a first recess, the first recess having a first bottom wall and a first side wall surrounding the first bottom wall, the first bottom wall having a second recess, the first sintered layer being located in the second recess and physically contacting and electrically connected to the plurality of wafers, the orthographic projection of the plurality of wafers toward the lead frame falling into the second recess, wherein the lead frame and the first sintered layer are fused together at the bottom wall of the second recess.

[0004] In some embodiments, the substrate includes a dielectric layer and a metal layer disposed on one side of the dielectric layer, the metal layer electrically connecting the lead frame and the plurality of wafers, the lead frame being fused together with the metal layer.

[0005] In some embodiments, the lead frame has a protrusion located on the bottom wall of the second groove and protruding toward the substrate, the protrusion being located between adjacent wafers.

[0006] In some embodiments, the protrusion height of the protrusion is equal to the depth of the second groove.

[0007] In some embodiments, the first sintered layer has a central region and an edge region surrounding the central region, the porosity of the central region being lower than that of the edge region, and the heat-affected zone of the first sintered layer fused with the lead frame is located in the central region.

[0008] In some embodiments, the lattice arrangement of the heat-affected zone is different from the lattice arrangement of the portion of the first sintered layer and the lead frame located outside the heat-affected zone.

[0009] In some embodiments, the heat-affected zone does not reach the bottom surface of the first sintered layer.

[0010] In some embodiments, the ratio of the thickness of the bottom wall of the second groove to the thickness of the first sintered layer is 1:0.5.

[0011] In some embodiments, the plurality of wafers have different thicknesses, and the second groove has different depths at portions of the wafers corresponding to the different thicknesses.

[0012] In some embodiments, the power module further includes a second sintered layer disposed between each of the wafers and the substrate, wherein the wafers are electrically connected to the substrate through the second sintered layer.

[0013] In some embodiments, the thickness of the first sintered layer is greater than the thickness of the second sintered layer.

[0014] In some embodiments, the power module further includes a resistor disposed on the substrate and electrically connected to the substrate, the resistor being disposed between the plurality of wafers and the first sidewall of the first groove.

[0015] In some embodiments, the first sintered layer is connected to the electrode of the wafer, and the width of the first sintered layer is the same as the width of the electrode, such that the sidewall of the first sintered layer is aligned with the electrode.

[0016] In some embodiments, the electrode, the first sintered layer, and the lead frame are made of the same material.

[0017] In some embodiments, the lead frame includes a first lead welded to the metal layer, the width of the end of the first lead welded to the metal layer being greater than the width of the other portions of the first lead.

[0018] Embodiments of this application also provide a process for manufacturing a power module, including: providing a plurality of laterally spaced wafers; forming a first sintered layer on each of the wafers; electrically connecting the plurality of wafers to a metal layer on a substrate; placing a lead frame on the substrate and the plurality of wafers, the bottom surface of the lead frame having a recessed region, the first sintered layer and the plurality of wafers being accommodated in the recessed region, the recessed region including a first recess, the first recess having a first bottom wall and a first side wall surrounding the first bottom wall, the first bottom wall having a second recess, the first sintered layer being located in the second recess, the orthogonal projection of the plurality of wafers toward the lead frame falling in the second recess; and melting the lead frame and the metal layer by laser welding, wherein at the bottom wall of the second recess, the lead frame and the first sintered layer are melted by laser welding.

[0019] In some embodiments, forming the first sintered layer on each of the wafers includes: forming a sintering paste layer on each of the wafers, the sintering paste layer including a solvent and copper particles mixed in the solvent, the solvent being a material including at least one of benzoic acid, phthalic acid, hexanoic acid, methanol, ethanol, and ethylene glycol; hot-pressing the sintering paste layer, the solvent evaporating, and the copper particles fusing together to obtain the first sintered layer.

[0020] In some embodiments, the first groove is formed by pressing the lead frame, and the second groove is formed by etching the lead frame.

[0021] In some embodiments, the thickness of the portion of the lead frame welded to the metal layer is greater than the thickness of the bottom wall of the second groove, and the power used to weld the lead frame to the metal layer is greater than the power used to weld the bottom wall of the second groove to the first sintered layer; or the thickness of the portion of the lead frame welded to the metal layer is equal to the thickness of the bottom wall of the second groove, and the power used to weld the lead frame to the metal layer is equal to the power used to weld the bottom wall of the second groove to the first sintered layer.

[0022] Embodiments of this application also provide a power module, comprising: a substrate including a dielectric layer and a metal layer disposed on one side of the dielectric layer; a wafer disposed on the metal layer and electrically connected to the metal layer; a lead frame disposed on the substrate and the wafer, the bottom surface of the lead frame having a groove region, the wafer being accommodated in the groove region, the lead frame being fused to the metal layer; and a first sintered layer accommodated in the groove region and located between the wafer and the lead frame, wherein the groove region includes a first groove, the first groove having a first bottom wall and a first side wall surrounding the first bottom wall, the first bottom wall having a second groove, the first sintered layer being located in the second groove and physically contacting and electrically connected to the wafer, the orthogonal projection of the wafer toward the lead frame falling in the second groove, wherein the lead frame is fused to the first sintered layer at the bottom wall of the second groove.

[0023] The embodiments of this application use lead frames to connect the wafer and the substrate, providing a high-voltage, high-current power module and reducing the thickness of the power module. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It is worth noting that, according to industry standard practice, the various components are not drawn to scale and are only used for illustrative purposes. In fact, for the sake of clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0025] Figure 1 Power modules of some embodiments are shown.

[0026] Figure 2 Power modules of other embodiments are shown.

[0027] Figure 3 A power module according to some embodiments of this application is shown.

[0028] Figure 4 A power module according to some other embodiments of this application is shown.

[0029] Figure 5 Compared to Figure 4 The heat-affected zone produced by laser welding is shown.

[0030] Figure 6 It shows the relationship with Figure 4 Exploded views of power modules in different embodiments.

[0031] Figure 7 A top view of several power modules according to some embodiments of this application is shown.

[0032] Figure 8 It shows the corresponding Figure 7 Cross-sectional views of the substrate and wafer in the illustrated embodiment.

[0033] Figure 9 The chip inside is shown.

[0034] Figure 10 A top view of several power modules according to some embodiments of this application is shown.

[0035] Figure 11 It shows the corresponding Figure 10 Cross-sectional views of the substrate and wafer in the illustrated embodiment.

[0036] Figure 12 The chip inside is shown.

[0037] Figure 13 It shows the relationship with Figure 4 Different implementations.

[0038] Figure 14 It shows the relationship with Figure 4 , Figure 13 Different implementations.

[0039] Figure 15 Multiple wafers are reconstructed on a first carrier.

[0040] Figure 16 The first sintering paste layer is printed on the wafer.

[0041] Figure 17 The first sintered layer is shown.

[0042] Figure 18 The illustration shows the substrate being placed on a second carrier.

[0043] Figure 19 The second sintering paste layer is printed on the substrate.

[0044] Figure 20 The diagram shows multiple wafers and resistors placed on a second sintering paste layer.

[0045] Figure 21 The second sintered layer is shown.

[0046] Figure 22 This illustrates forming the lead frame in Figure 21 The resulting structure.

[0047] Figure 23a , Figure 23b , Figure 23c , Figure 23d , 23e Different forms of laser welding leads are shown. Detailed Implementation

[0048] To better understand the spirit of the embodiments of this application, the following description is based on some preferred embodiments of this application.

[0049] Embodiments of this application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are represented by similar reference numerals. The embodiments described herein with reference to the accompanying drawings are illustrative and diagrammatic in nature and are intended to provide a basic understanding of this application. The embodiments of this application should not be construed as limiting this application.

[0050] The terms “approximately,” “generally,” “substantial,” “substantial,” “about,” and “approximately” used herein are used to indicate and explain minor variations. For example, when used in conjunction with numerical values, the above terms may refer to a range of variation less than or equal to ±10% of the corresponding numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another embodiment, the thickness of a film or layer being “substantially uniform” may refer to the average thickness of the film or layer being less than or equal to ±10% of the standard deviation, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" can refer to two surfaces that are within 50 μm along the same plane (such as within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm along the same plane). If, for example, two components overlap or overlap within 200 μm, 150 μm, 100 μm, 50 μm, 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm, then the two components can be considered "substantially aligned." If the angle between two surfaces or components is, for example, 90° ± 10° (such as ± 5°, ± 4°, ± 3°, ± 2°, ± 1°, ± 0.5°, ± 0.1°, or ± 0.05°), then the two surfaces or components can be considered "substantially perpendicular." When used in conjunction with an event or situation, the terms "approximately," "generally," "substantially," "materially," "about," and "approximately" can refer to the exact occurrence of the event or situation as well as the very close approximation of its occurrence.

[0051] In this specification, unless otherwise specified or limited, relative terms such as “central,” “longitudinal,” “lateral,” “front,” “rear,” “right,” “left,” “inner,” “outer,” “lower,” “higher,” “horizontal,” “vertical,” “above,” “below,” “above,” “below,” “top,” “backside,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) should be interpreted as referring to the directions described in the discussion or in the accompanying drawings. These relative terms are used for descriptive convenience only and do not require that this application be constructed or operated in a particular orientation.

[0052] For ease of description, "first," "second," "third," etc., can be used in this article to distinguish different components of a figure or a series of figures. "First," "second," "third," etc., are not intended to describe the corresponding components.

[0053] Figure 1 Some embodiments of the power module are shown, in which aluminum wire 1 (with a wire diameter of, for example, 300 μm) and copper wire 2 are used as interconnects for current conduction. To meet the future demands of high-voltage modules in the electric vehicle market, using thick aluminum wire (e.g., wire diameter > 12 mil) on the die 20 for current conduction is no longer sufficient, while using thick copper wire (e.g., wire diameter > 12 mil) poses a risk of damaging the die 20. Therefore, a buffer layer 3 (material, for example, Cu) needs to be soldered onto the die 20 to prevent damage. In some embodiments, copper strip bonding (Cu) can also be used for current conduction.

[0054] For the selection of interconnect wire materials, Cu is preferred. Cu wire has a diameter of, for example, 0.075 mm, a thermal conductivity of, for example, 386 W / (m×K) to 398 W / (m×K), and a coefficient of thermal expansion of, for example, 17.8 ppm / ℃. Al wire has a thermal conductivity of, for example, 205 W / (m×K) to 230 W / (m×K), and a coefficient of thermal expansion of, for example, 23.8 ppm / ℃ to 26.4 ppm / ℃. Au wire has a diameter of, for example, 0.500 mm, a thermal conductivity of, for example, 310 W / (m×K), and a coefficient of thermal expansion of, for example, 14 ppm / ℃. Ag wire has a thermal conductivity of, for example, 429 W / (m×K), and a coefficient of thermal expansion of, for example, 19 ppm / ℃.

[0055] Figure 2Other embodiments of the power module are shown, in which aluminum wire 1 and copper clips 4 are used as interconnects for current conduction. Clips 4 are soldered to the chip 20 via a solder layer 5 (material such as solder paste), a method of current conduction known as direct lead bonding (DLB).

[0056] Figure 3 A power module 100 according to some embodiments of this application is shown. The substrate 10 is, for example, an active metal brazing (AMB) substrate / direct copper cladding (DBC) substrate, including a dielectric layer 12 and metal layers 14 disposed on both sides of the dielectric layer 12. A wafer 20 is disposed on the substrate 10. A second sintered layer 42 connects the drain pad 24 of the wafer 20 and the metal layer 14. A first sintered layer 41 is disposed on the source pad 26 of the wafer 20, and a clip 4 is welded to the first sintered layer 41, the clip 4 and the metal layer 14 by laser welding (e.g., using an infrared laser / green laser) to electrically connect the source pad 26 of the wafer 20 and the metal layer 14.

[0057] In some embodiments, the dielectric layer 12 of the substrate 10 is, for example, a ceramic layer with a thickness of, for example, 300 μm to 600 μm (this thickness is beneficial for warpage control). The metal layer 14 of the substrate 10 on the side facing the wafer 20 is, for example, a copper layer with a thickness of, for example, 300 μm to 500 μm (this thickness is beneficial for warpage control). The first sintered layer 41 has a thickness of, for example, greater than 200 μm. The first sintered layer 41 is printed on the top of the wafer 20 as a buffer layer for laser bonding, preventing damage to the wafer 20 from laser thermal effects. The clip 4 is, for example, a copper clip with a thickness of, for example, greater than 250 μm, to achieve high power density.

[0058] In some embodiments, the electrodes of the wafer 20 (e.g., source pad 26) are, for example, a Cu plating layer, the first sintered layer 41 is, for example, a copper sintered material, and the clip 4 is, for example, a copper clip. The clip 4 is directly bonded to the first sintered layer 41 using laser welding. The embodiments of this application use direct bonding of metals of the same material, avoiding inter-diffusion between different metals, reducing porosity, improving product bonding strength, and enabling the product to perform better in high-voltage, high-current applications.

[0059] The embodiments of this application use clips 4 instead of interconnects, eliminating the increased product thickness caused by the arc height of interconnects. However, since clips 4 achieve simultaneous bonding of the metal layer 14 and the first sintered layer 41 on the wafer 20 through bending, the inclined section 5 of clips 4 (inclined relative to the sidewall of the wafer 20) needs to be higher than the total thickness of the wafer 20, the first sintered layer 41, and the second sintered layer 42 in the actual product to allow clips 4 to fit against the first sintered layer 41. That is, the thickness of the power module 100 is not only affected by the thickness of the substrate 10, the wafer 20, the first sintered layer 41, the second sintered layer 42, and clips 4, but also by the additional height generated by the inclined section 5 of clips 4. Furthermore, due to the tilt angle of the tilt segment 5, and the fact that the tilt segment 5 needs to be a certain distance from the wafer 20 in the lateral direction, when the top of the tilt segment 5 meets this distance, the distance between the bottom of the tilt segment 5 and the wafer 20 is larger, that is, it occupies a larger lateral space in the power module 100, which increases the size of the power module 100 in the lateral direction.

[0060] Figure 4 A power module 100 according to other embodiments of this application is shown. Figure 5 Compared to Figure 4 The heat-affected zone 502 produced by laser welding is shown.

[0061] In some embodiments, a plurality of laterally spaced wafers 20 are disposed on one side of a substrate 10 and electrically connected to the substrate 10. A lead frame 30 is disposed on the substrate 10 and the plurality of wafers 20. The bottom surface of the lead frame 30 is electrically connected to the substrate 10 and the wafers.

[0062] The bottom surface of the lead frame 30 has a recessed region 50 in which a plurality of wafers 20 are accommodated. The recessed region 50 includes a first recess 51 and a second recess 52. The first recess 51 has a first bottom wall 512 and a first side wall 514 surrounding the first bottom wall 512. The first bottom wall 512 has a second recess 52 in which the orthographic projection of the plurality of wafers 20 toward the lead frame 30 falls.

[0063] A first sintered layer 41 is housed in a recessed region 50 and is located between the plurality of wafers 20 and the lead frame 30. The first sintered layer 41 is located in a second recess 52 and is in physical contact with and electrically connected to the plurality of wafers 20. At the bottom wall 522 of the second recess 52, the lead frame 30 is fused to the first sintered layer 41. Furthermore, the lead frame 30 is fused to the metal layer 14.

[0064] The embodiments of this application further avoid the increased height of the power module 100 due to the bending of the clip 4 by forming a recessed region 50 on the lead frame 30 to accommodate the wafer 20. The sidewalls of the recessed region 50 (e.g., the first sidewall 514) are not inclined compared to the sidewalls of the wafer 20, and the lateral dimension of the power module 100 is further reduced compared to the embodiment of the clip 4.

[0065] In some embodiments, the lateral dimension of the second groove 52 is larger than the lateral dimension of the wafer 20. In some embodiments, the lead frame 30 has a protrusion 32 located on the bottom wall 522 of the second groove 52 and protruding toward the substrate 10, the protrusion 32 being located between adjacent wafers 20. The protrusion 32 helps align the lead frame 30 and the wafer 20. In some embodiments, the second groove 52 is formed by performing a half-etching process on the first bottom wall 512, while leaving the protrusion 32 unetched, such that the protrusion height of the protrusion 32 is equal to the depth of the second groove 52. In other embodiments, the thickness of the bottom wall 522 of the second groove 52 remains unchanged, i.e., it does not include the protrusion 32.

[0066] In some embodiments, after laser welding, welding marks are left on the surface of the lead frame 30, and the lattice arrangement of the heat-affected zone 502 generated by welding is different from the lattice arrangement of the first sintered layer 41 and the portion of the lead frame 30 located outside the heat-affected zone 502.

[0067] In some embodiments, the heat-affected zone 502 does not reach the bottom surface of the first sintered layer 41. That is, the heat-affected zone 502 does not reach the wafer 20. The ratio of the thickness of the bottom wall 522 of the second groove 52 to the thickness of the first sintered layer 41 is 1:0.5. In some embodiments, the thickness of the bottom wall 522 of the second groove 52 is 0.3 mm, and the thickness of the first sintered layer 41 is 0.15 mm. The welding depth of laser welding in the first sintered layer 41 is approximately 30 μm to 50 μm to prevent damage to the electrodes of the wafer 20. The thickness of the first sintered layer 41 is greater than the thickness of the second sintered layer 42. By thickening the first sintered layer 41, damage to the wafer 20 by laser welding is avoided.

[0068] In some embodiments, the plurality of wafers 20 have the same thickness, and the second groove 52 has the same depth at portions of the wafers 20 corresponding to different thicknesses. In other embodiments, the plurality of wafers 20 have different thicknesses, and the second groove 52 has different depths at portions of the wafers 20 corresponding to different thicknesses, to accommodate designs of wafers 20 with different thicknesses.

[0069] In some embodiments, the first peripheral sidewall 514 needs to be spaced apart from the wafer 20. A resistor 60 is disposed on and electrically connected to the substrate 10, and is positioned between the plurality of wafers 20 and the first sidewall 514 of the first recess 51. By placing the resistor 60 within the space separated from the wafer 20 by the first peripheral sidewall 514, the space utilization of the power module 100 is improved. The resistor 60 is, for example, a negative temperature coefficient (NTC) thermistor.

[0070] Figure 6 It shows the relationship with Figure 4 Exploded view of power module 100 in different embodiments, wherein molding layer 90 is not shown. Figure 6 The location where a laser welding head 200 is used to weld on the lead frame 30 is also shown.

[0071] exist Figure 4 In the illustrated embodiment, the electrodes (source pad 26, drain pad 24, and gate pad 28) of the plurality of wafers 20 are oriented in the same direction. The drain pad 24 of the wafer 20 is connected to the lead frame 30 through a first sintering layer 41, and the source pad 26 and gate pad 28 of the wafer 20 are connected to the metal layer 14 of the substrate 10 through a second sintering layer 42. Figure 6 In the embodiment shown, some wafers 20 have electrodes facing opposite directions to the other wafers 20.

[0072] In some embodiments, the width of the first sintered layer 41 is the same as the width of the corresponding electrode, such that the sidewalls of the first sintered layer 41 are aligned with the corresponding electrode, allowing for a larger tolerance in laser welding operations. In other embodiments, the width of the first sintered layer 41 may be smaller than the width of the corresponding electrode.

[0073] Figure 7 A top view of several power modules 100 according to some embodiments of this application is shown, wherein the molding layer 90 is shown as semi-transparent to show the structure it covers. Figure 8 It shows the corresponding Figure 7 Cross-sectional views of the substrate 10 and the wafer 20 in the illustrated embodiment. Figure 9 The chip 20 is shown. The electrodes of the multiple chips 20 are oriented in the same direction, providing a chip-in-the-loop connection design, for example, all with the drain pad 24 facing upwards.

[0074] Figure 10 A top view of several power modules 100 according to some embodiments of this application is shown, wherein the molding layer 90 is shown as semi-transparent to show the structure it covers. Figure 11 It shows the corresponding Figure 10 Cross-sectional views of the substrate 10 and the wafer 20 in the illustrated embodiment. Figure 12The chip 20 is shown. Some chips 20 have electrodes facing opposite directions to the other chips 20, providing a reverse chip connection design. For example, the drain pad 24 of some chips 20 faces upwards, while the source pad 26 and gate pad 28 of the other chips 20 face upwards.

[0075] See Figure 7 and Figure 10 The lead frame 30 includes a first lead 31 welded to the metal layer 14. The width of the end 312 of the first lead 31 welded to the metal layer 14 is greater than the width of the rest of the first lead 314. The first lead 31 is widened at the location where laser welding is performed to increase the bonding area and strength.

[0076] In some embodiments, the electrode material of the wafer 20 is Ti / Ni / Cu. In the embodiments of this application, the electrode, the first sintered layer 41, the metal layer 14 and the lead frame 30 of the wafer 20 are all made of Cu, that is, the same metal is directly bonded.

[0077] Figure 13 It shows the relationship with Figure 4 In different embodiments, the groove region 50 includes only the first groove 51 and does not include the second groove 52.

[0078] Figure 14 It shows the relationship with Figure 4 , Figure 13 Different implementations, in Figure 4 In the illustrated embodiment, the thickness of the portion of the lead frame 30 welded to the metal layer 14 is greater than the bottom wall 522 of the second groove 52 (for...). Figure 13 The thickness of the first bottom wall 512 of the first groove 51 is determined by laser welding in two stages. The machine parameters need to be changed: the power used when welding the lead frame 30 to the metal layer 14 is greater than that used when welding the bottom wall 522 of the second groove 52 (for...). Figure 13 This refers to the power of the first bottom wall 512 of the first groove 51 and the first sintered layer 41. Figure 14 In the embodiment shown, the thickness of the portion where the lead frame 30 is welded to the metal layer 14 is equal to the thickness of the bottom wall 522 of the second groove 52. Laser welding is performed in the same stage, and the machine parameters do not need to be changed: the power when welding the lead frame 30 to the metal layer 14 is equal to the power when welding the bottom wall 522 of the second groove 52 to the first sintered layer 41.

[0079] Figures 15 to 22 The manufacturing process of a power module 100 according to an embodiment of this application is shown.

[0080] Figure 15 This illustrates the reconstruction of multiple wafers 20 on a first carrier 300.

[0081] Figure 16The diagram illustrates the printing of a first sintering paste layer 410 on wafer 20. In some embodiments, the first sintering paste layer includes a solvent and copper particles mixed within the solvent, wherein the solvent material includes at least one of benzoic acid, phthalic acid, hexanoic acid, methanol, ethanol, and ethylene glycol.

[0082] Figure 17 The diagram illustrates a sintering process where a first sintered paste layer 410 is hot-pressed to obtain a first sintered layer 41. After hot-pressing the first sintered paste layer 410, the solvent evaporates, and the copper particles fuse together to form the first sintered layer 41. The first sintered layer 41 has a central region 412 and an edge region 414 surrounding the central region 412. The porosity of the central region 412 is lower than that of the edge region 414. The heat-affected zone 502 where the first sintered layer 41 and the lead frame 30 are fused is located in the central region 412. By welding at the central region 412, where the porosity is lower, the stability of the molten state is better, increasing the weld strength.

[0083] Figure 18 The illustration shows the substrate 10 placed on the second carrier 302.

[0084] Figure 19 The second sintering paste layer 42 is shown printed on the substrate 10.

[0085] Figure 20 This shows multiple wafers 20 and resistors 60 placed on a second sintering paste layer 420.

[0086] Figure 21 The process of hot pressing the second sintered paste layer 420 to obtain the second sintered layer 42 is shown.

[0087] Figure 22 This illustrates the formation of a 3D lead frame 30 on... Figure 21 In the resulting structure, a laser welding process is performed to weld the lead frame 30 to the first sintered layer 41 and the metal layer 14. Because the lateral dimension of the lead frame 30 is larger than that of the clip, the heat generated by laser welding can be conducted away laterally through the lead frame 30, preventing overheating from affecting the wafer 20. Figure 22 After the steps shown, a molding layer 90 is formed, and a cutting process is performed to obtain a power module 100.

[0088] Embodiments of this application provide a manufacturing process for a power module 100. The process includes: providing a plurality of laterally spaced wafers 20; forming a first sintered layer 41 on each wafer 20; electrically connecting the plurality of wafers 20 to a metal layer 14 on a substrate 10; placing a lead frame 30 on the substrate 10 and the plurality of wafers 20, wherein the bottom surface of the lead frame 30 has a recessed region 50, the first sintered layer 41 and the plurality of wafers 20 are accommodated in the recessed region 50, the recessed region 50 includes a first recess 51, the first recess 51 has a first bottom wall 512 and a first side wall 514 surrounding the first bottom wall 512, the first bottom wall 512 has a second recess 52, the first sintered layer 41 is located in the second recess 52, and the orthogonal projection of the plurality of wafers 20 toward the lead frame 30 falls in the second recess 52; and melting the lead frame 30 and the metal layer 14 by laser welding, wherein at the bottom wall of the second recess 52, the lead frame 30 and the first sintered layer 41 are melted by laser welding. In some embodiments, a first groove 51 is formed by pressing the lead frame 30, and a second groove 52 is formed by etching the lead frame 30.

[0089] Figure 23a , Figure 23b , Figure 23c , Figure 23d , 23e Different forms of laser bonding are shown, including the positional relationship between the lead frame 30 and the wafer 20. It should be understood that the actual bonding is between the lead frame 30 and the first sintered layer 41, which is located between the lead frame 30 and the wafer 20. In the process of this application, [the following is used]. Figure 23c The methods shown in this application are not limited to the embodiments described herein. Figure 23c The method shown can also be used Figure 23a , Figure 23b , Figure 23d , 23e The method shown.

[0090] The embodiments of this application utilize laser welding technology and adjust the bonding interface structure accordingly (direct bonding of the same metal) to bond the lead frame 30 / clamp 4 to the wafer 20 through the first sintering layer 41. This improves the bonding strength under high-voltage and high-current product applications, thereby increasing product lifespan, and also achieves a thinner power module 100 (reduced by 30%-50% compared to existing products). The embodiments of this application are applicable to single-sided cooling power modules 100, and are also applicable to multi-sided cooling power modules. The power module 100 of the embodiments of this application can achieve a maximum voltage and current of 1700V and 600A to 800A, while reducing the product thickness to 5 mm.

[0091] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A power module, characterized in that, include: substrate; Multiple wafers spaced laterally are disposed on one side of the substrate and electrically connected to the substrate; A lead frame is disposed on the substrate and the plurality of wafers. The bottom surface of the lead frame has a recessed area, the plurality of wafers are accommodated in the recessed area, and the bottom surface of the lead frame is electrically connected to the substrate. A first sintered layer is accommodated in the recessed region and is located between the plurality of wafers and the lead frame. The groove region includes a first groove having a first bottom wall and a first side wall surrounding the first bottom wall. The first bottom wall has a second groove. The first sintered layer is located in the second groove and is in physical contact with and electrically connected to the plurality of wafers. The orthographic projection of the plurality of wafers toward the lead frame falls in the second groove. In this configuration, at the bottom wall of the second groove, the lead frame is fused and welded together with the first sintered layer.

2. The power module according to claim 1, characterized in that, The substrate includes a dielectric layer and a metal layer disposed on one side of the dielectric layer, the metal layer being electrically connected to the lead frame and the plurality of wafers. The lead frame is fused and welded together with the metal layer.

3. The power module according to claim 1, characterized in that, The lead frame has a protrusion located on the bottom wall of the second groove and protruding toward the substrate, the protrusion being located between adjacent wafers.

4. The power module according to claim 3, characterized in that, The protrusion height of the protrusion is equal to the depth of the second groove.

5. The power module according to claim 1, characterized in that, The first sintered layer has a central region and an edge region surrounding the central region, the porosity of the central region being lower than that of the edge region, and the heat-affected zone of the first sintered layer fused with the lead frame is located in the central region.

6. The power module according to claim 5, characterized in that, The lattice arrangement of the heat-affected zone is different from that of the first sintered layer and the portion of the lead frame located outside the heat-affected zone.

7. The power module according to claim 5, characterized in that, The heat-affected zone does not reach the bottom surface of the first sintered layer.

8. The power module according to claim 1, characterized in that, The ratio of the thickness of the bottom wall of the second groove to the thickness of the first sintered layer is 1:0.

5.

9. The power module according to claim 1, characterized in that, The plurality of wafers have different thicknesses, and the second groove has different depths at portions of the wafers corresponding to the different thicknesses.

10. The power module according to claim 1, characterized in that, Also includes: A second sintered layer is disposed between each wafer and the substrate, and the wafer is electrically connected to the substrate through the second sintered layer.

11. The power module according to claim 10, characterized in that, The thickness of the first sintered layer is greater than the thickness of the second sintered layer.

12. The power module according to claim 1, characterized in that, Also includes: A resistor is disposed on the substrate and electrically connected to the substrate, the resistor being disposed between the plurality of wafers and the first sidewall of the first groove.

13. The power module according to claim 1, characterized in that, The first sintered layer is connected to the electrode of the wafer, and the width of the first sintered layer is the same as the width of the electrode, such that the sidewall of the first sintered layer is aligned with the electrode.

14. The power module according to claim 13, characterized in that, The electrodes, the first sintered layer, and the lead frame are made of the same material.

15. The power module according to claim 2, characterized in that, The lead frame includes a first lead welded to the metal layer, the width of the end of the first lead welded to the metal layer being greater than the width of the rest of the first lead.

16. A method for forming a power module, characterized in that, include: Provides multiple wafers spaced laterally; A first sintered layer is formed on each of the wafers; The plurality of wafers are electrically connected to the metal layer of the substrate; A lead frame is placed on the substrate and the plurality of wafers. The bottom surface of the lead frame has a recessed area. The first sintered layer and the plurality of wafers are accommodated in the recessed area. The recessed area includes a first recess. The first recess has a first bottom wall and a first side wall surrounding the first bottom wall. The first bottom wall has a second recess. The first sintered layer is located in the second recess. The orthogonal projection of the plurality of wafers toward the lead frame falls in the second recess. The lead frame and the metal layer are fused together by laser welding at the bottom wall of the second groove.

17. The method for forming a power module according to claim 16, characterized in that, Forming the first sintered layer on each of the wafers includes: A sintering paste layer is formed on each of the wafers. The sintering paste layer includes a solvent and copper particles mixed in the solvent. The solvent material includes at least one of benzoic acid, phthalic acid, hexanoic acid, methanol, ethanol, and ethylene glycol. The sintering paste layer is hot-pressed, the solvent evaporates, and the copper particles fuse together to form the first sintering layer.

18. The method for forming a power module according to claim 16, characterized in that, The first groove is formed by pressing the lead frame together, and the second groove is formed by etching the lead frame.

19. The method for forming a power module according to claim 16, characterized in that, The thickness of the portion of the lead frame welded to the metal layer is greater than the thickness of the bottom wall of the second groove, and the power used to weld the lead frame to the metal layer is greater than the power used to weld the bottom wall of the second groove to the first sintered layer, or The thickness of the portion of the lead frame welded to the metal layer is equal to the thickness of the bottom wall of the second groove, and the power used to weld the lead frame to the metal layer is equal to the power used to weld the bottom wall of the second groove to the first sintered layer.

20. A power module, characterized in that, include: The substrate includes a dielectric layer and a metal layer disposed on one side of the dielectric layer; A wafer is disposed on the metal layer and electrically connected to the metal layer; A lead frame is disposed on the substrate and the wafer. The bottom surface of the lead frame has a groove region, the wafer is accommodated in the groove region, and the lead frame is fused and welded to the metal layer. A first sintered layer is accommodated in the recessed region and is located between the wafer and the lead frame. The groove region includes a first groove having a first bottom wall and a first side wall surrounding the first bottom wall. The first bottom wall has a second groove. The first sintered layer is located in the second groove and is in physical contact with and electrically connected to the wafer. The orthographic projection of the wafer toward the lead frame falls in the second groove. In this configuration, at the bottom wall of the second groove, the lead frame is fused and welded together with the first sintered layer.

Images